A method for repairing IIC bus hangs based on Phytium 2000_4 processor

Abstract

This invention discloses a method for repairing IIC bus hangs based on the Phytium 2000_4 processor, belonging to the field of communication technology. This method solves the IIC bus hang problem caused by communication anomalies through software configuration: first, the corresponding pin of the serial data bus SDA is multiplexed as a GPIO function and set to output mode; then, 0 is written to the data register to force SDA to output a low level to simulate a slave device acknowledge signal; finally, the IIC module is reinitialized to restore communication. This invention requires no hardware modifications, effectively improves bus stability and device operational reliability, and is suitable for IIC communication systems using the Phytium 2000_4 processor.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and specifically to a method for repairing IIC bus hangs based on the Phytium 2000_4 processor. Background Technology

[0002] IIC (Inter-Integrated Circuit) is a two-wire serial bus used to connect microcontrollers and their peripheral devices.

[0003] IIC requires only two lines: a serial data bus (SDA) and a serial clock line (SCL). Devices connected to the IIC bus communicate via SCL and SDA. Each device is identified by a specific address and can act as either a master or a slave. A device is a master when sending data to the bus; it is a slave when receiving data from the bus. The master device needs to generate the clock signal SCL, control data transmission, and generate START and STOP states. The slave device needs to start and end data read / write operations based on the START and STOP states sent by the master device. The slave device also needs to send an ACK acknowledgement signal to the master device after receiving data.

[0004] The Phytium 2000_4 processor, acting as the master device, interacts with slave devices via the IIC bus. During this interaction, interference can cause IIC bus communication anomalies. The master device fails to receive the ACK signal from the slave device, and the serial data bus SDA remains high. The Phytium 2000_4 processor does not release the serial data bus SDA, leading to an IIC bus hang. Reinitializing the IIC module does not restore IIC bus communication. The Phytium 2000_4 processor does not provide a solution for this communication anomaly. Summary of the Invention

[0005] To address the aforementioned shortcomings in the existing technology, this invention provides a method for repairing IIC bus hangs based on the Phytium 2000_4 processor.

[0006] To achieve the above-mentioned objectives, the technical solution adopted by this invention is as follows:

[0007] A method for repairing IIC bus hangs based on the Phytium 2000_4 processor includes the following steps:

[0008] S1. Set the PAD multiplexing type of the corresponding pin of the serial data bus SDA to GPIO;

[0009] S2. Configure the direction register as an output;

[0010] S3. Write 0 to the corresponding bit in the data writing register to make the corresponding pin of the serial data bus SDA output a low level.

[0011] S4. Initialize the IIC module;

[0012] S5. The Phytium 2000_4 processor communicates with the slave device via IIC. If the communication fails, step S1 is executed again.

[0013] Furthermore, S1 specifically includes:

[0014] S11. Configure the pin function. Configure the multiplexing function of the control field cru_clk_obv_pad in the configuration register to FUN1;

[0015] S12. Set pin gpio0_porta_0 to GPIO function.

[0016] Furthermore, configuring the direction register as an output in S2 means:

[0017] Set the bit corresponding to pin gpio0_porta_0 in the direction register to 1.

[0018] Furthermore, writing 0 to the corresponding bit in the register in S3 means:

[0019] Set the bit corresponding to pin gpio0_porta_0 in the data register to 0.

[0020] Furthermore, the condition for determining IIC communication abnormality in S5 is as follows:

[0021] In the Phytium 2000_4 processor, the MST_ACTIVITY status bit is 1, indicating that the Master function of the I2C controller is active.

[0022] Furthermore, the specific method for configuring the pin function configuration register in S11 is as follows:

[0023] Offset address 0x0200 [25:24] indicates the function selection of cru_clk_obv_pad:

[0024] 2'b00: Select func0;

[0025] 2'b01: Select func1;

[0026] 2'b10: Select func2;

[0027] 2'b11: Select func3.

[0028] Furthermore, the direction register is the GPIO_SWPORTA_DDR register.

[0029] Furthermore, the method of initializing the IIC module in S4 is consistent with the normal method of initializing the IIC module.

[0030] Furthermore, S5 specifically includes the following steps:

[0031] If the S51 Phytium 2000_4 processor communicates with the slave device via IIC and the MST_ACTIVITY value in the Phytium 2000_4 processor is 1 after the normal communication time has elapsed, it indicates that the Master function of the I2C controller is active, and the IIC communication is determined to be abnormal.

[0032] S52. If IIC communication fails, re-execute step S1.

[0033] The present invention has the following beneficial effects:

[0034] The method described in this invention is based on pure software to restore IIC bus communication, which does not require hardware changes, saves costs, improves the stability of the IIC bus, and thus improves the stability and security of device operation. Attached Figure Description

[0035] Figure 1 It is a flowchart of a method in the existing technology.

[0036] Figure 2 This is a timing diagram for IIC bus communication.

[0037] Figure 3 This is a flowchart of the method of the present invention. Detailed Implementation

[0038] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0039] Figure 1 The flowchart of the method in the prior art includes the initialization of the IIC module and the Phytium 2000_4 processor communicating with the slave device via IIC. Figure 2 This is a timing diagram for the IIC bus communication.

[0040] This invention is based on IIC bus communication of the Phytium 2000_4 processor. For example... Figure 3 As shown, this invention provides a method for repairing IIC bus hangs based on the Phytium 2000_4 processor, the implementation of which is as follows:

[0041] S1. Set the PAD multiplexing type of the corresponding pin of the serial data bus SDA to GPIO. The implementation method is as follows:

[0042] S101. Configure the pin function register, as shown in Table 1. In offset address 0x0200, [25:24] indicates the function selection of cru_clk_obv_pad: 2'b00: select func0; 2'b01: select func1; 2'b10: select func2; 2'b11: select func3.

[0043] Table 1. Function Table of Pin Function Configuration Registers for Phytium 2000_4 Processor

[0044]

[0045] S102. Set the control field cru_clk_obv_pad to FUN1, as shown in Table 2, indicating that the pin (gpio0_porta_0) is a GPIO.

[0046] Table 2. Pin Multiplexing Function Table for Phytium 2000_4 Processor

[0047]

[0048] S2. Configure the direction register as an output. The implementation method is as follows:

[0049] S201. Set the bit corresponding to pin (gpio0_porta_0) in the direction register to 1; as shown in Table 3, this indicates that the pin is configured as an output.

[0050] Table 3 Function Table of Phytium 2000_4 Processor IIC Direction Register

[0051]

[0052] S3. When the corresponding bit in the data writing register is written to 0, the corresponding pin of the serial data bus SDA will output a low level. The implementation method is as follows:

[0053] S301, set the bit corresponding to pin (gpio0_porta_0) in the data register to 0; as shown in Table 4, this indicates that the pin will be output low level.

[0054] Table 4. Function Table of IIC Data Registers for Phytium 2000_4 Processor

[0055]

[0056] S4. Initialize the IIC module. The method for initializing the IIC module is the same as the normal method for initializing the IIC module.

[0057] S5. The Phytium 2000_4 processor communicates with the slave device via IIC. If an IIC communication failure occurs, step S1 is re-executed. The implementation method is as follows:

[0058] If the S501 and Phytium 2000_4 processors communicate with the slave devices via IIC and the MST_ACTIVITY value in the Phytium 2000_4 processor is 1 after the normal communication time has elapsed (as shown in Table 5), it indicates that the Master function of the I2C controller is active, and the IIC communication is determined to be abnormal.

[0059] Table 5 Function Table of Phytium 2000_4 Processor IIC Status Register

[0060]

[0061] S502. After an IIC communication failure, step S1 is re-executed.

[0062] Specific embodiments have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

[0063] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A method for repairing IIC bus hangs based on Phytium 2000_4 processor, characterized in that, Includes the following steps: S1. Set the PAD multiplexing type of the corresponding pin of the serial data bus SDA to GPIO, specifically including: S11. Configure the pin function. Configure the multiplexing function of the control field cru_clk_obv_pad in the configuration register to FUN1; S12. Set pin gpio0_porta_0 to GPIO function; S2. Configure the direction register as an output. Specifically, set the bit corresponding to pin gpio0_porta_0 in the direction register to 1. S3. Write 0 to the corresponding bit in the data writing register, causing the corresponding pin of the serial data bus SDA to output a low level. Writing 0 to the corresponding bit in the data writing register means: Set the bit corresponding to pin gpio0_porta_0 in the data register to 0; S4. Initialize the IIC module; S5. The Phytium 2000_4 processor communicates with the slave device via IIC. If the communication fails, step S1 is executed again.

2. The IIC bus hang repair method based on Phytium 2000_4 processor according to claim 1, characterized in that, The conditions for determining IIC communication abnormality in S5 are as follows: In the Phytium 2000_4 processor, the MST_ACTIVITY status bit is 1, indicating that the Master function of the I2C controller is active.

3. The IIC bus hang repair method based on Phytium 2000_4 processor according to claim 1, characterized in that, The specific method for configuring the pin function configuration register in S11 is as follows: Offset address 0x0200 [25:24] indicates the function selection of cru_clk_obv_pad: 2'b00: Select func0; 2'b01: Select func1; 2'b10: Select func2; 2'b11: Select func3.

4. The IIC bus hang repair method based on Phytium 2000_4 processor according to claim 1, characterized in that, The direction register is the GPIO_SWPORTA_DDR register.

5. The IIC bus hang repair method based on Phytium 2000_4 processor according to claim 1, characterized in that, The method of initializing the IIC module in S4 is the same as the normal method of initializing the IIC module.

6. The IIC bus hang repair method based on Phytium 2000_4 processor according to claim 1, characterized in that, S5 specifically includes the following steps: If the S51 Phytium 2000_4 processor communicates with the slave device via IIC and the MST_ACTIVITY value in the Phytium 2000_4 processor is 1 after the normal communication time has elapsed, it indicates that the Master function of the I2C controller is active, and the IIC communication is determined to be abnormal. S52. If IIC communication fails, re-execute step S1.

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