Hybrid reconfigurable computing chip based on encryption and decryption computing and computer equipment

Abstract

The invention relates to a hybrid reconfigurable computing chip based on encryption and decryption computing and computer equipment. The method comprises the following steps: acquiring a first prime number and a second prime number, and determining a public key and an Euler function value according to the first prime number and the second prime number; the public key comprises a public key index and a modulus; performing linear operation in a private key calculation process by using the public key index and the Euler function value to obtain a first calculation result; outputting a first calculation result to a Boolean processor calculation core of a fine-grained reconfigurable architecture through a processing unit array data transmission unit and a Boolean processor array data transmission unit in sequence, so that the Boolean processor calculation core performs structured operation in a private key calculation process by using the first calculation result and an Euler function value, and a private key is obtained and output to the coarse-grained calculation core through the Boolean processor array data transmission unit and the processing unit array data transmission unit in sequence. By adopting the method, the key calculation efficiency can be improved.

Description

Technical Field

[0001] This application relates to the field of encryption and decryption technology, and in particular to a hybrid reconfigurable computing chip and computer device based on encryption and decryption calculations. Background Technology

[0002] With the development and iteration of computer technology, the demand for encryption in areas such as file transfer, webpage verification, storage backup, and chip security is rapidly increasing. Obtaining the encryption key is crucial in data encryption and decryption.

[0003] In related technologies, coarse-grained computing kernels are often used to compute keys. However, the computational efficiency of structured operations in coarse-grained computing kernels is much lower than that of linear operations, resulting in low computational efficiency when computing keys.

[0004] Therefore, there is an urgent need to provide an encryption and decryption calculation method that can improve the efficiency of key calculation. Summary of the Invention

[0005] Based on this, this application provides a hybrid reconfigurable computing chip and computer device based on encryption and decryption calculations, which can improve key calculation efficiency.

[0006] In a first aspect, this application provides an encryption / decryption calculation method applied to a coarse-grained computation core of a coarse-grained reconfigurable architecture in a hybrid reconfigurable computing chip. The coarse-grained reconfigurable architecture further includes a processing unit array data transmission unit connected to the coarse-grained computation core. The hybrid reconfigurable computing chip also includes a fine-grained reconfigurable architecture, which includes a Boolean processor array data transmission unit connected to the processing unit array data transmission unit, and a Boolean processor computation core connected to the Boolean processor array data transmission unit. The method includes:

[0007] Obtain the first and second prime numbers, and determine the public key and Euler's totient function value based on the first and second prime numbers; the public key includes the public key exponent and the modulus;

[0008] Linear operations are performed during the private key calculation process using the public key exponent and Euler's totient function value to obtain the first calculation result;

[0009] The first calculation result is sequentially output to the Boolean processor computing core of the fine-grained reconfigurable architecture through the data transmission unit of the processing unit array and the data transmission unit of the Boolean processor array. This allows the Boolean processor computing core to perform structured operations in the private key calculation process using the first calculation result and the Euler function value. The result is then obtained and sequentially output to the coarse-grained computing core through the data transmission unit of the Boolean processor array and the data transmission unit of the processing unit array. The public key and the private key are used for encryption and decryption calculations.

[0010] In some embodiments, the coarse-grained reconfigurable architecture further includes a processing unit array sharing memory connected to the coarse-grained computing core, and the method further includes:

[0011] Retrieve the data to be encrypted from the shared memory of the processing unit array;

[0012] The second calculation result is determined based on the data to be encrypted and the public key index;

[0013] The second calculation result and modulus are sequentially output to the Boolean processor calculation core through the processing unit array data transmission unit and the Boolean processor array data transmission unit, so that the Boolean processor calculation core determines and sequentially outputs the encrypted data to the coarse-grained calculation core through the Boolean processor array data transmission unit and the processing unit array data transmission unit based on the second calculation result and modulus.

[0014] In some embodiments, the coarse-grained reconfigurable architecture further includes a processing unit array sharing memory connected to the coarse-grained computing core, and the method further includes:

[0015] Retrieve the data to be decrypted from the shared memory of the processing unit array;

[0016] Based on the data to be decrypted and the private key, determine the third calculation result;

[0017] The third calculation result and modulus are sequentially output to the Boolean processor calculation core through the processing unit array data transmission unit and the Boolean processor array data transmission unit, so that the Boolean processor calculation core determines and sequentially outputs the decrypted data to the coarse-grained calculation core through the Boolean processor array data transmission unit and the processing unit array data transmission unit based on the third calculation result and modulus.

[0018] In some embodiments, the coarse-grained reconfigurable architecture further includes a processing unit array configured with direct memory access connected to the coarse-grained computing cores, and the method further includes:

[0019] Obtain the processing unit array configuration information output by direct memory access; the processing unit array configuration information is used to indicate the computational function of each processing unit in the processing unit array of the coarse-grained computing core.

[0020] Configure the computational functions of each processing unit in the coarse-grained computational core based on the processing unit array configuration information.

[0021] In some embodiments, during the determination of the modulus and Euler's totient function value, the acquired processing unit array configuration information is used to indicate that half of the processing units in the coarse-grained computing core are used to calculate the modulus and the other half are used to calculate the Euler's totient function value.

[0022] In some embodiments, the Boolean processor array data transmission unit is further configured to, upon obtaining the first calculation result and the Euler function value, if the first calculation result and the Euler function value have been calculated multiple times, output a pre-stored private key to the coarse-grained calculation core through the processing unit array data transmission unit; and if the first calculation result and the Euler function value have not been calculated multiple times, output the first calculation result and the Euler function value to the Boolean processor calculation core.

[0023] In some embodiments, the coarse-grained reconfigurable architecture further includes a processing unit array sharing memory connected to the coarse-grained computation core, and obtaining a first prime number and a second prime number includes:

[0024] Read the first commonly used data, the location code of the first commonly used data, the second commonly used data, and the location code of the second commonly used data from the shared memory of the processing unit array;

[0025] The first prime number is determined based on the first frequently used data and its position code.

[0026] The second prime number is determined based on the positional encoding of the second most frequently used data.

[0027] In some embodiments, determining the public key and the Euler totient function value based on a first prime number and a second prime number includes:

[0028] Based on the number of bits processed by each processing unit, the first prime number is partitioned to obtain multiple partition results of the first prime number, and the second prime number is partitioned to obtain multiple partition results of the second prime number;

[0029] The public key and Euler's totient function value are determined based on multiple fragmentation results of the first prime number and multiple fragmentation results of the second prime number.

[0030] Secondly, this application provides a hybrid reconfigurable computing chip, which includes a coarse-grained reconfigurable architecture and a fine-grained reconfigurable architecture. The coarse-grained reconfigurable architecture includes a coarse-grained computing core and a processing unit array data transmission unit connected to the coarse-grained computing core. The fine-grained reconfigurable architecture includes a Boolean processor array data transmission unit connected to the processing unit array data transmission unit and a Boolean processor computing core connected to the Boolean processor array data transmission unit.

[0031] A coarse-grained computational core is used to obtain a first prime number and a second prime number, and to determine the public key and Euler's totient function value based on the first prime number and the second prime number; the public key includes the public key exponent and the modulus; linear operations are performed in the private key computation process using the public key exponent and the Euler's totient function value to obtain a first computation result; the first computation result is output to the Boolean processor computational core of the fine-grained reconfigurable architecture sequentially through the data transmission unit of the processing unit array and the data transmission unit of the Boolean processor array.

[0032] The Boolean processor computation core is used to perform structured operations in the private key calculation process using the first calculation result and the Euler function value, and obtains and outputs the private key to the coarse-grained computation core in sequence through the Boolean processor array data transmission unit and the processing unit array data transmission unit.

[0033] Thirdly, this application provides a computer device, which includes a hybrid reconfigurable computing chip as described in the second aspect.

[0034] In this embodiment, the calculation of the Euler's totient function, public key exponent, and modulus are all linear operations. The Euler's totient function, public key exponent, and modulus are calculated in a coarse-grained computing core, while the linear operations (including multiplication and addition) in the private key calculation process are performed in the coarse-grained computing core, and the structured operations (including modulo operations) are performed in the Boolean processor computing core. Thus, the coarse-grained computing core performs the linear operations in the key determination process, and the Boolean processor computing core performs the structured operations in the key determination process. The coarse-grained computing core has high efficiency in linear operations, and the Boolean processor computing core has high efficiency in structured operations. The efficiency of the Boolean processor computing core in structured operations is much higher than that of the coarse-grained computing core. Therefore, compared with the method of key determination by the coarse-grained computing core, the method of key determination by the coarse-grained computing core and the Boolean processor computing core in this embodiment can greatly improve the efficiency of key determination. In addition, the operations of the coarse-grained computing core and the Boolean processor computing core can be performed in parallel, thereby further improving the efficiency of key determination. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of the hybrid reconfigurable computing chip provided in the first embodiment;

[0037] Figure 2 A flowchart illustrating the encryption / decryption calculation method provided in the first embodiment;

[0038] Figure 3 A schematic diagram of the structure of the hybrid reconfigurable computing chip provided in the second embodiment;

[0039] Figure 4 A schematic diagram of the structure of the hybrid reconfigurable computing chip provided in the third embodiment;

[0040] Figure 5 A schematic diagram of the structure of the hybrid reconfigurable computing chip provided in the fourth embodiment;

[0041] Figure 6 A schematic diagram of the RSA-2048 calculation process is provided for some embodiments;

[0042] Figure 7 A schematic diagram illustrating the process of a computation method for RSA on a hybrid reconfigurable computing chip, provided for some embodiments;

[0043] Figure 8 A schematic diagram of the structure of a computer device provided for some embodiments. Detailed Implementation

[0044] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0046] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, "multiple groups" means two or more, and "each" means each of the multiple, unless otherwise explicitly defined.

[0047] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0048] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0049] Currently, with the development and iteration of computer technology, the demand for encryption in areas such as file transfer, web page verification, storage backup, and chip security is rapidly increasing. In file transfer, confidential documents need to be encrypted before transmission. For web page verification, plaintext passwords need to be encrypted and then obfuscated before encryption to improve password security. In storage backup, especially for companies operating network storage, rapid encryption of user data is crucial; otherwise, information leaks could lead to privacy and security incidents, causing a decline in the company's reputation and revenue. In chip security, it is necessary to ensure that chips can perform rapid encryption and decryption, enabling hardware-level encryption of host or cluster files and reducing data security risks associated with software encryption and decryption.

[0050] Encryption algorithms transform original data mathematically, making the original data unreadable. RSA, the first widely used public-key encryption algorithm, was proposed by Ron Rivest, Adi Shamir, and Leonard Adleman. Its core idea is based on the problem of factoring large integers in number theory. This algorithm solves the core problem of key distribution in symmetric encryption by generating a mathematically linked pair of public and private keys. The public key is used to encrypt data, and the private key is used for decryption. This asymmetric property makes RSA the cornerstone of digital signatures, Secure Sockets Layer (SSL) and Transport Layer Security (TLS) certificates, and secure communication. Currently, key lengths of 1024 / 2048 bits or more are used to resist most attacks, but its relatively low efficiency limits its application in large-scale data encryption; it is usually only used for encrypting small amounts of data (such as session keys) or for authentication.

[0051] Coarse-Grained Reconfigurable Architecture (CGRA) has become a hot research and development topic due to its reconfigurability and advantages in coarse-grained parallel computing. Unlike the traditional von Neumann architecture, CGRA enhances computational parallelism and pipelining capabilities through technologies such as computational arrays and Single Instruction Multiple Data (SIMD), significantly improving computational efficiency. The RSA algorithm includes not only coarse-grained arithmetic operations suitable for CGRA (e.g., multiplication and / or addition) but also numerous fine-grained logical operations (e.g., modulo operations and / or concatenation). This mixed-grained computation presents challenges to CGRA's computational patterns and data transmission. The slow acceleration of CGRA in RSA encryption is primarily due to the fact that CGRA's efficiency in handling logical computations in cryptographic algorithms is far lower than its efficiency in handling arithmetic computations, and the difficulty in implementing fine-grained control over cryptographic algorithms.

[0052] Therefore, related technologies suffer from slow RSA computation speeds (such as RSA encryption and RSA decryption).

[0053] Boolean processors (BPs) feature fine-grained, reconfigurable, and parallel computing capabilities, enabling them to better control logical computations in encryption algorithms.

[0054] Therefore, this application proposes a computation method for RSA encryption computation tasks in a coarse-fine granularity reconfigurable computing architecture, which accelerates the arithmetic and logical computations in the RSA encryption algorithm in the coarse-fine granularity reconfigurable architecture, thereby accelerating the RSA algorithm.

[0055] Figure 1 This is a schematic diagram of the structure of the hybrid reconfigurable computing chip provided in the first embodiment, as shown below. Figure 1As shown, the hybrid reconfigurable computing chip includes a coarse-grained reconfigurable architecture and a fine-grained reconfigurable architecture (BP architecture). The coarse-grained reconfigurable architecture includes a coarse-grained computing core (CGRACore) and a processing element array (PEA) data transmission unit connected to the coarse-grained computing core. The fine-grained reconfigurable architecture includes a Boolean processor array (BPA) data transmission unit connected to the processing element array data transmission unit and a Boolean processor computing core (BP Core) connected to the Boolean processor array data transmission unit.

[0056] Figure 2 This is a flowchart illustrating the encryption / decryption calculation method provided in the first embodiment, as shown below. Figure 2 As shown, the method is applied to the coarse-grained computing core of the coarse-grained reconfigurable architecture in a hybrid reconfigurable computing chip, and the method includes the following steps S201 to S203.

[0057] S201. Obtain the first prime number and the second prime number, and determine the public key and Euler's totient function value based on the first prime number and the second prime number; the public key includes the public key exponent and the modulus.

[0058] In some embodiments, the first prime number and the second prime number can be prime numbers with the same number of bits. For example, the number of bits in the first prime number and the second prime number can range from 256 bits to 2048 bits. For example, the first prime number and the second prime number can both be 256-bit prime numbers, 512-bit prime numbers, 1024-bit prime numbers, or 2048-bit prime numbers, etc., and this application embodiment does not impose any limitations on this.

[0059] In some embodiments, the first prime number and the second prime number may be output to the coarse-grained computing core by an external processing chip connected to the hybrid reconfigurable computing chip.

[0060] The Euler totient function value, the public key exponent, and the modulus can all be twice the number of bits of the first prime number or the second prime number.

[0061] For example, the public key and the Euler's totient function value can be determined by: determining the modulus by multiplying the first prime number and the second prime number; determining the Euler's totient function value by multiplying the result of subtracting 1 from the first prime number and the result of subtracting 1 from the second prime number; and determining the public key exponent that is prime to the Euler's totient function value.

[0062] In some embodiments, S201 may include: obtaining a first prime number and a second prime number, and determining a modulus and an Euler's totient function value based on the first prime number and the second prime number; determining multiple candidate values ​​based on the Euler's totient function value, and sequentially outputting the Euler's totient function value and multiple candidate values ​​to the Boolean processor computation core of the fine-grained reconfigurable architecture through the processing unit array data transmission unit and the Boolean processor array data transmission unit, so that the Boolean processor computation core selects a public key prime number that is prime to the Euler's totient function value from the multiple candidate values, and sequentially outputting the public key prime number to the coarse-grained computation core through the Boolean processor array data transmission unit and the processing unit array data transmission unit.

[0063] S202. Perform linear operations in the private key calculation process using the public key exponent and Euler's totient function value to obtain the first calculation result.

[0064] For example, the formula for calculating the private key d is as follows: d = e -1 modφ, where e represents the public key exponent and φ represents the Euler totient function value. In the private key calculation process, not only linear operations (e.g., multiplication) but also structured operations (e.g., modulo operation) exist. In this embodiment, linear and structured operations are executed in different cores; that is, linear operations are executed in a coarse-grained computation core, and structured operations are executed in a Boolean processor computation core.

[0065] S203. The first calculation result is sequentially output to the Boolean processor computing core of the fine-grained reconfigurable architecture through the processing unit array data transmission unit and the Boolean processor array data transmission unit, so that the Boolean processor computing core can use the first calculation result and the Euler function value to perform structured operations in the private key calculation process, and obtain and output the private key to the coarse-grained computing core through the Boolean processor array data transmission unit and the processing unit array data transmission unit.

[0066] In this system, the public and private keys are used for encryption and decryption calculations. For example, the public key is used for encryption calculations, and the public and private keys are used for decryption calculations.

[0067] In this embodiment, the calculation of the Euler's totient function, public key exponent, and modulus are all linear operations. The Euler's totient function, public key exponent, and modulus are calculated in a coarse-grained computing core, while the linear operations (including multiplication and addition) in the private key calculation process are performed in the coarse-grained computing core, and the structured operations (including modulo operations) are performed in the Boolean processor computing core. Thus, the coarse-grained computing core performs the linear operations in the key determination process, and the Boolean processor computing core performs the structured operations in the key determination process. The coarse-grained computing core has high efficiency in linear operations, and the Boolean processor computing core has high efficiency in structured operations. The efficiency of the Boolean processor computing core in structured operations is much higher than that of the coarse-grained computing core. Therefore, compared with the method of key determination by the coarse-grained computing core, the method of key determination by the coarse-grained computing core and the Boolean processor computing core in this embodiment can greatly improve the efficiency of key determination. In addition, the operations of the coarse-grained computing core and the Boolean processor computing core can be performed in parallel, thereby further improving the efficiency of key determination.

[0068] Figure 3 This is a schematic diagram of the structure of the hybrid reconfigurable computing chip provided in the second embodiment. Figure 3 Compared to the example Figure 1 The difference in the embodiments is that the coarse-grained reconfigurable architecture also includes a processing unit array that shares memory with the coarse-grained computing core.

[0069] In some embodiments, if a public key is obtained, it can also be used to encrypt the data to be encrypted. The method for encrypting the data to be encrypted using the public key is as follows: The data to be encrypted is obtained from the shared memory of the processing unit array; a second calculation result is determined based on the data to be encrypted and the public key exponent; the second calculation result and the modulus are sequentially output to the Boolean processor core through the processing unit array data transmission unit and the Boolean processor array data transmission unit, so that the Boolean processor core determines and sequentially outputs the encrypted data to the coarse-grained computing core through the Boolean processor array data transmission unit and the processing unit array data transmission unit based on the second calculation result and the modulus.

[0070] For example, the data to be encrypted in the shared memory of the processing unit array can be transferred from an external processing chip to the shared memory of the processing unit array.

[0071] In some embodiments, the public key of the data to be encrypted can be raised to a power to obtain a second calculation result. In some embodiments, the remainder after dividing the second calculation result by the modulus can be calculated to obtain the encrypted data.

[0072] In the technical solution provided in this application embodiment, since the coarse-grained computing core is highly efficient in linear operations, and the Boolean processor computing core is far more efficient in structured operations than the coarse-grained computing core, the coarse-grained computing core performs multiplication operations in encryption computing, while the Boolean processor computing core performs modulo operations in encryption computing. Through this precise division of labor based on operation type and computing core characteristics, the two types of computing cores can each play to their strengths in the encryption computing process, effectively reducing the performance bottleneck when different types of operations are processed on a single computing core, thereby improving the overall computing efficiency of encryption computing.

[0073] In some embodiments, if the public and private keys are obtained, the private key can also be used to decrypt the data to be decrypted. The method for decrypting the data to be decrypted using the public and private keys is as follows: The data to be decrypted is obtained from the shared memory of the processing unit array; a third calculation result is determined based on the data to be decrypted and the private key; the third calculation result and the modulus are sequentially output to the Boolean processor core through the processing unit array data transmission unit and the Boolean processor array data transmission unit, so that the Boolean processor core determines and sequentially outputs the decrypted data to the coarse-grained computing core through the Boolean processor array data transmission unit and the processing unit array data transmission unit based on the third calculation result and the modulus.

[0074] For example, the data to be decrypted in the shared memory of the processing unit array can be transferred from an external processing chip to the shared memory of the processing unit array.

[0075] In some embodiments, the private key power of the data to be decrypted can be calculated to obtain a third calculation result. In some embodiments, the remainder after dividing the third calculation result by the modulus can be calculated to obtain the decrypted data.

[0076] In the technical solution provided in this application embodiment, since the coarse-grained computing core is highly efficient in linear operations, and the Boolean processor computing core is far more efficient in structured operations than the coarse-grained computing core, the coarse-grained computing core performs multiplication operations in the decryption calculation, while the Boolean processor computing core performs modulo operations in the decryption calculation. Through this precise division of labor based on the operation type and the characteristics of the computing core, the two computing cores can each play to their strengths in the decryption calculation process, effectively reducing the performance bottleneck when different types of operations are processed on a single computing core, thereby improving the overall computational efficiency of the decryption calculation.

[0077] Figure 4 This is a schematic diagram of the structure of the hybrid reconfigurable computing chip provided in the third embodiment. Figure 4 Compared to the example Figure 1The difference in the embodiments is that the coarse-grained reconfigurable architecture also includes a processing unit array configuration direct memory access (PEAConfiguration DMA) connected to the coarse-grained computing core.

[0078] In some embodiments, the method may further include: obtaining processing unit array configuration information of the processing unit array configuration direct memory access output; the processing unit array configuration information is used to indicate the computational function of each processing unit of the processing unit array in the coarse-grained computing core; and configuring the computational function of each processing unit of the processing unit array in the coarse-grained computing core according to the processing unit array configuration information.

[0079] For example, a coarse-grained computing core includes at least one array of processing units, where processing units at the same location in different arrays are configured to perform the same computing function, or where processing units in one array are configured to perform the same computing function.

[0080] The calculation function can include addition and multiplication operations.

[0081] In some embodiments, the processing unit array configuration direct memory access can generate corresponding processing unit array configuration information based on the computation stage. For example, in the stage of determining the modulus and Euler's totient function values, processing unit array configuration information for the public key computation process is generated. Exemplarily, this information indicates that half of the processing units in the coarse-grained computation core's processing unit array are used to calculate the modulus, and the other half are used to calculate the Euler's totient function value. As another example, in the private key computation stage, processing unit array configuration information for the private key computation process is generated. Exemplarily, this information indicates that a small number of processing units are used for addition operations, and the majority are used for multiplication operations. As yet another example, in the encryption and / or decryption stages, processing unit array configuration information for these stages is generated. Exemplarily, this information indicates that all processing units in the coarse-grained computation core's processing unit array are used for multiplication operations.

[0082] Figure 4 Compared to the example Figure 1 The difference in the embodiments is that the coarse-grained reconfigurable architecture also includes a processing unit array configuration unit, and the fine-grained reconfigurable architecture also includes an instruction allocation unit connected to the processing unit array configuration unit, and the instruction allocation unit is also connected to the Boolean processor computing core.

[0083] In some embodiments, the processing unit array configuration unit is further configured to acquire Boolean processor array configuration information, output the Boolean processor array configuration information to the instruction allocation unit, the instruction allocation unit outputs the Boolean processor array configuration information to the Boolean processor computing core, and the Boolean processor computing core is configured to configure the computing functions of each Boolean processor in the Boolean processor array in the Boolean processor computing core according to the Boolean processor array configuration information.

[0084] In the technical solution provided in this application, the processing unit array in the coarse-grained computing core can flexibly adjust the computing functions of each processing unit according to different computing stages. For example, in the stage of determining the modulus and Euler's totient function, half of the processing units in the processing unit array can be dedicated to calculating the modulus, and the other half to calculating the Euler's totient function, so that different computing tasks are handled by corresponding processing units, avoiding the problem of unreasonable task allocation caused by fixed processing unit functions. In the private key calculation stage, a small number of processing units can be configured to perform addition operations, and most processing units can perform multiplication operations, so that the functions of the processing units match the characteristics of low addition operation requirements and high multiplication operation requirements in private key calculation, avoiding the situation where one type of operation processing unit is idle while another type of operation processing unit is overloaded. In the encryption and / or decryption stage, when all processing units are configured to perform multiplication operations, resources can be concentrated to efficiently complete the computing tasks that are mainly multiplication operations in this stage. Thus, the entire coarse-grained computing core can run in an optimal functional allocation state in different computing stages, effectively improving computing efficiency, reducing unnecessary resource waste, and ensuring that linear operations can be completed quickly.

[0085] In some embodiments, during the determination of the modulus and Euler's totient function value, the acquired processing unit array configuration information is used to indicate that half of the processing units in the coarse-grained computing core are used to calculate the modulus and the other half are used to calculate the Euler's totient function value.

[0086] In the technical solution provided in this application embodiment, the processing unit array configuration information instructs half of the processing units in the processing unit array to be dedicated to calculating the modulus and the other half to calculating the Euler's totient function value. This targeted functional allocation method allows the two core and parallel tasks of modulus calculation and Euler's totient function value calculation at this stage to each have independent processing unit resources. Since modulus calculation and Euler's totient function value calculation are different computational processes with different processing logic and computational steps, assigning them to different processing units for separate execution avoids the switching delay caused by processing units alternating between the two tasks at the same time, and also avoids the situation where all processing units are concentrated on processing one task, causing the other task to wait. At the same time, each processing unit only needs to focus on its assigned single computational task (modulus calculation or Euler's totient function value calculation) without having to consider multiple computational logics, which can give full play to its processing efficiency and reduce the waste of computational resources caused by functional mixing. As a result, the entire coarse-grained computing core can advance the two key computational tasks in a parallel and efficient manner during the determination of the modulus and Euler's totient function value, effectively shortening the overall computation time of this stage and improving the stability and resource utilization efficiency of the computation process.

[0087] In some embodiments, the Boolean processor array data transmission unit is further configured to, upon obtaining the first calculation result and the Euler function value, if the first calculation result and the Euler function value have been calculated multiple times, output a pre-stored private key to the coarse-grained calculation core through the processing unit array data transmission unit; and if the first calculation result and the Euler function value have not been calculated multiple times, output the first calculation result and the Euler function value to the Boolean processor calculation core.

[0088] In some embodiments, the Boolean processor array data transmission unit can also record the first calculation result and Euler function value obtained each time within the time period between a preset time and the current time. The preset time can be a time before the current time and an interval of a preset time from the current time, so as to determine whether the latest obtained first calculation result and Euler function value have been calculated multiple times.

[0089] For example, "multiple times" can include two or more times, and the embodiments of this application do not limit this.

[0090] In the technical solution provided in this application embodiment, when the first calculation result and Euler's function value are obtained, the Boolean processor array data transmission unit first determines whether these two data have been calculated multiple times. If they have been calculated multiple times, the pre-stored private key is directly output to the coarse-grained calculation core through the processing unit array data transmission unit, without repeating the private key calculation process. This avoids the waste of computing resources caused by repeatedly calculating the same data, reduces unnecessary calculation time, and allows the coarse-grained calculation core to quickly obtain the private key for subsequent work, effectively improving overall computing efficiency. If the first calculation result and Euler's function value have not been calculated multiple times, the unit outputs these two data to the Boolean processor calculation core, ensuring that the Boolean processor calculation core can perform private key calculation based on the latest data, guaranteeing the accuracy and validity of the private key calculation. By flexibly selecting the output content according to the number of times the data has been calculated, computing resources and time can be saved by calling the pre-stored private key when the data has been calculated multiple times, and the private key calculation can be guaranteed to be based on the correct data when the data has not been calculated multiple times, thereby improving computing efficiency while ensuring the reliability of the calculation results.

[0091] In some embodiments, obtaining a first prime number and a second prime number includes: reading stored first commonly used data, a position code of the first commonly used data, second commonly used data, and a position code of the second commonly used data from the shared memory of the processing unit array; determining a first prime number based on the first commonly used data and the position code of the first commonly used data; and determining a second prime number based on the second commonly used data and the position code of the second commonly used data.

[0092] The following explanation uses a prime number as an example to illustrate how prime numbers are stored using infrequent, frequent, and positional encodings of frequent data, and how prime numbers are determined based on these encodings. This explanation applies to both the first and second prime numbers: If a prime number (e.g., 1024 bits) is obtained via PEA Data Direct Memory Access (PEAData DMA) connected to the processing unit array's shared memory, it can be divided into 16 different combinations of four-bit data that appear repeatedly. During storage, these 16 combinations of four-bit data are stored (occupying 16 × 4 = 64 bits). When storing each four-bit combination, the actual data is not stored; instead, the positional encoding is stored. Since prime numbers store a large amount of consecutive repetitive data, only one positional encoding and the number of repetitions need to be stored, thus reducing the storage space required for data storage.

[0093] In some embodiments, determining the public key and Euler's totient function value based on the first prime number and the second prime number includes: partitioning the first prime number according to the number of bits processed by each processing unit to obtain multiple partitioning results of the first prime number, and partitioning the second prime number to obtain multiple partitioning results of the second prime number; determining the public key and Euler's totient function value based on the multiple partitioning results of the first prime number and the multiple partitioning results of the second prime number.

[0094] In some embodiments, the linear operation performed on the private key during the calculation process using the public key exponent and the Euler's totient function value to obtain a first calculation result may include: dividing the public key exponent and the Euler's totient function value according to the number of bits processed by each processing unit to obtain multiple fragments of the public key prime number and multiple fragments of the Euler's totient function value respectively; and determining the first calculation result based on the multiple fragments of the public key prime number and the multiple fragments of the Euler's totient function value.

[0095] In some embodiments, the Boolean processor core is further configured to: slice the first calculation result and the Euler function value according to the number of bits processed by each Boolean processor, to obtain multiple slices of the first calculation result and multiple slices of the Euler function value, and determine the private key based on the multiple slices of the first calculation result and the multiple slices of the Euler function value.

[0096] In some embodiments, determining the second calculation result based on the data to be encrypted and the public key index may include: dividing the data to be encrypted and the public key index into fragments according to the number of bits processed by each processing unit, to obtain multiple fragments of the data to be encrypted and multiple fragments of the public key index respectively; and determining the second calculation result based on the multiple fragments of the data to be encrypted and the multiple fragments of the public key index.

[0097] In some embodiments, the Boolean processor core is further configured to: slice the second calculation result and the modulus according to the number of bits processed by each Boolean processor, to obtain multiple slices of the second calculation result and multiple slices of the modulus, and determine the private key based on the multiple slices of the second calculation result and the multiple slices of the modulus.

[0098] In some embodiments, determining a third calculation result based on the data to be decrypted and the private key may include: dividing the data to be decrypted and the private key index into fragments according to the number of bits processed by each processing unit, to obtain multiple fragments of the data to be decrypted and multiple fragments of the private key index respectively; and determining a second calculation result based on the multiple fragments of the data to be decrypted and the multiple fragments of the private key index.

[0099] In some embodiments, the Boolean processor core is further configured to: slice the third calculation result and the modulus according to the number of bits processed by each Boolean processor, to obtain multiple slices of the third calculation result and multiple slices of the modulus, and determine the private key based on the multiple slices of the third calculation result and the multiple slices of the modulus.

[0100] For example, the number of bits processed by each processing unit can be the same as the number of bits processed by each Boolean processor.

[0101] In the technical solution provided in this application embodiment, by segmenting the data and then using the segmented data for calculation, the bit depth of the data calculation can be made to match the bit depth of each processing unit in the array. The processing unit can directly perform calculations on the segmented data without additional bit depth adaptation operations, thereby maximizing the hardware performance of each processing unit, reducing resource waste and computational loss caused by data bit depth mismatch, and ensuring that each calculation step can be performed within the optimal bit depth range of the processing unit, thus improving the efficiency of data calculation.

[0102] Some embodiments of this application also provide a hybrid reconfigurable computing chip, which includes a coarse-grained reconfigurable architecture and a fine-grained reconfigurable architecture. The coarse-grained reconfigurable architecture includes a coarse-grained computing core and a processing unit array data transmission unit connected to the coarse-grained computing core. The fine-grained reconfigurable architecture includes a Boolean processor array data transmission unit connected to the processing unit array data transmission unit and a Boolean processor computing core connected to the Boolean processor array data transmission unit.

[0103] A coarse-grained computational core is used to obtain a first prime number and a second prime number, and to determine the public key and Euler's totient function value based on the first prime number and the second prime number; the public key includes the public key exponent and the modulus; linear operations are performed in the private key computation process using the public key exponent and the Euler's totient function value to obtain a first computation result; the first computation result is output to the Boolean processor computational core of the fine-grained reconfigurable architecture in sequence through the data transmission unit of the processing unit array and the data transmission unit of the Boolean processor array.

[0104] The Boolean processor computation core is used to perform structured operations in the private key calculation process using the first calculation result and the Euler function value, and obtains and outputs the private key to the coarse-grained computation core in sequence through the Boolean processor array data transmission unit and the processing unit array data transmission unit.

[0105] This application's embodiments accelerate the computation of the RSA encryption algorithm through architectural design targeting both coarse-grained architecture (CGRA, i.e., coarse-grained reconfigurable architecture) and fine-grained architecture (Boolean Processor, i.e., fine-grained reconfigurable architecture), thereby effectively improving encryption efficiency.

[0106] Figure 5 A schematic diagram of the structure of the hybrid reconfigurable computing chip provided in the fourth embodiment is shown below. Figure 5 As shown, the hybrid reconfigurable computing chip includes a coarse-grained reconfigurable architecture and a fine-grained reconfigurable architecture.

[0107] During chip encryption, in the coarse-grained reconfigurable architecture (CGRAUnit), the system bus can connect to an external processing chip. For example, the system bus can obtain the data to be encrypted from the external processing chip. The data to be encrypted can sequentially pass through hierarchical memory and PEA data direct memory access (PEADataDMA) to reach PEA shared memory. The PEA cross-connect unit outputs the data to be encrypted stored in the PEA shared memory and the public key used to encrypt the data to the CGRA core, so that the PE array in the CGRA core can perform addition and multiplication operations in RSA calculations. For example, the global register files in the CGRA core are used to store temporary configuration / state, and the configuration memory is used to load the hardware logic of the PE array. In this embodiment, the PE array includes PE arrays 0-3. In other embodiments, other numbers of PE arrays may be included, and this embodiment does not limit this. After CGRACore obtains the encrypted data, it can sequentially transmit the encrypted data to the system bus through the PEA cross switch unit, PEA shared memory, PEAData DMA, and hierarchical memory, so that the external processing chip can obtain the encrypted data.

[0108] When the chip decrypts, the system bus, upon receiving the data to be decrypted from the external processing chip, sequentially outputs it to the CGRA core via hierarchical memory, PEAData DMA, PEA shared memory, and PEA crossbar switch unit. The PEA crossbar switch unit can also output the private and public keys stored in the PEA shared memory to the CGRA core, enabling the CGRA core to obtain the decrypted data. The CGRACore can sequentially transmit the decrypted data to the system bus via the PEA crossbar switch unit, PEA shared memory, PEAData DMA, and hierarchical memory, allowing the external processing chip to obtain the decrypted data.

[0109] For example, in a coarse-grained reconfigurable architecture (CGRA Unit), the system bus interacts with hierarchical memory to download or store data (LdORStData), such as the data listed herein, hierarchical memory interacts with PEA Data DMA to exchange PEA data (PEAData), and PEAData DMA interacts with PEA shared memory to exchange PEA data (PEAData), where PEA Data can be the data listed herein.

[0110] In the coarse-grained reconfigurable architecture (CGRAUnit), the computational capabilities of the PEs in the PE array can be configured. PEA Configuration Direct Memory Access (PEAConfiguration DMA) retrieves the PEA configuration (PEACfg) from hierarchical memory. PEAConfiguration DMA transfers PE configuration information (PECfgInfo) to the configuration memory in the CGRA core, enabling the PE configuration information (PECfgInfo) to instruct the computational capabilities of the PEs in the PE array. For example, the first half of the PEs in each PE array can be configured to perform addition calculations, and the second half can be configured to perform linear operations; alternatively, the first half of the PEs in each PE array can be configured to perform prime number linear operations, and the second half can be configured to perform Euler's totient function calculations. Exemplarily, when configuring the computational capabilities of PEs in a PE array, the computational capabilities of PEs at the same location in different PE arrays can be the same or different.

[0111] The computational functionality of bPEs (also known as BPs) in the BP array of the fine-grained reconfigurable architecture (BPAUnit) can also be configured. The BPA configuration unit in the coarse-grained reconfigurable architecture (CGRAUnit) can retrieve the BP configuration (BPCfg) from hierarchical memory and output BPA instructions (BPAInstructions) to the instruction allocation unit in the fine-grained reconfigurable architecture (BPAUnit). The instruction allocation unit then outputs BPA instructions to the BP array, enabling the BP array to configure the computational functionality of the bPEs in the BP array according to the BPA instructions. For example, when configuring the computational functionality of bPEs in the BP array, the computational functionality of BPs at the same location in different BP arrays can be the same or different.

[0112] In the coarse-grained reconfigurable architecture (CGRAUnit), the CPU can acquire CPU data (CPUData) and output CPU initialization information and CPU control information to the PEA interface. Based on the CPU initialization information and CPU control information, the PEA interface outputs PEA initialization information (PEAInitiInfo) and PEA control information (PEACtrlInfo) to the PEA controller. Based on the PEA initialization information and PEA control information, the PEA controller outputs data transmission unit control (DTUCtrl) to the PEA data transmission unit, outputs BP configuration control (BPCfg Control) to the BPA configuration unit, outputs configuration initialization (CfgInit), initialization information (InitInfo), control information (CtrlInfo), and data configuration (DataInfo) to the CGRA core, outputs PEA cross control (PEACBCtrl) to the PEA cross switch unit, outputs PEAData DMA control (PEADDCtrl) to the PEAData DMA, and outputs PEAConfiguration DMA control (PEACDCtrl) to the PEAConfiguration DMA.

[0113] The PEA interface also outputs BP initialization information (BPInit) and BP control information (BPCtrl) to the BPA interface; shared memory initialization information (SMInit) to the BPA shared memory; BPA crossbar initialization information (BPCBInit) to the BPA crossbar unit; BPA initialization information (BPAInit) to the BP array; BPA data transmission control information (BPDTUCtrl) to the BPA data transmission unit; and instruction allocation control information (IAUCtrl) to the instruction allocation unit.

[0114] The BPA data transmission unit receives data (Data To BP, where BPData is BPData) transmitted by the PEA data transmission unit and transmits the data to the BP array. The BPA data transmission unit receives data (PEData, where PEData is Data To PE) transmitted by the BP array and outputs the data to the CGRA core by the PEA data transmission unit.

[0115] The instruction allocation unit receives BPA instructions from the BPA configuration unit, and outputs BPA control (BPACtrls) and BPA instructions to the BP array. The instruction allocation unit also outputs cross-array network control to the cross-array interconnect network.

[0116] BPA shared memory transfers data between the BPA crossbar switch unit and the Boolean processor computing core. The Boolean processor computing core includes an internal interconnect network, BP arrays 0-3, and a cross-array interconnect network. The internal interconnect network is used to interconnect bPEs within a single BP array, and the cross-array interconnect network is used to interconnect bPEs between different BP arrays. For example, BP arrays 0-3 transfer BPA0Data to BPA3Data via the cross-array interconnect network, respectively.

[0117] The hybrid reconfigurable computing chip includes BP Arrays (Boolean Processor Arrays) for fine-grained computation and PEAs (Processing Element Arrays) for coarse-grained computation. This embodiment adds various logical computation functions, including modulo operations and concatenation, to the internal bPEs, thereby enhancing their logical operation capabilities. For the PEs, multiple addition circuits are added to ensure improved addition performance, simplifying the design and reducing redundant energy consumption, thus improving computational energy efficiency.

[0118] In the fine-grained reconfigurable architecture, the Intra-connect Network and Inter-connect Network implement communication between different arrays' bPEs and between bPEs within the same array, respectively. The BPAData Transmission Unit (DTU) is responsible for data communication between the BPA Unit and the CGRA, storing information, and identifying frequently reused data to improve reusability and reduce transmission latency. The InstructionAllocation Unit sends instructions to the bPEs and stores instruction configurations according to the scheduled tasks. BPAShared Memory stores intermediate data and results. In the CGRA Unit, the PEAController is responsible for controlling behavior, the PEA Crossbar is responsible for data transmission, and the PEA Shared Memory is divided into multiple banks for rule-based continuous storage. The PEA Data DMA is responsible for transferring data between the hierarchical memory and the PEAShared Memory, and the PEA Configuration DMA is responsible for configuration data transmission.

[0119] Figure 6The diagram illustrates the RSA-2048 calculation process for some embodiments, where RSA-2048 refers to the RSA encryption algorithm using a key length of 2048 bits. Figure 6 As shown, the RSA-2048 calculation process may include the following steps:

[0120] S601, Perform prime selection: p1024, q1024.

[0121] For example, in prime number selection, the CGRA core selects two 1024-bit prime numbers p1024 and q1024 from the PEA shared memory.

[0122] S602. Perform the modulus number calculation: n2048=p1024×q1024.

[0123] For example, the PE array in the CGRA core can perform modulo calculations, that is, multiplying two selected prime numbers p1024 and q1024 to obtain n2048, where n2048 represents a 2048-bit modulo.

[0124] S603. Perform Euler function: φ(n2048)=(p1024-1)×(q1024-1).

[0125] For example, the PE array in the CGRA core can be used to calculate the Euler's totient function, obtaining the Euler's totient function value φ(n2048).

[0126] S604. Determine the public key (e2048, n2048).

[0127] The public key consists of a 2048-bit public key exponent e (e2048) and a 2048-bit modulus n (n2048). e2048 is coprime to the Euler totient function value φ (n2048).

[0128] S605. Determine the private key: d = e2048 -1 modφ(n2048).

[0129] Here, the private key d is the modular inverse of e with respect to the Euler totient function. That is, the process of obtaining the private key d is: find a number d such that (e × d) mod φ(n2048) = 1. Here, d can be 2048 bits, i.e., d2048.

[0130] S606. Encryption.

[0131] The encrypted data is c2048 = m2048 e2048 modn2048. Where n2048 represents 2048 bits of encrypted data, and m2048 represents 2048 bits of data to be encrypted (also known as the data before encryption).

[0132] S607. Decryption.

[0133] The decrypted data (also known as the data before encryption) m2048 = c2048 d2048 modn2048.

[0134] Each step in S602 to S607 involves linear operations, which can include addition and multiplication. Exponentiation is essentially a form of multiplication. The linear operations in each step S602 to S607 are performed by the PE array.

[0135] Each step from S605 to S607 involves a modulo operation, which is performed by the BP array.

[0136] The first step in RSA computation is to find two large prime numbers, primarily sourced from storage. The second step involves multiplying the two 1024-bit prime numbers; this is a coarse-grained computation requiring numerous arithmetic units. The third step calculates the Euler's totient function, which is the product of two even numbers obtained by subtracting one from each of the 1024-bit prime numbers. The fourth step is to find the public key, primarily through comparison. Since only prime numbers smaller than the Euler's totient function are needed, complex calculations are not required; fine-grained operations and some coarse-grained operations suffice. The fifth step is to calculate the private key from the public key. This involves exponentiation and modulo operations, making this a mixed-grained computation. Finally, the public key is used for encryption, and the private key is used for decryption.

[0137] Therefore, the entire RSA computation process is a coarse-fine granularity computation, which is more compatible with the coarse-fine granularity reconfigurable computation architecture compared to the traditional CGRA.

[0138] In some embodiments, the basic principle of this application embodiment for RSA-2048 computation optimization is to divide 2048 into pieces, and then perform coarse-fine granularity computation with different granularity architectures, giving full play to the advantages of spatiotemporal partitioning and parallel computation, and using a pipelined approach to accelerate computation.

[0139] The calculation of RSA-2048 requires multiple 1024-bit and 2048-bit data processing operations, while the PEs and bPEs in this embodiment are both 32-bit.

[0140] Figure 7 This is a schematic diagram illustrating the process of a computation method for RSA on a hybrid reconfigurable computing chip, provided for some embodiments.

[0141] This application's embodiments employ a data fragmentation method, dividing 1024 (2 10 The data is divided into 32 (2) bits. 5 ) 32 (2 5 The 2048-bit data is divided into 64 32-bit data segments. These multiple 32-bit segments are then distributed among the four Processing Areas (PEs) and their corresponding 32-bit segments (bPEs) for processing, based on scheduling information. For example, in... Figure 7 In ①, multiple bPE processing fragments (Par) tio n) data.

[0142] The calculation begins with the selection of prime numbers. In PEA Shared Memory, storage space is reduced by adding position encoding to 16 4-bit commonly used data stores, thus representing the entire 1024-bit or 2048-bit data. For example, in... Figure 7 In section ②, different commonly used data are stored in different storage units (Banks).

[0143] PEAShared Memory distributes this data to corresponding PEs for modulus calculation. Within each PE, half of the PEs perform multiplication operations using a multiplication tree, while the other half calculates the Euler's totient function. Therefore, parallel calculation of the modulus and Euler's totient function speeds up computation. For example, in... Figure 7 In section ③, taking PEA0-3 as an example, the upper part PE is used to calculate the modulus, and the lower part PE is used to calculate the Euler totient function value.

[0144] After the modulus and Euler's totient function values ​​have been calculated, the public key prime number e is generated by searching for prime numbers based on the stored Euler's totient function values ​​with the help of the compiler. For example, bPE is used to search for the public key prime number e.

[0145] The BP array and PE array work together to perform modulo and multiplication calculations to obtain the private key. In this embodiment, encryption or decryption is determined under the action of a control signal. Both encryption and decryption utilize PEs and bPEs to perform modulo calculations of the ciphertext exponent and the plaintext exponent.

[0146] In this way, fast computation of RSA-2048 is achieved through fragmentation and coarse-grained parallel computing operations, and the flexibility of coarse-grained system computation is also higher than that of traditional CGRA.

[0147] This application proposes a computation method for RSA encryption computation tasks using a coarse-fine granularity reconfigurable computing architecture. By separating coarse and fine granularity computation mechanisms and making architectural improvements to the RSA encryption algorithm, the computation speed of RSA is increased. This allows the architecture to fully utilize parallelism to improve computation speed and reduce energy consumption in RSA encryption computation, thereby further improving energy efficiency.

[0148] In one exemplary embodiment, Figure 8 This is a schematic diagram of the structure of a computer device provided in some embodiments. The computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is used for exchanging information between the processor and external devices. The communication interface of the computer device is used for wired or wireless communication with external terminals. Wireless communication can be implemented through Wireless Fidelity (WIFI), mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements an encryption / decryption calculation method. The display unit of the computer device is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0149] The processor may include a hybrid reconfigurable computing chip connected to an external processing chip and a hybrid reconfigurable computing chip connected to an external processing chip.

[0150] Those skilled in the art will understand that Figure 8The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0151] For example, a computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the methods described in any of the above embodiments. The processor may include a hybrid reconfigurable computing chip connected to an external processing chip and a hybrid reconfigurable computing chip connected to an external processing chip.

[0152] In some embodiments, a computer device may include one or more of the following: a server, a mobile phone, a tablet computer, a computer with transceiver capabilities, a handheld computer, a desktop computer, a personal digital assistant, a portable media player, a smart speaker, a navigation device, a smartwatch, smart glasses, a smart necklace and other wearable devices, a pedometer, a digital TV, a virtual reality (VR) device, an augmented reality (AR) device, a device in industrial control, a device in self-driving, a device in remote medical surgery, a device in a smart grid, a device in transportation safety, a device in a smart city, a device in a smart home, a vehicle, an in-vehicle device, an in-vehicle module, etc.

[0153] In one embodiment, a computer-readable storage medium is provided, wherein a computer program, when executed by a processor, implements the steps of the method provided in any of the above embodiments.

[0154] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method provided in any of the above embodiments.

[0155] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the methods described above.

[0156] The chip, functional modules, or functional units in any embodiment of this application may include integrations of one or more of the following: general-purpose processors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), central processing units (CPUs), graphics processing units (GPUs), embedded neural network processing units (NPUs), controllers, microcontrollers, microprocessors, programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0157] The memory or computer-readable storage medium in any embodiment of this application may include at least one of non-volatile memory and volatile memory. Non-volatile memory includes integration of one or more of the following: Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Ferromagnetic Random Access Memory (FRAM), Flash Memory, Magnetic Surface Memory, Optical Disc, Compact Disc Read-Only Memory (CD-ROM), Magnetic Tape, Floppy Disk, Flash Memory, Optical Memory, High-Density Embedded Non-Volatile Memory, Resistive Random Access Memory (ReRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Graphene Memory, Volatile Memory, etc. Volatile memory includes one or more of the following: Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0158] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0159] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An encryption / decryption calculation method, characterized in that, A coarse-grained computing core is applied to a coarse-grained reconfigurable architecture in a hybrid reconfigurable computing chip. The coarse-grained reconfigurable architecture further includes a processing unit array data transmission unit connected to the coarse-grained computing core. The hybrid reconfigurable computing chip also includes a fine-grained reconfigurable architecture, which includes a Boolean processor array data transmission unit connected to the processing unit array data transmission unit and a Boolean processor computing core connected to the Boolean processor array data transmission unit. The method includes: Obtain a first prime number and a second prime number, and determine the public key and Euler's totient function value based on the first prime number and the second prime number; the public key includes the public key exponent and the modulus; A first calculation result is obtained by performing linear operations in the private key calculation process using the public key exponent and the Euler totient function value; The first calculation result is sequentially output to the Boolean processor computing core of the fine-grained reconfigurable architecture through the processing unit array data transmission unit and the Boolean processor array data transmission unit, so that the Boolean processor computing core uses the first calculation result and the Euler function value to perform structured operations in the private key calculation process, and obtains and sequentially outputs the private key to the coarse-grained computing core through the Boolean processor array data transmission unit and the processing unit array data transmission unit; wherein, the public key and the private key are used for encryption and decryption calculations.

2. The method according to claim 1, characterized in that, The coarse-grained reconfigurable architecture further includes a processing unit array connected to the coarse-grained computing core sharing memory, and the method further includes: The data to be encrypted is obtained from the shared memory of the processing unit array; The second calculation result is determined based on the data to be encrypted and the public key index; The second calculation result and the modulus are sequentially output to the Boolean processor calculation core through the processing unit array data transmission unit and the Boolean processor array data transmission unit, so that the Boolean processor calculation core determines and sequentially outputs encrypted data to the coarse-grained calculation core through the Boolean processor array data transmission unit and the processing unit array data transmission unit based on the second calculation result and the modulus.

3. The method according to claim 1 or 2, characterized in that, The coarse-grained reconfigurable architecture further includes a processing unit array connected to the coarse-grained computing core sharing memory, and the method further includes: The data to be decrypted is obtained from the shared memory of the processing unit array; Based on the data to be decrypted and the private key, determine the third calculation result; The third calculation result and the modulus are sequentially output to the Boolean processor calculation core through the processing unit array data transmission unit and the Boolean processor array data transmission unit, so that the Boolean processor calculation core determines and sequentially outputs the decrypted data to the coarse-grained calculation core through the Boolean processor array data transmission unit and the processing unit array data transmission unit based on the third calculation result and the modulus.

4. The method according to claim 1 or 2, characterized in that, The coarse-grained reconfigurable architecture further includes a processing unit array configured with direct memory access connected to the coarse-grained computing core, and the method further includes: Obtain the processing unit array configuration information of the direct memory access output of the processing unit array configuration; the processing unit array configuration information is used to indicate the computing function of each processing unit in the processing unit array of the coarse-grained computing core. Based on the processing unit array configuration information, configure the computational functions of each processing unit in the coarse-grained computation core's processing unit array.

5. The method according to claim 4, characterized in that, During the stage of determining the modulus and the Euler's totient function value, the acquired processing unit array configuration information is used to instruct that half of the processing units in the coarse-grained calculation core are used to calculate the modulus and the other half of the processing units are used to calculate the Euler's totient function value.

6. The method according to claim 1 or 2, characterized in that, The Boolean processor array data transmission unit is further configured to, in the case of the first calculation result and the Euler's function value obtained, if the first calculation result and the Euler's function value have been calculated multiple times, output a pre-stored private key to the coarse-grained calculation core through the processing unit array data transmission unit; If the first calculation result and the Euler's totient function value have not been calculated multiple times, then the first calculation result and the Euler's totient function value are output to the Boolean processor calculation core.

7. The method according to claim 1 or 2, characterized in that, The coarse-grained reconfigurable architecture further includes a processing unit array sharing memory with the coarse-grained computation core, and the acquisition of the first prime number and the second prime number includes: Read the first commonly used data, the position code of the first commonly used data, the second commonly used data, and the position code of the second commonly used data stored in the shared memory of the processing unit array; The first prime number is determined based on the first commonly used data and the position code of the first commonly used data; The second prime number is determined based on the second commonly used data and the position encoding of the second commonly used data.

8. The method according to claim 1 or 2, characterized in that, The step of determining the public key and Euler's totient function value based on the first prime number and the second prime number includes: Based on the number of bits processed by each processing unit, the first prime number is sliced ​​to obtain multiple slice results of the first prime number, and the second prime number is sliced ​​to obtain multiple slice results of the second prime number; The public key and the Euler totient function value are determined based on multiple sharding results of the first prime number and multiple sharding results of the second prime number.

9. A hybrid reconfigurable computing chip, characterized in that, The hybrid reconfigurable computing chip includes a coarse-grained reconfigurable architecture and a fine-grained reconfigurable architecture; the coarse-grained reconfigurable architecture includes a coarse-grained computing core and a processing unit array data transmission unit connected to the coarse-grained computing core; the fine-grained reconfigurable architecture includes a Boolean processor array data transmission unit connected to the processing unit array data transmission unit and a Boolean processor computing core connected to the Boolean processor array data transmission unit. The coarse-grained computation core is used to obtain a first prime number and a second prime number, and to determine the public key and Euler's totient function value based on the first prime number and the second prime number; the public key includes a public key exponent and a modulus; linear operations are performed in the private key computation process using the public key exponent and the Euler's totient function value to obtain a first computation result; the first computation result is output to the Boolean processor computation core of the fine-grained reconfigurable architecture sequentially through the processing unit array data transmission unit and the Boolean processor array data transmission unit; The Boolean processor computing core is used to perform structured operations in the private key calculation process using the first calculation result and the Euler function value, and to obtain and output the private key to the coarse-grained computing core in sequence through the Boolean processor array data transmission unit and the processing unit array data transmission unit.

10. A computer device, characterized in that, The computer device includes the hybrid reconfigurable computing chip as described in claim 9.

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