A chip circuit architecture and method for short-term memory when power is off.

Abstract

This invention discloses a chip circuit architecture for short-time power-off memory, relating to the field of timing chip integrated circuit design. It includes: an external power supply module powered by an external power supply VIN, which outputs a communication signal CLK, set as the minimum pulse time for chip circuit architecture recognition and processing; an internal power supply module powered by an internal power supply VDD, connected to the external power supply module and receiving the communication signal CLK; and a diode, through which the external power supply VIN supplies power to the internal power supply VDD, enabling the chip to maintain its timing state after power failure, providing short-time storage capability after power failure, avoiding intermediate states, and reducing power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of time chip integrated circuit design, and in particular to a chip circuit architecture and method for short-time memory after power-off. BACKGROUND

[0002] During battery replacement or collision, the battery is short-time loose, and the corresponding chip is short-time power-off. The chip needs to have short-time storage capability after power-off to maintain the timing state. Figure 1 As shown in the figure, VIN is an external power supply, C1 is an input capacitor; X1 is a timing clock circuit, X2 is a logic control circuit, X3 is a clock output circuit, X4 is a register circuit; Y1 is a crystal oscillator. In the original design, after the external power supply of the chip is disconnected, VIN is quickly powered off, and the short-time memory function after power-off cannot be realized. Increasing C1 is also not desirable. In actual application, increasing C1 will increase the cost, and the large size is not conducive to product design. Increasing C1 only has a limited effect on increasing the time of power-off memory. SUMMARY

[0003] In view of the above problems existing in the field of time chip integrated circuit design, the present application provides a chip circuit architecture and method for short-time memory after power-off, which can continue to maintain the timing state after the chip is powered off, has short-time storage capability after power-off, avoids the intermediate state, and reduces power consumption.

[0004] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0005] A chip circuit architecture for short-time memory after power-off, comprising:

[0006] An external power supply module, which is powered by an external power supply VIN, and outputs a communication signal CLK, wherein the communication signal CLK is set as the minimum pulse time recognized and processed by the chip circuit architecture;

[0007] An internal power supply module, which is powered by an internal power supply VDD, and is connected with the external power supply module and receives the communication signal CLK;

[0008] A diode, through which the external power supply VIN supplies power to the internal power supply VDD.

[0009] According to an aspect of the present application, the external power supply module comprises a timing clock circuit, a logic control circuit and a clock output circuit connected in sequence, the timing clock circuit is connected to the external power supply VIN for power supply, and the clock output circuit is grounded and outputs clock information to the outside.

[0010] According to an aspect of the present application, the timing clock circuit, the logic control circuit and the clock output circuit are connected with the internal power supply module through an inverter.

[0011] According to one aspect of the present application, the logic control circuit controls the storage and clearing of internal information of the on-chip power supply module, and the clock output circuit reads the internal information of the on-chip power supply module and outputs.

[0012] According to one aspect of the present application, the off-chip power supply module further comprises a crystal oscillator, which is connected in parallel with the timing clock module, and the timing clock module drives the crystal oscillator to generate a communication signal CLK.

[0013] According to one aspect of the present application, the off-chip power supply module further comprises a filter capacitor, one end of which is connected to the off-chip power supply VIN, and the other end of which is grounded.

[0014] According to one aspect of the present application, the on-chip power supply module comprises a register circuit, which is connected to the off-chip power supply module through an inverter, and the register circuit is connected to the on-chip power supply VDD and grounded.

[0015] According to one aspect of the present application, the on-chip power supply module further comprises a register power supply capacitor, which is connected in parallel with the register circuit, one end of the register power supply capacitor is connected to the on-chip power supply VDD, and the other end of the register power supply capacitor is grounded.

[0016] According to one aspect of the present application, when the off-chip power supply VIN is greater than the on-chip power supply VDD, the VIN charges the on-chip power supply VDD through a diode; when the off-chip power supply VIN is less than the on-chip power supply VDD, the diode is cut off, and the register power supply capacitor supplies power to the register circuit.

[0017] A method for power-off short-time memory, the off-chip power supply module comprises a crystal oscillator, a timing clock circuit, a logic control circuit, and a clock output circuit, the on-chip power supply module comprises a register circuit and a register power supply capacitor, and further comprises:

[0018] The off-chip power supply VIN normally supplies power, the off-chip power supply VIN supplies power to the on-chip power supply VDD through a diode, and the on-chip power supply VDD supplies power to the register circuit and the register power supply capacitor;

[0019] The timing clock circuit drives the crystal oscillator to generate a standard clock, the logic control circuit controls the storage and clearing of internal information of the register circuit through a generated control signal, and the clock output circuit reads the internal information of the register circuit and outputs;

[0020] The off-chip power supply VIN is disconnected, the register power supply capacitor supplies power to the register circuit, until the off-chip power supply VIN resumes power supply.

[0021] The advantages of the embodiment of the present application include an off-chip power supply module, which is powered by an off-chip power supply VIN, outputs a communication signal CLK, and the communication signal CLK is a clock signal with a very small duty cycle; an on-chip power supply module, which is powered by an on-chip power supply VDD, is connected with the off-chip power supply module and receives the communication signal CLK; and a diode, which supplies power to the on-chip power supply VDD through the diode, can continue to maintain a timing state after the chip is powered off, has a short-time storage capability after power-off, avoids an intermediate state, and reduces power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0023] Figure 1 A circuit structure diagram of a prior art chip circuit architecture and method for short-time memory after power-off according to the present application;

[0024] Figure 2 A structural schematic diagram of a chip circuit architecture and method for short-time memory after power-off according to the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort belong to the scope of protection of the present application.

[0026] Embodiment one:

[0027] As shown in Figure 2 A chip circuit architecture for short-time memory after power-off includes an off-chip power supply module, an on-chip power supply module, and a diode D1. The off-chip power supply module is powered by an off-chip power supply VIN and grounded, the on-chip power supply module is powered by an on-chip power supply VDD and grounded, the off-chip power supply module outputs a communication signal CLK to the on-chip power supply module, the communication signal CLK is a clock signal with a very small duty cycle, and is set as the minimum pulse time for chip circuit architecture identification and processing. The off-chip power supply VIN is connected with the anode of the diode D1, the on-chip power supply VDD is connected with the cathode of the diode D1, and the off-chip power supply VIN supplies power to the on-chip power supply VDD through the diode D1.

[0028] The off-chip power supply module includes a filter capacitor C1, one end of which is connected to the off-chip power supply VIN, and the other end of which is grounded.

[0029] The off-chip power supply module further includes a timing clock circuit X1, a logic control circuit X2, a clock output circuit X3 and a crystal oscillator Y1. The timing clock circuit X1 is connected to the off-chip power supply VIN and connected to the logic control circuit X2, the logic control circuit X2 is connected to the clock output circuit X3, and the clock output circuit X3 is grounded. The crystal oscillator Y1 is connected in parallel with the timing clock circuit X1, and the timing clock circuit X1 drives the crystal oscillator Y1 to generate a communication signal CLK.

[0030] The off-chip power supply module includes a register circuit X4 and a register power supply capacitor C2, one end of the register circuit X4 is powered by the on-chip power supply VDD, the other end of the register circuit X4 is grounded, and the register power supply capacitor C2 is connected in parallel with the register circuit X4.

[0031] Further comprising inverters I1, I2, I3, I4, I5 and I6, the timing clock circuit X1 is connected to the positive electrode of the inverter I1, the negative electrode of the inverter I1 is connected to the positive electrode of the inverter I4, the negative electrode of the inverter I4 is connected to the register circuit X4; the logic control circuit X2 is connected to the positive electrode of the inverter I2, the negative electrode of the inverter I2 is connected to the positive electrode of the inverter I5, the negative electrode of the inverter I5 is connected to the register circuit X4; the register circuit X4 is connected to the positive electrode of the inverter I6, the negative electrode of the inverter I6 is connected to the positive electrode of the inverter I3, and the negative electrode of the inverter I3 is connected to the clock output circuit.

[0032] When the off-chip power supply VIN is normally powered, that is, the off-chip power supply VIN is greater than the on-chip power supply VDD, the off-chip power supply VIN supplies power to the on-chip power supply VDD through the diode D1, the on-chip power supply VDD supplies power to the register circuit X4, and at the same time the register power supply capacitor C2 starts to charge. The timing clock circuit X1 drives the crystal oscillator Y1 to generate a communication signal CLK and inputs the register circuit X4, the communication signal CLK output by the timing clock circuit X1 is a clock signal with a very small duty cycle, as long as the period of the communication signal CLK is unchanged, it does not affect the timing function and the timing accuracy. The logic control circuit X2 generates a control signal to control the storage, zeroing and the like of the internal information of the register circuit X4. The clock output circuit X3 reads the internal information of the register circuit X4 and outputs.

[0033] When the external power supply VIN is disconnected, such as during battery replacement (i.e., VIN is lower than the internal power supply VDD), diode D1 is cut off. Due to the power consumption of the entire circuit, especially the crystal oscillator driver and output driver, the external power supply momentarily drops to 0V. However, the static power consumption of register circuit X4 is very small, almost zero. The charge stored in register power supply capacitor C2 can maintain the information stored in register circuit X4 for a long time. Furthermore, because the duty cycle of communication signal CLK is extremely small, CLK can continue to maintain a low level during the power outage of external voltage VIN, avoiding intermediate voltage fluctuations and reducing power consumption. When the external voltage VIN is restored, the timing resumes normal operation without the need for time readjustment.

[0034] The advantages of this invention are as follows: It includes an external power supply module, which is powered by an external power supply VIN and outputs a communication signal CLK, which is a clock signal with a very small duty cycle; an internal power supply module, which is powered by an internal power supply VDD and is connected to the external power supply module, and receives the communication signal CLK; and a diode, which supplies power from the external power supply VIN to the internal power supply VDD, enabling the chip to continue its timing state after power failure, providing short-term storage capability after power failure, avoiding intermediate states, and reducing power consumption.

[0035] Example 2:

[0036] like Figure 2 As shown, a method for short-term power-off memory is implemented based on the chip circuit architecture for short-term power-off memory described in Embodiment 1. It includes:

[0037] S1: External power supply VIN is powered normally. External power supply VIN supplies power to internal power supply VDD through diode D1. Internal power supply VDD supplies power to register circuit X4 and register power supply capacitor C2.

[0038] S2: The timing clock circuit X1 drives the crystal oscillator Y1 to generate a communication signal CLK and inputs it into the register circuit X4. The logic control circuit X2 controls the storage and clearing of information inside the register circuit X4 through the generated control signal. The clock output circuit X3 reads the information inside the register circuit X4 and outputs it.

[0039] S3: When the external power supply VIN is disconnected, the communication signal CLK remains low, and the register power supply capacitor C2 supplies power to the register circuit X4 until the external power supply VIN is restored.

[0040] The application has the advantages that: the off-chip power supply module is powered by the off-chip power supply VIN, the off-chip power supply module outputs the communication signal CLK, the communication signal CLK is a clock signal with a very small duty cycle; the on-chip power supply module is powered by the on-chip power supply VDD, the on-chip power supply module is connected with the off-chip power supply module and receives the communication signal CLK; the diode is used for supplying power from the off-chip power supply VIN to the on-chip power supply VDD, so that the timing state can be maintained after the chip is powered off, the short-time storage capability after power-off is achieved, the intermediate state is avoided, and the power consumption is reduced.

[0041] The above merely provides a specific implementation of the application, but the protection scope of the application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the application, which should be covered by the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. A chip circuit architecture for power-off short-term memory, characterized by, The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module.

2. The power-off short-term memory chip circuit architecture of claim 1, wherein, The application relates to a chip power supply module.

3. The power-off short-term memory chip circuit architecture of claim 2, wherein, The application relates to a chip power supply module.

4. The power-off short-term memory chip circuit architecture of claim 3, wherein, The application relates to a chip power supply module.

5. The power-off short-term memory chip circuit architecture of claim 2, wherein, The application relates to a chip power supply module.

6. The power-off short term memory chip circuit architecture of claim 1, wherein, The application relates to a chip power supply module.

7. A method for power-off short-time memory based on the chip circuit structure of claim 1, characterized in that, The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. The application relates to a chip power supply module. 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