Chip link signal quality evaluation method, computer device and storage medium

Abstract

The application provides a chip link signal quality evaluation method, a computer device and a storage medium. The method comprises the following steps: obtaining a parameter file of a chip design, analyzing the parameter file, modeling according to parameters extracted from the parameter file, obtaining a chip model, and obtaining a link trace path from the chip model; analyzing the geometric shape of the link according to the chip model, creating a simplified equivalent transmission line model for signal link paragraphs distributed on each layer of the chip model, and calculating the unit length resistance, unit length distributed capacitance, unit length distributed inductance, signal voltage and signal current of the equivalent transmission line model of each paragraph; calculating the S parameter matrix of the entire transmission link according to the signal link distribution of each layer of the chip model and the S parameter matrix of the equivalent transmission line model of each layer of the chip model, and correcting and evaluating the link signal quality. The computer device and the storage medium can realize the above method. The application can quickly realize the evaluation of the link signal quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, in particular, to a chip link signal quality evaluation method, and a computer device and a computer readable storage medium for implementing the method. BACKGROUND

[0002] With the development of chip technology, three-dimensional chips have been widely used, and the design efficiency of three-dimensional chips is increasingly valued by researchers. The three-dimensional chip design process involves multiple links. The functional circuit behavior of the three-dimensional chip can be described by a language such as Verilog or HDL, and then physical design is performed after gate level, circuit and synthesis. When performing circuit layer behavior and performance evaluation, it can be realized through open source circuit simulation tools and engines. After the physical design is completed, the performance of the signal link can be verified by the post-simulation tool to determine whether the design target is achieved.

[0003] However, in the physical design stage of the chip, there is still a lack of a fast signal link quality evaluation method. The physical design stage of the chip includes floor planning, placement, global routing, detail routing and other sub-stages, and there is a strong coupling between each sub-stage. The current mainstream electronic design automation (EDA) tool can only support the design automation of circuit logic connectivity, and does not have signal quality calculation or evaluation under signal link connectivity. After a long design stage and finally outputting the design layout for simulation verification, if it is found that the quality of the signal link cannot meet the design target, it will be difficult to repair by patching, and often the entire physical design process needs to be overturned: adjusting the layout planning of the chip function board, adjusting the layout or placement coordinates of a module or several modules, tilting the wiring resources to the important signal link with poor performance, and preferentially wiring the important signal link to optimize the signal link performance target by shortening the wire length.

[0004] However, the re-design of the physical design stage for repairing the quality of the important signal link will result in a substantial increase in design cost and a substantial extension of the research and development cycle. Since the circuit simulation tool in the previous stage is a circuit abstraction level tool, it cannot evaluate the signal attenuation caused by the proximity of the signal link wire in the physical design, and the later simulation tool cannot output the overall design layout required as input by the later simulation tool when exploring the scheme in the physical design several sub-stages. Therefore, the current circuit simulation tool or later overall simulation tool cannot meet the urgent need for signal link quality evaluation in the physical design stage, and the usual practice is to manually review and evaluate by experienced engineers, but this method will result in low design efficiency and increase the design cost of the chip. SUMMARY

[0005] A first object of the present application is to provide a chip link signal quality evaluation method capable of quickly evaluating link signal quality.

[0006] A second object of the present application is to provide a computer device implementing the above chip link signal quality evaluation method.

[0007] A third object of the present application is to provide a readable storage medium implementing the above chip link signal quality evaluation method.

[0008] To achieve the first object of the present application, the chip link signal quality evaluation method provided by the present application comprises: obtaining a parameter file of a chip design, parsing the parameter file, modeling according to parameters extracted from the parameter file, obtaining a chip model, and obtaining a link routing path from the chip model; analyzing the geometry of the link according to the chip model, and creating a simplified equivalent transmission line model for signal link paragraphs distributed on each layer of the chip model; calculating the unit length resistance, unit length distributed capacitance, and unit length distributed inductance of the equivalent transmission line model of each paragraph, solving the Telegrapher equation by solving the Helmholtz equation, thereby solving the signal voltage and signal current of the equivalent transmission line model of each paragraph, thereby solving the S parameters of the equivalent transmission line model of each paragraph, converting into a T parameter matrix to integrate and calculate to obtain an overall T parameter matrix, converting into an S parameter matrix of the entire transmission link through the S parameter T parameter conversion relationship, modifying the S parameter matrix of the entire transmission link based on the number of corner nodes and the number of through holes passing through each paragraph, and determining the link signal quality of the chip based on the modified S parameter matrix of the entire transmission link.

[0009] As can be seen from the above scheme, after obtaining the parameter file, the chip model is constructed and the routing path is extracted, a simplified equivalent transmission line model is created for signal link paragraphs distributed on each layer of the chip model, and then the Telegrapher equation is solved by solving the Helmholtz equation, thereby solving the signal voltage and signal current of the equivalent transmission line model of each paragraph, thereby solving the S parameters of the equivalent transmission line model of each paragraph, converting into a T parameter matrix to integrate and calculate to obtain an overall T parameter matrix, converting into an S parameter matrix of the entire transmission link through the S parameter T parameter conversion relationship, and determining the link signal quality of the chip after modifying the S parameter matrix. The present application can obtain the S parameter matrix of the entire transmission link based on the simplified equivalent transmission line model and through simple calculation, and can quickly judge the link signal quality of the chip.

[0010] In addition, since the application also corrects the S parameter matrix of the entire transmission link based on the number of inflection points and the number of through holes of each section, the S parameter matrix of the entire transmission link can be calculated more accurately, and the accuracy of the link signal quality determination is improved.

[0011] A preferred scheme is that when correcting the S parameter matrix of the entire transmission link, the attenuation coefficient is calculated according to the number of inflection points and the number of through holes of each section, and the S parameter matrix of the entire transmission link is corrected based on the attenuation coefficient.

[0012] Therefore, the corrected S parameter matrix can be quickly calculated by calculating the attenuation coefficient, and the efficiency of the link signal quality of the chip is higher.

[0013] A further scheme is that the attenuation coefficient is obtained by calculating a preset function, and the preset function is: wherein k is a preset factor number, X i , X j are independent variables, β0, β i , β ii , β ij are parameters determined by measurement, and ε is a preset error term.

[0014] Therefore, the calculation formula of the attenuation coefficient is a low-order operation, and the calculation of the attenuation coefficient can be completed in a short time, so that the efficiency of the link signal quality determination is very high.

[0015] A further scheme is that when calculating the unit length resistance, unit length distributed capacitance, unit length distributed inductance, signal voltage and signal current of the equivalent transmission line model of each section, a calculation formula of not more than two orders is used for calculation.

[0016] Therefore, since the parameters such as the unit length resistance of the equivalent transmission line model of each section are calculated, a low-order formula is used for calculation, avoiding complex operation process and high operation efficiency.

[0017] A further scheme is that when calculating the S parameter matrix of the entire transmission link, the S parameter matrix of the equivalent transmission line model of each section is calculated, and the S parameter matrix of the equivalent transmission line model of each section is merged one by one through the T parameter matrix, so as to calculate the S parameter matrix of the entire transmission link.

[0018] Therefore, by calculating the S parameter matrix of the equivalent transmission line model of each section and merging the S parameter matrix of the equivalent transmission line model of each section one by one through the T parameter matrix, the S parameter matrix of the entire transmission link can be quickly calculated in a simple way.

[0019] Further, when calculating the signal voltage and the signal current of the equivalent transmission line model of each section, the telegraph equation is applied to calculate the signal voltage and the signal current of the equivalent transmission line model of each section.

[0020] Since the calculation of the telegraph equation is a low-order calculation, when calculating the signal voltage and the signal current of the equivalent transmission line model of each section, a complex calculation method does not need to be applied, and the overall operation efficiency can be improved.

[0021] Further, before obtaining the parameter file of the chip design, the parameters required for calculation are extracted through the physical design interface and assembled into a parameter file.

[0022] Further, when modeling according to the parameters extracted from the parameter file, the metal layer and the dielectric layer required to be determined for chip link signal quality evaluation calculation are restored.

[0023] Therefore, by determining the metal layer and the dielectric layer of the chip, the number of corner nodes and the number of through holes of the equivalent transmission line model of each section can be accurately calculated, which is beneficial to subsequent correction calculation.

[0024] To achieve the second purpose, the computer device provided by the application comprises a processor and a memory, the memory stores a computer program, and the computer program realizes each step of the chip link signal quality evaluation method when executed by the processor.

[0025] To achieve the third purpose, the storage medium provided by the application stores a computer program, and the computer program realizes each step of the chip link signal quality evaluation method when executed by the processor. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a flow chart of the chip link signal quality evaluation method embodiment of the application.

[0027] Figure 2 is a structural schematic diagram of a chip model in the chip link signal quality evaluation method embodiment of the application.

[0028] Figure 3 is a schematic diagram of an equivalent transmission line model of a section in the chip link signal quality evaluation method embodiment of the application.

[0029] Figure 4 is a simulation diagram of the S matrix parameters calculated in the chip link signal quality evaluation method embodiment of the application.

[0030] The application will be further described below in combination with the drawings and embodiments. DETAILED DESCRIPTION

[0031] The chip link signal quality evaluation method of the present application is used to evaluate the link signal quality of a chip, and is mainly applicable to the link signal quality evaluation of chips and advanced packages. In particular, in the physical design stage, the method of the present application can quickly analyze whether the link design of the chip has quality defects, thereby avoiding processing after the chip design is completed. The method of the present application can be implemented on a computer device having a processor and a memory, which is a readable storage medium of the present application. The memory stores a computer program, and the computer program can implement the above-mentioned chip link signal quality evaluation method when executed by the processor.

[0032] Embodiment of the chip link signal quality evaluation method:

[0033] Referring to Figure 1 , the embodiment first performs step S1, extracts the required parameters through the physical design interface, and assembles them into a parameter file. For example, the parameter file is a parameter file in JSON format, and the parameters of the parameter model include model size units, model layer model information, signal link node definition information, signal link path definition information, and definition of the frequency point of interest, etc. The model size units can be nm, pm, mm, etc. The information of the model layer model can include the layer name, layer thickness, material characteristics (conductor / dielectric), electrical conductivity (S / m), relative dielectric constant, and loss tangent, etc. The signal link node definition information can include the X-axis coordinate of the node, the Y-axis coordinate of the node, and the layer where the node is located. The signal link path definition information includes the path name, the trace width, and the node list. The definition information of the frequency point of interest can include the frequency unit and the frequency point list, etc. Of course, the parameters of the parameter file can be flexibly adjusted according to actual conditions.

[0034] Then, step S2 is performed, and the received parameter file is parsed by the evaluation operation engine. For example, inter-process communication can be performed in a single computer local deployment mode, or the parameter file can be received based on the Webservice call of the cloud architecture. The parameter file is the data attachment of the Webservice POST method.

[0035] Next, step S3 is performed, and the chip model is created according to the parameters extracted by parsing the parameter file, and the metal layer and dielectric layer related to the link quality evaluation calculation are restored. For example, as shown in Figure 2 , the chip has three metal layers, namely M1, M2 and M3. The first via layer V1 is formed between the first metal layer M1 and the second metal layer M2, and the second via layer V2 is formed between the second metal layer M2 and the third metal layer M3.

[0036] Then, step S4 is performed, and the signal link trace path is extracted according to the chip model created in step S3. For example, referring to Figure 2The first trace segment 11 on the first metal layer M1 is named P1, the second trace segment 12 on the second metal layer M2 is named P2, the third trace segment 13 on the third metal layer M3 is named P3, the first via 14 connecting the first metal layer M1 and the second metal layer M2 is named P4, the second via 15 connecting the second metal layer M2 and the third metal layer M3 is named P5, and so on.

[0037] Next, step S5 is performed, and the link geometry of the chip is analyzed according to the information of the chip model, and a simplified equivalent transmission line model is created for the signal link segments distributed in each layer of the chip model. For example, the information of the simplified equivalent transmission line model created for the signal link segments of each layer is shown in Table 1.

[0038] Table 1

[0039]

[0040] The equivalent transmission line model of a certain segment is shown in Figure 3 , the length of the equivalent transmission line model 21 of the segment is l, the line width is w, and the line height is t. In addition, the total number of vias through which the entire transmission link passes is calculated to be M according to the equivalent transmission line model.

[0041] Then, step S6 is performed, and the unit length resistance, unit length capacitance, unit length distributed inductance, signal voltage, and signal current of the simplified segment transmission line model need to be calculated. First, the unit length resistance of the transmission line model of each simplified segment is calculated, and specifically, the unit length resistance of the transmission line model of a certain segment is calculated using the following formula:

[0042] (Formula 1)

[0043] wherein is the resistivity, which can be obtained by the conductivity of the parameters, and the resistivity and the conductivity are inversely related, and l, t, and w are the length, line width, and line height of the equivalent transmission line model, respectively. Through the above formula, the unit length resistance of each segment model can be calculated in turn, and is respectively recorded as R1, R2,..., and Rn.

[0044] In addition, the unit length distributed capacitance of the transmission line model of each simplified segment is calculated, and specifically, the following formula is used for calculation:

[0045] (Formula 2)

[0046] wherein h is the thickness of the dielectric layer, is the relative dielectric constant, is the vacuum permittivity. In addition, the edge field effect of the transmission link model conductor has been considered in Equation 2. Through the above equations, the unit length capacitance of each section model can be calculated in turn, and are denoted as C1, C2...Cn, respectively.

[0047] Then, the unit length distributed inductance of each simplified section transmission line model is calculated, and specifically, the following equation is used for calculation:

[0048] (Equation 3)

[0049] where is the vacuum permeability. Through the above equations, the unit length distributed inductance of each section model can be calculated in turn, and are denoted as L1, L2...Ln, respectively.

[0050] Next, the unit length dielectric conductance of each simplified section transmission line model is calculated, and the following equation is used for calculation:

[0051] (Equation 4)

[0052] where C is the unit length distributed capacitance obtained by calculation through Equation 2, is the loss tangent of the parameter file, is the relative permittivity. Through the above equations, the unit length dielectric conductance of each section model can be calculated in turn, and are denoted as G1, G2...Gn, respectively.

[0053] Then, the Telegrapher equation is applied to calculate the signal voltage and signal current of each simplified section transmission line model, and for example, the following equation is used for calculation:

[0054] (Equation 5)

[0055] where V(z), I(z) are the functions of the signal voltage and the signal current with respect to the propagation direction z, and z=0 at the excitation port. is the angular frequency, f is the frequency, and the frequency f can be obtained from the parameter file. is the unit length series impedance, is the unit length shunt admittance.

[0056] Through Equation 5, the second order differential equation for the signal voltage can be obtained as follows:

[0057] (Equation 6)

[0058] Equation 6 is a homogeneous Helmholtz equation, and in Equation 6, is the propagation constant.

[0059] According to the differential equation theory, the general solution of the differential equation of formula 6 is the superposition of forward and backward traveling waves: , combined with the Telegrapher equation The following formula can be obtained:

[0060] (Formula 7)

[0061] wherein, is the characteristic impedance, which is calculated by the following formula:

[0062] (Formula 8)

[0063] In addition, the boundary conditions are set as follows: at the excitation port, z = 0, ; at the port of the chip model opposite end, z = l, . Substituting the above boundary conditions into the general solution of the differential equation of formula 6, the signal voltage and signal current at the excitation port can be obtained as follows:

[0064] (Formula 9)

[0065] The signal voltage and signal current at the port of the model opposite end are as follows:

[0066] (Formula 10)

[0067] By solving the linear algebraic equations, the signal voltage and signal current at the port of the model opposite end can be used to represent the signal voltage and signal current at the excitation port, so that the ABCD matrix can be obtained:

[0068] (Formula 11)

[0069] According to the following S parameter matrix formula, the S parameter matrix can be obtained:

[0070] (Formula 12)

[0071] Thus, the S parameter matrix of the simplified transmission line model of each section can be calculated, and the transmission performance indicators of each section can be obtained.

[0072] Next, step S7 is performed, and the S parameter matrix of the entire transmission link is calculated according to the signal link distribution of each layer of the chip model and the S parameter matrix of the equivalent transmission line model of each layer of the chip model, so as to quantitatively evaluate the transmission performance of the entire transmission link. Specifically, assuming that the S parameter matrices of the transmission line models of each section are S1, S2…Sn, respectively, the S parameter matrix of the entire transmission link can be calculated as follows: nIn this embodiment, the S-parameter matrix of the entire transmission link is calculated by merging the T-parameter matrices one by one. The following example illustrates this using the transmission line model of the merged first and second segments. Assuming the S-parameter matrices of the first and second segments are S1 and S2 respectively, the T-parameter matrices of the first and second segments can be calculated using the following formulas:

[0073] T 11 =(S 21 ) -1

[0074] T 12 =-(S 21 ) -1 S 22

[0075] T 21 = S 11 (S 21 ) -1

[0076] T 22 = S 12 -S 11 (S 21 ) -1 S 22 (Equation 13)

[0077] (Equation 14)

[0078] By merging the T-parameter matrices of the transmission line models for each segment, a longer T-parameter matrix of the transmission line model can be obtained, for example, by using the following formula:

[0079] (Equation 15)

[0080] The S-parameter matrix of the longer transmission line model after merging can be obtained from the T-parameter matrix using the following formula. The reverse calculation yields the following:

[0081] S 11 =T 21 (T 11 ) -1

[0082] S 12 =T 22 - T 21 (T 11 ) -1 T 12

[0083] S 21 = (T 11 )-1

[0084] S 22 = -(T 11 ) -1 T 12 (16)

[0085] (17)

[0086] Finally, step S8 is performed to correct the S parameter matrix of the whole transmission link based on the number of corner nodes and the number of crossing holes of each paragraph. Since each corner and crossing hole of the whole transmission link causes a geometric mutation of the link, and further causes a mutation of the distributed parameters of the transmission line, thus causing an impedance mutation, signal reflection and reduced transmission performance. Therefore, the attenuation coefficient A of the whole link is related to the number of corners M of the whole link, the total number of crossing holes M and the frequency f, thus, the attenuation coefficient A of the whole link can be represented by the following formula:

[0087] (18)

[0088] wherein, i is the layer number of each paragraph, is the number of corners of the i-th paragraph, and M is the total number of crossing holes. Formula 18 can be calculated by using the following general quadratic model approximation function W:

[0089] (19)

[0090] wherein k is a preset factor number, in the embodiment, the value of k is 3, is a preset error term, k is a preset factor number, and X is an independent variable. Since the value of k is 3, the number of independent variables X in the embodiment is 3, i.e., X i , X j are independent variables, for example, the total number of crossing holes M and the frequency f in formula 18. β is a parameter determined by measurement, i.e., β0, β i , β ii , β ij are parameters determined by measurement. In addition, the embodiment can also set constraints, specifically, the following formula is used for constraints:

[0091] (20)

[0092] All parameters are determined by using formula 20, wherein k is a factor number, and P is the number of measurements needed to determine all parameters . ​

[0093] Finally, the transmission efficiency of the whole link can be calculated by the following formula:

[0094] (Formula 21)

[0095] After the transmission efficiency of the whole link is calculated, the signal quality of the whole link is judged according to the transmission efficiency of the whole link, for example, when the transmission efficiency of the link is greater than a pre-set threshold, it can be considered that the signal quality of the whole link meets the requirements.

[0096] Compared with the existing signal quality analysis method which only analyzes the circuit and analyzes the layout design after the whole simulation analysis in the early stage of chip development, the present application constructs a chip model and extracts a wiring path, creates a simplified equivalent transmission line model for the signal link paragraphs distributed in each layer of the chip model, then calculates the S parameter matrix of the whole transmission link by calculating the S parameter matrix of each layer of the equivalent transmission line model, and determines the link signal quality of the chip after correcting the S parameter matrix. The present application can calculate the S parameter matrix of the whole transmission link based on the simplified equivalent transmission line model and through simple calculation, and can quickly judge the link signal quality of the chip.

[0097] Although the present application uses many mathematical models and formulas in the calculation process of evaluating the link signal quality of the chip, since the formulas used are low-order calculations, the operation efficiency is very high. Referring to Figure 4 The operation method of the present application can correct the S parameter, and the starting calculation timestamp of the simulation is 02:50:20.923 seconds, and the completion calculation timestamp of the simulation is 02:50:21.998 seconds. From the starting calculation time to the completion calculation time, only 1 second is needed, which can realize the operation of seconds. The traditional finite element (FEM) operation of the post-simulation tool often needs a very long time to complete, so the present application can greatly shorten the time required for link signal quality evaluation.

[0098] In addition, since the present application also corrects the S parameter matrix of the whole transmission link based on the number of corner nodes and the number of through holes of each paragraph, the S parameter matrix of the whole transmission link can be calculated more accurately, and the accuracy of the link signal quality judgment is improved. Using the method of the present application, the calculation accuracy is sufficient to evaluate the pros and cons of the chip design scheme, and meets the needs of design index reachability evaluation and other scenes, and provides strong support for signal link quality analysis and evaluation in the microelectronic physical design stage.

[0099] Computer device embodiment:

[0100] The computer device of the embodiment can be a desktop computer or a data center, a data station, which has a processor, a memory, and a computer program stored in the memory and executable on the processor, such as an information processing program for implementing the information processing method described above, and the processor implements each step of the chip link signal quality evaluation method when executing the computer program.

[0101] For example, the computer program can be divided into one or more modules, one or more modules are stored in the memory, and are executed by the processor to complete each module of the application. One or more modules can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program in the terminal device.

[0102] The processor of the application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The processor is the control center of the terminal device, and connects all parts of the terminal device through various interfaces and lines.

[0103] The memory can be used to store computer programs and / or modules, and the processor realizes various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required by a function, etc.; and the data storage area can store data created according to the use of the mobile phone, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state memory devices.

[0104] Storage medium embodiment:

[0105] The computer program stored in the computer device, if implemented in the form of software functional units and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the above-mentioned embodiment methods can also be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by a processor, each step of the above-mentioned chip link signal quality evaluation method can be implemented.

[0106] The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate forms. The computer readable medium can include any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.

[0107] Finally, it should be emphasized that the above is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of chip link signal quality assessment, characterized by, The method comprises the following steps: obtaining a parameter file of a chip design, parsing the parameter file, modeling according to parameters extracted from the parameter file, obtaining a chip model, and obtaining a link trace path from the chip model; analyzing the geometric shape of the link according to the chip model, creating a simplified equivalent transmission line model for a signal link paragraph distributed on each layer of the chip model, calculating the unit length resistance, unit length distributed capacitance, and unit length distributed inductance of the equivalent transmission line model of each paragraph, solving the telegraph equation by solving the Helmholtz equation, thereby solving the signal voltage and signal current of the equivalent transmission line model of each paragraph, thereby solving the S parameters of the equivalent transmission line model of each paragraph, converting to a T parameter matrix to obtain an overall T parameter matrix, converting to an S parameter matrix of the entire transmission link through the S parameter T parameter conversion relationship, modifying the S parameter matrix of the entire transmission link based on the number of corner nodes and the number of through holes of each paragraph, and determining the link signal quality of the chip based on the modified S parameter matrix of the entire transmission link. In the modification of the S parameter matrix of the entire transmission link, the attenuation coefficient is calculated according to the number of corner nodes and the number of through holes of each paragraph, and the S parameter matrix of the entire transmission link is modified based on the attenuation coefficient.

2. The chip link signal quality evaluation method according to claim 1, wherein: The attenuation coefficient is calculated using a preset function, and the preset function W is: wherein k is a preset number of factors, X i , X j are all independent variables, β0, β i , β ii , β ij are all parameters determined by measurement, and ε is a preset error term.

3. The chip link signal quality evaluation method according to claim 1 or 2, wherein: When calculating the unit length resistance, unit length distributed capacitance, unit length distributed inductance, signal voltage, and signal current of the equivalent transmission line model of each paragraph, a calculation formula of not more than the second order is used.

4. The chip link signal quality evaluation method according to claim 1 or 2, wherein: When calculating the S parameter matrix of the entire transmission link, the S parameter matrix of the equivalent transmission line model of each paragraph is calculated, and the S parameter matrix of the equivalent transmission line model of each paragraph is merged one by one through the T parameter matrix to obtain the S parameter matrix of the entire transmission link.

5. The chip link signal quality evaluation method according to claim 1 or 2, wherein: When calculating the signal voltage and signal current of the equivalent transmission line model of each paragraph, the telegraph equation is used to calculate the signal voltage and signal current of the equivalent transmission line model of each paragraph.

6. The chip link signal quality evaluation method according to claim 1 or 2, wherein: Before obtaining the parameter file of the chip design, the parameters required for evaluation and calculation are extracted through a physical design interface and assembled into a parameter file.

7. The chip link signal quality evaluation method according to claim 1 or 2, wherein: When modeling according to the parameters extracted from the parameter file, the metal layer and dielectric layer required to be determined for chip link signal quality evaluation and calculation are restored.

8. Computer means, characterized in that The chip link signal quality evaluation method comprises the steps of: a processor and a memory are provided, the memory stores a computer program, and each step of the chip link signal quality evaluation method is implemented when the computer program is executed by the processor.

9. Storage medium having stored thereon a computer program, characterized in that: The computer program is executed by the processor to implement each step of the chip link signal quality evaluation method according to any one of claims 1 to 7.

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