Display device

Abstract

The display device comprises a light-emitting duration driving circuit and a light-emitting control circuit, a first capacitor and a third transistor are arranged in the light-emitting duration driving circuit to form a source follower circuit, and when the third transistor is turned off, the potential difference between the first end and the control end of the third transistor is the threshold voltage of the third transistor. The light-emitting duration driving circuit carries out threshold voltage compensation on light-emitting duration data through the voltage difference between the two ends of the first capacitor, the first capacitor is arranged to avoid short circuit of the first end and the control end of the third transistor, negative bias of the third transistor can be guaranteed, and therefore it is guaranteed that the light-emitting duration of a light-emitting element driven by the pixel driving circuit is accurate, and the light-emitting efficiency is improved. Besides, in the light-emitting control circuit, the adjusting transistor can perform function multiplexing on writing and regulation of the light-emitting current data, and the second capacitor can perform function multiplexing on storage and regulation of the light-emitting current data, so that the utilization rate of the device is improved, the circuit structure is simplified, and the production cost of the display device is reduced.

Description

Technical Field

[0001] Embodiments of this application relate to the field of display technology, and more particularly to a display device. Background Technology

[0002] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer lifespan, the application of micro-LEDs in displays has developed rapidly and has become a research hotspot in display devices.

[0003] The pixel driving circuit of a micro LED can drive the micro LED to emit light using pulse width modulation (PWM) + pulse amplitude modulation (PAM). In the PWM circuit within the pixel driving circuit, a threshold compensation transistor and a PWM driving transistor form a threshold compensation structure to compensate for the emission duration data. However, when the PWM driving transistor is turned on, there is a short circuit between its control terminal and the first terminal, causing the PWM driving transistor to fail to achieve negative bias. This affects the compensation of the emission duration data, resulting in threshold drift of the PWM driving transistor and impacting the accuracy of the driving duration.

[0004] In the pulse amplitude modulation circuit within the pixel driving circuit, multiple devices are set up to write, store, and regulate the luminous current data, resulting in a complex circuit structure and high production costs. Summary of the Invention

[0005] This application provides a display device to solve the above-mentioned technical problems.

[0006] This application provides a display device, including:

[0007] Gate driving circuit, data driving circuit, power supply circuit, at least one sub-pixel and corresponding sub-pixel driving circuit;

[0008] The sub-pixel driving circuit includes an emissivity duration adjustment circuit and an emissivity control circuit;

[0009] The light emission duration adjustment circuit includes a first capacitor and a third transistor, wherein the first capacitor is electrically connected between a first terminal and a control terminal of the third transistor;

[0010] The light emission duration adjustment circuit is electrically connected to the power supply circuit and the data driving circuit, and is configured to obtain a reference electrical signal, light emission duration data, and a first electrical signal, and to adjust the first capacitor and the third transistor based on the reference electrical signal to form a threshold compensation structure to generate light emission duration data with threshold voltage compensation of the third transistor.

[0011] During the display phase, an adjustment electrical signal is output based on the change in the first electrical signal and the light emission duration data compensated by the threshold voltage; the adjustment electrical signal includes a turn-off electrical signal and a light emission electrical signal.

[0012] The light-emitting control circuit includes a second capacitor, an adjustment transistor, and a driving transistor. The light-emitting control circuit and the third transistor are electrically connected and configured to obtain light-emitting current data and a second electrical signal.

[0013] When the light-emitting electrical signal is obtained during the display stage, the regulating transistor is controlled to write the light-emitting current data into the second capacitor;

[0014] When the power-off signal is obtained during the display phase, the data stored in the second capacitor is adjusted based on the change in the second electrical signal.

[0015] Based on the data stored in the second capacitor, the driving transistor is controlled to generate a driving signal;

[0016] The sub-pixel and the driving transistor are electrically connected and configured to emit light based on the driving signal.

[0017] The display device provided in this application embodiment includes a pixel driving circuit, comprising a light emission duration driving circuit and a light emission control circuit. The light emission duration driving circuit includes a first capacitor and a third transistor, forming a source follower circuit. In this circuit structure, when the third transistor is turned off, the potential difference between its first terminal and its control terminal is the threshold voltage of the third transistor. This allows the light emission duration driving circuit to compensate for the light emission duration data using the voltage difference across the first capacitor. The first capacitor prevents a short circuit between the first terminal and the control terminal of the third transistor, ensuring the negative bias of the third transistor and thus guaranteeing the accurate light emission duration of the light-emitting element driven by the pixel driving circuit. Furthermore, in the light emission control circuit, the regulating transistor can perform functional multiplexing for writing and regulating light emission current data, and the second capacitor can perform functional multiplexing for storing and regulating light emission current data, improving device utilization, simplifying the circuit structure, and reducing the production cost of the display device. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] Figure 1 This is a schematic diagram of the structure of a display provided according to an exemplary embodiment of this application;

[0020] Figure 2 This is a schematic diagram of the structure of a display provided in this application according to another exemplary embodiment;

[0021] Figure 3 This is a circuit structure diagram of a conventional pixel driving circuit provided in accordance with an exemplary embodiment of this application;

[0022] Figure 4 This is a schematic diagram of the structure of a sub-pixel driving circuit provided in an exemplary embodiment of this application;

[0023] Figure 5 This is a timing diagram of the driving signals for a sub-pixel driving circuit provided in this application according to an exemplary embodiment;

[0024] Figure 6A This is a diagram showing the operating state of a pixel driving circuit provided in this application according to an exemplary embodiment;

[0025] Figure 6B This is an operational state diagram of a pixel driving circuit provided in this application according to another exemplary embodiment;

[0026] Figure 6C This is an operational state diagram of a pixel driving circuit provided in this application according to another exemplary embodiment;

[0027] Figure 6D This is an operational state diagram of a pixel driving circuit provided in this application according to another exemplary embodiment;

[0028] Figure 6E This is a diagram showing the operating state of a pixel driving circuit provided in this application according to another exemplary embodiment.

[0029] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0030] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0031] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment. It should be further understood that the terms "comprising" or "including" indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups.

[0032] In the description of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise expressly specified. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition occur only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0033] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0034] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer lifespan, the application of micro-LEDs in displays has developed rapidly and has become a research hotspot in display devices.

[0035] A schematic diagram of the display device is shown below. Figure 1 and Figure 2As shown, the system includes a control circuit 250, a data drive circuit 20, a gate drive circuit 30, a display panel 40, and a power supply circuit 280. The control circuit 250 and the data drive circuit 20 are electrically connected, as are the gate drive circuit 30 and the display panel 40.

[0036] The display panel has a power line 90, multiple gate lines 60, multiple data lines 50 and multiple pixel units 80. The multiple pixel units 80 are arranged in an array, and each pixel unit 80 is located in the area where the gate line 60 and the data line 50 intersect.

[0037] The gate driving circuit 30 is electrically connected to the gate line 60. The gate driving circuit 30 is configured to obtain clock signals and trigger signals from the control circuit 250, generate gate driving signals according to the clock signals and trigger signals, and transmit the gate driving signals to the corresponding pixel unit 80 through the gate line 60 to control the transistors in the pixel unit 80 to be turned on or off.

[0038] More specifically, the gate driving circuit 30 can be fabricated as a separate gate driver integrated circuit (GDIC). Alternatively, the gate driving circuit 30 can be integrated into the display panel; this integration is called gate-in-panel (GIP). In some cases, the GDIC can be electrically connected to the display panel 40 via a COG (Chip on Glass) process, or via a COF (Chipon Film) process. In the COF process, the component is electrically connected to the display panel 40 via a flexible printed circuit (FPC).

[0039] The data driving circuit 20 is a circuit that drives the data line 50. It is configured to acquire display data from the control circuit 250 and convert it into an analog data voltage (Vdata). This analog data voltage is transmitted through the data line 50 to the corresponding pixel unit 80, so that the sub-pixel 813 in the pixel unit 80 emits light according to the analog data voltage. The magnitude of the analog data voltage determines the luminous brightness of the sub-pixel 813.

[0040] The data driving circuit 20 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, and output buffer, etc.

[0041] The power supply circuit 280 is a circuit that provides stable electrical signals and is configured to provide the corresponding power signals to the display panel 40, control circuit 250, data drive circuit 20 and gate drive circuit 30.

[0042] In one configuration, each pixel unit 80 includes three sub-pixel circuits 810, used to display red light, blue light, and green light respectively. In another configuration, each pixel unit 80 includes four sub-pixel circuits 810, used to display red light, blue light, green light, and white light respectively. No specific limitation is made here.

[0043] The emission color of each sub-pixel unit 810 is determined by the properties of its sub-pixel 813. The sub-pixel 813 can be any light-emitting device, including but not limited to OLED and micro LED.

[0044] A micro LED is a miniature light-emitting device manufactured using inorganic semiconductor layers. A micro LED typically includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, including vertical, horizontal, and flip-chip types, and is not particularly limited to a specific structure.

[0045] More specifically, a sub-pixel circuit 810 includes a sub-pixel driving circuit 814 and a sub-pixel 813. The sub-pixel driving circuit 814 is electrically connected to the sub-pixel 813 and is configured to drive the sub-pixel 813 to emit light. The signals required by the sub-pixel driving circuit 814 include a driving signal, a scan signal, and an emission control signal (EM control signal).

[0046] The driving signal can be generated by the control circuit 250 or obtained from an external source. This includes, but is not limited to, a start pulse signal, a clock signal, and an enable signal. The light emission control signal can be a global signal provided by the control circuit 250 or a signal generated by the gate driving circuit 30; no specific limitation is made here. The scanning signal is a successive displacement signal generated by the gate driving circuit 30.

[0047] If the EM control signal is a global signal generated by the control circuit 250, the gate drive circuit 30 obtains the EM control signal from the control circuit 250 and transmits the EM control signal to the corresponding pixel drive circuit 814 through the gate line 60.

[0048] If both the EM control signal and the scan signal are generated by the gate drive circuit 30, the gate drive circuit 30 includes a scan signal generation circuit 301 and an EM control signal generation circuit 302. The scan signal is output by the scan signal generation circuit 301, and the EM control signal is output by the EM control signal generation circuit 302.

[0049] Figure 3 This is a circuit structure diagram of a conventional pixel driving circuit provided in an exemplary embodiment of the present application, including a PWM driving circuit 803 and a PAM driving circuit 804.

[0050] The PWM drive circuit 803 is configured to acquire the light emission duration data PWMD and the power supply signal SWEEP, and adjust the level of the first light emission control signal it generates according to the light emission duration data PWMD and the power supply signal SWEEP. The level of the first light emission control signal is either a first level or a second level.

[0051] The PAM driver circuit 804 and the PWM driver circuit 803 are electrically connected to the light-emitting element LED and are configured to acquire a first light-emitting control signal and light-emitting current data PAMD, generate a driving signal based on the first light-emitting control signal and light-emitting current data PAMD, and drive the light-emitting element LED to emit light.

[0052] Among them, the first light emission control signal is an electrical signal that regulates the light emission duration of the light-emitting element LED, and the light emission current data PAMD is data that regulates the magnitude of the current passing through the light-emitting element LED.

[0053] The PWM drive circuit 803 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a sixth transistor T6, and a second capacitor C2.

[0054] The circuit structure and principle of the PWM drive circuit 803 will be explained below, assuming that the transistors in the traditional pixel drive circuit are all P-type transistors.

[0055] The first transistor T1 is electrically connected to power line 90 at its first terminal and to gate line 60 at its control terminal. It is configured to obtain an initialization signal RESET from its control terminal and a reference signal REF from its first terminal. When the initialization signal RESET is low, it is turned on and outputs the reference signal REF from its second terminal. The reference signal REF is a low-level signal.

[0056] The first terminal of the sixth transistor T6 is electrically connected to the data line 50, and the control terminal is electrically connected to the gate line 60. It is configured to obtain the scan signal SN from its control terminal and the light emission duration data PWMD from its first terminal. When the scan signal SN is low, it is turned on and the light emission duration data PWMD is output from its second terminal.

[0057] The control terminal of the fourth transistor T4 is electrically connected to the gate line 60, the first terminal is electrically connected to the control terminal of the third transistor T3, and the second terminal is electrically connected to the second terminal of the third transistor T3. It is configured to obtain the scan signal SN from its control terminal and turn on when the scan signal SN is low. It forms a threshold compensation structure with the third transistor T3.

[0058] The control terminal of the third transistor T3 is electrically connected to the second terminal of the first transistor T1, and the first terminal is electrically connected to the second terminal of the sixth transistor T6. It is configured to transmit an electrical signal to the control terminal when the fourth transistor T4 is turned on and its first terminal obtains the light emission duration data PWMD, until the third transistor T3 is turned off. When it is turned off, the potential at that point is determined from its control terminal to be the light emission duration data PWMD after threshold voltage compensation.

[0059] The first terminal of the second capacitor C2 is electrically connected to the control terminal of the third transistor T3, and is configured to store the light emission duration data of threshold voltage compensation generated by the control terminal of the third transistor T3 at its first terminal.

[0060] The second terminal of the second capacitor C2 is electrically connected to the power line 90, and is also configured to obtain the power signal SWEEP from the power line 90 at its second terminal, and adjust the voltage value of its first terminal according to the voltage change at its second terminal.

[0061] The first terminal of the second transistor T2 is electrically connected to the power supply line 90, the second terminal is electrically connected to the first terminal of the third transistor T3, and the control terminal is electrically connected to the gate line 60. It is configured to obtain a high-level fourth electrical signal VGH from its first terminal and a light emission control signal EM from its control terminal. When the light emission control signal EM is low, it is turned on and transmits the fourth electrical signal VGH obtained from its first terminal to the first terminal of the third transistor T3.

[0062] The third transistor T3 is also configured to receive an electrical signal generated at the first terminal of the second capacitor C2 from its control terminal when the fourth transistor T4 is turned off, and to receive a fourth electrical signal VGH from its first terminal. It is turned on when the difference between the potential values ​​at its control terminal and its first terminal is less than a preset threshold, and turned off when the difference between the potential values ​​at its control terminal and its first terminal is greater than or equal to the preset threshold.

[0063] When the third transistor T3 is turned on, the potential difference between its first and second terminals is negligible, which can be equivalent to a short circuit between the two terminals. At the same time, the fourth transistor T4 between the control terminal of the third transistor T3 and the first terminal is turned on, which can also be equivalent to a short circuit. This causes the third transistor T3 to be unable to achieve negative bias, thus making it impossible to compensate for the threshold voltage of the light emission duration data. As a result, the pixel driving circuit drives the light emission element to emit light for an inaccurate duration.

[0064] The PWM drive circuit 803 also includes a fifth transistor T5, the first terminal of the fifth transistor T5 and the second terminal of the third transistor T3 are electrically connected, the second terminal of the fifth transistor T5 is electrically connected to the power supply line 90, and the control terminal is electrically connected to the gate line 60. It is configured to obtain a light emission control signal EM from its control terminal and a third electrical signal VGL from its second terminal. It is turned on when the light emission control signal EM is low and outputs the third electrical signal VGL from its first terminal.

[0065] Since the aspect ratio of the third transistor T3 is greater than that of the fifth transistor T5, when both the third transistor T3 and the fifth transistor T5 are turned on, the potential of the second terminal of the third transistor T3 is the same as the potential of the fourth electrical signal VGH; when the third transistor T3 is turned off and the fifth transistor T5 is turned on, the potential of the second terminal of the third transistor T3 is the same as the potential of the third electrical signal VGL.

[0066] The PAM drive circuit 804 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a drive transistor T11.

[0067] The first terminal of the ninth transistor T9 is electrically connected to the data line 50, the control terminal is electrically connected to the gate line 60, and the second terminal is electrically connected to the second terminal of the first capacitor C1 and the control terminal of the driving transistor T11. It is configured to obtain the light emission current data PAMD from its first terminal and the scan signal SN from its control terminal. When the scan signal SN is low, it is turned on and outputs the light emission current data PAMD, which is stored in the first capacitor C1.

[0068] The first end of the driving transistor T11 is coupled to the power line 90, and the second end is electrically connected to the sub-pixel LED. It is configured to obtain the fifth electrical signal VDD from its first end and generate a driving signal when it obtains the light emission current data PAMD from its first end, thereby driving the sub-pixel LED to emit light.

[0069] The first terminal of the seventh transistor T7 is electrically connected to the power supply line 90, and its control terminal is electrically connected to the gate line 60. It is configured to obtain the fifth electrical signal VDD from its first terminal and the light emission control signal EM from its control terminal. It is turned on when the light emission control signal EM is low, and outputs the fifth electrical signal VDD from its second terminal.

[0070] The first terminal of the eighth transistor T8 is electrically connected to the second terminal of the seventh transistor T7, and its control terminal is electrically connected to the second terminal of the third transistor T3. It is configured to obtain the fifth electrical signal VDD from its first terminal and turn off when the potential of the second terminal of the third transistor T3 is the potential of the fourth electrical signal VGH. This does not affect the data stored in the first capacitor C1 and maintains the light-emitting state of the sub-pixel LED.

[0071] The eighth transistor T8 is also configured to turn on when the potential at the second terminal of the third transistor T3 is the potential of the third electrical signal VGL, and output the fifth electrical signal VDD, so that the driving transistor T11 turns off based on the fifth transistor VDD, stops the generation of the driving signal, and causes the sub-pixel LED to stop emitting light.

[0072] In the PAM driver circuit 804, each electronic device performs single data processing such as writing, storing and regulating the light-emitting current data PAMD, resulting in a complex circuit structure and high production cost for the PAM driver circuit 804.

[0073] To address the aforementioned problems, this application provides a display device to solve the technical issues described above. The technical concept of this application is as follows: a pixel driving circuit is provided, including a light-emitting duration driving circuit and a light-emitting control circuit. In the light-emitting duration driving circuit, a first capacitor and a third transistor are configured to form a source follower circuit. In this circuit structure, when the third transistor is turned off, the potential difference between its first terminal and its control terminal is the threshold voltage of the third transistor. This allows the light-emitting duration driving circuit to compensate for the light-emitting duration data using the voltage difference across the first capacitor. The first capacitor prevents a short circuit between the first terminal and the control terminal of the third transistor, ensuring the negative bias of the third transistor and thus guaranteeing the accurate light-emitting duration of the pixel driving circuit driving the light-emitting element. Furthermore, in the light-emitting control circuit, the regulating transistor can perform functional multiplexing for writing and regulating light-emitting current data, and the second capacitor can perform functional multiplexing for storing and regulating light-emitting current data, improving device utilization, simplifying the circuit structure, and reducing the production cost of the display device.

[0074] The pixel driving circuit proposed in this application will be explained in detail below. Figure 4 This is a schematic diagram of a pixel driving circuit provided according to an exemplary embodiment of this application. All transistors in this pixel driving circuit are P-type transistors.

[0075] like Figure 4 As shown, the pixel driving circuit provided in this application includes an emissive duration adjustment circuit 805, an emissive control circuit 806, and an emissive element LED.

[0076] The light emission duration driving circuit 805 is electrically connected to the power line 90 and the data line 50, and is configured to acquire the light emission duration data PWMD and the first electrical signal SWEEP1, and generate an adjustment electrical signal based on the light emission duration data PWMD and the first electrical signal SWEEP1.

[0077] The potential value of the regulating electrical signal can be represented by the potential value at point B.

[0078] The light emission control circuit 806 and the light emission duration adjustment circuit 805 are electrically connected and configured to obtain the second electrical signal SWEEP2, the adjustment electrical signal and the light emission current data PAMD, and regulate the process of generating a drive signal by the adjustment electrical signal. The light emission control circuit 806 generates a drive signal based on the second electrical signal SWEEP2 and the light emission current data PAMD.

[0079] The sub-pixel LED and the light-emitting control circuit 806 are electrically connected and configured to emit light according to the drive signal.

[0080] In some embodiments, the light emission duration adjustment circuit 805 includes a first capacitor C1 and a third transistor T3, wherein the first capacitor C1 is electrically connected between the first terminal and the control terminal of the third transistor T3.

[0081] The light emission duration adjustment circuit 805 is electrically connected to the power line 90 and the data line 50. It is configured to obtain the reference electrical signal REF, the light emission duration data PWMD, and the first electrical signal SWEEP1. Based on the reference electrical signal REF, the first capacitor C1 and the third transistor T3 are adjusted to form a threshold compensation structure to generate the light emission duration data PWMD with threshold voltage compensation of the third transistor T3.

[0082] The light emission duration adjustment circuit 805 is also configured to, during the display phase, output an adjustment signal based on the change in the first electrical signal SWEEP1 and the light emission duration data PWMD compensated by the threshold voltage; the adjustment signal includes a turn-off signal and a light emission signal.

[0083] In some embodiments, the light-emitting control circuit 806 includes a second capacitor C2, an adjustment transistor T7 and a driving transistor T9. The light-emitting control circuit 806 and the third transistor T3 are electrically connected and configured to obtain light-emitting current data PAMD and a second electrical signal SWEEP2.

[0084] When the light-emitting electrical signal is obtained during the display stage, the control regulating transistor T7 writes the light-emitting current data PAMD into the second capacitor C2;

[0085] When the power off signal is obtained during the display phase, the data stored in the second capacitor C2 is adjusted based on the change in the second electrical signal SWEEP2.

[0086] Based on the data stored in the second capacitor C2, the driving transistor T9 is controlled to generate a driving signal;

[0087] The sub-pixel LED and the driving transistor T9 are electrically connected and configured to emit light based on the driving signal.

[0088] In some embodiments, the light emission duration adjustment circuit 805 may include an initialization transistor T1.

[0089] The first terminal of the initialization transistor T1 is electrically connected to the power supply line 90, its control terminal is electrically connected to the gate line 60, and its second terminal is electrically connected to the control terminal of the third transistor T3. It is configured to obtain a reference electrical signal REF from its first terminal and a reset signal RESET from its control terminal, and its conduction state is controlled by the reset signal RESET.

[0090] The initialization transistor T1 is turned on when the reset signal RESET is low, and outputs the reference signal REF; it is turned off when the reset signal RESET is high, and stops the output of the reference signal REF.

[0091] The first terminal of the first capacitor C1 is electrically connected to the second terminal of the initialization transistor T1, and is configured to reset its first terminal based on the reference electrical signal REF.

[0092] In some embodiments, the light emission duration adjustment circuit 805 includes a third capacitor C3.

[0093] The second terminal of the third capacitor C3 is electrically connected to the second terminal of the initialization transistor T1, and is configured to reset its second terminal based on the reference electrical signal REF.

[0094] In some embodiments, the light emission duration adjustment circuit 805 may include a third transistor T3.

[0095] The control terminal of the third transistor T3 is electrically connected to the first terminal of the first capacitor C1, and its first terminal is electrically connected to the second terminal of the first capacitor C1. It is coupled to the data line 50. The third transistor T3 is configured to conduct based on the reference electrical signal REF and forms a threshold compensation structure with the first capacitor C1.

[0096] The third transistor T3 is also configured to obtain light emission duration data PWMD from its first terminal, charge the first capacitor C1, and determine its threshold voltage compensated light emission duration data PWMD from its control terminal when it is turned off.

[0097] The first capacitor C1 is configured to store the emission duration data PWMD of the third transistor T3, which is the threshold voltage compensation, at its first terminal, and is V. PWMD +Vth3, where V PWMD Vth3 represents the voltage value corresponding to the PWMD emission duration data, and Vth3 represents the threshold voltage of the third transistor T3.

[0098] In some embodiments, the light emission duration adjustment circuit 805 includes a second transistor T2.

[0099] The first terminal of the second transistor T2 is electrically connected to the power supply line 90, its second terminal is electrically connected to the second terminal of the first capacitor C1, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a light emission control signal EM from its control terminal and a fourth electrical signal VGH from its first terminal, and its conduction state is controlled by the light emission control signal EM.

[0100] The second transistor T2 is turned on when the light-emitting control signal EM is low, and outputs the fourth electrical signal VGH; it is turned off when the light-emitting control signal EM is high, and stops outputting the fourth electrical signal VGH.

[0101] The first terminal of the first capacitor C1 and the second terminal of the third capacitor C3 are electrically connected. The capacitor C1 is also configured to adjust the data stored in the first capacitor C1 based on the change of the fourth electrical signal VGH relative to the light emission duration data PWMD, its capacitance, and the capacitance of the third capacitor C3.

[0102] The adjusted data is as follows: Where c1 represents the capacitance of the first capacitor C1, and c3 represents the capacitance of the third capacitor C3.

[0103] The first terminal of the third capacitor C3 is electrically connected to the power supply line 90 and is configured to obtain a first electrical signal SWEEP1 from its first terminal. Based on the change in the first electrical signal SWEEP1 and its capacitance with respect to the first capacitor C1, the data stored in the first capacitor C1 is adjusted. The first electrical signal SWEEP1 is a changing electrical signal during the display phase.

[0104] The adjusted data is as follows: Wherein, SWEEP1 represents the amount of change of the first electrical signal SWEEP1 after the change relative to the default value of the electrical signal.

[0105] In some embodiments, the first electrical signal SWEEP1 is a gradually decreasing ramp signal during the display phase.

[0106] The third transistor T3 is also configured to obtain a fourth electrical signal VGH from its first terminal, obtain data stored in the first capacitor C1 from its control terminal, and control its conduction state based on the data stored in the first capacitor C1 and the fourth electrical signal VGH.

[0107] More specifically, when the potential value at the control terminal of the third transistor T3 is greater than or equal to the sum of the fourth electrical signal VGH and its threshold voltage, the third transistor T3 is turned off and does not output the fourth electrical signal VGH.

[0108] When the potential value at the control terminal of the third transistor T3 is less than the sum of the fourth electrical signal VGH and its threshold voltage, the third transistor T3 is turned on and outputs the fourth electrical signal VGH as a turn-off signal.

[0109] In some embodiments, the light emission duration adjustment circuit 805 includes a fifth transistor T5, the aspect ratio of which is smaller than that of the third transistor T3;

[0110] The first terminal of the fifth transistor T5 is electrically connected to the second terminal of the third transistor T3. Its second terminal is electrically connected to the power supply line 90, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a third electrical signal VGL from its second terminal and a light emission control signal EM from its control terminal, and its conduction state is controlled by the light emission control signal EM.

[0111] The fifth transistor T5 is turned on when the light-emitting control signal EM is low, and outputs the third electrical signal VGL from its first terminal. When the third transistor T3 is turned off, the third electrical signal VGL is used as the light-emitting signal. When the light-emitting control signal EM is high, it is turned off, and the output of the third electrical signal VGL is stopped.

[0112] In some embodiments, the light emission duration adjustment circuit 805 includes a data writing transistor T6;

[0113] The first terminal of the data writing transistor T6 is electrically connected to the data line 50, its control terminal is electrically connected to the gate line 60, and its second terminal is electrically connected to the first terminal of the third transistor T3. It is configured to obtain the light emission duration data PWMD from its first terminal and the scan signal SN from its control terminal, and its conduction state is controlled by the scan signal SN.

[0114] The data writing transistor T6 is turned on when the scan signal SN is low, and outputs the light emission duration data PWMD from its second terminal; it is turned off when the scan signal SN is high, and stops outputting the light emission duration data PWMD from its second terminal.

[0115] In some embodiments, the light emission duration adjustment circuit 805 includes a fourth capacitor C4.

[0116] The first terminal of the fourth capacitor C4 is electrically connected to the second terminal of the third transistor T3, and the second terminal is electrically connected to the power supply line 90. It is configured to filter and store the adjustment signal output by the light emission duration adjustment circuit 805.

[0117] In some embodiments, the control terminal of the regulating transistor T7 is electrically connected to the second terminal of the third transistor T3, and its first terminal is electrically connected to the data line 50, and is configured to obtain the luminous current data PAMD from its first terminal.

[0118] It is turned on when it receives a light-emitting electrical signal from its control terminal, and outputs light-emitting current data PAMD from its second terminal;

[0119] The first terminal of the second capacitor C2 is electrically connected to the second terminal of the regulating transistor T7, and its second terminal is electrically connected to the power line 90. It is configured to store the light-emitting current data PAMD at its first terminal when the regulating transistor T7 is turned on.

[0120] The control terminal of the driving transistor T9 is electrically connected to the first terminal of the second capacitor C2, and its first terminal is coupled to the power line 90. It is configured to obtain the fifth electrical signal VDD from its first terminal, and generate a driving signal based on the light emission current data PAMD and the fifth electrical signal VDD.

[0121] In some embodiments, the regulating transistor T7 is also configured to turn off when a turn-off electrical signal is received from its control terminal, thereby stopping the output of the light-emitting current data PAMD.

[0122] The second capacitor C2 is also configured to obtain a second electrical signal SWEEP2 from its second terminal, the second electrical signal SWEEP2 being a changing electrical signal during the display phase;

[0123] The stored luminous current data PAMD is adjusted based on the change in the second electrical signal SWEEP2;

[0124] The driving transistor T9 is also configured to generate a driving signal based on the adjusted light-emitting current data PAMD and the fifth electrical signal VDD when the adjusted light-emitting current data PAMD is within a preset conduction data range.

[0125] If the adjusted luminous current data PAMD is not within the preset conduction data range, the generation of drive signals will stop.

[0126] In some embodiments, the light-emitting control circuit further includes a light-emitting control transistor T8;

[0127] The first terminal of the light-emitting control transistor T8 is electrically connected to the power supply line 90, its control terminal is electrically connected to the gate line 60, and its second terminal is electrically connected to the first terminal of the driving transistor T9. It is configured to obtain a fifth electrical signal VDD from its first terminal and a light-emitting control signal EM from its control terminal, and its conduction state is controlled by the light-emitting control signal EM.

[0128] The light-emitting control transistor T8 is turned on when the light-emitting control signal EM is low, and outputs the fifth electrical signal VDD from its second terminal; it is turned off when the light-emitting control signal EM is high, and stops outputting the fifth electrical signal VDD from its second terminal.

[0129] The following is a combination Figure 5 The driving signal timing diagram and Figures 6A to 6E The process diagram shown is for Figure 4 The operation of the circuit structure shown will be explained.

[0130] A display cycle T consists of a reset phase t1, a data writing phase t2, and a display phase t3.

[0131] During the time period corresponding to the reset phase t1 in the driving signal timing diagram, the reset signal RESET is at a low level, the scan signal SN and the light emission control signal EM are at a high level, the first electrical signal SWEEP1 is at a first preset potential, and the second electrical signal SWEEP2 is at a second preset potential.

[0132] Since the reset signal RESET is low, the initialization transistor T1 is turned on, and the reference electrical signal REF obtained from its first terminal is transmitted to the first terminal of the first capacitor C1.

[0133] The first capacitor C1 resets its first terminal according to the reference electrical signal REF, and the voltage value after reset is the same as the voltage value of the reference electrical signal REF.

[0134] The third capacitor C3 resets its second terminal according to the reference electrical signal REF, and the voltage value after reset is the same as the voltage value of the reference electrical signal REF.

[0135] Since the light emission control signal EM is at a high level, the light emission control transistor T8 is turned off and does not transmit the fifth electrical signal VDD;

[0136] Since the driving transistor T9 does not receive the fifth electrical signal VDD, it does not generate a driving signal.

[0137] Sub-pixel LEDs do not emit light.

[0138] During the reset phase t1, the operating state of the sub-pixel driving circuit is as follows: Figure 6A As shown, the initialization transistor T1, marked with an arrow, is turned on, while the other transistors are turned off.

[0139] During the time period corresponding to the data writing stage t2 in the driving signal timing diagram, the scan signal SN is at a low level, while the reset signal RESET and the light emission control signal EM are at a high level.

[0140] Since the scanning signal SN is low, the data writing transistor T6 is turned on, and the light emission duration data PWMD obtained from its first terminal is output from its second terminal.

[0141] Since the reference electrical signal REF is low, the third transistor T3 is turned on, forming a threshold compensation structure with the first capacitor C1.

[0142] The first capacitor C1 adjusts the potential value of its first terminal based on the emission duration data PWMD until the third transistor T3 is turned off. The potential value of its first terminal is then determined to be the potential value corresponding to the emission duration data PWMD compensated by the threshold voltage of the third transistor T3, which is V. PWMD +Vth3, where VPWMD Vth3 represents the voltage value corresponding to the PWMD emission duration data, and Vth3 represents the threshold voltage of the third transistor T3.

[0143] The states of other transistors remain unchanged.

[0144] Then, during the time period corresponding to data writing phase t2, the operating state of the sub-pixel driving circuit is as follows: Figure 6B As shown, the data writing transistor T6 and the third transistor T3, marked with arrows, are turned on, while the other transistors are turned off.

[0145] During the time period corresponding to stage t3 shown in the driving signal timing diagram, the light emission control signal EM is at a low level, while the reset signal RESET and the scan signal SN are at a high level.

[0146] The first electrical signal SWEEP1 is a ramp signal that drops from the first preset potential to the third preset potential, and the second electrical signal SWEEP2 is a ramp signal that rises from the second preset potential to the fourth preset potential.

[0147] Since the light emission control signal EM is at a low level, the second transistor T2 is turned on and outputs the fourth electrical signal VGH obtained from its first terminal.

[0148] The first capacitor C1 adjusts the electrical signal stored at its first terminal based on the difference between the fourth electrical signal VGH and the emission duration data PWMD, its capacitance, and the capacitance of the third capacitor C3; the adjusted data is... Where c1 represents the capacitance of the first capacitor C1, and c3 represents the capacitance of the third capacitor C3.

[0149] The third capacitor C3 adjusts the electrical signal stored at the first terminal of the first capacitor C1 based on the change in the first electrical signal SWEEP1, its capacitance, and the capacitance of the first capacitor C1; the adjusted data is... Wherein, SWEEP1 represents the amount of change of the first electrical signal SWEEP1 after the change relative to the default value of the electrical signal.

[0150] The third transistor T3 receives a fourth electrical signal VGH at its first terminal and is turned off when the potential value at its control terminal is greater than or equal to the sum of the fourth electrical signal VGH and its threshold voltage.

[0151] Since the light emission control signal EM is low, the fifth transistor T5 is turned on, and the third electrical signal VGL obtained from its second terminal is output from its first terminal as the light emission signal.

[0152] Since the light-emitting electrical signal is at a low level, the regulating transistor T7 turns on when it receives the light-emitting electrical signal, and writes the light-emitting current data PAMD obtained at its first terminal into the first terminal of the second capacitor C2.

[0153] Since the light emission control signal EM is low, the light emission control transistor T8 is turned on and outputs the fifth electrical signal VDD obtained from its first terminal.

[0154] The driving transistor T9 generates a driving signal based on the fifth electrical signal VDD and the light-emitting current data PAMD;

[0155] The sub-pixel LEDs emit light according to the driving signal.

[0156] During the period when transistor T7 is turned on, the operating state of the sub-pixel driving circuit is as follows: Figure 6C As shown, the second transistor T2, the fifth transistor T5, the regulating transistor T7, the light-emitting control transistor T8, and the driving transistor T9, which are marked with arrows, are turned on, while the other transistors are turned off.

[0157] As the first electrical signal SWEEP1 decreases, when the electrical signal stored at the first terminal of the first capacitor C1 is within its conduction signal range, the third transistor T3 outputs the fourth electrical signal VGH obtained at its first terminal as a turn-off signal.

[0158] The regulating transistor T7 is turned off according to the turn-off signal;

[0159] The second capacitor C2 adjusts the data stored at its first terminal according to the change in the second electrical signal SWEEP2.

[0160] When the data stored at the first terminal of the second capacitor C2 is within its conduction data range, the driving transistor T9 generates a driving signal based on the data stored at the first terminal of the second capacitor C2 and the fifth electrical signal VDD.

[0161] Its corresponding operating status is as follows Figure 6D As shown, the second transistor T2, the third transistor T3, the fifth transistor T5, the light-emitting control transistor T8, and the driving transistor T9, which are marked with arrows next to them, are turned on, while the other transistors are turned off.

[0162] When the data stored at the first terminal of the second capacitor C2 is not within its conduction data range, the driving transistor T9 is turned off and stops generating driving signals.

[0163] The sub-pixel LEDs emit light according to the driving signal.

[0164] Its corresponding operating status is as follows Figure 6E As shown, the second transistor T2, the third transistor T3, the fifth transistor T5, and the light-emitting control transistor T8, which are marked with arrows, are turned on, while the other transistors are turned off.

[0165] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0166] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A display device, comprising: Gate driving circuit, data driving circuit, power supply circuit, at least one sub-pixel and corresponding sub-pixel driving circuit; The sub-pixel driving circuit is characterized in that it includes a light emission duration adjustment circuit and a light emission control circuit; The light emission duration adjustment circuit includes a first capacitor and a third transistor, wherein the first capacitor is electrically connected between a first terminal and a control terminal of the third transistor; The light emission duration adjustment circuit is electrically connected to the power supply circuit and the data driving circuit, and is configured to obtain a reference electrical signal, light emission duration data, and a first electrical signal, and to adjust the first capacitor and the third transistor based on the reference electrical signal to form a threshold compensation structure to generate light emission duration data with threshold voltage compensation of the third transistor. During the display phase, an adjustment electrical signal is output based on the change in the first electrical signal and the light emission duration data compensated by the threshold voltage; the adjustment electrical signal includes a turn-off electrical signal and a light emission electrical signal. The light-emitting control circuit includes a second capacitor, an adjustment transistor, and a driving transistor. The light-emitting control circuit and the third transistor are electrically connected and configured to obtain light-emitting current data and a second electrical signal. When the light-emitting electrical signal is obtained during the display stage, the regulating transistor is controlled to write the light-emitting current data into the second capacitor; When the power-off signal is obtained during the display phase, the data stored in the second capacitor is adjusted based on the change in the second electrical signal. Based on the data stored in the second capacitor, the driving transistor is controlled to generate a driving signal; The sub-pixel and the driving transistor are electrically connected and configured to emit light based on the driving signal.

2. The display device according to claim 1, characterized in that, The light emission duration adjustment circuit includes: An initialization transistor is configured to receive the reference electrical signal from its first terminal and a reset signal from its control terminal, and to output the reference electrical signal by the reset signal. The control terminal of the third transistor is electrically connected to the first terminal of the first capacitor, and its first terminal is electrically connected to the second terminal of the first capacitor. It is coupled to the data driving circuit. The third transistor is configured to conduct based on the reference electrical signal and forms the threshold compensation structure with the first capacitor. The light emission duration data is obtained from its first end, the first capacitor is charged, and when it is turned off, the light emission duration data with threshold voltage compensation is determined from its control end. The first capacitor is configured to store light emission duration data of the third transistor at its first terminal, which is compensated for the threshold voltage.

3. The display device according to claim 2, characterized in that, The light emission duration adjustment circuit includes a second transistor and a third capacitor; The first terminal of the second transistor is electrically connected to the power supply circuit, its second terminal is electrically connected to the second terminal of the first capacitor, its control terminal is electrically connected to the gate drive circuit, and it is configured to obtain a light emission control signal from its control terminal and a fourth electrical signal from its first terminal, and to output the fourth electrical signal by the light emission control signal. The first terminal of the first capacitor and the second terminal of the third capacitor are electrically connected and configured to adjust the data stored in the first capacitor based on the change of the fourth electrical signal relative to the light emission duration data, its capacitance, and the capacitance of the third capacitor. The first terminal of the third capacitor is electrically connected to the power supply circuit and is configured to obtain the first electrical signal from its first terminal, and adjust the data stored in the first capacitor based on the change in the first electrical signal and its capacitance with respect to the first capacitor.

4. The display device according to claim 3, characterized in that, The light emission duration adjustment circuit includes a fifth transistor, the aspect ratio of which is smaller than that of the third transistor; The fifth transistor has its first terminal electrically connected to the second terminal of the third transistor, its second terminal electrically connected to the power supply circuit, and its control terminal electrically connected to the gate drive circuit. It is configured to obtain a third electrical signal from its second terminal and a light-emitting control signal from its control terminal. The light-emitting control signal controls its first terminal to output the third electrical signal as the light-emitting electrical signal. The third transistor is also configured to receive the fourth electrical signal from its first terminal, receive the data stored in the first capacitor from its control terminal, and control its conduction state based on the data stored in the first capacitor and the fourth electrical signal. When it is turned on, the fourth electrical signal is output as the turn-off electrical signal; When it is turned off, the fourth electrical signal is not output.

5. The display device according to any one of claims 2 to 4, characterized in that, The light emission duration adjustment circuit includes a data writing transistor; The first terminal of the data writing transistor is electrically connected to the data driving circuit, its control terminal is electrically connected to the gate driving circuit, and its second terminal is electrically connected to the first terminal of the third transistor. It is configured to obtain the light emission duration data from its first terminal, obtain a scan signal from its control terminal, and control its second terminal to output the light emission duration data by the scan signal.

6. The display device according to any one of claims 1 to 4, characterized in that, The control terminal of the regulating transistor is electrically connected to the second terminal of the third transistor, and its first terminal is electrically connected to the data driving circuit, and is configured to obtain luminous current data from its first terminal. When the light-emitting electrical signal is obtained from its control terminal, it is turned on, and the light-emitting current data is output from its second terminal; The first terminal of the second capacitor is electrically connected to the second terminal of the regulating transistor, and its second terminal is electrically connected to the power supply circuit. It is configured to store the light-emitting current data at its first terminal when the regulating transistor is turned on. The control terminal of the driving transistor is electrically connected to the first terminal of the second capacitor, and the first terminal is coupled to the power supply circuit. It is configured to obtain a fifth electrical signal from its first terminal and generate the driving signal based on the light emission current data and the fifth electrical signal.

7. The display device according to claim 6, characterized in that, The regulating transistor is also configured to turn off when it receives the turn-off electrical signal from its control terminal, thereby stopping the output of the light-emitting current data. The second capacitor is also configured to receive a second electrical signal from its second terminal, the second electrical signal being a changing electrical signal during the display phase; The stored luminous current data is adjusted based on the change in the second electrical signal; The driving transistor is further configured to generate the driving signal based on the adjusted light-emitting current data and the fifth electrical signal when the adjusted light-emitting current data is within a preset conduction data range; If the adjusted luminous current data is not within the preset conduction data range, the generation of the drive signal is stopped.

8. The display device according to claim 6, characterized in that, The light-emitting control circuit also includes a light-emitting control transistor; The first terminal of the light-emitting control transistor is electrically connected to the power supply circuit, its control terminal is electrically connected to the gate driving circuit, and its second terminal is electrically connected to the first terminal of the driving transistor. It is configured to obtain the fifth electrical signal from its first terminal and obtain a light-emitting control signal from its control terminal, and control its conduction state by the light-emitting control signal.

9. The display device according to claim 1, characterized in that, The display cycle of the sub-pixel includes a reset phase, a data writing phase, and a display phase in sequence. During the reset phase, the reset signal is at a first level, the scan signal and the light emission control signal are at a second level, the first electrical signal is at a first preset potential, and the second electrical signal is at a second preset potential. The initialization transistor is turned on according to the reset signal, and the reference electrical signal obtained at its first terminal is transmitted to the first terminal of the first capacitor. The light-emitting control transistor is turned off according to the light-emitting control signal and does not transmit the fifth electrical signal; The driving transistor does not receive the fifth electrical signal and does not generate the driving signal; The sub-pixel does not emit light.

10. The display device according to claim 9, characterized in that, During the data writing phase, the scan signal is at a first level, and the reset signal and the light emission control signal are at a second level. The data writing transistor is turned on according to the scanning signal, and outputs the light emission duration data obtained at its first terminal from its second terminal; The third transistor is turned on according to the reference electrical signal, and together with the first capacitor, they form a threshold compensation structure. The first capacitor adjusts the potential value of its first terminal based on the light emission duration data until the third transistor is turned off, and determines that the potential value of its first terminal is the potential value corresponding to the light emission duration data compensated by the threshold voltage of the third transistor.

11. The display device according to claim 10, characterized in that, During the display phase, the light emission control signal is at a first level, and the reset signal and the scan signal are at a second level. The first electrical signal is a ramp signal that drops from the first preset potential to the third preset potential, and the second electrical signal is a ramp signal that rises from the second preset potential to the fourth preset potential. The second transistor is turned on according to the light emission control signal and outputs the fourth electrical signal obtained at its first terminal. The first capacitor adjusts the electrical signal stored at its first terminal based on the difference between the fourth electrical signal and the light emission duration data, its capacitance, and the capacitance of the third capacitor. The third capacitor adjusts the electrical signal stored at the first terminal of the first capacitor according to the change in the first electrical signal, its capacitance, and the capacitance of the first capacitor. The third transistor is turned off when the electrical signal stored at the first terminal of the first capacitor is not within its conduction signal range; The fifth transistor is turned on according to the light emission control signal, and outputs the third electrical signal obtained at its second terminal from its first terminal as the light emission signal; The regulating transistor is turned on when it receives the light-emitting electrical signal, and the light-emitting current data obtained at its first terminal is written into the first terminal of the second capacitor. The light-emitting control transistor is turned on according to the light-emitting control signal and outputs the fifth electrical signal obtained at its first terminal. The driving transistor generates a driving signal based on the fifth electrical signal and the light-emitting current data; The sub-pixel emits light according to the driving signal.

12. The display device according to claim 11, characterized in that, When the electrical signal stored at the first terminal of the first capacitor is within its conduction signal range, the third transistor outputs the fourth electrical signal obtained at its first terminal as a turn-off signal. The regulating transistor is turned off according to the turn-off electrical signal; The second capacitor adjusts the data stored at its first terminal according to the change in the second electrical signal; When the data stored at the first terminal of the second capacitor is within its conduction data range, the driving transistor generates a driving signal based on the data stored at the first terminal of the second capacitor and the fifth electrical signal. The driving transistor is turned off and stops generating driving signals when the data stored at the first terminal of the second capacitor is not within its conduction data range. The sub-pixel emits light according to the driving signal.

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