Manufacturing method of semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device, which comprises the following steps of: providing furnace tube equipment which comprises a furnace tube cavity and a wafer boat positioned in the furnace tube cavity; a bonding wafer is provided, the bonding wafer is placed on the wafer boat, a bonding starting point of the bonding wafer is determined, and the bonding starting point is located at the position close to the edge of the bonding wafer and close to the wafer boat; and carrying out heat treatment on the bonded wafer through furnace tube equipment. Therefore, when heat treatment is carried out, the area with the weak bonding force in the bonding wafer can be located in the area with the high temperature in the furnace tube equipment, and therefore the surface flatness of the area with the weak bonding force in the bonding wafer is improved, and the surface roughness is reduced; the bonding starting point has strong bonding force, so that the surface flatness of the area around the bonding starting point in the bonded wafer after heat treatment is high, the surface roughness of the bonded wafer after heat treatment is reduced, and the roughness uniformity of the surface of the bonded wafer is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] SOI (Silicon-on-Insulator) technology offers significant advantages in semiconductor devices, including reduced parasitic capacitance, lower power consumption, increased operating speed, and enhanced radiation resistance. However, the performance of SOI devices is also affected by various factors, among which surface roughness has a significant impact. Surface roughness increases scattering loss, especially when the waveguide width is small, where the effect is more pronounced. For example, when the surface roughness is reduced from 3.3 nm to 2 nm, the scattering loss can be reduced from 0.9 dB / cm to 0.3 dB / cm. Furthermore, surface roughness also leads to changes in electron mobility, particularly in ultra-thin SOI devices, where the impact of interface roughness scattering on electron transport characteristics is significantly enhanced. Therefore, reducing surface roughness is one of the key directions for improving SOI device performance. However, in current semiconductor device manufacturing methods, after thermal treatment (e.g., stripping thermal treatment), the bonded wafers exhibit high surface roughness and poor uniformity, which negatively impacts device performance. Summary of the Invention

[0003] The purpose of this invention is to provide a method for manufacturing semiconductor devices to reduce the surface roughness of bonded wafers after heat treatment.

[0004] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0005] A furnace tube assembly is provided, the furnace tube assembly comprising a furnace tube cavity and a crystal boat located within the furnace tube cavity;

[0006] A bonding wafer is provided, the bonding wafer is placed on the crystal boat, and a bonding start point of the bonding wafer is determined, the bonding start point being located near the edge of the bonding wafer and close to the crystal boat;

[0007] The bonding wafer is heat-treated using the furnace tube equipment.

[0008] Optionally, in the method for manufacturing the semiconductor device, determining the bonding start point further includes:

[0009] Two contact points between the bonding wafer and the crystal boat are determined, and the perpendicular bisector of the line segment connecting the two contact points is determined. The intersection of the perpendicular bisector and the edge of the bonding wafer near the crystal boat is used as a reference point.

[0010] There is a set angle A between the line connecting the reference point and the center of the bonding wafer and the line connecting the bonding start point and the center of the bonding wafer.

[0011] Optionally, in the semiconductor device manufacturing method, the set angle A satisfies the following relationship:

[0012] -45°≤A≤45°.

[0013] Optionally, in the method for manufacturing the semiconductor device, the heat treatment includes bonding heat treatment and peeling heat treatment.

[0014] Optionally, in the semiconductor device manufacturing method, the stripping heat treatment includes a pre-annealing process and an annealing process performed sequentially.

[0015] Optionally, in the semiconductor device manufacturing method, the annealing process is performed at a temperature higher than the pre-annealing process.

[0016] Optionally, in the semiconductor device manufacturing method, the pre-annealing process includes a first pre-annealing process, wherein the temperature of the first pre-annealing process is 100℃~250℃ and the time is 10min~60min.

[0017] Optionally, in the semiconductor device manufacturing method, the pre-annealing process further includes a second pre-annealing process, which is performed after the first pre-annealing process. The temperature of the second pre-annealing process is 250°C to 400°C, and the time is 10 min to 60 min.

[0018] Optionally, in the semiconductor device manufacturing method, the heating rate of the first pre-annealing process and the heating rate of the second pre-annealing process are the same.

[0019] Optionally, in the semiconductor device manufacturing method, the bonding wafer includes a bonded device wafer and a support wafer, an insulating layer is disposed between the device wafer and the support wafer, and the device wafer has an ion implantation layer.

[0020] During the peeling heat treatment of the bonding wafer, the device wafer is peeled off along the ion implantation layer to form the target wafer from the peeled portion of the device wafer, the insulating layer and the support wafer.

[0021] The semiconductor device manufacturing method provided by this invention includes: providing a furnace tube apparatus, the furnace tube apparatus including a furnace tube cavity and a crystal boat located within the furnace tube cavity; providing a bonding wafer, placing the bonding wafer on the crystal boat, determining the bonding initiation point of the bonding wafer, the bonding initiation point being located near the edge of the bonding wafer and close to the crystal boat; and performing heat treatment on the bonding wafer using the furnace tube apparatus. Thus, during heat treatment, areas with weaker bonding forces in the bonding wafer are placed in higher-temperature areas within the furnace tube apparatus, thereby improving the surface smoothness of these weaker bonding forces and reducing surface roughness. Furthermore, because the bonding initiation point has stronger bonding forces, the surface smoothness of the bonding initiation point and its surrounding area is higher after heat treatment, thereby reducing the surface roughness of the bonded wafer after heat treatment and improving the uniformity of the surface roughness distribution of the bonded wafer. Attached Figure Description

[0022] Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the furnace tube equipment in the semiconductor device manufacturing method according to an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the surface of a bonding wafer in the manufacturing method of a semiconductor device according to an embodiment of the present invention;

[0025] Figure 4 and Figure 5 This is a schematic diagram illustrating the principle of placing a bonding wafer on a wafer boat in the semiconductor device manufacturing method of this invention.

[0026] Figure 6 and Figure 7 This is a schematic cross-sectional view of the structure formed in the manufacturing method of the semiconductor device according to an embodiment of the present invention;

[0027] Figure 8 This is a schematic diagram of the surface of the bonding wafer in Embodiment 1 of the semiconductor device manufacturing method of the present invention;

[0028] Figure 9 This is a schematic diagram of the surface RMS of the bonding wafer after heat treatment in the semiconductor device manufacturing method of this embodiment of the invention.

[0029] Figure 10 and Figure 11 This is a schematic diagram of the bonding wafer surface in different comparative proportions in the semiconductor device manufacturing method of this invention.

[0030] The reference numerals in the attached figures are explained as follows:

[0031] 100 - Bonding wafer; 100a - Bonding start point; 110 - Device wafer; 111 - Ion implantation layer; 120 - Support wafer; 130 - Insulating layer; 200 - Furnace tube equipment; 210 - Furnace tube cavity; 220 - Crystal boat. Detailed Implementation

[0032] The manufacturing method of the semiconductor device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only used to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may have different emphases and sometimes use different scales.

[0033] Figure 1 This is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for manufacturing a semiconductor device, including:

[0034] Step S1: Provide furnace tube equipment, the furnace tube equipment including furnace tube cavity and crystal boat located in the furnace tube cavity;

[0035] Step S2: Provide a bonding wafer, place the bonding wafer on the crystal boat, and determine the bonding start point of the bonding wafer. The bonding start point is located near the edge of the bonding wafer and close to the crystal boat.

[0036] Step S3: Anneal the bonding wafer using the furnace tube equipment.

[0037] Figure 2 This is a schematic diagram of the furnace tube equipment in the semiconductor device manufacturing method according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the surface of a bonding wafer in the manufacturing method of a semiconductor device according to an embodiment of the present invention; Figure 4 and Figure 5 This is a schematic diagram illustrating the principle of placing a bonding wafer on a wafer boat in the semiconductor device manufacturing method of this invention. Figure 6 and Figure 7 This is a schematic cross-sectional view of the structure formed in the manufacturing method of the semiconductor device according to an embodiment of the present invention. The following will refer to the accompanying drawings. Figures 2-7 The manufacturing method of the semiconductor device provided in this embodiment will be described in more detail.

[0038] First, such as Figure 2As shown, in step S1, a furnace tube device 200 is provided, which includes a furnace tube cavity 210 and a crystal boat 220 located within the furnace tube cavity 210. The furnace tube device 200 can be a horizontal furnace tube device.

[0039] Next, as Figure 5 As shown, in step S2, a bonding wafer 100 is provided and placed on the boat 220. The bonding initiation point 100a of the bonding wafer 100 is determined, located near the edge of the bonding wafer 100 and close to the boat 220. Thus, during heat treatment, areas with weaker bonding forces in the bonding wafer 100 can be placed in higher-temperature regions, thereby improving the surface smoothness of these areas and reducing surface roughness. Conversely, because the bonding initiation point 100a has stronger bonding forces, the area surrounding it in the heat-treated bonding wafer 100 has higher surface smoothness, further reducing surface roughness and improving uniformity.

[0040] Specifically, such as Figure 6 As shown, the bonding wafer 100 includes a bonded device wafer 110 and a support wafer 120. An insulating layer 130 is disposed between the device wafer 110 and the support wafer 120, and the device wafer 110 has an ion implantation layer 111. The device wafer 110 can be made of silicon, and the insulating layer 130 can be made of silicon oxide. In other specific embodiments, the device wafer 110 can also be made of germanium silicon, germanium, or compound semiconductors, while the insulating layer 130 can be made of silicon nitride, silicon oxynitride, germanium silicon oxide, or other common insulating materials.

[0041] In this embodiment, an ion implantation process is performed on the device wafer 110 to form an ion implantation layer 111 within the device wafer 110. Specifically, the ions implanted in the ion implantation process can be hydrogen ions, and the ion implantation layer 111 is used to subsequently peel off a portion of the thickness of the device wafer 110.

[0042] For example, when performing an ion implantation process on the device wafer 110, the implantation energy can be 60 keV and the implantation dose can be 5.5 E16 atom / cm². 2 .

[0043] In this embodiment, the material of the supporting wafer 120 can be silicon, and the material of the insulating layer 130 is silicon oxide. In other specific embodiments, the material of the device wafer 110 can also be germanium-silicon, germanium, or compound semiconductors, etc.

[0044] In this embodiment, the support wafer 120 and the device wafer 110 are bonded together by a bonding process to form a bonded wafer 100. The support wafer 120 and the device wafer 110 can be bonded using a conventional bonding process or a plasma-assisted bonding process.

[0045] Specifically, during the bonding process between the support wafer 120 and the device wafer 110, the non-uniformity of the bonding force results in an uneven distribution of the bonding force at the bonding interface between the support wafer 120 and the device wafer 110.

[0046] like Figure 3 As shown, the contact sufficiency is high at the bonding initiation point 100a (i.e., the local region that first contacts and forms the initial bond during the bonding process), and the interatomic interaction is stronger, resulting in a stronger bonding force at the bonding initiation point 100a. When the bonded wafer 100 is placed on the boat 220, due to the thermal conductivity of the boat, the temperature of the region of the bonded wafer 100 near the boat 220 is lower during heat treatment, while the temperature of the region of the bonded wafer 100 far from the boat 220 is higher.

[0047] Based on this, in this embodiment, when placing the bonding wafer on the crystal boat, the bonding start point 100a is first determined and located near the edge of the bonding wafer 100 and near the crystal boat. In this way, during heat treatment, the area with weaker bonding force in the bonding wafer 100 can be placed in a higher temperature area, thereby improving the surface flatness of the area with weaker bonding force in the bonding wafer 100 and reducing the surface roughness. Since the bonding start point 100a has a strong bonding force, the surface flatness of the area around the bonding start point in the bonding wafer 100 after heat treatment is relatively high, thereby reducing the surface roughness of the bonding wafer 100 after heat treatment and improving the uniformity of the surface roughness distribution of the bonding wafer 100.

[0048] In this embodiment, as Figure 4 As shown, determining the bonding start point further includes: first, determining two contact points between the bonding wafer 100 and the crystal boat 220, and determining the perpendicular bisector of the line segment connecting the two contact points. The intersection of the perpendicular bisector and the edge of the bonding wafer 100 near the crystal boat 220 is used as a reference point. Then, a set angle A is set between the line connecting the reference point and the center of the bonding wafer 100 and the line connecting the bonding start point and the center of the bonding wafer 100. This is beneficial for placing the bonding start point near the edge of the bonding wafer 100 and near the crystal boat 220.

[0049] In this embodiment, the set angle A satisfies the following relationship:

[0050] -45°≤A≤45°.

[0051] For example, the set angle A can be -40°, -30°, -20°-10°, 0°, 10°, 20°, 30° or 40°.

[0052] Since there is a set angle A between the line connecting the reference point and the center of the bonding wafer 100 and the line connecting the bonding start point 100a and the center of the bonding wafer 100, during subsequent heat treatment, it is beneficial to place the area with weaker bonding force in the bonding wafer 100 in the area with higher temperature in the furnace tube equipment, thereby improving the surface flatness of the area with weaker bonding force in the bonding wafer 100.

[0053] Next, step S3 is performed, in which the bonded wafer 100 is heat-treated by the furnace tube equipment 200. The heat treatment includes bonding heat treatment and peeling heat treatment.

[0054] The stripping heat treatment includes a pre-annealing process and an annealing process performed sequentially, wherein the temperature of the annealing process is higher than the temperature of the pre-annealing process.

[0055] Specifically, the stripping heat treatment includes a pre-annealing process and an annealing process performed sequentially, wherein the temperature of the annealing process is higher than the temperature of the pre-annealing process. Both the pre-annealing and annealing processes are performed in the same furnace tube equipment, and during both processes, the bonded wafer 100 remains stationary within the furnace tube equipment to ensure that the temperature of the region is higher than the temperature of the bonding initiation point.

[0056] More specifically, the pre-annealing process includes a first pre-annealing process, wherein the temperature of the first pre-annealing process is 100℃~250℃ and the time of the first pre-annealing process is 10min~60min.

[0057] Optionally, the pre-annealing process further includes a second pre-annealing process, which is performed after the first pre-annealing process. The temperature of the second pre-annealing process is 250℃~400℃, and the time of the second pre-annealing process is 10min~60min.

[0058] In this embodiment, the heating rate of the first pre-annealing process is the same as that of the second pre-annealing process. This allows the bonding wafer 100 to gradually adapt to temperature changes, reducing the thermal stress impact caused by rapid temperature rise.

[0059] For example, the heating rate of the first pre-annealing process and the heating rate of the second pre-annealing process can be 1℃ / min.

[0060] After performing the pre-annealing process, the bonding wafer 100 is subjected to an annealing process at a temperature greater than 500°C, for example, the annealing temperature can be 550°C or 600°C.

[0061] The following examples and two comparative examples are provided to further illustrate the effects of the semiconductor device manufacturing method provided in this embodiment.

[0062] Table 1. Comparison of Example 1, Comparative Example 1, and Comparative Example 2

[0063] Example Angle A RMS mean(nm) RMS range (nm) Example 1 0° 4.3 0.6 Comparative Example 1 180° 4.9 0.9 Comparative Example 2 90° 4.8 0.7

[0064] In Table 1, angle A represents the angle between the line connecting the reference point and the center of the bonded wafer and the line connecting the bonding start point and the center of the bonded wafer. RMS mean (Root Mean Square) represents the root mean square of the bonded wafer surface after peeling, obtained by calculating the square root of the average square of the height deviations on the bonded wafer surface, reflecting the average level of surface roughness. RMS range represents the range of the root mean square of the bonded wafer surface after peeling, i.e., the difference between the maximum and minimum RMS values ​​of the bonded wafer surface, used to evaluate the consistency of surface roughness and process stability.

[0065] In Example 1, as Figure 8 As shown, the angle A between the straight line from reference point X to the center of the bonding wafer and the straight line from the bonding start point 100a to the center of the bonding wafer 100 is 0°. Figure 9 As shown, after annealing, the RMS mean of the bonding wafer 100 surface is 4.3 nm and the RMS range is 0.6.

[0066] In Comparative Example 1, such as Figure 10 As shown, the angle between the line connecting the reference point X and the center of the bonding wafer 100 and the line connecting the bonding start point 100a and the center of the bonding wafer 100 is 180°. After the bonding wafer 100 is annealed, the RMS mean of the bonding wafer surface is 4.9 nm and the RMS range is 0.9.

[0067] In Comparative Example 2, such as Figure 11 As shown, the angle A between the line connecting the reference point and the center of the bonding wafer 100 and the line connecting the bonding start point 100a and the center of the bonding wafer 100 is 90°. After the bonding wafer 100 is annealed, the RMS mean of the surface of the bonding wafer 100 is 4.8 nm and the RMS range is 0.7.

[0068] As can be seen from the above examples 1, 1, and 2, the semiconductor device manufacturing method provided in this example (Example 1) has the smallest RMS mean and RMS range on the surface of the bonded wafer after annealing, compared to 1 and 2. This means that the surface roughness of the bonded wafer is the smallest, thereby reducing the surface roughness of the bonded wafer after heat treatment. In addition, the wafer surface has no special patterns, which reduces the number of particles on the wafer surface and improves the uniformity of the surface roughness of the bonded wafer after peeling.

[0069] In summary, the semiconductor device manufacturing method provided in this embodiment of the invention includes: providing a furnace tube apparatus, the furnace tube apparatus including a furnace tube cavity and a crystal boat located within the furnace tube cavity; providing a bonding wafer, placing the bonding wafer on the crystal boat, determining the bonding initiation point of the bonding wafer, the bonding initiation point being located near the edge of the bonding wafer and close to the crystal boat; and performing heat treatment on the bonding wafer using the furnace tube apparatus. Thus, during heat treatment, areas with weaker bonding forces in the bonding wafer are placed in higher-temperature areas within the furnace tube apparatus, thereby improving the surface smoothness of these weaker bonding forces and reducing surface roughness. Furthermore, because the bonding initiation point has strong bonding forces, the surface smoothness of the bonding initiation point and its surrounding area is higher after heat treatment, thereby reducing the surface roughness of the bonded wafer after heat treatment and improving the uniformity of the surface roughness distribution of the bonded wafer.

[0070] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

[0071] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A furnace tube assembly is provided, the furnace tube assembly comprising a furnace tube cavity and a crystal boat located within the furnace tube cavity; A bonding wafer is provided, the bonding wafer is placed on the crystal boat, and a bonding start point of the bonding wafer is determined, the bonding start point being located near the edge of the bonding wafer and close to the crystal boat; The bonding wafer is heat-treated using the furnace tube equipment.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Determining the bonding start point also includes: Two contact points between the bonding wafer and the crystal boat are determined, and the perpendicular bisector of the line segment connecting the two contact points is determined. The intersection of the perpendicular bisector and the edge of the bonding wafer near the crystal boat is used as a reference point. There is a set angle A between the line connecting the reference point and the center of the bonding wafer and the line connecting the bonding start point and the center of the bonding wafer.

3. The method for manufacturing a semiconductor device as described in claim 2, characterized in that, The set angle A satisfies the following relationship: -45°≤A≤45°。 4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The heat treatment includes bonding heat treatment and peeling heat treatment.

5. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, The stripping heat treatment includes a pre-annealing process and an annealing process performed sequentially.

6. The method for manufacturing a semiconductor device as described in claim 5, characterized in that, The temperature of the annealing process is higher than the temperature of the pre-annealing process.

7. The method for manufacturing a semiconductor device as described in claim 5, characterized in that, The pre-annealing process includes a first pre-annealing process, wherein the temperature of the first pre-annealing process is 100℃~250℃ and the time is 10min~60min.

8. The method for manufacturing a semiconductor device as described in claim 7, characterized in that, The pre-annealing process further includes a second pre-annealing process, which is performed after the first pre-annealing process. The temperature of the second pre-annealing process is 250℃~400℃ and the time is 10min~60min.

9. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The heating rate of the first pre-annealing process is the same as that of the second pre-annealing process.

10. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, The bonding wafer includes a bonded device wafer and a support wafer, an insulating layer is disposed between the device wafer and the support wafer, and the device wafer has an ion implantation layer. During the peeling heat treatment of the bonding wafer, the device wafer is peeled off along the ion implantation layer to form the target wafer from the peeled portion of the device wafer, the insulating layer and the support wafer.

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