Method for forming semiconductor die

Abstract

A method for forming a semiconductor die. A method and a semiconductor die are disclosed. The method comprises forming a semiconductor die (3) based on a wafer (100). The wafer (100) includes a semiconductor layer (110) and a sacrificial layer (120) formed on opposite sides of an insulating layer (130). The method comprises: forming a separation structure (2), the separation structure (2) comprising a separation trench (21) laterally surrounding a die region (31) in a first semiconductor layer (110) of the wafer (100) and extending vertically from a first surface (111) of the wafer (100) through the semiconductor layer (110) to an insulating layer (130) of the wafer (100); removing the sacrificial layer (120); and detaching the die region (31) along the separation structure (2) to separate the semiconductor die (3) from the wafer (100).

Description

Technical Field

[0001] This disclosure generally relates to a method for forming a semiconductor die. Background Technology

[0002] A semiconductor die is a semiconductor wafer separated from a semiconductor wafer. Typically, a semiconductor die is separated from the wafer through a dicing process.

[0003] A semiconductor die may include one or more semiconductor devices integrated therein. A vertical semiconductor device, such as a vertical transistor, is a device having load terminals (such as source and drain terminals in a vertical transistor) on opposite sides of the die, such that the load current path of the semiconductor device extends vertically through the semiconductor die.

[0004] In the case of vertical semiconductor devices, the die thickness—the dimension of the die in the vertical direction—has a significant impact on the resistance of the load current path. Therefore, it is desirable to precisely adjust the die thickness. Conventional methods for adjusting die thickness include, for example, using etching or polishing processes to thin the wafer before separating it to form individual semiconductor dies. However, such etching or polishing processes are subject to fluctuations, making it impossible to always adjust the die thickness with the desired accuracy.

[0005] Therefore, a process is needed to produce semiconductor dies with desired thicknesses. Summary of the Invention

[0006] One example relates to a method for forming a semiconductor die based on a wafer. The wafer includes a semiconductor layer and a sacrificial layer formed on opposite sides of an insulating layer. The method includes forming a separation structure including a separation trench that laterally surrounds a die region in the semiconductor layer of the wafer and extends vertically from a first surface through the semiconductor layer to the insulating layer of the wafer. The method further includes removing the sacrificial layer and detaching the die region along the separation structure to separate the semiconductor die from the wafer.

[0007] Another example involves a semiconductor die with a shape that differs from a rectangular shape. Attached Figure Description

[0008] The following explanations are based on the accompanying drawings. The drawings are used to illustrate certain principles, showing only the aspects necessary for understanding these principles. The drawings are not drawn to scale. In the drawings, the same reference characters denote similar features.

[0009] Figure 1 The illustration shows a vertical cross-sectional view of a wafer including a semiconductor layer and a sacrificial layer arranged on opposite sides of an insulating layer;

[0010] Figure 2 The diagram illustrates the use of based on Figure 1 An example of a method for forming a semiconductor die from a wafer is illustrated in the figure.

[0011] Figure 3A and Figure 3B The diagram illustrates the process after the separation structure surrounding the core region is formed. Figure 1 A portion of a semiconductor wafer of the type illustrated in the figure;

[0012] Figures 4A-4C The schematic illustration shows top views of semiconductor wafers according to different examples, each semiconductor wafer including multiple die regions surrounded by discrete structures;

[0013] Figure 5 The diagram illustrates the process after removing the sacrificial layer. Figure 3A The wafer portion shown in the diagram;

[0014] Figure 6 The diagram illustrates the process of removing the core area. Figure 5 The wafer portion shown in the diagram;

[0015] Figures 7A-7C The illustration shows an example of a method for forming a split structure;

[0016] Figure 8 The die region with a lateral transistor device integrated therein is schematically illustrated;

[0017] Figure 9 The die region with vertical transistor devices integrated therein is schematically illustrated;

[0018] Figures 10A-10B The illustration shows an example of a method for forming a load path electrode for a vertical transistor device;

[0019] Figure 11 The illustration shows an example of a method for forming doped regions in a vertical transistor device;

[0020] Figures 12A-12B An example of a vertical transistor device is illustrated in more detail;

[0021] Figures 13A-13B The diagram illustrates the process after the separation and isolation structures are formed. Figure 1 A portion of the type of chip illustrated in the figure;

[0022] Figures 14A-14B The diagram shows... Figure 13B Different modifications to the isolation structure illustrated in the diagram;

[0023] Figure 15The illustration schematically shows a vertical cross-sectional view of a portion of a wafer after the second semiconductor layer has been removed and electrodes for semiconductor devices integrated in different isolation regions have been formed.

[0024] Figures 16A-16D The illustration shows an example of a method for forming separate and isolated structures based on common process steps; and

[0025] Figures 17A-17D The illustration shows a top view of a semiconductor die based on different examples. Detailed Implementation

[0026] In the following detailed description, reference is made to the accompanying drawings. The drawings form part of the specification and, for illustrative purposes, illustrate examples of how the invention can be used and implemented. It should be understood that, unless specifically indicated otherwise, features of the various embodiments described herein can be combined with each other.

[0027] Figure 1 A vertical cross-sectional view of a wafer 100 is shown, upon which at least one semiconductor die can be formed. The wafer 100 includes a semiconductor layer 110 and a sacrificial layer 120 formed on opposite sides of an insulating layer 130.

[0028] According to one example, semiconductor layer 110 includes a single-crystal semiconductor material. Examples of single-crystal semiconductor materials include, but are not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP).

[0029] According to one example, sacrificial layer 120 is a semiconductor layer. According to one example, sacrificial layer 120 includes a single-crystal semiconductor material. Examples of single-crystal semiconductor materials include, but are not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). Semiconductor layer 110 and sacrificial layer 120 may include the same type of single-crystal semiconductor material, or they may include different types of single-crystal semiconductor materials.

[0030] According to another example, semiconductor layer 110 comprises a single-crystal semiconductor material, such as one of the single-crystal semiconductor materials explained earlier herein, and sacrificial layer 120 comprises a polycrystalline semiconductor material. For example, the polycrystalline semiconductor material is polycrystalline silicon.

[0031] According to one example, the insulating layer 130 separating the semiconductor layer 110 and the sacrificial layer 120 comprises an oxide. According to one example, the oxide is a semiconductor oxide. According to one example, when the sacrificial layer is a semiconductor layer, the semiconductor oxide is an oxide of the semiconductor material of the semiconductor layer 110 or the sacrificial layer 120. According to one example, the insulating layer 130 comprises silicon dioxide (SiO2).

[0032] For example, the thickness of the insulating layer 130 is selected from the range of 100 nanometers (nm) and 5 micrometers (μm), particularly the range of 1 μm and 3 μm. The thickness of the insulating layer 130 is its dimension in the vertical direction of the wafer 100. The vertical direction of the wafer 100 is a direction substantially perpendicular to the first surface 111 and the second surface 121 of the wafer 100. The first surface 111 of the wafer 100 is formed by the semiconductor layer 110 facing away from the surface of the insulating layer 130, while the second surface 121 of the wafer 100 is formed by the sacrificial layer 120 facing away from the surface of the insulating layer 130.

[0033] For example, the thickness of semiconductor layer 110 is selected from the range of 50 nm and 20 μm, particularly the range of 2 μm and 25 μm. The thickness of semiconductor layer 110 is its dimension in the vertical direction of wafer 100. As further explained below, at least one semiconductor device can be integrated in semiconductor layer 110. The thickness of semiconductor layer 110 can be selected depending on the type and desired properties of the semiconductor device to be integrated in semiconductor layer 110.

[0034] For example, the thickness of the sacrificial layer 120 is selected from the range of 50 μm and 1500 μm, particularly the range of 600 μm and 1200 μm.

[0035] according to Figure 1 In one example illustrated by the dashed line, semiconductor layer 110 includes a first sublayer 113 adjacent to insulating layer 130 and a second sublayer 114 formed on top of the first sublayer 113. According to one example, the second sublayer 114 is an epitaxial layer formed on top of the first sublayer 113. According to one example, the first sublayer 113 has a thickness of less than 1 μm, less than 0.5 μm (500 nm), or even less than 0.1 μm (100 nm), and the desired total thickness of semiconductor layer 110 is adjusted by adjusting the thickness of the epitaxial layer 113 during the epitaxial growth process used to form the second sublayer 114. In this example, a wafer precursor of the same type, including sacrificial layer 120, insulating layer 130, and first sublayer 113, can be manufactured for various types of applications. Based on one of the wafer precursors, a wafer 100 for a specific application can then be manufactured by forming an epitaxial layer 113 of a desired thickness on top of the first sublayer 112.

[0036] Referring to the above, it can be based on Figure 1 The wafer 100 shown in the figure forms at least one semiconductor die. Figure 2 The diagram illustrates an example of a method for producing semiconductor dies based on wafer 100.

[0037] refer to Figure 2The method includes (201) forming a separation structure having a separation trench that laterally surrounds a die region in a semiconductor layer and extends vertically through the semiconductor layer to an insulating layer; (202) removing a sacrificial layer; and (203) detaching the die region along the separation structure to form a semiconductor die and detach the semiconductor die from the wafer.

[0038] Figure 2 Examples of the methods illustrated in the figures are explained in the following sections with reference to the other figures.

[0039] Figures 3A-3B An example of a semiconductor layer 110 after the formation of a separation structure 2 with separation trenches 21 is illustrated. Figure 3A A vertical cross-sectional view of a portion of wafer 100 is shown. More specifically, Figure 3A A vertical cross-sectional view is shown, including a portion of a semiconductor layer 110 including a die region 31 and a separation structure 2 surrounding the die region, a portion of an insulating layer 130 adjacent to the illustrated portion of the semiconductor layer 110, and a portion of a sacrificial layer 120 adjacent to the illustrated portion of the insulating layer 130. Figure 3B A top view of a semiconductor layer 110 and a separation structure 2 having a separation trench 21 laterally surrounding a die region 31 in the semiconductor layer 110 is shown. "Laterally surrounding" includes surrounding in a lateral direction, which is a direction substantially parallel to the first surface 111 and the second surface 121 of the wafer 100.

[0040] exist Figure 3B In the example illustrated, the separation groove 21 is essentially a rectangle with rounded corners. However, this is just an example. The separation groove 21 is not limited to a rectangle, but can be implemented using a wide variety of different geometries. Further examples are explained below.

[0041] refer to Figures 3A-3B The separation structure 2 may further include a dielectric layer 22 covering the sidewalls and bottom of the separation trench 21, and a void 23 surrounded by the dielectric layer 22. According to one example, the dielectric layer 22 is a single layer of the same material. According to another example, the dielectric layer 22 is a stack of layers comprising two or more sublayers of different dielectric materials. According to one example, the dielectric layer 22 comprises at least one of an oxide (such as silicon oxide) and a nitride (such as silicon nitride).

[0042] Figures 4A-4C A top view of the overall wafer 100 after forming a separation structure 2 with several separation trenches 21, according to different examples, is shown, each separation trench 21 surrounding a corresponding die region 31. Figures 4A-4C The separation trench 21 is illustrated in bold lines.

[0043] according to Figure 4A In one example illustrated, the separation trenches 21 are spaced apart from each other, such that portions of the semiconductor layer 110 remain between the separation trenches 21. The portions of the semiconductor layer 110 remaining between the separation trenches 21 may be referred to as cuts. These cuts may remain after the individual die regions 31 have been removed from the wafer 100 along the separation trenches 21.

[0044] according to Figures 4B-4C In another example illustrated in the diagram, the separation grooves 21 of the separation structure 2 form a grid, wherein the grid openings define a plurality of die regions 31. Figure 4B In the example illustrated, die region 31 is essentially a rectangle with rounded corners. In this example, adjacent to the corners of the adjacent die region 31, the piling portion of the semiconductor layer 110 remains outside the die region 31 and can be retained after the die region 31 is removed from the wafer.

[0045] exist Figure 4C In the example shown in the figure, the die region 31 is essentially a rectangle with sharp corners.

[0046] and Figure 4A Compared to the example shown in the figure, Figure 4B and 4C The example illustrated is more efficient in terms of space consumption and results in higher yield for a given wafer size.

[0047] Figure 5 The image shows the result after removing the sacrificial layer 120. Figures 3A-3B The arrangement is illustrated in the diagram. According to one example, during the removal of sacrificial layer 120, insulating layer 130 acts as a stop layer that has not been removed or has been removed at most partially. This is in... Figure 5 The diagram is shown in the middle. According to another example (not shown), after the sacrificial layer 120 is removed, the insulating layer 130 is completely removed.

[0048] Removing the sacrificial layer 120 may include any type of process suitable for removing the sacrificial layer 120 from the top of the insulating layer 130. Examples of removal processes include, but are not limited to, etching processes, mechanical polishing processes, chemical mechanical polishing (CMP) processes, or combinations of two or more of these processes.

[0049] according to Figure 5In one example illustrated by the dashed line, a carrier 300 is mounted to a first surface 111 prior to the removal of the sacrificial layer 120. It should be noted that "mounting the carrier 300 to the first surface 111" can include mounting the carrier 300 directly to the first surface 111, or mounting the carrier 300 to a layer or layer stack formed on top of the first surface 111. Such a layer or layer stack can include one or more metal layers and / or one or more dielectric layers. For example, the carrier 300 provides mechanical stability to the wafer during the removal process. Any type of carrier 300 suitable for stabilizing the wafer can be used. According to one example, the carrier 300 is a glass carrier.

[0050] Figure 6 The illustration shows the process of separating the die region 31 from the wafer 100 to separate the die region 31 from the remainder of the wafer 100, thereby forming the semiconductor die 3. Figure 5 The arrangement is illustrated in the figure. In addition to the die region 31, the semiconductor die 3 may further include portions of the insulating layer 130 and the dielectric layer 22 previously included in the separation trench 21. According to one example, portions of the dielectric layer 22 retained at the sidewalls of the die region 31 form a passivation layer laterally surrounding the semiconductor die 3. The sidewalls of the die region 31 are formed by the sidewalls of the separation trench 21 before being removed from the remainder of the wafer 100.

[0051] Referring to the above, during the process of removing the sacrificial layer 120, the carrier 300 can be mounted to the first surface 111. According to one example, the carrier 300 is removed before the die region 31 is removed from the wafer 100.

[0052] According to one example, after the removal of the sacrificial layer 120 and before the removal process, the wafer 100 is placed on the carrier 400 such that the first surface 111 faces away from the carrier 400. Figure 5 and Figure 6 In the example illustrated, the insulating layer 130 has not been completely removed after the sacrificial layer 120 has been removed. In this example, the insulating layer 130 faces the carrier 400, and the carrier 400 is mounted to the insulating layer 130. In another example (not shown) where the insulating layer 130 is completely removed after the sacrificial layer 120 has been removed, the carrier 400 is mounted directly to the surface of the semiconductor layer 110 opposite to the first surface 111. The carrier 400 is a flexible carrier, such as a foil, and stabilizes the wafer during this removal process.

[0053] Die region 31 can be detached from the remainder of wafer 100 in various ways.

[0054] According to one example, a lifting tool or pick-and-place tool (such as a vacuum tool) contacts the die region 31 at the first surface 111 of the wafer. Using the lifting tool, the die region 31 is pulled away from the wafer 100. The force applied by the lifting tool causes the dielectric layer 22 to break at the bottom and top of the separation trench 21, and causes the insulating layer 130 to break below the separation trench 21. This breaking of the dielectric layer 22 and the insulating layer 130 makes it possible to remove the die region 31 from the remainder of the wafer 100. If the wafer 100 is placed on a carrier 400, the lifting tool, in addition to breaking the dielectric layer 22 and the insulating layer 130, also lifts the semiconductor die 3 from the carrier 400.

[0055] According to another example, in order to remove the semiconductor die 3 from the wafer 100, a force is applied to the insulating layer 130 on the side opposite to the first surface 111 to push the die region 31 away from the remainder of the wafer 100. If the wafer is placed on a carrier 400, the pushing force is applied to the insulating layer 130 through the carrier 400. The pushing force can be applied by a pushing tool. The applied pushing force causes the dielectric layer 22 to break at the bottom and top of the separation trench 21, and causes the insulating layer 132 to break below the separation trench 21, making it possible to remove the die region 31 from the remainder of the wafer 100.

[0056] The previously explained method makes it possible to manufacture a semiconductor die 3 having a semiconductor layer of a defined thickness included within the semiconductor die 3. The thickness of the semiconductor layer included in the die 3 is defined by the thickness of the semiconductor layer 110 of the wafer 100. Referring to the above, the thickness of the semiconductor layer 110 can be precisely adjusted during the manufacture of the wafer 100.

[0057] Referring to the above, the separation structure 2 may include a dielectric layer 22 and a void 23 surrounded by the dielectric layer 22. See below for further details. Figures 7A-7C Here is an example of a method used to form this type of separation structure 2. Figures 7A-7C Each of these shows a vertical cross-sectional view of a portion of a semiconductor wafer 100, in which a separation trench 21 with a dielectric layer 22 and voids 23 is formed.

[0058] refer to Figure 7AThe method includes forming a separation trench 21 extending downward from the first surface 111 to the insulating layer 130. According to one example, forming the separation trench 21 includes an etching process, such as an anisotropic etching process, using an etching mask 560 (illustrated in dashed lines) formed on top of the first surface 111. According to one example, etching the semiconductor layer 110 to form the separation trench 21 includes selectively etching the semiconductor layer 110 relative to the insulating layer 130 such that the etching process stops at the insulating layer 130, and the separation trench 21 is etched downward into the insulating layer 130, but not into the insulating layer 130.

[0059] The depth of the separation trench 21—the dimension of the separation trench in the vertical direction of the wafer—is defined by the thickness of the semiconductor layer 110. For example, the width of the separation trench 21—the shortest lateral dimension of the separation trench 21—is between 0.5 μm and 2 μm. According to one example, the aspect ratio of the separation trench—the ratio between the trench width and the trench depth—is between 1:25 and 1:50. According to one example, the separation trench 21 has tapered sidewalls, causing the separation trench 21 to narrow towards the bottom of the trench. According to another example, the separation trench 21 has paper sidewalls, causing the separation trench 21 to widen towards the bottom of the trench. In both cases, the trench width explained above refers to the average trench width.

[0060] refer to Figure 7B The method further includes forming a dielectric layer 220 on the top of the first surface 111, along the sidewalls of the separation trench, and at the bottom of the separation trench. According to one example, forming the dielectric layer 220 includes a deposition process in which the dielectric layer 220 is deposited. Inside the separation trench 21, the deposited dielectric layer 220 forms the dielectric layer 22 surrounding the void 23 as explained above. The void 23 is automatically formed during the deposition process. The formation of the void 23 can be supported by appropriately selecting process parameters during the deposition process. However, the formation of the void is primarily supported by having narrow trenches. Furthermore, the trench supporting the formation of the void may have sharp angles between the sidewalls and the first surface 111, and the sidewalls are substantially perpendicular to the first surface 111 (non-conical). According to one example, the narrow trench is a trench with a trench width of less than 3 μm, particularly less than 2 μm, and particularly less than 1.5 μm. In the case of narrow trenches, the upper portion of the separation trench 21 is completely filled with the dielectric layer 222 before the separation trench 21 can be completely filled with the dielectric layer 220, so as to form a plug on the top of the gap 23.

[0061] Due to gap 23, the core region 31 (see example) Figure 5 and Figure 6Only portions of the dielectric layer 22 at the bottom and top of the trench 21 are connected to the remaining portion of the wafer 100 via the insulating layer 130. As explained above, these portions of the dielectric layer 22 at the bottom and top of the trench, as well as the insulating layer 130, can be easily broken by applying a pulling or pushing force to the die region 31.

[0062] according to Figure 7C As illustrated in one example, dielectric layer 220 is removed from first surface 111 such that only the dielectric layer 22 surrounding the void 23 remains in separation trench 21. Removing dielectric layer 220 from first surface 110 can include any kind of removal process, such as, for example, mechanical polishing, CMP, etching, or a combination of two or more of these processes.

[0063] Referring to the above, at least one semiconductor device can be formed in the die region 31 before it is removed from the wafer 100. Any type of semiconductor device can be implemented in the die region 31.

[0064] As an example, the semiconductor device is a transistor device. An example of a transistor device integrated in die region 31 is shown below. Figure 8 The diagram in the middle shows, Figure 8 A schematic diagram illustrates a vertical cross-sectional view of a core region 31.

[0065] Figure 8 The transistor device illustrated is a lateral transistor device. The transistor device includes a control node and a first load node and a second load node. The control node is connected to a control terminal 51 formed on a first surface 111, and the first and second load nodes are each connected to corresponding load terminals 52 and 53 formed on the first surface 111. Figure 8 In the example illustrated, the transistor device is represented by its circuit symbol, and the device area of ​​the transistor device is... Figure 8 There are no detailed illustrations. They are for illustrative purposes only. Figure 8 The transistor device illustrated is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In this example, the control node is the gate node, and the first load path node and the second load path node are the drain node and source node of the MOSFET, respectively.

[0066] Figure 8The circuit symbol illustrated represents an N-type enhancement-mode MOSFET. However, the transistor device implemented in die region 31 is not limited to being implemented as a specific type of transistor device. Instead, any type of transistor device, particularly any type of MOSFET, can be integrated in die region 31. Other examples of transistor devices that can be implemented in die region 31 include, but are not limited to, IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Field-Effect Transistors), or BJTs (Bipolar Junction Transistors).

[0067] Alternatively, or in addition to transistor devices, at least one passive device, such as a resistor or capacitor, may be integrated in die region 31.

[0068] Such as Figure 8 Lateral devices such as the lateral transistor device 4 illustrated herein can be fully formed in the die region 31 prior to performing any process sequence explained above, including removing the sacrificial layer 120 and separating the die region 31 from the wafer 100.

[0069] according to Figure 9 In another example illustrated, transistor device 4 is a vertical transistor device. In this example, a control node, such as the gate node of a MOSFET, is connected to a control terminal 51 on the first surface 111, and a first load path node, such as the source node of a MOSFET, is connected to a first load terminal 52 on the first surface 111. Referring above, the first surface 111 of the wafer is formed by the first surface of the semiconductor layer 110. In a vertical transistor device, the first load path terminal and the second load path terminal, such as the source and drain terminals of a MOSFET, can be arranged on opposite sides of the semiconductor die. Therefore, in Figure 9 In the example illustrated, the second load terminal of the transistor device, such as the drain terminal of a MOSFET, will be formed on the second surface 112 of the semiconductor layer 110. The second surface 112 is opposite to the first surface 111 and faces the insulating layer 130.

[0070] Figure 9 The illustration shows a portion of wafer 100 before the sacrificial layer 120 is removed. In this state of the manufacturing process, the vertical transistor device is not yet complete because at least the second load terminal cannot be produced, since the insulating layer 130 covers the second surface 112 and the sacrificial layer 120 covers the insulating layer 130.

[0071] Used to complete Figure 9 An example of the method of the vertical transistor device 4 illustrated in the figure is shown in Figures 10A-10B The diagrams are shown in the image. Each of these diagrams illustrates a sequence of processes. Figure 9 The layout is shown in the diagram.

[0072] refer to Figure 10A The method includes removing the sacrificial layer 120 from the insulating layer 130 and removing the insulating layer 130 as explained above, or forming an opening in the insulating layer 130 to expose a portion of the second surface 112 adjacent to the die region 31. The sacrificial layer 120 can be removed by methods according to any of the examples explained herein. Forming an opening in the insulating layer 130 can include an etching process that selectively etches the insulating layer 130 relative to the semiconductor layer 110. The etching process can include forming an etching mask (not shown) on top of the insulating layer 130, wherein the etching mask covers those portions of the insulating layer 130 that remain after the etching process.

[0073] According to one example, forming an opening in the insulating layer 130 includes forming an opening such that the insulating layer remains at least adjacent to the separation structure 2, i.e., adjacent to the separation trench 21.

[0074] refer to Figure 10B The method further includes forming a second load terminal 53 on a second surface 112 adjacent to the die region 31. Forming the second load terminal 53 may include depositing an electrode layer and patterning the electrode layer during etching. The electrode layer is a conductive layer, such as a metal layer. This type of process is well known, so no further explanation is required in this regard.

[0075] refer to Figures 10A-10B Before removing the sacrificial layer 120, a carrier 300 can be formed on the first surface 111 of the semiconductor layer 110. The carrier 300 can remain in place during the processes of removing the sacrificial layer, forming an opening in the insulating layer 130, and forming the second load terminal 53.

[0076] according to Figure 11 In one example illustrated, dopant atoms are implanted into the die region 31 through the exposed portion of the first surface 112 before forming the second load terminal 53 to form the device region 41 of the transistor device 4. According to one example, the device region 41 is the drain region of the transistor device. In addition to implanting dopant atoms, forming the device region 41 may include an annealing process, in which the implanted dopant atoms are activated. According to one example, the second load terminal 53 is formed to contact the device region 41. Optionally, the device region 41 is in… Figure 10B The diagram is shown in dashed lines.

[0077] According to one example, during the implantation process used to form device region 41, insulating layer 130 acts as an implantation mask, preventing dopant atoms from being implanted into those regions of semiconductor layer 110 covered by insulating layer 130. According to another example, prior to the implantation process, an implantation mask (not shown) is formed on top of insulating layer 130 and optionally on portions of second surface 112. In this example, the implantation mask covers those regions where dopant atoms will not be implanted.

[0078] exist Figure 12A-12B The diagram illustrates a detailed example of a vertical transistor device, specifically a vertical MOSFET. Figure 12A The illustration shows a vertical cross-sectional view of the die region 31 in which vertical transistor devices are integrated. The transistor devices include multiple transistor units 40. Figure 12B A transistor unit 40 is illustrated in detail.

[0079] refer to Figure 12B Each transistor cell 40 includes a source region 43 of a first doped type and a body region 42 of a second doped type complementary to the first doped type. The body region 42 is disposed between the source region 43 and a drift region 47 of the first doped type. According to one example, the drift region 47 of the transistor device is formed by an adjacent doped region of the first doped type. Each transistor cell 40 further includes a gate electrode 44 disposed adjacent to the body region 42 and dielectrically insulated from the body region 42 by a gate dielectric 45. In a conventional manner, the gate electrode 44 is configured to control a conductive channel in the body region 42 between the source region 43 and the drift region 47.

[0080] exist Figures 12A-12B In the example illustrated, gate electrode 44 is a trench electrode, which is an electrode disposed in a trench extending from the first surface 111 into the semiconductor layer 110. However, this is merely an example. It is also possible to implement the gate electrode as a planar electrode formed on the first surface 111. This is well known, so no further explanation is required in this regard.

[0081] The source region 43 and the body region 42 are connected to a first load terminal (source terminal) formed on the first surface 111. The first load terminal 52 is electrically insulated from the gate electrode 44 of the transistor unit 40 by a corresponding insulating layer 46.

[0082] According to one example, the transistor device is a superjunction transistor device. In this example, the transistor device further includes a plurality of compensation regions of a second doping type. Compensation region 48 is adjacent to drift region 47, such that a PN junction is formed between compensation region 48 and drift region 47. Compensation region 48 is connected to a first load terminal 52. For this purpose, compensation region 48 may be adjacent to body region 42 connected to the first load terminal 52.

[0083] In addition to drift region 47 and as explained above, the transistor device may include a drain region 41 connected to the second load terminal 53. For example, the drain region 41 is adjacent to the drift region 47. The drift region 47 is disposed between the drain region 41 and the body region 42 and is spaced apart from the body region 42 in the vertical direction of the die region 31. The vertical direction of the die region 31 is equal to the vertical direction of the semiconductor layer 130.

[0084] exist Figures 12A-12B In the device of the type illustrated, each device region except for the drain region 41 and the gate electrode 44 indicates that the dielectric 45 can be formed before the sacrificial layer 120 is removed. That is, the source region 43 and the body region 42, the optional compensation region 48, and the drift region 47 can be formed before the sacrificial layer 120 is removed. As explained above, the drain region 48 can be formed after the sacrificial layer 120 is removed and the insulating layer 132 is partially removed to expose a portion of the second surface 112.

[0085] Referring to the above, the transistor device can be implemented as a MOSFET. In this example, the drain region 41 has a first doping type, which is the same doping type as the source region 43 and the drift region 47. According to another example, the transistor device is implemented as an IGBT. In this example, the drain region 41 has a second doping type, which is the same doping type as the body region 42. In an IGBT, the drain region can also be referred to as the collector region.

[0086] Transistor devices can be implemented as N-type (N-channel) or P-type (P-channel) transistor devices. In an N-type device, the dopant atoms of the first doping type are N-type dopant atoms, and the dopant atoms of the second doping type are P-type dopant atoms. In a P-type device, the dopant atoms of the first doping type are P-type dopant atoms, and the dopant atoms of the second doping type are N-type dopant atoms.

[0087] Semiconductor layer 110 may have a basic doping of a first doping type. Source region 43 and body region 42, optional compensation region 48, and drain region 41 can be formed via an implantation process, in which dopant atoms of the respective device regions are implanted into the semiconductor layer, followed by an annealing process. In this example, the doping concentration of drift region 47 is equal to the basic open concentration of semiconductor layer 110. The basic doping concentration of semiconductor layer 110 can be adjusted during the fabrication of wafer 100.

[0088] In a vertical transistor device, the voltage blocking capability—the maximum voltage the transistor device can withstand between the first load terminal 52 and the second load terminal 53 in the off state—depends primarily on the doping concentration of the drift region 47 and the length of the drift region 47, which is the minimum vertical distance between the drain region 41 and the body region 42. The vertical dimensions of the body region 42 and the drain region 41 are typically much smaller than the length of the drift region 47, such that the thickness of the semiconductor layer 110 primarily defines the length of the drift region 47. Given that the length of the drift region 47 defines the voltage blocking capability, thus precisely defining the thickness of the semiconductor layer 110 and therefore the vertical dimension of the die region 31 are relevant aspects. This can be achieved through the methods explained above.

[0089] In Figure 7- Figure 12B In the example illustrated, die region 31 also forms a device region for integrating semiconductor devices, such as transistor devices. Figures 13A-13B In another example illustrated, the device region 311 for integrating semiconductor devices is part of the die region 31 surrounded by the isolation trench 51 of the isolation structure 5. Figure 13A A vertical cross-sectional view of the die region 31, including the device region 311 surrounded by isolation trenches 51, is shown. Figure 13B A top view of the die region 31 is shown. Figure 13B In the diagram, the separation structure 2 and the isolation structure 5 are schematically illustrated as thick lines. Figure 13A The diagram below illustrates the separation structure 2 and the isolation structure 5 in more detail.

[0090] The isolation structure 5 separates the device region 311 from the other semiconductor regions of the die region 31 in the lateral direction. (Reference) Figure 13A The isolation structure 5 includes an isolation trench 51 laterally surrounding the device region 311. The isolation structure 5 may further include a dielectric layer 52 covering the sidewalls and bottom of the isolation trench 51, and a filling layer 53 at least partially filling any remaining trenches or spaces defined by the dielectric layer 52 in the isolation trench 51. Figure 13A In the example shown in the figure, the filler layer completely fills the remaining trench.

[0091] According to one example, insulating layer 52 is a dielectric layer of the same material as dielectric layer 22 in separation trench 21. According to one example, dielectric layer 22 in separation trench 21 and insulating layer 52 in isolation trench 51 are formed by the same process. This is explained in further detail below.

[0092] For example, the filler layer 53 is an electrically insulating layer or a conductive layer. According to one example, the filler layer 53 is a conductive layer and comprises a polycrystalline semiconductor material, such as polycrystalline silicon.

[0093] exist Figures 13A-13B In the example illustrated, a device region 311 surrounded by the isolation structure 5 has been formed within a die region 31. However, this is merely an example. Figures 14A-14B The figures illustrate other examples, each showing a top view of die region 31 according to one example. In each example, die region 31 includes several device regions.

[0094] exist Figure 14A In the example illustrated, the isolation structure 5 forms an isolation grid, wherein device regions 311, 312, 313, and 314 are formed in each grid opening of the isolation grid.

[0095] exist Figure 14B In the example illustrated, the isolation structure 5 includes a plurality of isolation trenches spaced apart from each other. A first isolation trench 511 and a second isolation trench 512 each surround a corresponding portion of the die region 31 to form a first device region 321 and a second device region 322. A third isolation trench 513 surrounds the portion of the die region 31 including the first device region 321 and the second device region 322, such that the third isolation trench 513, combined with the first isolation trench 511 and the second isolation trench 512, forms a third device region 323, which is the portion of the die region 31 between the first isolation trench 511 and the second isolation trench 512 arranged on one side and the third isolation trench 513 arranged on the other side.

[0096] It should be noted that Figure 13B and Figures 14A-14B The examples illustrated are just three of a variety of different examples of forming a device region in die region 31 using an isolation structure 5 having at least one isolation trench. Figure 13B and Figures 14A-14B Any combination of the examples illustrated herein is possible. In each case, an isolation trench surrounds a portion of the die region 31 to form a device region. In each case, the isolation structure 5 electrically insulates the respective device regions from each other.

[0097] Within each device region, semiconductor devices can be implemented. This is in Figure 15 The diagram in the middle shows, Figure 15 The die region 31 is shown, comprising three distinct device regions 331, 332, and 333, which are separated from each other by an isolation structure 5.

[0098] For illustrative purposes only, vertical transistor devices 41, 42, and 43 having second load terminals 531 and 532 at the second surface 112 of semiconductor layer 110 are integrated in each device region 331, 332, and 333. For ease of illustration, the first load terminals and control terminals of transistor devices 41, 42, and 43 are not shown in the diagram. Figure 15The diagram shows that these control terminals and first load terminals can be implemented according to any of the examples previously explained herein. According to one example, each transistor device includes drain regions 411, 412, 413 adjacent to the second surface 112 and connected to the corresponding second load terminals (drain terminals) 531, 532.

[0099] Semiconductor devices integrated in the respective device regions formed in the die region 31 can be interconnected in various ways by connecting the terminals (such as control terminals and load terminals of transistor devices) of semiconductor devices formed on the top of the first surface 111 and the second surface 112 to each other. However, this is only an example. According to another example, the semiconductor devices integrated in the device regions have separate terminals that are not connected to each other.

[0100] exist Figure 15 In the example illustrated, the drain regions 412 and 413 of transistor devices 42 and 43 are connected to the same drain terminal 532, while the drain region 411 of another transistor device 41 is connected to a separate drain terminal 531. Similarly, the source regions (not shown) of two or more transistor devices 41, 42, and 43 can be connected to the same source terminal, and the gate electrodes of two or more transistor devices 41, 42, and 43 can be connected to the same control terminal (gate terminal).

[0101] It should be noted that different types of electronic devices can be integrated into the same die 3 in different device areas. According to one example, only lateral devices are integrated into the same die 3. According to another example, only vertical devices are integrated into the same die 3. According to yet another example, both vertical and lateral devices are integrated into the same die 3.

[0102] Referring to the above, the dielectric layer 22 of the separation structure 2 and the insulating layer 51 of the isolation structure 5 can be formed through the same process. Figures 16A-16D The figures illustrate an example of a method for forming the separation structure 2 and the isolation structure 5 in this manner. Each of these figures shows a vertical cross-sectional view of a portion of the wafer during the manufacturing process.

[0103] Figure 16A The image shows a wafer after a separation trench 21 and an isolation trench 51 have been formed. According to one example, these trenches 21, 51 are created using an etch mask (…). Figure 16A The same etching process (not shown in the figure) is used to form the isolation trench 51. According to one example, the isolation trench 51 is wider than the separation trench 21. According to one example, the width of the isolation trench 51 is greater than 1.5 μm. According to one example, the width of the isolation trench 51 is at least 1.5 times, at least 2 times, or at least 3 times the width of the separation trench 21.

[0104] Figure 16B This shows the process after the formation of dielectric layer 220 according to... Figure 16A The arrangement is as follows: As explained above, the dielectric layer 220 in the separation trench 21 forms a dielectric layer 22 surrounding the gap 23. In the isolation trench 51, the dielectric layer 220 covers the sidewalls and bottom, forming an insulating layer 52. Because the isolation trench 51 is wider than the separation trench 21, the formation of a gap surrounded by a dielectric layer in the isolation trench 51 is avoided.

[0105] As explained above, the method further includes removing the dielectric layer 220 from the first surface 111. Further still, the method includes filling any remaining trenches in the isolation trench 51 after the formation of the insulating layer 52 with a filler material 53. (See reference...) Figure 16C Filling the residual trench includes depositing a fill layer 530 after removing the dielectric layer 220 from the first surface 111, such that the fill layer 530 fills the residual trench and covers the first surface 111. Further, filling the residual trench includes removing the fill layer 530 from the first surface 111. Removing the fill layer 530 from the first surface 111 includes, for example, a mechanical polishing process, a CMP process, an etching process, or a combination of two or more of these processes.

[0106] Referring to the above, the previously explained method enables the formation of a semiconductor die 3 having a semiconductor layer of precisely defined thickness included within the die 3. The geometry of the semiconductor die 3 is defined by the shape of the separation structure 2 having separation trenches 21. Based on this, various different geometries of the semiconductor die 3, other than a rectangular shape, are possible. For illustrative purposes only, in Figures 17A-17D The diagram illustrates some possible shapes for the semiconductor die 3. Such geometries include, but are not limited to, those shown below. Figure 17A The L-shape shown in the diagram; as Figure 17B The U-shape shown in the diagram; polygons, such as Figure 17C The hexagon shown in the diagram; or as Figure 17D The hexagon shown in the diagram. In each case, if available, the corners can be rounded, for example, as shown in the diagram. Figure 17A and Figure 17B As shown in the diagram, or implemented as a sharp corner, for example... Figure 17C and Figure 17D As shown in the diagram.

[0107] As an example, the shape of a semiconductor die includes at least five corners, such as... Figure 17A , Figure 17B and Figure 17C As shown in the diagram. Figure 17AIn the example illustrated, the L-shaped semiconductor die 3 includes six corners: five outward-pointing (outer) corners 341, 342, 343, 344, and 345, and one inward-pointing (inner) corner 346. Figure 17B In the example illustrated, the U-shaped semiconductor die 3 includes eight corners: six outward-pointing corners 351, 352, 353, 354, 355, and 356, and two inward-pointing corners 357 and 358. However, this is only an example. Combinations of outward-pointing and inward-pointing corners are possible.

[0108] According to one example, the shape of the semiconductor die 3 includes at least five outward-pointing corners and at least one inward-pointing corner.

[0109] Some of the aspects explained above are briefly summarized in the following examples with reference numbers.

[0110] Example 1. A method for forming a semiconductor die based on a wafer, the wafer including a semiconductor layer and a sacrificial layer formed on opposite sides of an insulating layer, wherein the method includes: forming a separation structure including a separation trench laterally surrounding a die region in a first semiconductor layer of the wafer and extending perpendicularly from a first surface of the wafer through the semiconductor layer to an insulating layer of the wafer; removing the sacrificial layer; and detaching the die region along the separation structure to separate the semiconductor die from the wafer.

[0111] Example 2. According to the method of Example 1, the separation structure further includes a dielectric layer covering the sidewalls and bottom of the separation trench; and a void surrounded by the dielectric layer.

[0112] Example 3. The method according to Example 2, wherein the dielectric layer comprises an oxide.

[0113] Example 4. The method according to any one of Examples 1 to 3, wherein forming the semiconductor die further comprises: at least partially removing the insulating layer before removing the die region.

[0114] Example 5. The method according to Example 4, wherein at least partial removal of the insulation layer includes the portion of the insulation layer that maintains the adjacent separated structure.

[0115] Example 6. The method according to any one of Examples 1 to 5, wherein forming a semiconductor die further comprises: forming at least one semiconductor device in the die region before removing the die region.

[0116] Example 7. According to the method of Example 6, forming the at least one semiconductor device includes: forming a doped device region in the die region before removing the second semiconductor layer.

[0117] Example 8. According to the method of Example 7, forming the at least one semiconductor device further includes: at least partially removing an insulating layer to expose at least a portion of a second surface opposite to a first surface of the first semiconductor layer; and forming an electrode adjacent to the second surface.

[0118] Example 9. According to the method of Example 8, forming the at least one semiconductor device further includes: implanting dopant atoms for at least one additional doped device region into the die region via a second surface before forming the electrode.

[0119] Example 10. The method according to any one of Examples 1 to 9, wherein forming a semiconductor die further comprises: forming an isolation structure in a die region, wherein the isolation structure includes an isolation trench that laterally surrounds at least one device region in the die region and extends vertically from a first surface through a first semiconductor layer to an insulating layer.

[0120] Example 11. According to the method of Example 10, the isolation structure further includes: an insulating layer covering the sidewalls and bottom of the isolation trench; and a filling layer that at least partially fills the space defined by the insulating layer in the isolation trench.

[0121] Example 12. The method according to Example 11, wherein the filling layer comprises a conductive material.

[0122] Example 13. The method according to any one of Examples 6 to 12, wherein forming the at least one semiconductor device includes forming the at least one semiconductor device in the at least one device region.

[0123] Example 14. The method according to any one of Examples 10 to 13, wherein the separation trench and the isolation trench are formed by the same process.

[0124] Example 15. The method according to Example 14, wherein the passivation layer of the separation structure and the insulating layer of the isolation structure are formed by the same process.

[0125] Example 16. The method according to any one of Examples 1 to 15, wherein the sacrificial layer is a semiconductor layer.

[0126] Example 17. A semiconductor die having a shape other than a rectangular shape.

[0127] Example 18. A semiconductor die according to Example 17, wherein the semiconductor die includes at least five corners.

[0128] Example 19. A semiconductor die according to Example 18, wherein the corners are rounded.

[0129] Example 20. A semiconductor die according to Example 18 or 19, wherein the at least five corners include at least five outer corners and at least one inner corner.

[0130] Example 21. A semiconductor die according to Example 20, wherein the semiconductor die has an L-shape or a U-shape.

[0131] Example 22. A semiconductor die according to any one of Examples 17 to 21, wherein the semiconductor die includes a dielectric layer covering the semiconductor die sidewalls forming the shape of the semiconductor die.

Claims

1. A method for forming a semiconductor die (3) based on a wafer (100), the wafer (100) comprising a semiconductor layer (110) and a sacrificial layer (120) formed on opposite sides of an insulating layer (130), wherein the method comprises: A separation structure (2) is formed, the separation structure (2) including a separation trench (21) that laterally surrounds a die region (31) in a first semiconductor layer (110) of the wafer (100) and extends vertically from a first surface (111) of the wafer (100) through the semiconductor layer (110) to an insulating layer (130) of the wafer (100); Remove the sacrificial layer (120); and The die region (31) is detached along the separation structure (2) to separate the semiconductor die (3) from the wafer (100).

2. The method according to claim 1, The separation structure (2) further includes a dielectric layer (22) covering the sidewalls and bottom of the separation trench (21); and The void (23) is surrounded by the dielectric layer (22).

3. The method according to claim 2, The dielectric layer (22) therein comprises an oxide.

4. The method according to any one of claims 1 to 3, wherein forming the semiconductor die (3) further comprises: At least part of the insulation layer (130) shall be removed before the core area (31) is removed.

5. The method of claim 4, wherein at least partial removal of the insulating layer (130) includes retaining portions of the adjacent separation structure (2) of the insulating layer (130).

6. The method according to any one of claims 1 to 5, wherein forming the semiconductor die (3) further comprises: At least one semiconductor device (4) is formed in the die region (31) before being removed from the die region (31); 41，42，43)。 7. The method of claim 6, wherein forming the at least one semiconductor device (4; 41, 42, 43) comprises: Before removing the second semiconductor layer (120), a doped device region (42, 43) is formed in the die region (31).

8. The method of claim 7, wherein forming the at least one semiconductor device (4; 41, 42, 43) further comprises: At least a portion of the insulating layer (130) is removed to expose at least a portion of the second surface (112) opposite the first surface (111) of the first semiconductor layer (110); as well as An electrode (53) is formed adjacent to the second surface (112).

9. The method of claim 8, wherein forming the at least one semiconductor device (4; 41, 42, 43) further comprises: Before forming the electrode (53), dopant atoms for at least one additional doped device region (41) are implanted into the die region (31) via the second surface (112).

10. The method according to any one of claims 1 to 9, wherein forming the semiconductor die (3) further comprises: An isolation structure (5) is formed in the core region (31). The isolation structure (5) includes an isolation trench (51) that laterally surrounds at least one device region (311-314; 321-323) in the die region (31). (331-333) and extends vertically from the first surface (111) through the first semiconductor layer (110) to the insulating layer (130).

11. The method of claim 10, wherein the isolation structure (5) further comprises: Insulation layer (52) covering the sidewalls and bottom of the isolation trench (51); as well as A filling layer (53) that at least partially fills the space defined by the insulating layer (52) in the isolation trench (51).

12. The method according to claim 11, The filling layer (53) comprises a conductive material.

13. The method according to any one of claims 6 to 12, The formation of the at least one semiconductor device (4; 41, 42, 43) includes forming the at least one semiconductor device (4; 41, 42, 43) in the at least one device region (311, 312, 313, 314).

14. The method according to any one of claims 10 to 13, The separation trench (21) and the isolation trench (51) are formed by the same process.

15. The method according to claim 14, The passivation layer (22) of the separation structure (2) and the insulating layer (52) of the isolation structure (5) are formed by the same process.

16. The method according to any one of claims 1 to 15, The sacrificial layer (120) is a semiconductor layer.

17. A semiconductor die having a shape different from a rectangular shape.

18. The semiconductor die of claim 17, wherein the semiconductor die comprises at least five corners.

19. The semiconductor die of claim 18, wherein the corner is a rounded corner.

20. The semiconductor die according to claim 18 or 19, The at least five corners include at least five exterior corners (341-345; 351-356) and at least one interior corner (346; 357, 358).

21. The semiconductor die according to claim 20, The semiconductor die is L-shaped or U-shaped.

22. The semiconductor die according to any one of claims 17 to 21, wherein the semiconductor die includes a dielectric layer (22) covering the semiconductor die sidewalls forming the shape of the semiconductor die.

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