Chip with multi-stage annular shallow trench isolation structure silicon through hole

Abstract

The invention belongs to the technical field of semiconductors, and discloses a chip with a multi-stage annular shallow trench isolation structure silicon through hole. The chip comprises a silicon wafer, a through hole arranged in the silicon wafer and a multi-stage annular shallow trench isolation structure arranged on the silicon wafer, an insulating layer and a conductor layer are sequentially arranged in the through hole from the hole wall to the center; the multi-stage annular shallow trench isolation structure comprises at least two annular shallow trenches which are arranged from inside to outside, are coaxial with the through hole and are in direct contact with the side walls, and filling materials filled in the annular shallow trenches; and the depths of the annular shallow grooves are different. The chip is low in thermal stress level, small in high stress area range and simple in preparation process.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a chip with a multi-level annular shallow trench isolation structure through-silicon via. Background Technology

[0002] Three-dimensional integrated circuit (3D-IC) packaging, achieved by vertically stacking chips, has become a key technology for improving device performance, increasing integration density, and optimizing space utilization. However, as chip and package sizes continue to shrink, the limited silicon area significantly restricts the possibility of further increasing integration density. Furthermore, the realization of high-density ICs has brought about numerous thermomechanical reliability issues, particularly thermal stress. Therefore, effectively increasing the functional area of ​​the chip while simultaneously ensuring thermomechanical reliability has become a critical challenge for the continued development of 3D-IC technology.

[0003] As one of the core technologies for realizing 3D-IC, through-silicon vias (TSVs) provide high aspect ratio vertical interconnect paths, thereby shortening the signal transmission distance between components on different chips and significantly reducing latency, power consumption, and circuit footprint. The reliability of TSVs directly determines the stability and performance of the entire 3D-IC package. Due to the significant mismatch in thermal expansion coefficients between copper (Cu), silicon dioxide (SiO2), and silicon (Si) wafers, TSVs generate significant thermal stress when subjected to temperature changes. These thermal stresses lead to mechanical stress concentration within the material, causing various reliability issues such as delamination, protrusions, and cracks, and in severe cases, even device failure. Furthermore, due to the piezoresistive effect, the thermal stress caused by TSVs alters the carrier mobility in the silicon wafer surrounding the via, affecting the electrical performance of semiconductor devices, reducing their efficiency, and even causing irreversible performance degradation. Therefore, solving the thermal stress problem caused by TSVs has become one of the key research directions for improving the reliability of 3D-IC technology.

[0004] CN103378028A discloses a semiconductor structure with a stress protection structure, including a substrate, a stress generating element, and a stress protection device. The substrate has a first surface and a second surface, which are disposed opposite to each other. The stress generating element is disposed in the substrate. The stress protection structure is disposed on one side of the first surface of the substrate, surrounds the stress generating element, and has a sealed air space inside the stress protection structure.

[0005] While the aforementioned applications and existing technologies can reduce the thermal stress generated by through-silicon vias (TSVs) to some extent, thereby improving device integration and reliability, the stress protection structures involved in these applications suffer from small diameters and high aspect ratios. This not only increases process complexity and manufacturing difficulty but also introduces numerous process challenges. Small diameter and high aspect ratio structures tend to lead to reduced etching efficiency, increased sidewall roughness, and decreased etching quality. Furthermore, ensuring the uniformity of the entire structure is difficult, resulting in localized defects or performance differences. In addition, the stress protection structure itself has a complex design, further increasing the overall process implementation difficulty.

[0006] Therefore, it is necessary to design a three-dimensional integrated circuit chip with silicon through-holes that has low thermal stress level, small high stress area, and simple fabrication process. Summary of the Invention

[0007] The purpose of this invention is to at least partially solve the above-mentioned technical problems and provide a chip with a multi-stage annular shallow trench isolation structure silicon via. This chip adopts a multi-stage annular shallow trench isolation structure silicon via, which has the characteristics of low thermal stress level and small high stress area.

[0008] In a first aspect, the present invention provides a chip having a multi-stage annular shallow trench isolation structure via silicon vias, the chip comprising:

[0009] It includes a silicon wafer, a via disposed in the silicon wafer, and a multi-stage annular shallow trench isolation structure disposed on the silicon wafer;

[0010] An insulating layer and a conductive layer are sequentially arranged from the hole wall to the center inside the through hole;

[0011] The multi-stage annular shallow trench isolation structure includes at least two annular shallow trenches arranged from the inside out, which are coaxial with the through hole and directly contact the sidewalls, and a filling material filled in the annular shallow trenches. The Young's modulus and coefficient of thermal expansion of the filling material are lower than those of the silicon wafer and the conductor layer.

[0012] The depths of each of the aforementioned annular shallow trenches are different.

[0013] In some embodiments of the present invention, the silicon wafer is made of silicon.

[0014] In some embodiments of the present invention, the inner edge of the annular shallow trench near the central axis of the through hole of the multi-stage annular shallow trench isolation structure has a preset distance between it and the outer wall of the conductor layer.

[0015] In some embodiments of the present invention, the preset spacing is 1-10 μm.

[0016] In some embodiments of the present invention, the widths of the various annular shallow trenches are the same, resulting in optimal performance.

[0017] In some embodiments of the present invention, the width of the annular shallow groove is 0.5-4 μm and the depth is 1-15 μm.

[0018] In some embodiments of the present invention, the number of the annular shallow grooves is 2-4.

[0019] In some embodiments of the present invention, the number of annular shallow grooves is 2, the width of each annular shallow groove is 3μm, the depth of the annular shallow groove near the central axis of the through hole is 1μm, and the depth of the annular shallow groove away from the central axis of the through hole is 2μm, which achieves optimal performance.

[0020] In some embodiments of the present invention, the conductor layer is a cylinder with a base radius of 1-20 μm.

[0021] In some embodiments of the present invention, the thickness of the insulating layer is 0.1-5 μm.

[0022] In some embodiments of the present invention, the thickness of the silicon wafer is 40-100 μm;

[0023] In some embodiments of the present invention, the height of the silicon wafer, the conductor layer and the insulating layer is 50-300 μm.

[0024] In some embodiments of the present invention, the conductor layer is one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb, W and alloys thereof, polymer conductors, or doped polycrystalline silicon, and the insulating layer is one of silicon dioxide, benzocyclobutene, and polyimide.

[0025] In some embodiments of the present invention, the filler material is silicon dioxide.

[0026] A chip with a multi-stage annular shallow trench isolation structure via silicon via according to an embodiment of the present invention has at least one of the following advantages:

[0027] (1) By etching multiple annular shallow trench isolation structures coaxial with the vias in the silicon wafer region and reasonably setting the size of these trenches, the thermal stress generated by the vias can be effectively reduced, the high-stress area can be reduced, thereby improving the integration and thermomechanical reliability of the vias. These shallow trench isolation structures only require local optimization of the silicon wafer surface layer. Compared with the stress protection structure etched deep to the bottom of the silicon wafer near the vias, this allows for the integration of more devices and components in the silicon wafer.

[0028] (2) It avoids the complex process problems caused by deep trench stress protection structures, thereby simplifying the manufacturing process and reducing the difficulty of the process. In addition, the structure also reserves more space deep in the silicon wafer, which is conducive to integrating more functional devices and improving the overall integration and manufacturability. Attached Figure Description

[0029] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0030] Figures 1-7 This is a schematic diagram of the structure after each step of the fabrication method of the chip with a second-order annular shallow trench isolation structure silicon via provided in Embodiment 1 of the present invention.

[0031] Figure 8 This is a three-dimensional structural diagram of a chip with a second-order annular shallow trench isolation structure through-silicon via provided in Embodiment 1 of the present invention;

[0032] Figure 9 This is a cross-sectional view of a chip with a two-stage annular shallow trench isolation structure via silicon via provided in Embodiment 1 of the present invention;

[0033] Figure 10 This is a cross-sectional view of a chip with a 3-stage annular shallow trench isolation structure via provided in Embodiment 2 of the present invention;

[0034] Figure 11 This is a cross-sectional view of a chip with a 4-stage annular shallow trench isolation structure via provided in Embodiment 3 of the present invention.

[0035] Figure 12 This is a three-dimensional structural diagram of a chip with a single-stage annular shallow trench isolation structure through-silicon via provided as a comparative example of the present invention.

[0036] Figure 13 yes Figure 12 The image shows a cross-sectional view of a chip with a single-stage annular shallow trench isolation structure via silicon vias.

[0037] Figure 14 yes Figure 12 The stress cloud diagram of KOZ for characterizing a chip with a single-stage annular shallow trench isolation structure through-silicon via is shown.

[0038] Figure 15 This is a KOZ stress cloud diagram characterizing a chip with a second-order annular shallow trench isolation structure silicon via provided in Embodiment 1 of the present invention.

[0039] Figure 16 This is a KOZ stress cloud diagram characterizing a chip with a 3-order annular shallow trench isolation structure silicon via provided in Embodiment 2 of the present invention.

[0040] Figure 17 This is a KOZ stress cloud diagram characterizing a chip with a 4-order annular shallow trench isolation structure through-silicon via provided in Embodiment 3 of the present invention. Detailed Implementation

[0041] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0042] It should be noted that the terms used in this application are generally those commonly used by those skilled in the art. If there is any inconsistency with commonly used terms, the terms used in this application shall prevail.

[0043] In this paper, the term "etching" refers to the process of selectively removing unwanted material from the surface of a silicon wafer using chemical or physical methods; the term "photolithography" refers to projecting a pattern onto a photoresist surface using ultraviolet light or other types of light sources through a mask or projection system, and using the chemical reaction of the photoresist to form a specific pattern; the term "chemical mechanical polishing" refers to planarizing a wafer during processing, combining chemical action and mechanical polishing techniques to remove micron- or nanometer-level material from the surface of the polished workpiece, making its surface highly planar.

[0044] In this paper, the term "thermal oxidation" refers to the process of growing a silicon dioxide (SiO2) film on the silicon surface by exposing the silicon wafer to an oxygen or water vapor environment at high temperature through a chemical reaction; the term "electroplating" refers to the process of reducing metal ions from an electrolyte and depositing them on the surface of a conductive object by using an electric current; the term "high-stress zone" refers to a region where no device is allowed to be placed in order to ensure that the high stress generated by the through-silicon via does not significantly affect the device performance, and the standard is set to control the change in carrier mobility caused by stress to within 5%.

[0045] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0046] The embodiments of this application will be described in detail below.

[0047] Example 1

[0048] See Figure 1-7 The present invention provides a method for fabricating a chip with a second-order annular shallow trench isolation structure silicon via according to Embodiment 1 of the present invention, comprising the following steps:

[0049] Step 1, see Figure 1 Photoresist is applied to the surface of silicon wafer 10, and the position of the annular shallow trench 11 is defined by photolithography. An annular shallow trench 11 close to the central axis of the via is fabricated on silicon wafer 10 by etching.

[0050] Step 2, see Figure 2 Silica material is deposited in an annular shallow trench 11 near the central axis of the through hole using chemical vapor deposition, and excess filler material is removed using chemical mechanical polishing to ensure a smooth surface.

[0051] Step 3, see Figure 3 Repeat steps S1 and S2 above to obtain an annular shallow trench 12 far from the central axis of the through hole and fill it with silica material.

[0052] Step 4, see Figure 4 Photoresist is coated again on the silicon wafer 10. The location of the through-hole (TSV) is determined by photolithography. The TSV holes are made in the silicon wafer 10 by etching. After etching, the photoresist is removed and the surface of the silicon wafer 10 is cleaned.

[0053] Step 5, see Figure 5 An insulating layer 30 is deposited on the sidewall of the TSV aperture;

[0054] Step 6, see Figure 6 Copper is filled into the TSV holes and chemical mechanical polishing is performed to remove excess conductor layer 20;

[0055] Step 7, see Figure 7 Wafer thinning: Thinning is performed on the other side of the fabricated and filled TSV to convert the TSV blind via into a through via, resulting in a chip 100 with a second-order annular shallow trench isolation structure silicon through via.

[0056] Specifically, the etching in steps S1 and S4 employs deep reactive ion etching.

[0057] In step S5, the insulating layer 30 is deposited using a thermal oxidation method.

[0058] In step S6, copper filling is typically achieved using electroplating.

[0059] The three-dimensional structure diagram of the chip 100 with the second-order annular shallow trench isolation structure silicon via is shown below. Figure 8 As shown, the cross-sectional view is as follows Figure 9 As shown.

[0060] The chip 100 has a two-stage annular shallow trench isolation structure via silicon via. The chip 100 mainly comprises a silicon wafer 10, a conductor layer 20, and an insulating layer 30. Specifically, the upper surface of the silicon wafer 10 is provided with annular shallow trenches 11 and 12 that are coaxial with the conductor layer 20 and directly contact the sidewalls, and the annular shallow trenches 11 and 12 are filled with silicon dioxide.

[0061] The annular shallow trench 11 has a width of 3 μm and a depth of 1 μm, and the distance between the inner edge of the annular shallow trench 11 and the edge of the conductor layer 20 is 1 μm; the annular shallow trench 12 has a width of 3 μm and a depth of 2 μm; the radius of the conductor layer 20 is 5 μm; the insulating layer 30 is arranged around the central conductor layer 20 and has a thickness of 0.1 μm; the thickness of the silicon wafer is 45 μm; the height of the silicon wafer 10, the conductor layer 20 and the insulating layer 30 is the same, all being 50 μm.

[0062] Example 2

[0063] A cross-sectional view of the chip 200 with a three-stage annular shallow trench isolation structure via is shown below. Figure 10 As shown.

[0064] The chip 200 has a three-tiered annular shallow trench isolation structure via silicon vias. The chip 200 mainly comprises a silicon wafer 210, a conductor layer 220, and an insulating layer 230. Specifically, the upper surface of the silicon wafer 210 is provided with annular shallow trenches 211, 212, and 213 that are coaxial with the conductor layer 220 and directly contact its sidewalls. The annular shallow trenches 211, 212, and 213 are filled with silicon dioxide.

[0065] The annular shallow trench 211 has a width of 2μm and a depth of 3μm; the annular shallow trench 212 has a width of 3μm and a depth of 1μm; the annular shallow trench 213 has a width of 1μm and a depth of 2μm, and other parameters are the same as in Example 1.

[0066] Example 3

[0067] A cross-sectional view of the chip 300 with a 4-stage annular shallow trench isolation structure via is shown below. Figure 11 As shown.

[0068] The chip 300 has a four-stage annular shallow trench isolation structure via silicon vias. The chip 300 mainly comprises a silicon wafer 310, a conductor layer 320, and an insulating layer 330. Specifically, the upper surface of the silicon wafer 310 has annular shallow trenches 311-314 that are coaxial with the conductor layer 320 and directly contact its sidewalls. The annular shallow trenches 311-314 are filled with silicon dioxide.

[0069] The annular shallow trench 311 has a width of 1 μm and a depth of 4 μm; the annular shallow trench 312 has a width of 4 μm and a depth of 1 μm; the annular shallow trench 313 has a width of 3 μm and a depth of 3 μm; the annular shallow trench 314 has a width of 2 μm and a depth of 2 μm, and other parameters are the same as in Example 1.

[0070] Comparative example (a chip with a single-stage annular shallow trench isolation structure via silicon via)

[0071] The three-dimensional structure diagram of the chip 400 with a single-stage annular shallow trench isolation structure silicon via is shown below. Figure 12 As shown, the cross-sectional view is as follows Figure 13 As shown.

[0072] The chip 400 has a single-stage annular shallow trench isolation structure via. This chip 400 also includes a silicon wafer 410, a conductor layer 420, an insulating layer 430, and an annular shallow trench 411 coaxial with the conductor layer 420 on the upper surface of the silicon wafer 410. The structural difference between this chip 400 and the chip 100 with a two-stage annular shallow trench isolation structure via provided in Embodiment 1 of the present invention lies in the order and dimensional parameters of the shallow trench isolation structure formed on the silicon wafer to reduce thermal stress. Considering that other structural configurations are the same as those of the chip 100 with a two-stage annular shallow trench isolation structure via in the embodiment of the present invention, its structural parameters and fabrication process details will not be discussed further.

[0073] It should be noted that, in order to conduct the following comparative analysis, in Figures 8-13 The differences between the chip 400 with a single-order annular shallow trench isolation structure, the chip 100 with a second-order annular shallow trench isolation structure, the chip 200 with a third-order annular shallow trench isolation structure, and the chip 300 with a fourth-order annular shallow trench isolation structure in the embodiments of the present invention lie in the order and size parameters of the shallow trench isolation structure on the silicon wafer; all other structural parameters are the same.

[0074] Simulation analysis was performed using ANSYS Workbench software on chip 400 with a single-order annular shallow trench isolation structure silicon via (STI) and chips 100, 200, and 300 of the embodiments of the present invention with two-order annular shallow trench isolation structure STIs, respectively. The results are as follows: Figure 14-17 The stress contour plot shown represents the KOZ.

[0075] Figure 14 The stress cloud diagram characterizing the KOZ of the chip 400 with a single-stage annular shallow trench isolation structure provided as a comparative example is shown. As can be seen from the figure, the KOZ is maximum at 11.6 μm when a PMOS is placed and the transistor channel is parallel to the radial stress.

[0076] Figure 15 The stress cloud diagram characterizing the KOZ of the chip 100 with a second-order annular shallow trench isolation structure through-silicon via provided in Embodiment 1 of the present invention. The comparison shows that when a PMOS is placed and the transistor channel is parallel to the radial stress, the KOZ decreases to 7.2 μm (a reduction of 37.9%).

[0077] Figure 16 The stress cloud diagram characterizing the KOZ of the chip 200 with a three-stage annular shallow trench isolation structure via provided in Embodiment 2 of the present invention. Compared with the chip 400 with a single-stage annular shallow trench isolation structure via, it was found that when a PMOS was placed and the transistor channel was parallel to the radial stress, the KOZ was reduced to 8.8 μm (a reduction of 24.1%).

[0078] Figure 17 The stress cloud diagram characterizing the KOZ of the chip 300 with a 4-order annular shallow trench isolation structure through-silicon via provided in Embodiment 3 of the present invention is shown. The comparison shows that when a PMOS is placed and the transistor channel is parallel to the radial stress, the KOZ decreases to 8.1 μm (a reduction of 30.2%).

[0079] according to Figure 14-17 It is evident that among chips with multi-level annular shallow trench isolation structures in vias, those with annular shallow trench isolation structure order of 2 exhibit the best performance. Among chips with two-level annular shallow trench isolation structures in vias, the best performance is achieved when the width of each annular shallow trench is 3 μm, the depth of the annular shallow trench near the via's central axis is 1 μm, and the depth of the annular shallow trench farther from the via's central axis is 2 μm. Compared to chips with single-level annular shallow trench isolation structures in vias, when a PMOS is placed and the transistor channel is parallel to the radial stress, the KOZ is reduced to 7.2 μm, a reduction of 37.9%.

[0080] A multi-level annular shallow trench structure with depth gradients is designed around the via region on the silicon wafer surface and filled with a material whose coefficient of thermal expansion and Young's modulus are significantly lower than those of the silicon wafer. Through continuous variation of its geometric parameters, a non-uniform material system with spatially gradient performance is constructed, creating a gradient stress buffer layer. Under thermal load, this gradient distribution of material properties induces complex multi-source stress fields between different material interfaces. Utilizing the superposition effect of stress fields in space, the amplitude and range of stress regulation can be expanded, and thermal stress can be significantly reduced through the destructive superposition of some stress components, greatly reducing the high-stress zone (KOZ) around the TSV and improving integration density. Furthermore, the gradient stress buffer design slows down stress transmission by increasing the stress transmission path, reducing stress fatigue accumulation during thermal cycling, and decreasing the probability of microcrack initiation, thereby significantly improving the long-term reliability and lifespan of the device.

[0081] While some embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A chip with a multi-stage annular shallow trench isolation structure via silicon vias, characterized in that, It includes a silicon wafer, a via disposed in the silicon wafer, and a multi-stage annular shallow trench isolation structure disposed on the silicon wafer; An insulating layer and a conductive layer are sequentially arranged from the hole wall to the center inside the through hole; The multi-stage annular shallow trench isolation structure includes at least two annular shallow trenches arranged from the inside out, which are coaxial with the through hole and directly contact the sidewalls, and a filling material filled in the annular shallow trenches. The Young's modulus and thermal expansion coefficient of the filling material are both lower than those of the silicon wafer and the conductor layer. The depths of each of the aforementioned annular shallow trenches are different.

2. The chip according to claim 1, characterized in that, The multi-stage annular shallow trench isolation structure has a preset distance between the inner edge of the annular shallow trench near the central axis of the through hole and the outer wall of the conductor layer.

3. The chip according to claim 1, characterized in that, The preset spacing is 1-10μm.

4. The chip according to claim 1, characterized in that, Each of the aforementioned annular shallow trenches has the same width, resulting in optimal performance.

5. The chip according to claim 1, characterized in that, The width of the annular shallow groove is 0.5-4μm and the depth is 1-15μm.

6. The chip according to claim 1, characterized in that, The number of the annular shallow grooves is 2-4.

7. The chip according to claim 1, characterized in that, The number of annular shallow grooves is 2, the width of each annular shallow groove is 3μm, the depth of the annular shallow groove close to the central axis of the through hole is 1μm, and the depth of the annular shallow groove far from the central axis of the through hole is 2μm, which results in optimal performance.

8. The chip according to claim 1, characterized in that, The conductor layer is one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb, W and their alloys, polymer conductors, or doped polycrystalline silicon, and the insulating layer is one of silicon dioxide, benzocyclobutene and polyimide.

9. The chip according to claim 1, characterized in that, The filler material is silicon dioxide.

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