Protection circuit, protection device, chip, circuit board and electronic equipment

Abstract

The invention relates to the technical field of integrated circuits, and discloses a protection circuit, a protection device, a chip, a circuit board and electronic equipment. The protection circuit comprises a trigger unit, a driving unit, a positive feedback unit and a discharge unit, the trigger unit can start the positive feedback unit while starting the driving unit. When the positive feedback unit is in the open state, the positive feedback unit ensures that the capacitor has no voltage rise by discharging charges accumulated on the capacitor in the trigger unit, so that the driving unit keeps the open state, and then the driving unit can continuously output sufficiently high driving voltage to the discharge unit, so that the circuit area and the cost do not need to be increased; therefore, it can be ensured that the discharge unit can continuously discharge the overcurrent within the pulse time of the overvoltage pulse. Moreover, the trigger voltage of the discharge unit can be adaptive to the working voltage, the normalization and simplification of the protection circuit are realized, and the protection circuit is suitable for a multi-power-supply scene.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a protection circuit, protection device, chip, circuit board, and electronic device. Background Technology

[0002] Electrostatic discharge (ESD) and electrical overstress (EOS) events are increasingly threatening the reliability of integrated circuits, making ESD / EOS protection circuit design a crucial part of integrated circuit design. For example, in power supply scenarios, an ESD / EOS protection circuit is needed between the power supply line and ground line for the protected device. This circuit discharges the overcurrent generated by ESD / EOS events on the power supply line. In other words, the ESD / EOS protection circuit clamps abnormal overvoltages on the power supply line, limiting the voltage within the safe tolerance range of the protected device and preventing damage.

[0003] Currently, there are two common types of ESD / EOS protection circuits / devices. One type is fixed threshold voltage triggered protection devices, which include a variety of devices, each with its own advantages. However, because the trigger voltage is fixed, a single design can only be used to protect a circuit with a specific operating voltage, limiting its flexibility. The other type is a pulse-time related structure, such as the common RC-triggered clamping circuit. This ESD / EOS protection circuit detects ESD / EOS events by setting a resistor-capacitor (RC) circuit and triggers a bleeder to discharge the ESD / EOS current when an ESD / EOS event is detected. This protection circuit can respond to ESD / EOS pulses at different operating voltages, while remaining closed during normal operation of the protected circuit, without affecting its normal operation. However, currently, increasing the time constant of the RC circuit is necessary to ensure continuous and effective discharge of ESD / EOS current during ESD / EOS events, which significantly increases the area and cost of the protection circuit. Furthermore, an excessively large RC time constant can cause false triggering, affecting the normal power-on and operation of the protected circuit. Summary of the Invention

[0004] This application provides a protection circuit, protection device, chip, circuit board, and electronic device that can ensure continuous discharge of overcurrent during ESD / EOS events, clamp the voltage at an extremely low level, fully protect the safety of the protected circuit, and reduce the area and cost of the protection circuit. In addition, the trigger voltage is adapted to the operating voltage of the protected circuit, which can realize the normalization and simplification of the protection circuit and is compatible with multiple power supply scenarios.

[0005] In a first aspect, embodiments of this application provide a protection circuit, including a trigger unit, a drive unit, a positive feedback unit, and a discharge unit; wherein, the discharge unit is used to connect to the protected device protected by the protection circuit, and is used to turn on after obtaining a drive voltage under an ESD / EOS pulse, to discharge the overcurrent corresponding to the overvoltage pulse, and to clamp the overvoltage; the trigger unit is used to turn on the drive unit so that the drive unit outputs a drive voltage to the discharge unit when an overvoltage pulse is detected and the overvoltage pulse meets the turn-on condition of the drive unit, and to turn on the positive feedback unit; the positive feedback unit is used to control the drive unit to maintain the turn-on state of the drive unit during the pulse time corresponding to the overvoltage pulse and to continuously output a drive voltage to the discharge unit when the drive unit is in the turn-on state.

[0006] It is understandable that the trigger unit can simultaneously activate the positive feedback unit and the drive unit, with the positive feedback unit then entering the on state. In the on state, the positive feedback unit discharges the charge accumulated on the capacitor in the trigger unit, ensuring no voltage rise in the capacitor and keeping the drive unit on. This allows the drive unit to continuously output a sufficiently high drive voltage to the discharge unit, ensuring that the discharge unit can continuously discharge the overcurrent within the pulse duration of the overvoltage pulse. This eliminates the need to increase the RC time constant of the trigger unit, reducing the area and cost of the protection circuit.

[0007] Furthermore, even during normal operation of the protected circuit, once the capacitor of the trigger unit has been charged to the same level as the operating voltage, the activation condition of the drive unit can be met in the early rising stage of the overvoltage pulse, which means that the positive feedback unit can be activated. The positive feedback unit discharges the charge accumulated in the capacitor, so that the trigger voltage of the discharge unit is only slightly higher than the operating voltage. This allows the trigger voltage of the discharge unit to adapt to the operating voltage, realizing the normalization and simplification of the protection circuit. This makes the protection circuit applicable to multi-power supply scenarios, providing ESD / EOS protection for protected devices with different operating voltages.

[0008] In some embodiments of the first aspect described above, the positive feedback unit includes a timing module and a feedback module; wherein, the timing module is used to trigger and control the opening and closing of the feedback module when the driving unit is in the on state; the feedback module is used to control the driving unit to continuously output driving voltage to the bleeder unit when in the on state, and to control the driving unit to stop outputting driving voltage to the bleeder unit when in the off state.

[0009] The timing module serves two purposes: to trigger positive feedback and to shut it down, so that the discharge unit is turned off after the ESD / EOS energy has passed, thus avoiding affecting the normal operation of the protected device.

[0010] In some embodiments of the first aspect described above, the protected device includes a first protection terminal and a second protection terminal, and an overvoltage pulse is generated on the first protection terminal or the second protection terminal; the triggering unit, the driving unit, and the bleedering unit are all connected to the first protection terminal and the second protection terminal, and the output terminal of the triggering unit is connected to the input terminal of the driving unit, the output terminal of the driving unit is connected to the control terminal of the bleedering unit and the input terminal of the timing module in the positive feedback unit, and the output terminal of the timing module is connected to the control terminal of the feedback module; and the feedback module also includes a first terminal and a second terminal, the first terminal is connected to the output terminal of the triggering unit, and the second terminal is connected to the first protection terminal or the second protection terminal.

[0011] The first protection terminal and the second protection terminal can be the positive power supply terminal and the negative power supply terminal of the protected device, respectively. Alternatively, the first protection terminal and the second protection terminal can be any two ports on the protected device that may have ESD / EOS discharge loops.

[0012] In some embodiments of the first aspect described above, the triggering unit is a resistor-capacitor (RC) circuit.

[0013] In some embodiments of the first aspect described above, the triggering unit includes a first resistor and a first capacitor connected in series, and the output terminal of the triggering unit is the common terminal of the first resistor and the first capacitor; the first resistor also includes a third terminal, and the first capacitor also includes a fourth terminal, and the third terminal and the fourth terminal are respectively connected to the first protection terminal and the second protection terminal; the second terminal of the feedback module is connected to the fourth terminal.

[0014] In some embodiments of the first aspect described above, the feedback module includes a first metal-oxide-semiconductor field-effect transistor; the control terminal of the feedback module is the gate of the first metal-oxide-semiconductor field-effect transistor, the first terminal of the feedback module is the drain of the first metal-oxide-semiconductor field-effect transistor, and the second terminal of the feedback module is the source of the first metal-oxide-semiconductor field-effect transistor.

[0015] In some embodiments of the first aspect described above, the timing module is a resistor-capacitor (RC) circuit.

[0016] In some embodiments of the first aspect described above, the timing module includes a second resistor and a second capacitor connected in series, and the output terminal of the timing module is the common terminal of the second resistor and the second capacitor; the second resistor also includes a fifth terminal, which is connected to the first protection terminal or the second protection terminal; the second capacitor also includes a sixth terminal, which is the input terminal of the timing module.

[0017] In some embodiments of the first aspect described above, the driving unit includes a single-stage driving circuit or an N-stage driving circuit, where N is an odd number greater than 1; each stage of the N-stage driving circuit includes a second metal-oxide-semiconductor field-effect transistor and a first resistor network, wherein one end of the first resistor network is connected in series with the drain of the second metal-oxide-semiconductor field-effect transistor, and the source of the second metal-oxide-semiconductor field-effect transistor and the other end of the first resistor network are respectively connected to one of the first protection terminal and the second protection terminal.

[0018] In some embodiments of the first aspect described above, the driving unit includes a primary driving circuit, wherein the source of the second metal-oxide-semiconductor field-effect transistor in the primary driving circuit is the input terminal of the driving unit, and the drain of the second metal-oxide-semiconductor field-effect transistor is the output terminal of the driving unit.

[0019] In some embodiments of the first aspect described above, the driving unit includes an N-stage driving circuit, wherein the source of the second metal-oxide-semiconductor field-effect transistor of the first stage driving circuit in the N-stage driving circuit is the input terminal of the driving unit, and the drain of the second metal-oxide-semiconductor field-effect transistor of the Nth stage driving circuit in the N-stage driving circuit is the output terminal of the driving unit; and the channel polarities of the two second metal-oxide-semiconductor field-effect transistors in adjacent driving circuits are different.

[0020] In some embodiments of the first aspect described above, the positive feedback unit further includes a driving module, wherein the output terminal of the timing module is connected to the control terminal of the feedback module through the driving module; and the driving module is also connected to the input terminal of the timing module, as well as the first protection terminal or the second protection terminal.

[0021] In some embodiments of the first aspect described above, the driving module includes an M-level driving circuit, where M is an even number greater than or equal to 2; each level of the M-level driving circuit includes a third metal-oxide-semiconductor field-effect transistor and a second resistor network, wherein one end of the second resistor network is connected in series with the drain of the third metal-oxide-semiconductor field-effect transistor, and the source of the third metal-oxide-semiconductor field-effect transistor and the other end of the second resistor network are respectively connected to the input terminal of the timing module, a first protection terminal, and a second protection terminal.

[0022] In some embodiments of the first aspect described above, the discharge unit includes a fourth metal-oxide-semiconductor field-effect transistor, the gate of the fourth metal-oxide-semiconductor field-effect transistor is the control terminal of the discharge unit, and the source and drain of the fourth metal-oxide-semiconductor field-effect transistor are respectively connected to the first protection terminal and the second protection terminal.

[0023] The channel polarity of the first / second / third / fourth metal-oxide-semiconductor field-effect transistor is selected according to the actual circuit design.

[0024] Secondly, embodiments of this application provide a protection device that includes at least a portion of the protection circuit described in the first aspect.

[0025] In some embodiments of the second aspect described above, the protection device is integrated by at least a portion of the protection circuitry.

[0026] In some embodiments of the second aspect described above, the protection device further includes a circuit board on which a plurality of electronic components are disposed, the plurality of electronic components being used to overlap to form at least a portion of the protection circuit.

[0027] Thirdly, embodiments of this application provide a chip, which includes the protection circuit and the protected device described in the first aspect, with the protection circuit and the protected device connected together.

[0028] Fourthly, embodiments of this application provide a circuit board on which the protection circuit and the protected device described in the first aspect are provided, and the protection circuit and the protected device are connected.

[0029] Fifthly, embodiments of this application provide an electronic device, which includes a protected device and the protection circuit described in the first aspect, wherein the protection circuit is connected to the protected device. Attached Figure Description

[0030] Figure 1A This is a block diagram of a protection circuit 10 provided in an embodiment of this application;

[0031] Figure 1B This is a schematic diagram of the structure of a protection circuit 10 provided in an embodiment of this application;

[0032] Figure 2A This is a block diagram of a protection circuit 00 provided in an embodiment of this application;

[0033] Figure 2B This is an architecture diagram of a power supply network in an electronic device provided in an embodiment of this application;

[0034] Figure 3 This is a schematic diagram of the structure of a protection circuit 30 provided in an embodiment of this application;

[0035] Figure 4 This is a schematic diagram of a test circuit for a protection circuit 30 provided in an embodiment of this application;

[0036] Figure 5 This is provided by the embodiments of this application. Figure 4 The simulation result of the test circuit shown is under one test parameter.

[0037] Figure 6 This is provided by the embodiments of this application. Figure 4 The simulation result of the test circuit shown is under another set of test parameters;

[0038] Figure 7 This is provided by the embodiments of this application. Figure 4 The simulation result of the test circuit shown is under another set of the same test parameters.

[0039] Figure 8 This is a schematic diagram of a test circuit for another protection circuit 30 provided in an embodiment of this application;

[0040] Figure 9 This is provided by the embodiments of this application. Figure 8 The simulation result of the test circuit shown is under one test parameter.

[0041] Figure 10 This is a schematic diagram of a packaging method for a protection circuit provided in an embodiment of this application;

[0042] Figure 11 This is a schematic diagram of a protection circuit 40 provided in an embodiment of this application;

[0043] Figure 12 This is a schematic diagram of a test circuit for a protection circuit 40 provided in an embodiment of this application;

[0044] Figure 13 This is provided by the embodiments of this application. Figure 12 The simulation result of the test circuit shown is under one test parameter.

[0045] Figure 14 This is provided by the embodiments of this application. Figure 12 The simulation result of the test circuit shown is under another set of test parameters;

[0046] Figure 15 This is a schematic diagram of a protection circuit 50 provided in an embodiment of this application;

[0047] Figure 16 This is a schematic diagram of a protection circuit 60 provided in an embodiment of this application;

[0048] Figure 17 This is a schematic diagram of a protection circuit 170 provided in an embodiment of this application;

[0049] Figure 18 This is a schematic diagram of a protection circuit 180 provided in an embodiment of this application. Detailed Implementation

[0050] The illustrative embodiments of this application include, but are not limited to, protection circuits, protection devices, chips, circuit boards, and electronic devices.

[0051] First, the relevant abbreviations involved in this application will be explained.

[0052] NMOS transistor: N-channel metal oxide semiconductor field-effect transistor (NMOS).

[0053] PMOS transistor: P-channel metal oxide semiconductor field-effect transistor (PMOS).

[0054] Please see Figure 1A and Figure 1B , Figure 1A This is a block diagram of an ESD / EOS protection circuit (hereinafter referred to as the protection circuit) 10 provided in an embodiment of this application. Figure 1B This is a schematic diagram of the structure of a protection circuit 10 provided in an embodiment of this application. For example... Figure 1A and Figure 1B As shown, a protection circuit 10 and a protected device 20 are provided between power line 10a (an example of the first protection terminal of this application) and ground line 10b (an example of the second protection terminal of this application). The protection circuit 10 includes a trigger unit 101, a drive unit 102, and a discharge unit 103. When an overvoltage pulse of an ESD / EOS event occurs on power line 10a, the trigger unit 101 and drive unit 102 in the protection circuit 10 can detect the overvoltage pulse and activate the discharge unit 103 to discharge the ESD / EOS current, thus preventing the overvoltage pulse from damaging the protected device 20. The overvoltage pulse is a pulse signal whose amplitude exceeds the normal operating voltage of the protected device 20.

[0055] Continue to refer to Figure 1BThe trigger unit 101 includes a resistor R1 (an example of a first resistor in this application) and a capacitor C1 (an example of a first capacitor in this application) connected in series. Resistor R1 is connected to power line 10a, and capacitor C1 is connected to ground line 10b. The drive unit 102 includes a PMOS transistor T1 (an example of a second metal-oxide-semiconductor field-effect transistor in this application) and a resistor R2 (an example of a first resistor network in this application). The discharge unit 103 includes an NMOS transistor T2 (an example of a fourth metal-oxide-semiconductor field-effect transistor in this application). The common terminal A of resistor R1 and capacitor C1 is connected to the gate (G) of PMOS transistor T1. The source (S) of PMOS transistor T1 is connected to power line 10a, and its drain (D) is connected to resistor R2. The other end of resistor R2 is connected to ground line 10b. The source (S) of NMOS transistor T2 is connected to ground line 10b, its drain (D) is connected to power line 10a, and its gate (G) is connected to the common terminal B of PMOS transistor T1 and resistor R2. It is understandable that the trigger unit 101 is an RC delay circuit, and the voltage change across capacitor C1 will have a time delay effect.

[0056] In a power-off scenario (power off, no operating voltage or signal applied to the entire circuit), the working principle of the above protection circuit 10 is as follows:

[0057] In a power-off scenario, if an overvoltage pulse of an ESD / EOS event with a duration less than the RC delay occurs on power line 10a, this ESD / EOS pulse has a very fast rise rate (e.g., the rise time of ESD is on the order of nanoseconds, such as 5-15 nanoseconds). That is, the overvoltage pulse has a short rise edge. Due to the RC delay effect, the voltage at common terminal A cannot keep up with the rise rate of the ESD / EOS voltage on power line 10a. Therefore, the voltage at common terminal A is close to 0V, meaning the ESD / EOS voltage is almost entirely applied across resistor R1. Since the source and gate of PMOS transistor T1 are respectively across resistor R1, the voltage drop across resistor R1 is V. R1 That is, the negative of the gate-source voltage Vgs of PMOS transistor T1, so that when the voltage drop V across resistor R1... R1 When the voltage exceeds the turn-on voltage of PMOS transistor T1 (i.e., the absolute value of the threshold voltage Vgs(th),) PMOS transistor T1 turns on, changing from high resistance to low resistance, and shares the ESD / EOS voltage with resistor R2 in series. Since the turn-on resistance Ron of PMOS transistor T1 is much smaller than that of resistor R2, resistor R2 will receive most of the voltage. That is, the drain terminal of PMOS transistor T1 outputs a high voltage close to the ESD / EOS voltage to the gate of NMOS transistor T2, making the gate-source voltage Vgs of NMOS transistor T2 greater than its threshold voltage, and thus NMOS transistor T2 turns on, bypassing the ESD / EOS current.

[0058] During normal power-on, the power supply line 10a gradually rises from 0V to the operating voltage of the protected device 20. The rise time of this operating voltage (milliseconds, typically greater than 1 millisecond) is much greater than the RC time constant of the trigger unit 101 (microseconds, for example, 0.1 to 1 microsecond). The RC time constant characterizes the charging time of capacitor C1; a larger RC time constant results in a longer charging time. Therefore, the voltage at the common terminal A keeps pace with the rise rate of the operating voltage on the power supply line 10a, and the voltage drop V across resistor R1... R1 The voltage will not exceed the turn-on voltage of PMOS transistor T1. Therefore, PMOS transistor T1 will not be turned on, and the voltage at the common terminal B is 0V. NMOS transistor T2 will also not be turned on, thus not affecting the normal operation of the protected device.

[0059] Therefore, the working principle of the protection circuit 10 can be simply understood as follows: Under normal power-on conditions, the output terminal of the trigger unit 101, i.e., the common terminal A, is at a high potential, and the output terminal of the drive unit 102, i.e., the common terminal B, is at a low potential. Neither PMOS transistor T1 nor NMOS transistor T2 is turned on. Under abnormal conditions, such as when an overvoltage pulse is detected, the common terminal A is at a low potential, the common terminal B is at a high potential, and PMOS transistor T1 and NMOS transistor T2 are turned on sequentially to discharge the ESD / EOS current.

[0060] However, during the continuous output of overvoltage pulses in an ESD / EOS event, especially when the duration of ESD / EOS is close to or even exceeds the RC constant, capacitor C1 will slowly charge, causing the voltage drop across resistor R1 to gradually decrease or even fall below the turn-on voltage of PMOS transistor T1. This makes it impossible for the output of drive unit 102 to output a sufficiently high drive voltage to NMOS transistor T2, resulting in insufficient channel opening of NMOS transistor T2, increased on-resistance, and a worse overvoltage clamping effect on power line 10a, making it unable to effectively discharge ESD / EOS current.

[0061] In some embodiments, during the continuous output of overvoltage pulses in an ESD / EOS event, to ensure that the NMOS transistor T2 can continuously and effectively discharge the ESD / EOS current, the RC time constant of the trigger unit 101 can be increased, so that there is essentially no voltage rise across capacitor C1 during the continuous output of overvoltage pulses in an ESD / EOS event. For example, the RC time constant needs to be much larger than the pulse width of the ESD / EOS overvoltage pulse. However, this requires a very large RC time constant, which will greatly increase the area and cost of the protection circuit 10.

[0062] Furthermore, as mentioned earlier, the rise time of the operating voltage is much longer than the RC time constant. Therefore, during the rise of the operating voltage, capacitor C1 will gradually charge until the voltage across its terminals reaches its initial voltage, which can be the operating voltage. If an ESD / EOS overvoltage pulse occurs after capacitor C1 is fully charged during the rise of the operating voltage, because the voltage at the beginning of the ESD / EOS overvoltage pulse is relatively large, even if capacitor C1 has an initial voltage, resistor R1 can initially obtain a large voltage drop, causing NMOS transistor T2 to fully turn on and quickly clamp the voltage on power line 10a to a very low level. However, after the voltage on power line 10a is clamped to a very low level, because of the initial voltage on capacitor C1, resistor R1 can only obtain a small voltage drop during the subsequent ESD / EOS overvoltage pulse time. This prevents NMOS transistor T2 from continuously obtaining a high drive voltage, causing NMOS transistor T2 to enter saturation, reducing its discharge capability, and resulting in a worse clamping effect on the voltage on power line 10a.

[0063] In some embodiments, a voltage regulator can be added to the protection circuit 10 based on the operating voltage on power line 10a. This allows NMOS transistor T2 to continuously obtain a driving voltage close to the voltage on the power line during the continuous output of overvoltage pulses in an ESD / EOS event, thereby enabling NMOS transistor T2 to continuously and effectively discharge ESD / EOS current. However, existing voltage regulator implementations require that a single design parameter can only be used at one voltage level. Using it at another voltage level necessitates modifying the design parameters. Therefore, in multi-power supply scenarios, such as those with multiple power lines providing different operating voltages, separate protection circuits need to be configured for each operating voltage, resulting in a significant workload for development.

[0064] In other words, the current design of ESD / EOS protection circuits cannot be standardized or simplified, and it is impossible to achieve compatibility of a single design with multiple power supply scenarios, resulting in high circuit development costs.

[0065] Based on this, the embodiments of this application provide a protection circuit 00, such as Figure 2AAs shown, the protection circuit 00 includes a trigger unit 001, a drive unit 002, and a discharge unit 004, as well as a positive feedback unit 003. The positive feedback unit 003 includes a timing module 0031 and a feedback module 0032. The feedback module 0032 is connected across the capacitor in the trigger unit 001. After the drive unit 002 is turned on, the feedback module 0032 is activated and continuously discharges the charge on the capacitor, ensuring that there is virtually no voltage rise on the capacitor during the duration of the ESD / EOS pulse. This reduces the RC time constant requirement for the trigger unit 001, thereby reducing the area and cost of the protection circuit 00. Furthermore, the timing module 0031 can be an RC circuit, with its output connected to the control terminal of the feedback module 0032. Thus, the timing module 0031 can periodically turn off the feedback module 0032 to shut down the discharge tube after the ESD / EOS event has passed, preventing the discharge tube from continuously discharging the voltage and current required for the normal operation of the protected circuit and ensuring that the normal operation of the protected circuit / device is not affected.

[0066] For example, the protection circuit 00 in this embodiment can be obtained by adding a positive feedback unit to the protection circuit 10. This positive feedback unit includes a timing module and a pull-down module (i.e., the feedback module mentioned in this application). The first end of the pull-down module is connected to the common terminal A of capacitor C1 and resistor R1, and the other end is connected to ground 10b. Thus, the pull-down module spans across capacitor C1. After PMOS transistor T1 is turned on, the pull-down module pulls the potential of the common terminal A low, continuously discharging the charge accumulated on capacitor C1 during the continuous output of overvoltage pulses in an ESD / EOS event. The timing module can periodically disable the function of the pull-down module discharging the charge on capacitor C1, as well as disable the discharging function of NOMS transistor T2. It can be understood that the pull-down module can continuously discharge the charge accumulated on capacitor C1 after PMOS transistor T1 is turned on, resulting in virtually no voltage rise on capacitor C1 during the continuous output of overvoltage pulses in an ESD / EOS event. This reduces the RC time constant requirement for the trigger unit 101, thereby reducing the area and cost of the protection circuit. Furthermore, even during operation, if an ESD / EOS overvoltage pulse occurs after capacitor C1 is fully charged, the pull-down module can discharge capacitor C1 after PMOS transistor T1 is turned on, without sharing the voltage drop across resistor R1. Therefore, NMOS transistor T2 can continuously obtain a high drive voltage during the continuous output of overvoltage pulses in the ESD / EOS event, ensuring a good voltage clamping effect on the power line.

[0067] It can be understood that NMOS transistor T2, as an ESD / EOS discharge device, only needs the voltage drop across resistor R1 to meet the turn-on voltage of PMOS transistor T1, allowing PMOS transistor T1 to conduct. This enables NMOS transistor T2 to turn on and discharge, and the positive feedback unit to activate positive feedback. During the continuous output of overvoltage pulses in an ESD / EOS event, it continuously discharges the charge accumulated on capacitor C1, maintaining NMOS transistor T2's continuous operation. Since capacitor C1 has an initial voltage (operating voltage), the voltage on the power line when NMOS transistor T2 turns on, or the voltage that triggers NMOS transistor T2 to turn on (hereinafter referred to as the trigger voltage), is the operating voltage plus the turn-on voltage of PMOS transistor T1 (threshold voltage). Therefore, the trigger voltage of NMOS transistor T2 is only slightly higher than the operating voltage. It can be triggered and kept fully turned on in the early rising stage of the ESD / EOS overvoltage pulse. Moreover, the trigger voltage of NMOS transistor T2 changes with the operating voltage, always remaining slightly higher than the operating voltage. Thus, the protection circuit provided in this application embodiment can achieve trigger voltage adaptation to operating voltage, making the protection circuit applicable to multi-power supply scenarios and providing ESD / EOS protection for protected devices with different operating voltages.

[0068] The protection circuit provided in this application can be used for ESD / EOS protection of various ports in chips, modules, and electronic devices with multiple power domains. Before further describing the protection circuit of this application, an electronic device with multiple power domains is first introduced.

[0069] Please see Figure 2B , Figure 2BThis is an architecture diagram of a power supply network in an electronic device provided in an embodiment of this application. The power supply network includes a charging port, a charging chip, and an overvoltage protection circuit disposed between the charging chip and the charging port. The charging port can provide charging voltages of 5V / 10V / 11V / 20V. The charging chip can provide a 5V operating voltage to a power management chip and an RF power management chip, enabling the RF power management chip to power the RF front-end power amplifier chip / RF module. The power management chip can power other loads or modules in the electronic device, such as flash memory drives, audio, display / fingerprint modules, headphones, secure digital cards (memory cards) / user identification modules (phone cards), camera modules, application processor chips (main chips), and positioning / wireless communication / Bluetooth / broadcast / FM chips. It is understood that the power management chip can provide different operating voltages for different loads, for example, providing a 2.8V operating voltage for headphones and a 1.8V operating voltage for the secure digital card (memory card) / user identification module (phone card). In addition, the power supply network may also include a fast charging switch chip and a battery, which can provide 5V fast charging to the charging chip, RF front-end power amplifier chip / RF module, secondary SIM card GSM power amplifier chip, and battery.

[0070] In the aforementioned power supply network, to ensure the normal power supply to each chip and load / module and to prevent malfunctions caused by ESD / EOS events, ESD / EOS protection devices are installed at the ports of the charging chip, power management chip, and RF power management chip. For example, protection device 01 is installed at the charging port, protection device 02 is installed at the fast charging switch chip port, protection device 03 is installed at the charging chip port, and protection device 04 is installed at the RF power management chip port. Furthermore, the operating voltage of protection device 01 can be 5V, 10V, 11V, 20V, etc., depending on the charger and charging protocol; for example, the operating voltage of protection devices 02 to 04 is all 5V. Protection devices 05 and 06 are installed at different ports of the power management chip, with operating voltages of 2.8V and 1.8V respectively.

[0071] The protection devices 01 to 06 mentioned above can all adopt the protection circuit provided in the embodiments of this application. That is, in a power supply network with multiple power domains, the same protection device can be used in different power domains. The protection circuit provided in the embodiments of this application realizes the normalization of ESD / EOS design in multi-power supply scenarios, which can reduce circuit development costs.

[0072] The following is combined with Figure 3 This application describes a protection circuit 30 provided in an embodiment. It is understood that the protection circuit 30 can be a specific circuit structure of the protection circuit 00.

[0073] like Figure 3 As shown, the protection circuit 30 includes a trigger unit 301, a drive unit 302, a positive feedback unit 303, and a discharge unit 304. The trigger unit 301, drive unit 302, and discharge unit 304 can be configured with the same circuit structure as the trigger unit 101, drive unit 102, and discharge unit 103 described above, and will not be elaborated further here. The positive terminal P1 represents the power supply connection port, and the negative terminal P2 represents the ground connection port. The positive feedback unit 303 will be mainly described below.

[0074] The positive feedback unit 303 may include a timing module 3031 and a pull-down module 3032. The timing module 3031 may include a resistor R3 (an example of a second resistor in this application) and a capacitor C2 (an example of a second capacitor in this application) connected in series. The other end of capacitor C2 is connected to the gate of NMOS transistor T2, and the other end of resistor R3 is connected to the negative terminal P2. The pull-down module 3032 may include an NMOS transistor T3 (an example of a first metal-oxide-semiconductor field-effect transistor in this application). The gate of NMOS transistor T3 is connected to the common terminal of resistor R3 and capacitor C2, the source of NMOS transistor T3 is connected to the negative terminal P2, and the drain of NMOS transistor T3 is connected to the common terminal of resistor R1 and capacitor C1. NMOS transistor T3 primarily serves as the positive feedback element, and capacitor C2 and resistor R3 constitute the positive feedback trigger and timing shutdown circuit.

[0075] The positive feedback unit 303 works as follows: When the driving unit 302 outputs a driving voltage equal to the threshold voltage of a MOS transistor during the rising edge of ESD / EOS, this voltage acts on the time delay circuit composed of capacitor C2 and resistor R3. Since the voltage of capacitor C2 cannot change abruptly and can only charge slowly, this voltage drops instantly across resistor R3, causing NMOS transistor T3 to turn on. After NMOS transistor T3 turns on, it can release the charge on capacitor C1 in trigger circuit 301 and pull its voltage down to the same potential as the negative terminal P2. In this way, the voltage on the positive terminal P1 will drop entirely across resistor R1, that is, resistor R1 will receive a large voltage drop at the moment the rising edge of ESD / EOS begins, causing PMOS transistor T1 in driving unit 302 to turn on completely, outputting the voltage on the positive terminal P1 to the gate of NMOS transistor T2 in discharge unit 304 and the positive feedback trigger circuit composed of capacitor C2 and resistor R3, and maintaining the positive feedback on. During the duration of the ESD / EOS pulse, NMOS transistor T3 can continuously pull capacitor C1 low, which will result in a higher voltage drop across resistor R1, thus forming positive feedback. Meanwhile, NMOS transistor T2 continuously receives a drive voltage equal to that of the positive terminal P1, fully turning on and clamping the voltage on the positive terminal P1 at an extremely low level.

[0076] It can be understood that the positive feedback triggering condition of protection circuit 30 is that there is a voltage drop across resistor R1, causing PMOS transistor T1 to turn on and output a high level to the positive feedback triggering circuit composed of capacitor C2 and resistor R3. The condition for PMOS transistor to turn on is to reach the threshold voltage Vgs(th), that is, the voltage drop across resistor R1 only needs to be slightly greater than the absolute value of the threshold voltage to trigger NMOS transistor T2 to turn on and establish positive feedback to maintain the continuous turn-on of NMOS transistor T2 during the continuous output of overvoltage pulses in the ESD / EOS event.

[0077] Compared to a solution that maintains the NMOS transistor T2 continuously on throughout the entire ESD / EOS duration by increasing the RC time constant of the trigger unit 101, which requires setting the RC time constant to be much larger than the rise time and pulse width of the ESD / EOS pulse, in the protection circuit 30 of this embodiment, the RC time constant of the trigger unit 301 only needs to be comparable to the rise time, and therefore can be set very small. For example, to discharge the same pulse width of ESD / EOS energy, the RC time constant of the trigger unit 301 can be reduced by more than 100 times, thus greatly reducing the area and cost of the protection circuit 30.

[0078] During power-up, due to the positive feedback, NMOS transistor T3 can release the initial charge of capacitor C1. Therefore, resistor R1 will no longer be restricted and can achieve a high voltage drop. NMOS transistor T2 can clamp the voltage below the normal operating voltage, exhibiting a snapback phenomenon similar to that of a silicon controlled rectifier (SCR), meaning it has strong current discharge capability. Furthermore, when NMOS transistor T2 is turned on, the voltage (trigger voltage) on the positive terminal P1 is only slightly higher than the power-up voltage (operating voltage), specifically the power-up voltage plus the threshold voltage. Therefore, it can be seen that the trigger voltage of NMOS transistor T2 can change with the power-up voltage and always remains slightly higher than the power-up voltage. This allows the trigger voltage of protection circuit 30 to adapt to the power-up voltage, enabling protection circuit 30 to be used to provide ESD / EOS protection for each port in different power domains.

[0079] In addition, continue to refer to Figure 3 The timing module 3031 has two functions: one is to trigger positive feedback, and the other is to shut down positive feedback, so that the NMOS transistor T2 in the discharge unit 304 is turned off after the ESD / EOS energy has passed, thus avoiding affecting the normal operation of the protected device.

[0080] The principle behind the timing module 3031 disabling positive feedback is as follows: Capacitor C2 slowly charges under the drive voltage output by the drive unit 302, and correspondingly, the voltage drop across resistor R3 gradually decreases. When capacitor C2 charges to near the drive voltage, the voltage drop across resistor R3 will be less than the threshold voltage of NMOS transistor T3. At this point, the positive feedback is turned off, and capacitor C1 will stop being pulled low. As capacitor C1 gradually charges to the positive terminal P1 voltage, the voltage drop across resistor R1 becomes less than the absolute value of the threshold voltage of PMOS transistor T1. The drive unit 302 cannot provide sufficient drive voltage, causing NMOS transistor T2 in the discharge unit 304 to turn off.

[0081] Furthermore, during power-up, i.e., the rise of the operating voltage, before the arrival of the ESD / EOS pulse, capacitor C1, after being fully charged, can be at the same potential as the positive terminal P1, causing the voltage drop across resistor R1 to 0V. PMOS transistor T1 is turned off, meaning it is in a high-resistance state with a resistance much greater than that of resistor R2. At this time, the gate of NMOS transistor T2 is pulled low to ground by resistor R2, i.e., 0V. Therefore, capacitor C2 has no initial voltage and is not charged. The effect of capacitor C2 is not suppressed by the operating voltage (the effective capacitance value decreases under bias, resulting in a shorter effective RC time; since C2 has no initial voltage, its capacitance value is unaffected). Thus, the RC time constant of timing module 3031 does not need to be much greater than the pulse width of the ESD / EOS to be discharged, saving significant circuit area. For example, to discharge a 50µs surge energy, the RC time constant typically needs to be set to 500µs, while timing module 3031 only needs a 25µs time constant, reducing the area by 20 times. Therefore, without increasing the circuit area, it is possible to completely discharge ESD / EOS energy within a certain pulse width range simply by designing a suitable RC time constant for the timing module 3031.

[0082] In this embodiment, an ESD / EOS protection test environment is set up to simulate the protection effect of the protection circuit 30. Please refer to... Figure 4 and Figure 8 , Figure 4 and Figure 8 This is a schematic diagram of the test circuit for two types of protection circuits 30. Figure 5 , Figure 6 and Figure 7 yes Figure 4 The simulation results of the test circuit shown are displayed under different test parameters. Figure 9 yes Figure 8 The simulation result of the test circuit is shown.

[0083] like Figure 4As shown, the square wave pulse symbol V1 represents the ESD / EOS pulse source. The DC symbol V2 represents the DC source, i.e., the power-on voltage, simulating the power supply voltage during normal operation. Resistors R4 and R5 represent the internal resistances of the ESD / EOS pulse source and the DC source, respectively. It can be understood that any source has internal resistance; the DC source has a very small internal resistance but a maximum current limit. To limit the current, resistors with resistances of 1 ohm or 2 ohms are used in the simulation. Simultaneously, resistor R4 is connected in series with diode D2, and resistor R5 is connected in series with diode D3. Diodes D2 and D3 form a coupling-decoupling network, mainly to avoid mutual interference between the DC source and the pulse source, and to prevent reverse current flow. Figure 8 As shown, Figure 8 and Figure 4 In contrast, no DC source or coupling / decoupling network is required.

[0084] In addition, Vclamp represents the real-time voltage across the positive terminal P1. Ammeter Pr1 measures the real-time current It flowing through the protection circuit. Vdiver represents the gate voltage of NMOS transistor T2 in the bleeder unit 304. Vmos represents the gate voltage of NMOS transistor T3 in the positive feedback unit 303.

[0085] Figure 5 , Figure 6 , Figure 7 and Figure 9 In the various graphs, the waveform graph on the left shows the curve of Vclamp changing with time as a solid line, and the waveform graph on the right shows the curve of the real-time current of ammeter Pr1 changing with time as a dashed line; the waveform graph on the left shows the curve of Vmos changing with time as a solid line, and the waveform graph on the right shows the curve of Vdiver changing with time as a dashed line. Figure 5 The corresponding test parameters are: power-on voltage 20V, EOS (resistor R4 has a resistance of 2 ohms) pulse voltage 30V, rise / fall time 1.2us, pulse width time 100us. Figure 6 The corresponding test parameters are: power-on voltage 10V, EOS (resistor R4 has a resistance of 2 ohms) pulse overvoltage 12V, rise / fall time 1.2us, and pulse width time 100us. Figure 7 The corresponding test parameters are: power-on voltage 20V, transmission line pulse TLP (resistor R4 has a resistance of 50 ohms) pulse voltage 200V, rise / fall time 10ns, and pulse width time 100ns. Figure 9 The corresponding test parameters are a square wave with an amplitude of 10V, a rise time of 100us, and a pulse time of 2ms, simulating a rapid power-on scenario (to illustrate that the embodiments of this application will not be falsely triggered during normal power-on and will not affect the normal operation of the protected circuit).

[0086] Depend on Figures 5 to 7As can be seen, Vclamp is not zero at the initial moment; it has an initial value, which is the power-on voltage. When the current just begins to increase, Vclamp will show a small spike (…). Figure 6 and Figure 7 (This small spike is blocked by the current curve). The peak value of this small spike is the trigger voltage of NMOS transistor T2 in the discharge unit 304. After triggering (after the small spike), Vclamp decreases, indicating that NMOS transistor T2 is fully turned on, clamping the voltage at the positive terminal P1, and the clamping voltage can be lower than the power-on voltage. The reason is that the charge on capacitor C1 in the trigger unit 301 is released by NMOS transistor T3 in the positive feedback unit, and PMOS transistor T1 can be turned on without an excessively high voltage drop across resistor R1. Therefore, NMOS transistor T2 can clamp the voltage to below the normal operating voltage, achieving ultra-low clamping. For example, Figure 5 After the small spike in Vclamp, the voltage is clamped to below 10V, which is less than the power-on voltage of 20V. In conventional circuits such as protection circuit 10, because there is an initial voltage on capacitor C1 during power-on, it will only charge to a higher level during the entire ESD / EOS duration and will not decrease. Therefore, its clamping voltage will not be lower than the power-on voltage, and ultra-low clamping cannot be achieved.

[0087] Depend on Figure 9 As can be seen, the value of Pr1 is 0 throughout the entire process of Vclamp rising to 10V and falling from 10V to 0V. This indicates that during the rapid power-up process simulating normal operation, the protection circuit 30 will not trigger the discharge of normal operating current. Therefore, the protection circuit 30 will not affect the normal operation of the protected circuit and will only respond when an ESD / EOS event occurs.

[0088] The above simulation results show that the trigger voltage of NMOS transistor T2 in the bleeder unit 304 can change with the power-on voltage, adapting to the power-on voltage and always being slightly higher than the power-on voltage, exhibiting excellent clamping characteristics. Furthermore, NMOS transistor T2 remains continuously turned on within the 100µs duration of the ESD / EOS pulse and automatically turns off after the ESD / EOS pulse, avoiding latch-up effects compared to SCR bleeder devices. Simultaneously, it does not respond to the normal power-on or power-off cycles of the protected device, thus not affecting its normal operation.

[0089] Furthermore, in related technologies, the driving unit uses an inverter composed of a PMOS transistor and an NMOS transistor. When an ESD / EOS pulse occurs, the charging of capacitor C1 in the trigger unit causes the NMOS transistor in the inverter to turn on. The low-resistance pull-down then competes with the PMOS transistor, making it difficult for the driving unit to output a high driving voltage. However, in the aforementioned driving unit 302, using resistor R2 instead of the NMOS transistor in the inverter can improve the driving capability of the driving unit 302.

[0090] It is understandable that the protection circuit 30 can be packaged as a whole, and the packaged device can be directly applied to the protected circuit or equipment as a protection device. The protection circuit 30 can also be partially packaged; for example, at least one of the capacitor C2 and resistor R3 in the positive feedback unit 303 and the capacitor C1 in the trigger unit 301 can be removed, and the remaining parts can be packaged separately. When using the packaged device, the discrete capacitors and resistors need to be arranged according to... Figure 3 The circuit connection shown is connected to the packaged device, so the values ​​of capacitor C1, capacitor C2 and resistor R3 can be flexibly changed according to the needs, thereby obtaining an ESD / EOS protection circuit that can respond to different rising edges and pulse widths.

[0091] Please see Figure 10 , Figure 10 This is a schematic diagram of a partial encapsulation method. For example... Figure 10 As shown in (a), capacitors C1, C2, and resistor R3 in protection circuit 30 are removed, and the remaining part is handled as follows: Figure 10 The circuit to be packaged shown in (b) is packaged to obtain... Figure 10 The packaged device shown in (c) includes two P1 ports, one P2 port, one G1 port, one G2 port, and one CD port. When using this packaged device, follow... Figure 10 The connection shown in (d) connects the discrete capacitors C1, C2, and R3 to the respective ports on the packaged device. Specifically, one end of capacitor C2 is connected to port G1 and the other end is connected to port G2; one end of resistor R3 is connected to port G2 and the other end is connected to ports P2 and CD respectively; one end of capacitor C1 is connected to port CD and the other end is connected to port P2.

[0092] Continue reading Figure 10The circuit to be packaged shown in (b) has multiple nodes that require pins to form the ports of the packaged device. Since these pins are exposed to the external environment, and these exposed nodes are susceptible to ESD damage during production and application, ESD protection is necessary. Therefore, ESD protection devices can be added between the pins in the circuit to be packaged. Here, a Zener diode is used as an example of an ESD protection device, but it is not limited to Zener diodes; any ESD protection device or circuit with the same protection effect can be used. For example, diode D3 is placed between port P1 and port CD, diode D4 is placed between port G1 and port P2, and diode D5 is placed between port G2 and port P2. Furthermore, since NMOS transistor T2 and resistor R2 form a gate-coupling NMOS structure commonly used for ESD protection, there is a low-impedance discharge path from port P1 to port P2 under ESD conditions. Therefore, no additional ESD protection is needed between ports P1 and P2. ESD events occurring between ports G1, G2, and CD can be discharged through diodes D3 / D4 / D5 and NMOS transistor T2, thus solving the risk of ESD damage to the protection circuit itself due to multiple pins being brought out during the packaging process.

[0093] Please see Figure 11 , Figure 11 This is a schematic diagram of another protection circuit 40 provided in an embodiment of this application. It can be understood that the protection circuit 40 can be a specific circuit structure of the protection circuit 00. The protection circuit 40 includes a trigger unit 401, a drive unit 402, a positive feedback unit 403, and a discharge unit 404.

[0094] The trigger unit 401 includes a resistor R4 (an example of a first resistor in this application) and a capacitor C3 (an example of a first capacitor in this application) connected in series. The other end of resistor R4 is connected to the negative terminal P2, and the other end of capacitor C3 is connected to the positive terminal P1. The drive unit 402 includes an NMOS transistor T4 (an example of a second metal-oxide-semiconductor field-effect transistor in this application) and a resistor R5 (an example of a first resistor network in this application). The gate of the NMOS transistor T4 is connected to the common terminal of capacitor C3 and resistor R4, its source is connected to the negative terminal P2, its drain is connected to one end of resistor R5, and the other end of resistor R5 is connected to the positive terminal P1. The positive feedback unit 403 includes a timing module 4031 and a pull-up module 4032 (an example of a feedback module in this application). The timing module 4031 includes a resistor R6 (an example of a second resistor in this application) and a capacitor C4 (an example of a second capacitor in this application) connected in series. The pull-up module includes a PMOS transistor T5 (an example of a first metal-oxide-semiconductor field-effect transistor in this application). The gate of the PMOS transistor T5 is connected to the common terminal of the capacitor C4 and the resistor R6, its source is connected to the positive terminal P1, and its drain is connected to the common terminal of the capacitor C3 and the resistor R4. The discharge unit 404 includes a PMOS transistor T6 (an example of a fourth metal-oxide-semiconductor field-effect transistor in this application). Its gate is connected to the drain of the NMOS transistor T4, its source is connected to the positive terminal P1, and its drain is connected to the negative terminal P2.

[0095] It is understandable that the difference between protection circuit 40 and protection circuit 30 lies in the discharge units used: one uses an NMOS transistor T2, and the other uses a PMOS transistor T6, thus their triggering logic is reversed. By swapping the components in each unit of protection circuit 30 and replacing the PMOS transistor with an NMOS transistor and vice versa, protection circuit 40 can be obtained. Therefore, protection circuit 40 and protection circuit 30 have similar ESD / EOS protection principles and can achieve the same effect, so further details are omitted here.

[0096] In this embodiment, an ESD / EOS protection test environment is set up to simulate the protection effect of the protection circuit 40. Please refer to... Figures 12 to 14 , Figure 12 A schematic diagram of the test circuit for protection circuit 40. Figure 13 and Figure 14 Simulation results of the test circuit for protection circuit 40 under different test parameters.

[0097] Figure 12 The test circuit for the protection circuit 40 shown can be referred to Figure 4 The test circuit of the protection circuit 30 shown is provided below, and the meaning of each symbol will not be repeated. Figure 13 and Figure 14In the waveform diagram on the left, the solid line shows the curve of Vclamp changing with time, and the dashed line shows the curve of the real-time current of ammeter Pr1 changing with time; in the waveform diagram on the right, the solid line shows the curve of Vmos changing with time, and the dashed line shows the curve of Vdiver changing with time. Figure 13 The corresponding test parameters are: power-on voltage 20V, EOS pulse voltage 100V, rise / fall time 1.2us, and pulse width time 100us. Figure 14 The corresponding test parameters are: power-on voltage 20V, TLP pulse voltage 1000V, rise / fall time 10ns, and pulse width time 100ns.

[0098] Depend on Figure 13 and Figure 14 As can be seen, the trigger voltage of PMOS transistor T6 in the discharge unit 404 can change with the power-on voltage, adapting to the power-on voltage and always being slightly higher than the power-on voltage, exhibiting excellent clamping characteristics. It should be noted that... Figure 14 The trigger voltage is not visible within the 250µs simulation time because the simulation step is greater than 10ns. Reducing the simulation time reveals that the trigger voltage is slightly higher than the power-on voltage. Furthermore, PMOS transistor T6 remains on during the ESD / EOS pulse duration and automatically turns off after the ESD / EOS pulse.

[0099] It is understandable that simulation testing of protection circuit 40 can yield the same simulation test results as protection circuit 30. That is, protection circuit 40 and protection circuit 30 have the same function, so it will not be elaborated here.

[0100] In the above embodiments, both drive unit 302 and drive unit 402 are implemented using a single-stage drive circuit. In other embodiments, the drive unit may use a two-stage drive circuit, a three-stage drive circuit, or other multi-stage drive circuits; this application does not limit this. The output of the timing module in positive feedback unit 303 and positive feedback unit 403 can also be connected to the drive module first and then to the pull-down module. Here, the drive module can also use a single-stage drive circuit, a two-stage drive circuit, or other multi-stage drive circuits; this application does not limit this.

[0101] Please see Figure 15 , Figure 15 This is a schematic diagram of another protection circuit 50 provided in an embodiment of this application. It can be understood that the protection circuit 50 can be a specific circuit structure of the protection circuit 00. The protection circuit 50 includes a trigger unit 501, a drive unit 502, a positive feedback unit 503, and a discharge unit 504. The trigger unit 501 and the discharge unit 504 can refer to the trigger unit 301 and discharge unit 304 described above, and can be configured with the same circuit structure, which will not be elaborated here.

[0102] The difference between protection circuit 50 and protection circuit 30 is that in protection circuit 50, the drive unit 502 adopts a three-stage drive circuit, and the positive feedback unit 503, in addition to the timing module 5031 and the pull-down module 5032, also includes a drive module 5033, which adopts a two-stage drive circuit. The timing module 5031 can refer to the timing module 3031 described above, and the pull-down module 5032 can refer to the pull-down module 3032 described above; they can be configured with the same circuit structure, which will not be elaborated here.

[0103] Specifically, the driving unit 502 may include a PMOS transistor T1, a resistor R2, an NMOS transistor T7, a resistor R7, a PMOS transistor T8, and a resistor R8. PMOS transistor T1 and resistor R2 can form a first-stage driving circuit, NMOS transistor T7 and resistor R7 can form a second-stage driving circuit, and PMOS transistor T8 and resistor R8 can form a third-stage driving circuit. NMOS transistor T7 and PMOS transistor T8 are examples of the second metal-oxide-semiconductor field-effect transistor of this application, and resistors R7 and R8 are examples of the first resistor network of this application. The gate of NMOS transistor T7 is connected to the drain of PMOS transistor T1, the source of NMOS transistor T7 is connected to the negative terminal P2, the drain of NMOS transistor T7 is connected to one end of resistor R7, and the other end of resistor R7 is connected to the positive terminal P1. The gate of PMOS transistor T8 is connected to the drain of NMOS transistor T7, the source of PMOS transistor T8 is connected to the positive terminal P1, the drain of PMOS transistor T8 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the negative terminal P2.

[0104] The driving module 5033 may include an NMOS transistor T9, a resistor R9, a PMOS transistor T10, and a resistor R10. Specifically, NMOS transistor T9 and PMOS transistor T10 are examples of the third metal-oxide-semiconductor field-effect transistor of this application, and resistors R9 and R10 are examples of the second resistor network of this application. It should be noted that the first / second resistor network in the embodiments of this application may include one or more resistors, and multiple resistors may be connected in series, parallel, or a combination of series and parallel; this application does not limit this connection.

[0105] The gate of NMOS transistor T9 is connected to the common terminal of resistor R3 and capacitor C2. The source of NMOS transistor T9 is connected to the negative terminal P2. The drain of NMOS transistor T9 is connected to one end of resistor R9, and the other end of resistor R9 is connected to the gate of NMOS transistor T2. The gate of PMOS transistor T10 is connected to the drain of NMOS transistor T9. The source of PMOS transistor T10 is connected to the gate of NMOS transistor T2. The drain of PMOS transistor T10 is connected to one end of resistor R10, and the other end of resistor R10 is connected to the negative terminal P2.

[0106] Please see Figure 16 , Figure 16 This is a schematic diagram of another protection circuit 60 provided in an embodiment of this application. It can be understood that the protection circuit 60 can be a specific circuit structure of the protection circuit 00. The protection circuit 60 includes a trigger unit 601, a drive unit 602, a positive feedback unit 603, and a discharge unit 604. The trigger unit 601 and the discharge unit 604 can refer to the trigger unit 401 and discharge unit 404 described above, and can be configured with the same circuit structure, which will not be elaborated here.

[0107] The difference between protection circuit 40 and protection circuit 60 is that the drive unit 602 in protection circuit 60 adopts a three-stage drive circuit, and the positive feedback unit 603, in addition to the timing module 6031 and the pull-up module 6032, also includes a drive module 6033, which adopts a two-stage drive circuit. The timing module 6031 can refer to the timing module 3031 described above, and the pull-up module 6032 can refer to the pull-up module 4032 described above; they can be configured with the same circuit structure, which will not be elaborated here.

[0108] Specifically, the driving unit 602 may include an NMOS transistor T4, a resistor R5, a PMOS transistor T11, a resistor R11, an NMOS transistor T12, and a resistor R12. The NMOS transistor T4 and resistor R5 can constitute a first-stage driving circuit, the PMOS transistor T11 and resistor R11 can constitute a second-stage driving circuit, and the NMOS transistor T12 and resistor R12 can constitute a third-stage driving circuit. Both the PMOS transistor T11 and the NMOS transistor T12 are examples of the second metal-oxide-semiconductor field-effect transistor of this application, and both resistors R11 and R12 are examples of the first resistor network of this application. The gate of PMOS transistor T11 is connected to the drain of NMOS transistor T4. The source of PMOS transistor T11 is connected to the positive terminal P1. The drain of PMOS transistor T11 is connected to one end of resistor R11, and the other end of resistor R11 is connected to the negative terminal P2. The gate of NMOS transistor T12 is connected to the drain of PMOS transistor T11. The source of NMOS transistor T12 is connected to the negative terminal P2. The drain of NMOS transistor T12 is connected to one end of resistor R12, and the other end of resistor R12 is connected to the positive terminal P1.

[0109] The driving module 6033 may include a PMOS transistor T13, a resistor R13, an NMOS transistor T14, and a resistor R14. Both PMOS transistor T13 and NMOS transistor T14 are examples of the third metal-oxide-semiconductor field-effect transistor of this application, and both resistors R13 and R14 are examples of the second resistor network of this application. The gate of PMOS transistor T13 is connected to the common terminal of resistor R6 and capacitor C4. The source of PMOS transistor T13 is connected to the positive terminal P1. The drain of PMOS transistor T13 is connected to one end of resistor R13, and the other end of resistor R13 is connected to the gate of PMOS transistor T6. The gate of NMOS transistor T14 is connected to the drain of PMOS transistor T13. The source of NMOS transistor T14 is connected to the gate of PMOS transistor T6. The drain of NMOS transistor T14 is connected to one end of resistor R14, and the other end of resistor R14 is connected to the positive terminal P1.

[0110] In summary, this application addresses the issue that the start-up / trigger voltage parameters of current board-level protection circuits / devices and on-chip protection circuits for various power supplies and signal ports are fixed. Once the protection scheme is determined, its protection window and application scenario are difficult to change. This makes it impossible to achieve adaptability of a single device / structure under different application voltages, i.e., the problem of voltage adaptive regulation. Therefore, this application proposes multiple protection circuits (30 / 40 / 50 / 60) that can use the same protection scheme in multi-power supply domains with multiple different voltage levels. Furthermore, by adjusting the resistance values ​​of capacitors and resistors in the circuit, ESD / EOS pulses of different pulse widths can be discharged.

[0111] For example, taking the application of electronic device protection devices as an example, the power supply scenarios that need to be protected in electronic devices include multiple voltage levels such as 3.3V, 4.2V, 5V, 7.8V, 12V, and 24V. Since the failure voltage of the chip / module to be protected follows the operating voltage, and ESD / EOS events can occur in both power-on and power-off scenarios, the protection window of the protection circuit device 30 / 40 / 50 / 60 provided in this application embodiment can adapt to the operating voltage in both power-on and power-off scenarios, which can ensure the normal function and protection performance of each port in the chip / module, and realize the normalization and simplification of the protection circuit design.

[0112] In addition, please see Figure 17 , Figure 17This is a schematic diagram of a protection circuit 170 provided in an embodiment of this application. The protection circuit 170 includes an RC timing circuit 1701, an inverter 1702, a flip-flop 1703, a latch 1704, and a Darlington transistor 1705. The protection circuit 170 can regulate the trigger voltage of the Darlington transistor 1705. Specifically, the timing circuit 1701 monitors ESD pulses and outputs an ESD signal to the flip-flop 1703 under an ESD pulse, which is then output to the latch 1704 via the inverter 1702. The flip-flop 1703 includes a series resistor. After the flip-flop 1703 is turned on, the series resistor in the flip-flop 1703 divides the voltage to regulate the trigger voltage of the Darlington transistor 1705. Simultaneously, the latch 1704 latches the ESD signal and holds it for a period of time, outputting a drive current to the Darlington transistor 1705 to discharge ESD energy. While the protection circuit 170 can adjust the trigger voltage of the Darlington transistor 1705, it primarily achieves this adjustment through a fixed-value series resistor in the flip-flop 1703. Therefore, this design is limited to a single voltage domain, making normalization and simplification impossible when used for discrete device protection. Furthermore, under power-on conditions, the signal output from the timing circuit 1701 weakens, pulling the N-transistor in the inverter 1702 low. This prevents the inverter 1702 from quickly outputting a high level to the flip-flop 1703 and latch 1704, leading to an increased trigger voltage. Consequently, the drive current to the Darlington transistor 1705 decreases, resulting in poorer clamping characteristics. This deterioration worsens with higher operating voltages. Additionally, the Darlington transistor 1705 exhibits latch-up characteristics, making it unsuitable for protection on high-voltage power supplies.

[0113] Please see Figure 18 , Figure 18 This is a schematic diagram of a protection circuit 180 provided in an embodiment of this application. The protection circuit 180 includes an RC circuit 1801, a PMOS transistor 1802, and an SCR device 1803. The protection circuit 180 triggers the PMOS transistor 1802 to turn on via the RC circuit 1801, injecting a trigger current into the SCR device 1803 to discharge ESD energy. This scheme uses the SCR device 1803 for discharge, which has excellent clamping characteristics, and the trigger voltage of the SCR device 1803 is adaptive to the power supply voltage. However, the SCR device 1803 has a latch-up structure and cannot be used for power supply protection. Furthermore, the driving capability of the RC circuit 1801 and the PMOS transistor 1802 is limited; for long-pulse ESD / EOS energy and under power-on conditions, it only has a momentary and small driving capability, which cannot achieve effective driving throughout the entire energy duration.

[0114] In comparison, the protection circuits 30 / 40 / 50 / 60 provided in this application embodiment can all make the trigger voltage of the discharge unit adapt to the working voltage, change with the working voltage, and always be slightly higher than the working voltage. At the same time, they have ultra-low clamping, and the clamping characteristics are stable and do not deteriorate with the increase of the working voltage. They can achieve effective driving throughout the entire energy duration, and realize the normalization and simplification of the protection circuit design.

[0115] As mentioned above, the protection circuits 30 / 40 / 50 / 60 provided in this application embodiment can be packaged as a whole or partially as a protection device. Alternatively, they can be directly connected using discrete components (MOSFETs, resistors, capacitors), and the protection circuits 30 / 40 / 50 / 60 obtained by connecting discrete components can be placed on a circuit board, which also has the chip or device that needs to be protected.

[0116] Therefore, embodiments of this application also provide a protection device, which may include at least a portion of the protection circuits 30 / 40 / 50 / 60 in any of the above embodiments.

[0117] In some embodiments, the protection device may be at least partially integrated from protection circuits 30 / 40 / 50 / 60, as detailed in the following references. Figure 10 Description of related embodiments.

[0118] In other embodiments, the protection device may include a circuit board on which multiple electronic components, such as discrete devices (MOSFETs, resistors, capacitors), are disposed, and these multiple electronic components are interconnected to form at least a portion of the protection circuit 30 / 40 / 50 / 60 in any of the above embodiments. Furthermore, the circuit board may also include a protected device connected to the protection circuit 30 / 40 / 50 / 60.

[0119] This application also provides a chip / circuit board / electronic device, which includes a protected device, and the port of the protected device is provided with the protection circuit 30 / 40 / 50 / 60 in any of the above embodiments.

[0120] It is understood that the electronic devices in the embodiments of this application may also be referred to as terminals, user equipment (UE), mobile stations (MS), mobile terminals (MT), etc. Electronic devices can be mobile phones, smart TVs, wearable devices, tablets, computers with wireless transceiver capabilities, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0121] Furthermore, energy-related and wireless electronic devices have higher operating voltages and more operating voltage levels. In power supply scenarios with higher operating voltages, considering that the gate-source withstand voltage of the MOSFET in the discharge unit is not high enough, Zener diodes and resistors can be added to clamp the gate-source voltage.

[0122] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0123] It should be noted that in the examples and description of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the aforementioned element.

[0124] Although this application has been illustrated and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the scope of this application.

Claims

1. A protection circuit, characterized in that, It includes a trigger unit, a drive unit, a positive feedback unit, and a discharge unit; among which, The discharge unit is used to connect to the protected device protected by the protection circuit, and is used to discharge the overcurrent corresponding to the overvoltage pulse according to the driving voltage. The triggering unit is configured to, when the overvoltage pulse is detected and the overvoltage pulse satisfies the activation condition of the driving unit, activate the driving unit so that the driving unit outputs the driving voltage to the discharge unit and activates the positive feedback unit. The positive feedback unit is used to control the drive unit to maintain the drive unit in the on state and continuously output the drive voltage to the discharge unit during the pulse time corresponding to the overvoltage pulse when the drive unit is in the on state.

2. The protection circuit according to claim 1, characterized in that, The positive feedback unit includes a timing module and a feedback module; wherein... The timing module is used to trigger and control the opening and closing of the feedback module when the drive unit is turned on. The feedback module is used to control the drive unit to continuously output the drive voltage to the discharge unit when it is turned on, and to control the drive unit to stop outputting the drive voltage to the discharge unit when it is turned off.

3. The protection circuit according to claim 2, characterized in that, The protected device includes a first protection terminal and a second protection terminal, and the overvoltage pulse is generated on the first protection terminal or the second protection terminal. The triggering unit, the driving unit, and the venting unit are all connected to the first protection terminal and the second protection terminal. The output terminal of the triggering unit is connected to the input terminal of the driving unit. The output terminal of the driving unit is connected to the control terminal of the venting unit and the input terminal of the timing module in the positive feedback unit. The output terminal of the timing module is connected to the control terminal of the feedback module. Furthermore, the feedback module includes a first terminal and a second terminal. The first terminal is connected to the output terminal of the triggering unit, and the second terminal is connected to either the first protection terminal or the second protection terminal.

4. The protection circuit according to claim 3, characterized in that, The triggering unit is a resistor-capacitor (RC) circuit.

5. The protection circuit according to claim 3 or 4, characterized in that, The triggering unit includes a first resistor and a first capacitor connected in series, and the output terminal of the triggering unit is the common terminal of the first resistor and the first capacitor; The first resistor further includes a third terminal, and the first capacitor further includes a fourth terminal, wherein the third terminal and the fourth terminal are respectively connected to the first protection terminal and the second protection terminal; The second end of the feedback module is connected to the fourth end.

6. The protection circuit according to claim 5, characterized in that, The feedback module includes a first metal-oxide-semiconductor field-effect transistor; The control terminal of the feedback module is the gate of the first metal-oxide-semiconductor field-effect transistor, the first terminal of the feedback module is the drain of the first metal-oxide-semiconductor field-effect transistor, and the second terminal of the feedback module is the source of the first metal-oxide-semiconductor field-effect transistor.

7. The protection circuit according to claim 3, characterized in that, The timing module is a resistor-capacitor (RC) circuit.

8. The protection circuit according to claim 3 or 7, characterized in that, The timing module includes a second resistor and a second capacitor connected in series, and the output terminal of the timing module is the common terminal of the second resistor and the second capacitor; The second resistor also includes a fifth terminal, which is connected to either the first protection terminal or the second protection terminal; The second capacitor also includes a sixth terminal, which is the input terminal of the timing module.

9. The protection circuit according to claim 3, characterized in that, The driving unit includes a single-stage driving circuit or an N-stage driving circuit, where N is an odd number greater than 1. The primary driving circuit and the N-level driving circuit each stage of the driving circuit include: The second metal-oxide-semiconductor field-effect transistor and the first resistor network are provided. One end of the first resistor network is connected in series with the drain of the second metal-oxide-semiconductor field-effect transistor. The source of the second metal-oxide-semiconductor field-effect transistor and the other end of the first resistor network are respectively connected to one of the first protection terminal and the second protection terminal.

10. The protection circuit according to claim 9, characterized in that, The driving unit includes a single-stage driving circuit. The source of the second metal-oxide-semiconductor field-effect transistor in the first-stage driving circuit is the input terminal of the driving unit, and the drain of the second metal-oxide-semiconductor field-effect transistor is the output terminal of the driving unit.

11. The protection circuit according to claim 9, characterized in that, The driving unit includes N-stage driving circuits. In the N-stage driving circuit, the source of the second metal-oxide-semiconductor field-effect transistor in the first-stage driving circuit is the input terminal of the driving unit, and the drain of the second metal-oxide-semiconductor field-effect transistor in the Nth-stage driving circuit is the output terminal of the driving unit; and... The two second metal-oxide-semiconductor field-effect transistors in adjacent driving circuits have different channel polarities.

12. The protection circuit according to claim 3, characterized in that, The positive feedback unit further includes a drive module, and the output of the timing module is connected to the control terminal of the feedback module through the drive module; and... The driving module is also connected to the input terminal of the timing module, as well as the first protection terminal or the second protection terminal.

13. The protection circuit according to claim 12, characterized in that, The driving module includes M-level driving circuits, where M is an even number greater than or equal to 2; The M-level drive circuit includes the following drive circuits at each stage: The system comprises a third metal-oxide-semiconductor field-effect transistor (MOSFET) and a second resistor network, wherein one end of the second resistor network is connected in series with the drain of the third MOSFET, and the source of the third MOSFET and the other end of the second resistor network are respectively connected to the input terminal of the timing module, the first protection terminal, and one of the second protection terminals.

14. The protection circuit according to any one of claims 3, 4, 6, 7, 9-13, characterized in that, The discharge unit includes a fourth metal-oxide-semiconductor field-effect transistor (MOSFET), the gate of which is the control terminal of the discharge unit, and the source and drain of which are respectively connected to the first protection terminal and the second protection terminal.

15. A protective device, characterized in that, Includes at least a portion of the protection circuit according to any one of claims 1-14.

16. The protection device according to claim 15, characterized in that, The protection device is formed by encapsulating and integrating at least a portion of the protection circuit.

17. The protection device according to claim 15, characterized in that, The protection device also includes a circuit board on which multiple electronic components are disposed, the multiple electronic components being used to form at least a portion of the protection circuit.

18. A chip, characterized in that, The chip includes a protection circuit and a protected device as described in any one of claims 1-14, wherein the protection circuit is connected to the protected device.

19. A circuit board, characterized in that, The circuit board is provided with a protection circuit and a protected device as described in any one of claims 1-14, wherein the protection circuit is connected to the protected device.

20. An electronic device, characterized in that, The electronic device includes a protected device and a protection circuit as described in any one of claims 1-14, wherein the protection circuit is connected to the protected device.

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