Device control method and device, electronic equipment, storage medium and program product

Abstract

The invention relates to a device control method and device, electronic equipment, a storage medium and a program product, and relates to the field of semiconductors, and the method comprises the steps: obtaining a control time sequence of a target device, and controlling a plurality of transistors according to the control time sequence. Wherein the target device comprises a plurality of transistors, and the plurality of transistors are connected in parallel. The control time sequence comprises a turn-on time sequence and / or a turn-off time sequence, the turn-on time sequence is used for representing turn-on interval time of the plurality of transistors, the turn-off time sequence is used for representing turn-off interval time of the plurality of transistors, the turn-on time sequence is determined according to turn-on delay time of the plurality of transistors, and the turn-off time sequence is determined according to zero-voltage turn-off time of a target transistor; the target transistor is at least one of the plurality of transistors. Thus, the turn-on time sequence and the turn-off time sequence are quantified, the turn-on time sequence and the turn-off time sequence with low loss can be obtained, and the loss in the turn-on and turn-off processes of the transistor is reduced as much as possible.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to a device control method, apparatus, electronic device, storage medium, and program product. Background Technology

[0002] The motor controller is the control center of the electric drive system of new energy vehicles, and power semiconductors are the core components of the motor controller. Commonly used power semiconductors include Si IGBTs (Silicon Insulated Gate Bipolar Transistors) and SiC MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors). These two devices have significantly different properties. By using Si IGBTs and SiC MOSFETs in parallel, the advantages of both can be combined to obtain a device with low conduction and switching losses, a small temperature coefficient, and relatively low cost, while also improving the reliability of the motor controller. Summary of the Invention

[0003] To overcome the problems existing in related technologies, this disclosure provides a device control method, apparatus, electronic device, storage medium, and program product.

[0004] According to a first aspect of the present disclosure, a device control method is provided, the method comprising: The control timing sequence of a target device is obtained; the target device includes multiple transistors connected in parallel; the control timing sequence includes turn-on timing and / or turn-off timing, wherein the turn-on timing sequence is used to characterize the interval time during which the multiple transistors are turned on, and the turn-off timing sequence is used to characterize the interval time during which the multiple transistors are turned off. The turn-on timing sequence is determined based on the turn-on delay time of the multiple transistors, and the turn-off timing sequence is determined based on the zero-voltage turn-off time of the target transistor. The target transistor is at least one of the multiple transistors. The plurality of transistors are controlled according to the control timing.

[0005] In this way, by quantifying the turn-on and turn-off timings, we can determine the turn-on and turn-off timings with lower losses, thereby minimizing the losses during the transistor turn-on and turn-off processes.

[0006] In one possible embodiment, the control timing is determined in the following manner: A double-pulse test is performed on the plurality of transistors to obtain test results; the test results include: the turn-on delay time of the plurality of transistors, and / or the zero-voltage turn-off time of the target transistor; The control timing is determined based on the test results.

[0007] In this way, characteristic data of multiple transistors can be obtained through double-pulse testing, thereby enabling accurate determination of the control timing of the target device.

[0008] In one possible embodiment, the control timing includes a turn-on timing, and the test result includes the turn-on delay time of the plurality of transistors; determining the control timing based on the test result includes: Based on the preset turn-on sequence of the plurality of transistors, the difference in turn-on delay time between two transistors with adjacent turn-on sequences is determined to obtain at least one turn-on time interval. The activation sequence is determined based on the preset activation order and the activation time interval.

[0009] In this way, by determining the turn-on delay time of two transistors with adjacent turn-on sequences, the turn-on time interval between each pair of transistors is determined, resulting in the turn-on timing sequence of multiple transistors. By turning on multiple transistors sequentially according to the turn-on timing sequence, the fastest turn-on speed and the lowest turn-on loss can be achieved.

[0010] In one possible embodiment, the control timing includes a turn-off timing, and the test result includes the zero-voltage turn-off time of the target transistor; determining the control timing based on the test result includes: The turn-off timing is determined based on the preset turn-off order of the plurality of transistors and the minimum value of the zero-voltage turn-off time of the target transistor.

[0011] In this way, since the turn-off timing is determined based on the zero-voltage turn-off time, it can be ensured that the next transistor is turned off only after the previous transistor is completely turned off, thus avoiding the problem of the previous transistor generating a large tail current and reducing turn-off losses.

[0012] In one possible embodiment, the plurality of transistors includes: Si IGBTs and SiC MOSFETs.

[0013] In this way, by quantifying the turn-on and turn-off timings of Si IGBTs and SiC MOSFETs, it is possible to determine turn-on and turn-off timings with lower losses, thereby minimizing the losses during the turn-on and turn-off processes of the target device composed of Si IGBTs and SiC MOSFETs connected in parallel.

[0014] In one possible embodiment, the turn-on time of the Si IGBT is earlier than the turn-on time of the SiC MOSFET; the turn-off time of the Si IGBT is earlier than the turn-off time of the SiC MOSFET.

[0015] In this way, turning on the Si IGBT first and then the SiC MOSFET, and turning off the Si IGBT first and then the SiC MOSFET, can minimize the losses of the target device composed of Si IGBT and SiC MOSFET connected in parallel during the turn-on and turn-off processes.

[0016] According to a second aspect of the present disclosure, a device control apparatus is provided, the apparatus comprising: An acquisition module is configured to acquire the control timing of a target device; the target device includes multiple transistors connected in parallel; the control timing includes an on-time sequence and / or an off-time sequence, wherein the on-time sequence characterizes the interval between the on-time of the multiple transistors, the off-time sequence characterizes the interval between the off-time of the multiple transistors, the on-time sequence is determined based on the on-time delay of the multiple transistors, and the off-time sequence is determined based on the zero-voltage off-time of the target transistor, wherein the target transistor is at least one of the multiple transistors; The control module is configured to control the plurality of transistors according to the control timing.

[0017] In one possible embodiment, the control timing is determined in the following manner: A double-pulse test is performed on the plurality of transistors to obtain test results; the test results include: the turn-on delay time of the plurality of transistors, and / or the zero-voltage turn-off time of the target transistor; The control timing is determined based on the test results.

[0018] In one possible embodiment, the control timing includes a turn-on timing, and the test result includes the turn-on delay time of the plurality of transistors; determining the control timing based on the test result includes: Based on the preset turn-on sequence of the plurality of transistors, the difference in turn-on delay time between two transistors with adjacent turn-on sequences is determined to obtain at least one turn-on time interval. The activation sequence is determined based on the preset activation order and the activation time interval.

[0019] In one possible embodiment, the control timing includes a turn-off timing, and the test result includes the zero-voltage turn-off time of the target transistor; determining the control timing based on the test result includes: The turn-off timing is determined based on the preset turn-off order of the plurality of transistors and the minimum value of the zero-voltage turn-off time of the target transistor.

[0020] According to a third aspect of the present disclosure, an electronic device is provided, comprising: processor; Memory used to store processor-executable instructions; The processor is configured to execute processor-executable instructions in the memory to implement the steps of the method described in the first aspect of the present disclosure.

[0021] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect of the present disclosure.

[0022] According to a fifth aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method described in the first aspect of the present disclosure.

[0023] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: This disclosure obtains the control timing of a target device and controls multiple transistors according to the control timing. The target device includes multiple transistors connected in parallel. The control timing includes turn-on timing and / or turn-off timing, where the turn-on timing characterizes the interval between the turn-on of the multiple transistors, and the turn-off timing characterizes the interval between the turn-off of the multiple transistors. This disclosure determines the turn-on timing of the multiple transistors based on their turn-on delay times and determines their turn-off timing based on the zero-voltage turn-off time of the target transistor. Quantizing the turn-on and turn-off timings allows for the determination of turn-on and turn-off timings with lower losses, thereby minimizing losses during transistor turn-on and turn-off processes.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0026] Figure 1 This is a schematic diagram of the operating region of a hybrid parallel device of Si IGBT and SiC MOSFET.

[0027] Figure 2This is a schematic diagram of multiple switching timings for a hybrid parallel device of Si IGBT and SiC MOSFET.

[0028] Figure 3 This is a flowchart illustrating a device control method according to an exemplary embodiment.

[0029] Figure 4 This is a flowchart illustrating a method for determining control timing according to an exemplary embodiment.

[0030] Figure 5 It is based on Figure 4 An embodiment shows a schematic diagram of a dual-pulse test.

[0031] Figure 6 This is a schematic diagram illustrating the turn-on loss of a hybrid parallel device of Si IGBT and SiC MOSFET according to an exemplary embodiment.

[0032] Figure 7 This is a schematic diagram illustrating the turn-off loss of a hybrid parallel device of Si IGBT and SiC MOSFET according to an exemplary embodiment.

[0033] Figure 8 This is a block diagram illustrating a device control apparatus according to an exemplary embodiment.

[0034] Figure 9 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0036] Before introducing a device control method, apparatus, electronic device, storage medium, and program product shown in the embodiments of this disclosure, the application scenarios of the embodiments of this disclosure will be introduced first.

[0037] The embodiments disclosed herein can be applied to high-voltage, high-power components such as motor controllers, on-board chargers, and DC-DC converters for new energy vehicles. They can also be widely applied to charging piles, photovoltaics, wind power, energy storage devices, smart grids, rail transit, consumer electronics, industrial automation, and other fields. This disclosure does not specifically limit the application scenarios.

[0038] Taking applications in the new energy vehicle sector as an example, new energy vehicles currently generally have a medium-voltage 400V platform and a high-voltage 800V platform. The motor controller is the control center of the electric drive system of new energy vehicles, and power semiconductors are the core components of the motor controller. On the medium-voltage 400V platform, the motor controller mainly uses Si IGBTs, and may also use SiC MOSFETs to improve efficiency; on the high-voltage 800V platform, the motor controller mainly uses SiC MOSFETs, and may also use SiIGBTs to reduce costs.

[0039] Si IGBTs and SiC MOSFETs have significantly different device properties. Si IGBTs have higher conduction losses at low currents and lower conduction losses at high currents, with a smaller temperature coefficient (the degree to which conduction losses increase with increasing temperature); however, they have higher switching losses and a higher temperature coefficient. SiC MOSFETs, on the other hand, have lower conduction losses at low currents, higher conduction losses at high currents, and a higher temperature coefficient; they also have very low switching losses and a low temperature coefficient. In recent years, the cost of SiC MOSFETs has decreased significantly, but it is still 2 to 2.5 times that of Si IGBTs of the same voltage and power rating.

[0040] By using Si IGBTs and SiC MOSFETs in parallel, the advantages of both can be combined to obtain a device with low conduction and switching losses, a small temperature coefficient, and relatively low cost. Specifically, at the same voltage and power rating, a hybrid parallel device of Si IGBTs and SiC MOSFETs will have lower losses and more stable temperature characteristics than Si IGBTs, while also being less expensive than SiC MOSFETs. Using Si IGBTs and SiC MOSFETs in parallel also allows the motor controller to operate independently of the other device in the event of a non-short-circuit fault in either the Si IGBT or SiC MOSFET, thus improving the reliability of the motor controller.

[0041] Based on the magnitude of the load current and the operating states of Si IGBTs and SiC MOSFETs, the operating regions of hybrid parallel Si IGBT and SiC MOSFET devices can be divided into three types, such as... Figure 1 As shown, in operating region I, the load current is less than i 1. SiCMOSFET operates independently; in operating region II, the load current is greater than... i l Less than i rate Si IGBTs and SiC MOSFETs operate simultaneously; in operating region III, the load current is greater than... i rate Si IGBTs operate independently. i1 represents the intersection of the output characteristic curves of Si IGBT and SiC MOSFET. i rate This is the rated current of the SiC MOSFET.

[0042] Reference Figure 1 In operating region II, Si IGBTs and SiC MOSFETs operate simultaneously, with various switching timing modes. For example... Figure 2 As shown in (a), the SiC MOSFET turns on earlier than the Si IGBT (ton_delay≥0) and turns off later than the Si IGBT (toff_delay≥0), thereby achieving zero-voltage turn-on and zero-voltage turn-off of the Si IGBT and reducing switching losses.

[0043] Wherein, ton_delay is the turn-on interval between the SiC MOSFET drive signal and the Si IGBT drive signal. If the SiC MOSFET drive signal turns on before the Si IGBT drive signal, ton_delay > 0; if the SiC MOSFET drive signal and the Si IGBT drive signal turn on simultaneously, ton_delay = 0; if the SiC MOSFET drive signal lags behind the Si IGBT drive signal, ton_delay < 0. toff_delay is the turn-off interval between the SiC MOSFET drive signal and the Si IGBT drive signal. If the SiC MOSFET drive signal turns off before the Si IGBT drive signal, toff_delay < 0; if the SiC MOSFET drive signal and the Si IGBT drive signal turn off simultaneously, toff_delay = 0; if the SiC MOSFET drive signal lags behind the Si IGBT drive signal, toff_delay > 0.

[0044] When using switching timing mode I, the switching losses are entirely borne by the SiC MOSFET. SiC MOSFETs experience significant thermal stress. To reduce the junction temperature of SiC MOSFETs under high load currents, various methods are typically employed. Figure 2 The control timing shown in (b)-(c) reduces the operating time of the SiC MOSFET. However, the control timing for each timing mode is not quantized, making it impossible to determine the control timing with the minimum loss, resulting in high losses during turn-on and turn-off.

[0045] The embodiments disclosed herein can be applied to Figure 2The control timing is shown in any of (b)-(c). In this embodiment, the turn-on timing of multiple transistors is determined based on their turn-on delay times, and the turn-off timing of multiple transistors is determined based on the zero-voltage turn-off time of the target transistor. Quantizing the turn-on and turn-off timings allows for the determination of turn-on and turn-off timings with lower losses, thereby minimizing losses during transistor turn-on and turn-off processes.

[0046] Figure 3 This is a flowchart illustrating a device control method according to an exemplary embodiment, such as... Figure 3 As shown, the method may include the following steps.

[0047] In step S101, the control timing of the target device is obtained.

[0048] The target device may include multiple transistors, which may be connected in parallel in a mixed manner. The control timing may include turn-on timing, turn-off timing, or both. Turn-on timing can be used to characterize the interval between the turn-on of multiple transistors, and turn-off timing can be used to characterize the interval between the turn-off of multiple transistors.

[0049] For example, the turn-on timing can be determined based on the turn-on delay times of multiple transistors, and the turn-off timing can be determined based on the zero-voltage turn-off time of the target transistor, where the target transistor can be at least one of the multiple transistors. The turn-on delay time can be understood as the time interval between the gate voltage rising to 10% of its peak value and the load current rising to 10% of its peak value. The zero-voltage turn-off time can be understood as the time elapsed from when the gate voltage begins to turn the transistor off until the voltage across the transistor rises to near zero voltage (e.g., 1% - 5% of the bus voltage). Both the turn-on and turn-off timings can be predetermined, and the predetermined turn-on and / or turn-off timings can be directly obtained when controlling the target device.

[0050] In some embodiments, the turn-on timing can be determined based on a preset turn-on sequence of multiple transistors and a turn-on delay time for each transistor. Similarly, the turn-off timing can be determined based on a preset turn-off sequence of multiple transistors and a zero-voltage turn-off time for the target transistor.

[0051] For example, multiple transistors include a first transistor, a second transistor, and a third transistor. A preset turn-on sequence could be: the first transistor, the second transistor, and the third transistor turn on sequentially; a preset turn-off sequence could be: the first transistor, the second transistor, and the third transistor turn off sequentially. The target transistor could be the first transistor or the second transistor. A first turn-on time interval between the first transistor and the second transistor can be determined based on the turn-on delay time of the first transistor and the turn-on delay time of the second transistor. A second turn-on time interval between the second transistor and the third transistor can be determined based on the turn-on delay time of the second transistor and the turn-on delay time of the third transistor. The turn-on timing sequence can include a first turn-on timing interval and a second turn-on time interval. A first turn-off time interval between the first transistor and the second transistor can be determined based on the zero-voltage turn-off time of the first transistor. A second turn-off time interval between the second transistor and the third transistor can be determined based on the zero-voltage turn-off time of the second transistor. The turn-off timing sequence can include a first turn-off time interval and a second turn-off time interval.

[0052] In other embodiments, the plurality of transistors may include a first transistor and a second transistor, the turn-on timing can be determined based on the turn-on delay time of the first transistor and the turn-on delay time of the second transistor, and the turn-off timing can be determined based on the zero-voltage turn-off time of the first transistor or the second transistor.

[0053] For example, the switching loss of the first transistor can be greater than that of the second transistor. The turn-on sequence of the first and second transistors can be that the first transistor turns on first, followed by the second. The turn-off sequence of the first and second transistors can be that the first transistor turns off first, followed by the second. The target transistor can be the first transistor, and the turn-off sequence can be determined based on the zero-voltage turn-off time of the first transistor. This ensures that the second transistor is turned off only after the first transistor is completely turned off, avoiding the problem of insufficient turn-off time interval causing a large tail current in the first transistor and increasing turn-off losses.

[0054] In step S102, multiple transistors are controlled according to the control timing.

[0055] For example, when the control timing includes a turn-on timing sequence, multiple transistors can be controlled to turn on in a preset turn-on order according to the turn-on timing sequence. When the control timing includes a turn-off timing sequence, multiple transistors can be controlled to turn off in a preset turn-off order according to the turn-off timing sequence. When the control timing includes both turn-on and turn-off timing sequences, multiple transistors can be controlled to turn on in a preset turn-on order according to the turn-on timing sequence, and multiple transistors can be controlled to turn off in a preset turn-off order according to the turn-off timing sequence.

[0056] In summary, this disclosure obtains the control timing of a target device and controls multiple transistors based on the control timing. The target device includes multiple transistors connected in parallel. The control timing includes turn-on timing and / or turn-off timing, where the turn-on timing characterizes the interval between the turn-on of the multiple transistors, and the turn-off timing characterizes the interval between the turn-off of the multiple transistors. This disclosure determines the turn-on timing of the multiple transistors based on their turn-on delay times and determines their turn-off timing based on the zero-voltage turn-off time of the target transistor. Quantizing the turn-on and turn-off timings allows for the determination of turn-on and turn-off timings with lower losses, thereby minimizing losses during transistor turn-on and turn-off processes.

[0057] Figure 4 This is a flowchart illustrating a method for determining control timing according to an exemplary embodiment, such as... Figure 4 As shown, the control timing is determined in the following way: In step S201, a double-pulse test is performed on multiple transistors to obtain the test results.

[0058] For example, a double-pulse test can be performed on each transistor to obtain results such as... Figure 5 The test results are shown. These results may include at least: the turn-on delay times of multiple transistors, and / or the zero-voltage turn-off time of the target transistor. (Refer to...) Figure 5 , Figure 5 In v ge Gate voltage, v ce The voltage across the transistor. i c The current flowing through the transistor, i L For load current, v dc Bus voltage t d(on) This can be the turn-on delay time of a transistor.

[0059] In step S202, the control timing is determined based on the test results.

[0060] In some embodiments, where the control timing includes a turn-on timing, the test result of the double-pulse test may include the turn-on delay times of multiple transistors. One implementation of step S202 may be: determining the difference in turn-on delay times between two transistors with adjacent turn-on sequences based on a preset turn-on order of the multiple transistors, thereby obtaining at least one turn-on time interval.

[0061] The activation sequence is determined based on the preset activation order and activation time interval.

[0062] For example, refer to Figure 2 In (d), multiple transistors may include Si IGBTs and SiC MOSFETs. The turn-on time of the Si IGBT can be earlier than that of the SiC MOSFET, i.e., the preset turn-on sequence is: turn on the Si IGBT first, then turn on the SiC MOSFET. A dual-pulse test can be performed on the Si IGBT and SiC MOSFET to obtain the turn-on delay time of the Si IGBT and the turn-on delay time of the SiC MOSFET. The difference between the turn-on delay times of the Si IGBT and the SiC MOSFET is taken as the turn-on time interval ton_delay, which can be calculated using Formula 1.

[0063] ton_delay = ton_delay_SiC - ton_delay_IGBT (Formula 1) Where ton_delay_SiC is the turn-on delay time of the SiC MOSFET, and ton_delay_IGBT is the turn-on delay time of the Si IGBT. Thus, the turn-on sequence is: the Si IGBT is turned on first, followed by the SiC MOSFET, with a turn-on time interval of ton_delay between the SiIGBT and the SiC MOSFET.

[0064] By employing the turn-on timing shown in the embodiments of this disclosure, when the target device is turned on, it can be ensured that the Si IGBT and SiC MOSFET are turned on simultaneously, that is, the load current flows through the Si IGBT and SiC MOSFET at the same time, thereby achieving the fastest turn-on speed and the lowest turn-on loss.

[0065] In other embodiments, where the control timing includes a turn-off timing, the test result of the double-pulse test may include the zero-voltage turn-off time of the target transistor. One implementation of step S202 may be: determining the turn-off timing based on a preset turn-off order of multiple transistors and the minimum value of the zero-voltage turn-off time of the target transistor.

[0066] For example, refer to Figure 2 In section (d), multiple transistors can include Si IGBTs and SiC MOSFETs. The turn-off time of the Si IGBT can be earlier than that of the SiC MOSFET, i.e., the preset turn-off sequence is: turn off the Si IGBT first, then turn off the SiC MOSFET. A double-pulse test can be performed on the Si IGBT to obtain its zero-voltage turn-off time, and the minimum value of the zero-voltage turn-off time of the Si IGBT is used as the turn-off time interval toff_delay.

[0067] toff_delay = toff_IGBT_ZVS_min (Formula 2) Here, tof_IGBT_ZVS_min can be the minimum value of the zero-voltage turn-off time of the Si IGBT. Thus, the turn-off sequence can be obtained as follows: turn off the Si IGBT first, then turn off the SiC MOSFET, and the turn-off time interval between the Si IGBT and the SiC MOSFET is tof_delay.

[0068] Since the Si IGBT must be completely turned off before the SiC MOSFET can be turned off when the target device is turned off, insufficient time intervals can cause a large tail current in the Si IGBT when the SiC MOSFET is turned off, increasing turn-off losses. By using the turn-off timing shown in the embodiments of this disclosure, the SiC MOSFET is turned off when the gate voltage of the Si IGBT is close to zero, which avoids a large tail current in the Si IGBT and thus reduces turn-off losses.

[0069] In other embodiments, a first drive signal and a second drive signal can be generated based on a driving PWM (Pulse Width Modulation) signal. The first drive signal can be used to drive the SiC MOSFET in a hybrid parallel device of Si IGBT and SiC MOSFET, and the second drive signal can be used to drive the Si IGBT in the same device. The first and second drive signals can be configured as follows: Figure 2 As shown in (d), the second drive signal can be turned on earlier than the first drive signal according to the turn-on time interval ton_delay, and the second drive signal can be turned off earlier than the first drive signal according to the turn-off time interval ton_delay.

[0070] This disclosure presents embodiments for a 1200V / 200A Si IGBT and SiC MOSFET hybrid parallel device, simulating the turn-on loss and total loss under different ton_delay and tof_delay conditions. Figure 6 This is a diagram illustrating the activation loss. Figure 7 This is a schematic diagram of the shutdown loss, such as... Figure 6 and Figure 7 As shown, by adopting the turn-on timing and turn-off timing proposed in the embodiments of this disclosure, the loss of turning on and off the target device is minimized.

[0071] exist Figure 6 In the middle, E on_MOS_IGBT For the turn-on loss of a hybrid parallel device of Si IGBT and SiC MOSFET; E on_MOSand E on_IGBT The turn-on losses of SiC MOSFETs and Si IGBTs are respectively; E cond_on The conduction loss during the turn-on process of a hybrid parallel device of Si IGBT and SiC MOSFET. Figure 7 In the middle, E off_Hys E represents the total turn-off loss of a hybrid parallel device of Si IGBTs and SiC MOSFETs. off_MOS and E off_IGBT The turn-off losses of SiC MOSFETs and Si IGBTs are respectively; E cond_off E represents the conduction loss during the turn-off process of a hybrid parallel device of Si IGBT and SiC MOSFET; off_MOS_IGBT E represents the turn-off loss during the turn-off process of a hybrid parallel device consisting of Si IGBTs and SiC MOSFETs. cond_off_IGBT and E cond_off_MOS These represent the conduction losses of Si IGBT and SiC MOSFET during the turn-off process of a hybrid parallel device consisting of Si IGBT and SiC MOSFET.

[0072] In summary, this disclosure obtains the control timing of a target device and controls multiple transistors based on the control timing. The target device includes multiple transistors connected in parallel. The control timing includes turn-on timing and / or turn-off timing, where the turn-on timing characterizes the interval between the turn-on of the multiple transistors, and the turn-off timing characterizes the interval between the turn-off of the multiple transistors. This disclosure determines the turn-on timing of the multiple transistors based on their turn-on delay times and determines their turn-off timing based on the zero-voltage turn-off time of the target transistor. Quantizing the turn-on and turn-off timings allows for the determination of turn-on and turn-off timings with lower losses, thereby minimizing losses during transistor turn-on and turn-off processes.

[0073] Figure 8 This is a block diagram illustrating a device control apparatus according to an exemplary embodiment, such as... Figure 8 As shown, the device 300 includes: Acquisition module 301 is configured to acquire the control timing of a target device. The target device includes multiple transistors connected in parallel. The control timing includes turn-on timing and / or turn-off timing. The turn-on timing characterizes the interval between the turn-on of the multiple transistors, and the turn-off timing characterizes the interval between the turn-off of the multiple transistors. The turn-on timing is determined based on the turn-on delay time of the multiple transistors, and the turn-off timing is determined based on the zero-voltage turn-off time of the target transistor. The target transistor is at least one of the multiple transistors.

[0074] The control module 302 is configured to control multiple transistors according to a control timing sequence.

[0075] In some embodiments, control timing is determined in the following ways: A double-pulse test is performed on multiple transistors to obtain test results. These results include the turn-on delay time of the multiple transistors and / or the zero-voltage turn-off time of the target transistor.

[0076] The control timing is determined based on the test results.

[0077] In other embodiments, the control timing includes turn-on timing, and the test results include the turn-on delay times of multiple transistors. Determining the control timing based on the test results includes: Based on the preset turn-on sequence of multiple transistors, the difference in turn-on delay time between two transistors with adjacent turn-on sequences is determined to obtain at least one turn-on time interval.

[0078] The activation sequence is determined based on the preset activation order and activation time interval.

[0079] In other embodiments, the control timing includes a turn-off timing, and the test results include the zero-voltage turn-off time of the target transistor. Determining the control timing based on the test results includes: The turn-off sequence is determined based on the preset turn-off order of multiple transistors and the minimum zero-voltage turn-off time of the target transistor.

[0080] In other embodiments, the plurality of transistors include: silicon insulated gate bipolar transistors (Si IGBTs) and silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs).

[0081] In other embodiments, the turn-on time of the Si IGBT is earlier than the turn-on time of the SiC MOSFET. The turn-off time of the Si IGBT is earlier than the turn-off time of the SiC MOSFET.

[0082] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0083] In summary, this disclosure obtains the control timing of a target device and controls multiple transistors based on the control timing. The target device includes multiple transistors connected in parallel. The control timing includes turn-on timing and / or turn-off timing, where the turn-on timing characterizes the interval between the turn-on of the multiple transistors, and the turn-off timing characterizes the interval between the turn-off of the multiple transistors. This disclosure determines the turn-on timing of the multiple transistors based on their turn-on delay times and determines their turn-off timing based on the zero-voltage turn-off time of the target transistor. Quantizing the turn-on and turn-off timings allows for the determination of turn-on and turn-off timings with lower losses, thereby minimizing losses during transistor turn-on and turn-off processes.

[0084] This disclosure also provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the steps of the device control method provided in this disclosure.

[0085] Figure 9 This is a block diagram illustrating an electronic device according to an exemplary embodiment. For example, the electronic device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0086] Reference Figure 9 The electronic device 800 may include one or more of the following components: processing component 802, memory 804, power supply component 806, multimedia component 808, audio component 810, input / output interface 812, sensor component 814, and communication component 816.

[0087] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the device control method described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0088] Memory 804 is configured to store various types of data to support the operation of electronic device 800. Examples of such data include instructions for any application or method operating on electronic device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0089] Power supply component 806 provides power to various components of electronic device 800. Power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 800.

[0090] Multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0091] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when electronic device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0092] Input / output interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, start buttons, and lock buttons.

[0093] Sensor assembly 814 includes one or more sensors for providing state assessments of various aspects of electronic device 800. For example, sensor assembly 814 can detect the on / off state of electronic device 800, the relative positioning of components such as the display and keypad of electronic device 800, changes in position of electronic device 800 or a component of electronic device 800, the presence or absence of user contact with electronic device 800, orientation or acceleration / deceleration of electronic device 800, and temperature changes of electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0094] Communication component 816 is configured to facilitate wired or wireless communication between electronic device 800 and other devices. Electronic device 800 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0095] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the device control method described above.

[0096] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, which can be executed by a processor 820 of an electronic device 800 to complete the aforementioned device control method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0097] In an exemplary embodiment, a vehicle is also provided that can be used to perform the device control method shown in the embodiments of this disclosure.

[0098] In another exemplary embodiment, a computer program product is also provided, which includes a computer program executable by a programmable electronic device, the computer program having a code portion for performing the device control method described above when executed by the programmable electronic device.

[0099] Those skilled in the art will also understand that the various illustrative logical blocks and steps listed in the embodiments of this application can be implemented by electronic hardware, computer software, or a combination of both. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the described functionality using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of this application.

[0100] It should be understood that, unless otherwise specifically indicated, features of various embodiments of this disclosure described herein can be combined with each other. As used herein, the term “and / or” includes any one of the relevant listed items and any combination of any two or more; similarly, “at least one of…” includes any one of the relevant listed items and any combination of any two or more.

[0101] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited to these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section. Furthermore, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include at least one of that feature. In the description herein, “a plurality” means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0102] Furthermore, the term “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as advantageous compared to other aspects or designs. Rather, the use of the term “exemplary” is intended to present the concept in a concrete manner. As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X applies A or B” is intended to mean any of the natural inclusive arrangements. That is, “X applies A or B” satisfies any of the foregoing instances if X applies A; X applies B; or both X applies A and B. Additionally, unless otherwise specified or clear from the context to refer to the singular form, the articles “a” and “an” as used in this application and the appended claims are generally understood to mean “one or more.”

[0103] Similarly, although this disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and variations and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terminology used to describe such components is intended to correspond to any component (functionally equivalent) that performs the specific function of the described component, even if structurally not equivalent to the disclosed structure. Furthermore, although specific features of this disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations, as may be desired and advantageous to any given or particular application. Moreover, with regard to the terms “comprising,” “owning,” “having,” “having,” or variations thereof as used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term “including.”

[0104] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

[0105] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A device control method, characterized in that, The method includes: The control timing sequence of a target device is obtained; the target device includes multiple transistors connected in parallel; the control timing sequence includes turn-on timing and / or turn-off timing, wherein the turn-on timing sequence is used to characterize the interval time during which the multiple transistors are turned on, and the turn-off timing sequence is used to characterize the interval time during which the multiple transistors are turned off. The turn-on timing sequence is determined based on the turn-on delay time of the multiple transistors, and the turn-off timing sequence is determined based on the zero-voltage turn-off time of the target transistor. The target transistor is at least one of the multiple transistors. The plurality of transistors are controlled according to the control timing.

2. The method according to claim 1, characterized in that, The control timing is determined in the following way: A double-pulse test is performed on the plurality of transistors to obtain test results; the test results include: the turn-on delay time of the plurality of transistors, and / or the zero-voltage turn-off time of the target transistor; The control timing is determined based on the test results.

3. The method according to claim 2, characterized in that, The control timing includes the turn-on timing, and the test results include the turn-on delay time of the plurality of transistors; Determining the control timing based on the test results includes: Based on the preset turn-on sequence of the plurality of transistors, the difference in turn-on delay time between two transistors with adjacent turn-on sequences is determined to obtain at least one turn-on time interval. The activation sequence is determined based on the preset activation order and the activation time interval.

4. The method according to claim 2, characterized in that, The control timing includes a turn-off timing, and the test result includes the zero-voltage turn-off time of the target transistor; Determining the control timing based on the test results includes: The turn-off timing is determined based on the preset turn-off sequence of the plurality of transistors and the minimum value of the zero-voltage turn-off time of the target transistor.

5. The method according to any one of claims 1-4, characterized in that, The plurality of transistors include: silicon insulated gate bipolar transistors (Si IGBTs) and silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs).

6. The method according to claim 5, characterized in that, The turn-on time of the Si IGBT is earlier than the turn-on time of the SiC MOSFET; the turn-off time of the Si IGBT is earlier than the turn-off time of the SiC MOSFET.

7. A device control apparatus, characterized in that, The device includes: An acquisition module is configured to acquire the control timing of a target device; the target device includes multiple transistors connected in parallel; the control timing includes an on-time sequence and / or an off-time sequence, wherein the on-time sequence characterizes the interval between the on-time of the multiple transistors, the off-time sequence characterizes the interval between the off-time of the multiple transistors, the on-time sequence is determined based on the on-time delay of the multiple transistors, and the off-time sequence is determined based on the zero-voltage off-time of the target transistor, wherein the target transistor is at least one of the multiple transistors; The control module is configured to control the plurality of transistors according to the control timing.

8. The apparatus according to claim 7, characterized in that, The control timing is determined in the following way: A double-pulse test is performed on the plurality of transistors to obtain test results; the test results include: the turn-on delay time of the plurality of transistors, and / or the zero-voltage turn-off time of the target transistor; The control timing is determined based on the test results.

9. The apparatus according to claim 8, characterized in that, The control timing includes the turn-on timing, and the test results include the turn-on delay time of the plurality of transistors; Determining the control timing based on the test results includes: Based on the preset turn-on sequence of the plurality of transistors, the difference in turn-on delay time between two transistors with adjacent turn-on sequences is determined to obtain at least one turn-on time interval. The activation sequence is determined based on the preset activation order and the activation time interval.

10. The apparatus according to claim 8, characterized in that, The control timing includes a turn-off timing, and the test result includes the zero-voltage turn-off time of the target transistor; Determining the control timing based on the test results includes: The turn-off timing is determined based on the preset turn-off order of the plurality of transistors and the minimum value of the zero-voltage turn-off time of the target transistor.

11. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to execute processor-executable instructions in the memory to implement the steps of the method according to any one of claims 1-6.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the method described in any one of claims 1-6.

13. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1-6.

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