Ultra-short dead zone phase frequency detector, high-speed ultra-low jitter charge pump circuit and phase-locked loop

Abstract

The invention discloses an ultra-short dead zone phase frequency detector, a high-speed ultra-low jitter charge pump circuit and a phase-locked loop. The circuit comprises a phase frequency detector, a high-speed level conversion circuit module and a high-speed low-noise charge pump circuit module, the output end of the phase frequency detector is connected with the input end of the high-speed level conversion circuit module, and the input end of the high-speed low-noise charge pump circuit module is connected with the output end of the high-speed level conversion circuit module; the phase frequency detector is used for generating a DN signal and a UP signal according to an input signal; the high-speed level conversion circuit module is used for converting the DN signal and the UP signal into signals adaptive to the high-speed low-noise charge pump circuit module to obtain the converted DN signal and the converted UP signal; and the high-speed low-noise charge pump circuit module is used for obtaining an output current according to the converted DN signal and the converted UP signal. The invention has the advantages of high speed, low noise, low stray, low power consumption and the like.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit technology, specifically relating to an ultra-short dead-time frequency and phase detector, a high-speed ultra-low jitter charge pump circuit, and a phase-locked loop. Background Technology

[0002] A phase-locked loop (PLL) is a closed-loop circuit system based on feedback control principles, widely used in communications, clock recovery, and other fields. Its core function is to precisely control the frequency and phase of an internal oscillator using an external reference signal, enabling the output signal to automatically track the input signal. In 5G communication systems, the frequency stability and phase noise performance of PLLs face even stricter requirements—excessive phase noise can cause spectral interference between adjacent channels, while spurious components can significantly degrade communication quality. Therefore, developing novel PLL phase noise suppression techniques is of great value.

[0003] The core of a phase-locked loop (PLL) mainly consists of a phase-frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider, as shown in Figure 1. The PFD detects the phase difference between the input and feedback signals and outputs an error voltage. The CP converts the error voltage output by the PFD into current and injects it into the loop filter. The loop filter removes high-frequency noise and generates a smooth DC control voltage, which also determines the system's dynamic response and stability. The VCO adjusts its output frequency according to the control voltage to achieve frequency and phase synchronization; its output frequency is linearly related to the control voltage. The frequency divider divides the VCO output signal in the feedback path, expanding the frequency synthesis range. The PLL achieves frequency tracking through closed-loop negative feedback. When the input and output signal frequencies are equal and the phase difference is stable, the system enters a locked state and outputs a high-quality clock signal. Phase-locked loops (PLLs) possess high-precision synchronization characteristics, achieving precise frequency and phase matching through closed-loop control. Simultaneously, loop filters effectively eliminate high-frequency interference, enhancing system stability. Their flexible application characteristics allow for a wide tuning range through frequency dividers, making them widely used in frequency synthesis, clock recovery, and other scenarios. With their stability and adaptability, PLLs have become a core module of modern electronic systems, playing a crucial role in various electronic devices.

[0004] As the core modules of a phase-locked loop (PLL), the circuit performance of the frequency and phase detector (PFD) and charge pump directly affects the quality of the final output signal of the entire PLL loop, and has a crucial impact on the performance of the PLL. However, traditional PFD and CP circuits have several key drawbacks: the excessively long dead time of the PFD degrades phase noise; the CP current mismatch problem is prominent, leading to worse PLL noise and spurious performance. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an ultra-short dead-time frequency and phase detector, a high-speed ultra-low jitter charge pump circuit, and a phase-locked loop, which have advantages such as high speed, low noise, low spurious emissions, and low power consumption.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides an ultra-short dead-time frequency and phase detector and a high-speed, ultra-low jitter charge pump circuit, comprising: a frequency and phase detector with an ultra-short dead time, a high-speed level conversion circuit module, and a high-speed, low-noise charge pump circuit module, wherein the output terminal of the frequency and phase detector is connected to the input terminal of the high-speed level conversion circuit module, and the input terminal of the high-speed, low-noise charge pump circuit module is connected to the output terminal of the high-speed level conversion circuit module. The frequency and phase detector is used to generate DN and UP signals based on the input signal; The high-speed level conversion circuit module is used to convert the DN signal and the UP signal into signals adapted to the high-speed low-noise charge pump circuit module, to obtain the converted DN signal and the converted UP signal. The high-speed, low-noise charge pump circuit module includes a current source using a short-channel transistor as a switch and a clamping operational amplifier, used to obtain the output current based on the converted DN signal and the converted UP signal.

[0007] The present invention also provides a phase-locked loop, including the above-mentioned ultra-short dead-time frequency detector and high-speed ultra-low jitter charge pump circuit.

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The circuit structure of the frequency and phase detector with ultra-short dead time designed in this invention has a very small dead time compared with the traditional PFD structure. It can achieve dead time control at the level of 40ps, which can effectively reduce the current noise injected into the loop filter by the charge pump.

[0009] (2) The high-speed charge pump circuit structure designed in this invention can effectively improve the switching speed of the charge pump by using a standard short-channel transistor as the current source switch, while also reducing the influence of the parasitic capacitance of the switching transistor; and, by using a clamping operational amplifier to reduce the current mismatch between the upper and lower currents of the charge pump, a current mismatch rate of less than 1% is achieved. This feature ensures the high precision and stability of the charge pump.

[0010] (3) The high-speed level conversion circuit structure designed in this invention can convert the output signal of PFD into a DN signal of 0~0.9V and a UP signal of 0.9V~1.8V. Combined with the charge pump structure designed in this invention, it can effectively reduce the noise of the current source while ensuring the ultra-high switching speed of the charge pump, and achieve better circuit performance.

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a phase-locked loop circuit structure; Figure 2 This is a schematic diagram of the structure of the ultra-short dead-zone frequency and phase detector and the high-speed ultra-low jitter charge pump circuit provided in the embodiment of the present invention; Figure 3 This is a circuit structure diagram of the frequency and phase detector and a timing diagram of the frequency and phase detector and the charge pump provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of a high-speed, low-noise charge pump circuit module provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of current mismatch of the charge pump under different output voltages provided in the embodiments of the present invention; Figure 6 This is a schematic diagram of a high-density MOM capacitor implemented using CMOS technology with multiple metal layers. Figure 7 This is a schematic diagram comparing the current noise before and after the introduction of a low-pass filter; Figure 8 This is a schematic diagram of a high-speed level conversion circuit module provided in an embodiment of the present invention; Figure 9 This is a waveform diagram of the input and output signals of the high-speed level conversion circuit module provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the instantaneous waveform and the upper and lower currents of the switch in the main current source when the charge pump is working, as provided in an embodiment of the present invention. Detailed Implementation

[0013] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0014] This invention provides an ultra-short dead-time frequency and phase detector and a high-speed, ultra-low jitter charge pump circuit. The circuit includes: a frequency and phase detector with an ultra-short dead time, a high-speed level conversion circuit module, and a high-speed, low-noise charge pump circuit module. The output terminal of the frequency and phase detector is connected to the input terminal of the high-speed level conversion circuit module, and the input terminal of the high-speed, low-noise charge pump circuit module is connected to its output terminal. The frequency and phase detector generates a DN signal and a UP signal based on the input signal, both of which are a differential signal pair. The high-speed level conversion circuit module converts the DN signal and the UP signal into signals adapted to the high-speed, low-noise charge pump circuit module, obtaining the converted DN signal and the converted UP signal. The high-speed, low-noise charge pump circuit module includes a current source using a short-channel transistor as a switch and a clamping operational amplifier, used to obtain an output current based on the converted DN signal and the converted UP signal. For example... Figure 2 This is a schematic diagram of the structure of the ultra-short dead-time frequency and phase detector and the high-speed, ultra-low jitter charge pump circuit provided in an embodiment of the present invention. Figure 2 As shown, the delay time of the frequency and phase detector in the circuit designed in this invention is adjustable, for example, it can be 40ps, 80ps, 160ps, and 320ps, and the MOS transistors in the frequency and phase detector are all low-voltage threshold transistors, i.e., LVT transistors. Figure 2 As shown, the high-speed level shifter module in this circuit design consists of an inverter, a capacitor, and a MOSFET. The high-speed, low-noise charge pump module includes two 8-bit current sources, V... CTRL This represents the voltage signal converted from the current output by the high-speed, low-noise charge pump circuit module.

[0015] Here, the frequency-phase detector (PFPD), as the core phase detection module in the phase-locked loop (PLL) system, possesses characteristics not only in phase difference detection but also in frequency difference detection. For example, the minimum dead time of the PFPD designed in this invention is 40 ps. Since the charge pump injection noise only contributes when the current is turned on, that is, the charge pump current noise, in addition to the noise contributed by the device itself, is also controlled by the dead time of the PFD. Therefore, this invention reduces loop noise by decreasing the minimum dead time of the PFD. In the PFD designed in this invention, utilizing the high-speed advantage of CMOS technology, the dead time of the PFD is successfully controlled to within 40 ps. This means that less current noise is injected into the loop filter during locking, significantly reducing the in-band noise contribution of the PFD+CP. Furthermore, the PFD adopts a fully differential form, which can effectively suppress common-mode noise and reduce the interference of power supply fluctuations and temperature drift on the PFD output, thereby improving the overall noise performance of the PLL. For example, Figure 3 The circuit structure diagram and charge pump timing diagram of the frequency and phase detector provided by this invention are shown. Specifically, Figure 3 Figure (a) is a circuit diagram of the frequency and phase detector provided by the present invention, as shown in Figure (a). Figure 3 As shown in Figure (a), the frequency and phase detector includes: a first D flip-flop D1, a second D flip-flop D2, an AND gate Y, and a delay unit T with controllable delay time. For example, the delay time of the delay unit can be 40 ps, ​​80 ps, ​​160 ps, ​​and 320 ps, ​​etc. (Continue to refer to...) Figure 3 In Figure (a), the Rst (reset) terminals of the first and second D flip-flops are connected to the output of the delay unit, and the input of the delay unit is connected to the output of the AND gate. The D terminals of both the first and second D flip-flops are connected to the power supply voltage VDD. The clk terminal of the first D flip-flop is connected to the frequency divider signal Div. The Q terminal of the first D flip-flop serves as the output of a frequency and phase detector for the DN signal, and is connected to one input of the AND gate. The clk terminal of the second D flip-flop is connected to the reference signal Ref. The Q terminal of the second D flip-flop serves as the output of a frequency and phase detector for the UP signal, and is connected to the other input of the AND gate. Specifically, Figure 3 Figure (b) shows the timing diagram of the frequency and phase detector and the high-speed, low-noise charge pump circuit module, where I cp The current output by the high-speed, low-noise charge pump circuit module, such as Figure 3 As shown in Figure (b), after the phase-locked loop is locked, signals Div, Ref, DN, UP, and I... cp The frequencies are the same, and within one cycle, the signals Div, Ref, DN, UP, and I... cpThe rising edge triggers at the same time, and the rising edge durations of Div and Ref are the same. DN, UP, and I cp The rising edges of Div and Ref have the same duration, and the rising edge duration of Div and Ref is greater than that of DN, UP, and I. cp The duration of the rising edge.

[0016] In a charge pump phase-locked loop (CPPLL), a frequency and phase discriminator controls the conduction state of a switch via UP / DN pulse signals, thereby adjusting the operating state of the upper and lower current sources (IUP / IDN) in the charge pump and converting phase error information into a current signal. This current signal drives the loop filter to generate a tuning voltage Vctrl, which ultimately controls the output frequency of the voltage-controlled oscillator. A high-speed charge pump helps reduce the loop division ratio of the PLL, thus achieving lower jitter performance. Simultaneously, the matching accuracy of the charge pump current source directly affects the linearity of the phase-to-voltage conversion. Specifically, the high-speed, low-noise charge pump circuit module designed in this invention includes: a mirror current feedback operational amplifier AMP1, a bias isolation drive operational amplifier AMP2, a clamping operational amplifier AMP3, resistors R1, R2, and R3, a capacitor C05, low-pass filters LPF1 and LPF2, MOSFETs M11, M12, M15, and M16, a main current source, and a calibration current source. The main current source and the calibration current source are connected in parallel, and both the main current source and the calibration current source are connected to the power supply voltage VDD. The ground terminals of both the main current source and the calibration current source are grounded. The negative input terminal of AMP1 is used to connect the reference current signal IREF and is also connected to one end of R1, with the other end of R1 grounded. The positive input terminal of AMP1 is connected to the source of M11 and one end of R2, with the other end of R2 grounded. The output terminal of AMP1 is connected to the gate of M11, the drain of M11, the drain of M12, the positive input terminal of AMP3, and the negative input terminal of AMP2. The positive input terminal of AMP2 is connected to its own output terminal and one end of LPF2. The other end of LPF2 is connected to the gate of M16, one end of C05, and the main current source. The first terminal is connected to the first terminal of the calibration current source. The negative input terminal of AMP3 is connected to the second terminal of both the main current source and the calibration current source, serving as the output terminal of the high-speed low-noise charge pump circuit module. The output terminal of AMP3 is connected to the gate of M12 and one end of LPF1. The source of M12 is connected to one end of R3, and the other end of R3 is grounded. The other end of LPF1 is connected to the gate of M15, the other end of C05, the third terminal of the main current source, and the third terminal of the calibration current source. The control terminals of the first switch in the main current source and the second switch in the calibration current source are both connected to the converted UP signal. The control terminals of the third switch in the main current source and the fourth switch in the calibration current source are both connected to the converted DN signal.For example, both the main current source and the calibration current source are eight-bit current sources. The control terminal of the first switch in the i-th bit circuit structure of the main current source and the control terminal of the second switch in the i-th bit circuit structure of the calibration current source are connected to the i-th bit signal in the converted UP signal; the control terminal of the third switch in the i-th bit circuit structure of the main current source and the control terminal of the fourth switch in the i-th bit circuit structure of the calibration current source are connected to the i-th bit signal in the converted DN signal, where i takes the value of 0 to 7. The circuit structure of the i-th position of the main current source includes: switch S4, resistor R03, MOSFET M13, MOSFET M14, resistor R02, and switch S5. S4 is the first switch, and S5 is the third switch. One end of S4 is connected to the power supply voltage VDD, and the other end of S4 is connected to one end of R03. The other end of R03 is connected to the source of M13. The gate of M13 serves as the third terminal of the main current source, and the drain of M13 serves as the second terminal of the main current source. Furthermore, the drain of M13 is connected to the drain of M14, and the gate of M14 serves as the first terminal of the main current source. The source of M14 is connected to one end of R02, and the other end of R02 is connected to one end of S5. The other end of S5 is grounded. The circuit structure of the i-th bit of the calibration current source includes: switch S6, resistor R13, MOSFET M17, MOSFET M18, resistor R12, and switch S7. S6 is the second switch, and S7 is the fourth switch. One end of S6 is connected to the power supply voltage VDD, and the other end of S6 is connected to one end of R13. The other end of R13 is connected to the source of M17. The gate of M17 serves as the third terminal of the calibration current source, and the drain of M17 serves as the second terminal of the calibration current source. Furthermore, the drain of M17 is connected to the drain of M18, and the gate of M18 serves as the first terminal of the calibration current source. The source of M18 is connected to one end of R12, and the other end of R12 is connected to one end of S7. The other end of S7 is grounded. (Example...) Figure 4 This is a schematic diagram of a circuit structure for a high-speed, low-noise charge pump circuit module designed in this invention. Figure 4 As shown, CP[7:0] represents an eight-bit main current source, Cal_CP[7:0] represents an eight-bit calibration current source, and UP[0] represents the 0th bit signal in the converted UP signal, used to control the on / off state of S4 in the 0th bit circuit structure of CP[7:0] and S6 in the 0th bit circuit structure of Cal_CP[7:0]. Correspondingly, DN[0] represents the 0th bit signal in the converted DN signal, used to control the on / off state of S5 in the 0th bit circuit structure of CP[7:0] and S7 in the 0th bit circuit structure of Cal_CP[7:0]. Continuing as... Figure 4 As shown, the high-speed, low-noise charge pump circuit module also includes switches S1, S2, and S3. LPF1 is composed of resistor R4, capacitor C01, and capacitor C03, and R4, C01, and C03 are arranged according to... Figure 4 The connection method is as follows: LPF2 consists of resistor R5, capacitor C02, and capacitor C04, and R5, C02, and C04 are connected in accordance with... Figure 4 Connection method.

[0017] Figure 4 In this configuration, M11, M12, M13, and M14 form a current mirror. R1, R2, R3, R03, R13, R02, and R12 are all source degradation resistors, with R3, R03, and R13 having the same resistance value, and R2, R02, and R12 also having the same resistance value. S4, S5, S6, and S7 are all standard short-channel transistors, meaning their gate breakdown voltage is 1V in TSMC's 28nm process. Figure 4 As shown, AMP1 achieves efficient current conversion and precise current control by mirroring and amplifying the IREF current to a multiple of R2 / R1, and converting the N-type current mirror to a P-type current mirror using M11 and M12. AMP2 isolates the reference current source IREF from the charge pump switch to reduce the coupling interference of switch S5 to the gate of M11 at M14. AMP3 effectively reduces the charge / discharge current mismatch caused by the output voltage difference by clamping the drain voltage of M12 to the output node voltage. Low-pass filters LPF1 and LPF2 and source degradation resistors help optimize the noise of the charge pump, giving it better performance. In this invention, the main current source is composed of an eight-bit current switch CP[7:0], which can provide a wide range of current regulation from 2mA to 32mA and achieves a current mismatch rate of less than 1%, a feature that ensures the high accuracy and stability of the charge pump. For example, Figure 5 This is a schematic diagram illustrating the current mismatch of the charge pump (i.e., the high-speed, low-noise charge pump circuit module) under different output voltages, such as... Figure 5 As shown, the current mismatch remains below 0.26% within the output swing range. Current calibration is controlled by another set of eight-bit current switches, Cal_CP[7:0], with a control accuracy of 2mA / 256 steps. The calibration current supports three modes: charge compensation, discharge compensation, and follow compensation, adaptable to different operating conditions. Since the noise characteristics of CMOS technology are inherently inferior to low-noise technologies such as SiGe, to further optimize performance, capacitors C01 and C02 in this invention are both high-density MOM capacitors implemented using multilayer metals in CMOS technology. For example... Figure 6 These are high-density MOM capacitors implemented using CMOS multilayer metal technology, which have a larger capacitance value per unit area, effectively saving chip area. And, as... Figure 4 As shown, this invention also connects the VUP and VDN nodes to external capacitors C03 and C04 for filtering. This reduces noise and the coupling of the charge pump reference clock. For example, Figure 7 This diagram illustrates the comparison of current noise before and after the introduction of a low-pass filter. Simulation verification shows that this scheme reduces the charge pump current noise by 15dB at a 1MHz frequency offset, and optimizes the phase noise contribution to -222dBA / Hz@1MHz. Furthermore, to ensure sufficient output swing for the UP and DN current sources, thereby maintaining linear current output and avoiding increased VCO noise and reduced PLL spurious performance caused by high KVCO requirements, the entire high-speed, low-noise charge pump circuit module designed in this invention needs to operate under a 1.8V power supply. This balances high precision, low noise, and high-speed performance, providing a stable and high-performance current source solution for the charge pump.

[0018] To effectively reduce noise in the current source, this invention employs a 1.8V thick-gate transistor to construct a mirrored current source. However, this design choice conflicts to some extent with the goal of pursuing high-speed performance. Therefore, this invention uses a standard short-channel transistor as the switch for the current source. However, the breakdown voltage of the gate of a standard short-channel transistor in TSMC's 28nm process is 1V, which cannot withstand an input signal with a swing of 1.8V. This necessitates level conversion of the drive signals (DN and UP signals) for the current source switch in the high-speed, low-noise charge pump circuit module. The charging current is controlled by a switching voltage of 1.8V to 0.9V, and the discharging current is controlled by a switching voltage of 0V to 0.9V. Based on this, this invention provides a high-speed level conversion circuit module that can convert the output DN and UP signals of the PFD into 0~0.9V DN signals and 0.9V~1.8V UP signals, respectively.

[0019] In this invention, the high-speed level conversion circuit module includes a first conversion unit and a second conversion unit, both of which are composed of an inverter, a capacitor, and a MOSFET. The two input terminals of the first conversion unit are connected to a pair of differential signals constituting a UP signal, and the output terminal of the first conversion unit is used to output the converted UP signal. The two input terminals of the second conversion unit are connected to a pair of differential signals constituting a DN signal, and the output terminal of the second conversion unit is used to output the converted DN signal. For example... Figure 8 This is a schematic diagram of the circuit structure of the high-speed level conversion circuit module designed in this invention. For example... Figure 8As shown, the first conversion unit includes: a first inverter F1, a second inverter F2, a third inverter F3, a fourth inverter F4, capacitors C1 and C2, PMOS transistors M1 and M2; the second conversion unit includes: a fifth inverter F5, a sixth inverter F6, a seventh inverter F7, an eighth inverter F8, capacitors C3 and C4, NMOS transistors M3 and M4. The power supply terminals of F1 and F2 are both connected to the first power supply voltage VDD10, and the ground terminals of F1 and F2 are both grounded to GND. The input terminal of F1 is one of the two differential signals that constitute the UP signal, and the input terminal of F2 is the other of the two differential signals that constitute the UP signal. The output terminal of F1 is connected to one end of C1 and the gate of M2, and the other end of C1 is connected to the drain of M1 and the input terminal of F3. The source terminals of M1 and M2 are both connected to the third power supply voltage VDD09. The power supply terminals of F3 and F4 are both connected to the second power supply voltage VDD18, and the ground terminals of F3 and F4 are both connected to the third power supply voltage VDD09. The output terminal of F3 is used to output the converted UP signal. The output terminal of F2 is connected to one end of C2 and the gate of M1, and the other end of C2 is connected to the drain of M2 and the input terminal of F4. The power supply terminals of F5 and F6 are both connected to the first power supply voltage VDD10, and the ground terminals of F5 and F6 are both grounded to GND. The input terminal of F5 is one of the two differential signals constituting the DN signal, and the input terminal of F6 is the other of the two differential signals constituting the DN signal. The output terminal of F5 is simultaneously connected to one end of C3 and the gate of M4, and the other end of C3 is simultaneously connected to the drain of M3 and the input terminal of F7. The sources of M3 and M4 are both grounded to GND. The power supply terminals of F7 and F8 are both connected to the third power supply voltage VDD09, and the ground terminals of F7 and F8 are both grounded to GND. The output terminal of F8 is used to output the converted DN signal. The output terminal of F6 is simultaneously connected to one end of C4 and the gate of M3, and the other end of C4 is simultaneously connected to the drain of M4 and the input terminal of F8. The first power supply voltage VDD10 is used to provide a 1V voltage, the second power supply voltage VDD18 is used to provide a 1.8V voltage, and the third power supply voltage VDD09 is used to provide a 0.9V voltage.

[0020] Figure 8 In this circuit, C1, C2, C3, and C4 are all AC coupling capacitors. After passing through these capacitors, the signal is no longer affected by the common-mode voltage at the front end. This common-mode voltage is determined by transistors M1, M2, M3, and M4. The power supply and ground voltages for the input stage inverter are 1V and 0V, respectively. The power supply and ground voltages for the output UP stage inverter are 1.8V and 0.9V, respectively. The power supply and ground voltages for the output DN stage inverter are 0.9V and 0V, respectively. An example is shown below: [Example waveform diagram of the input and output signals of the high-speed level conversion circuit module]. Figure 9 As shown, Figure 9(a) shows the input signal V of the high-speed level conversion circuit module.PFD_P and V PFD_N That is, the 0~1V ultra-narrow pulse width signal output by the PFD is converted into a 0~0.9V DN signal after passing through the high-speed level conversion circuit module. UP and UP signal V of 0.9V~1.8V DN ,like Figure 9 As shown in Figure (b) above. This ensures both the ultra-high switching speed of the current source and effectively reduces its noise, achieving better phase-locked loop performance. For example, when the charge pump (i.e., the high-speed, low-noise charge pump circuit module) is operating, the instantaneous waveforms of the switches in the main current source and the current rise and fall are as follows: Figure 10 As shown, where, Figure 10 Figure (a) shows the voltage V of switch S4 in the main current source when the charge pump is working. UP and the voltage V of switch S5 DN Instantaneous waveform diagram, Figure 10 Figure (b) shows the current I during the operation of the charge pump. UP and the current I DN The diagram illustrates the changes. Clearly, the high-speed level conversion circuit module designed in this invention not only converts the PFD output signal into a 0~0.9V DN signal and a 0.9V~1.8V UP signal, but also, in conjunction with the charge pump structure designed in this invention, effectively reduces the noise of the current source while ensuring the ultra-high switching speed of the charge pump, achieving better circuit performance.

[0021] The present invention also provides a phase-locked loop, including the above-mentioned ultra-short dead-time frequency and phase detector, a high-speed ultra-low jitter charge pump circuit, a voltage-controlled oscillator, and a frequency divider.

[0022] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0024] In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. While different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce a good effect.

[0025] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A frequency and phase detector with ultra-short dead time and a charge pump circuit with high speed and ultra-low jitter, characterized in that, include: The device includes a frequency and phase detector with an ultra-short dead time, a high-speed level conversion circuit module, and a high-speed low-noise charge pump circuit module. The output terminal of the frequency and phase detector is connected to the input terminal of the high-speed level conversion circuit module, and the input terminal of the high-speed low-noise charge pump circuit module is connected to the output terminal of the high-speed level conversion circuit module. The frequency and phase detector is used to generate DN and UP signals based on the input signal; The high-speed level conversion circuit module is used to convert the DN signal and the UP signal into signals adapted to the high-speed low-noise charge pump circuit module, to obtain the converted DN signal and the converted UP signal. The high-speed, low-noise charge pump circuit module includes a current source using a short-channel transistor as a switch and a clamping operational amplifier, used to obtain the output current based on the converted DN signal and the converted UP signal.

2. The ultra-short dead-time frequency and phase detector and the high-speed, ultra-low jitter charge pump circuit according to claim 1, characterized in that, The frequency and phase detector includes: a first D flip-flop, a second D flip-flop, an AND gate, and a delay unit with controllable delay time; The Rst terminals of the first D flip-flop and the second D flip-flop are connected to the output terminal of the delay unit, and the input terminal of the delay unit is connected to the output terminal of the AND gate. The D terminals of both the first and second D flip-flops are connected to the power supply voltage VDD. The clk terminal of the first D flip-flop is connected to the frequency divider signal Div. The Q terminal of the first D flip-flop serves as the output terminal of the frequency and phase detector for outputting the DN signal. Furthermore, the Q terminal of the first D flip-flop is connected to one input terminal of the AND gate. The clk terminal of the second D flip-flop is connected to the reference signal Ref. The Q terminal of the second D flip-flop serves as the output terminal of the frequency and phase detector for outputting the UP signal. Furthermore, the Q terminal of the second D flip-flop is connected to the other input terminal of the AND gate.

3. The ultra-short dead-time frequency and phase detector and the high-speed, ultra-low jitter charge pump circuit according to claim 1, characterized in that, The converted DN signal is 0~0.9V, and the converted UP signal is 0.9~1.8V.

4. The ultra-short dead-time frequency and phase detector and the high-speed, ultra-low jitter charge pump circuit according to claim 1, characterized in that, Both the DN signal and the UP signal are a pair of differential signals; The high-speed level conversion circuit module includes: a first conversion unit and a second conversion unit, and both the first conversion unit and the second conversion unit are composed of an inverter, a capacitor and a MOSFET; The first conversion unit has two input terminals connected to a pair of differential signals constituting the UP signal, and its output terminal is used to output the converted UP signal. The second conversion unit has two input terminals connected to a pair of differential signals constituting the DN signal, and its output terminal is used to output the converted DN signal.

5. The ultra-short dead-time frequency and phase detector and the high-speed, ultra-low jitter charge pump circuit according to claim 4, characterized in that, The first conversion unit includes: a first inverter F1, a second inverter F2, a third inverter F3, a fourth inverter F4, a capacitor C1, a capacitor C2, a PMOS transistor M1, and a PMOS transistor M2; In this configuration, the power supply terminals of F1 and F2 are both connected to the first power supply voltage VDD10, and the ground terminals of F1 and F2 are both grounded. The input terminal of F1 is one of the two differential signals constituting the UP signal, and the input terminal of F2 is the other of the two differential signals constituting the UP signal. The output terminal of F1 is simultaneously connected to one end of C1 and the gate of M2, and the other end of C1 is simultaneously connected to the drain of M1 and the input terminal of F3. The sources of M1 and M2 are both connected to the third power supply voltage VDD09. The power supply terminals of F3 and F4 are both connected to the second power supply voltage VDD18, and the ground terminals of F3 and F4 are both connected to the third power supply voltage VDD09. The output terminal of F3 is used to output the converted UP signal. The output terminal of F2 is simultaneously connected to one end of C2 and the gate of M1, and the other end of C2 is simultaneously connected to the drain of M2 and the input terminal of F4.

6. The ultra-short dead-time frequency and phase detector and the high-speed, ultra-low jitter charge pump circuit according to claim 4, characterized in that, The second conversion unit includes: a fifth inverter F5, a sixth inverter F6, a seventh inverter F7, an eighth inverter F8, a capacitor C3, a capacitor C4, an NMOS transistor M3, and an NMOS transistor M4; In this configuration, the power supply terminals of F5 and F6 are both connected to the first power supply voltage VDD10, and the ground terminals of F5 and F6 are both grounded. The input terminal of F5 is one of the two differential signals constituting the DN signal, and the input terminal of F6 is the other of the two differential signals constituting the DN signal. The output terminal of F5 is simultaneously connected to one end of C3 and the gate of M4, and the other end of C3 is simultaneously connected to the drain of M3 and the input terminal of F7. The source terminals of M3 and M4 are both grounded. The power supply terminals of F7 and F8 are both connected to the third power supply voltage VDD09, and the ground terminals of F7 and F8 are both grounded. The output terminal of F8 is used to output the converted DN signal. The output terminal of F6 is simultaneously connected to one end of C4 and the gate of M3, and the other end of C4 is simultaneously connected to the drain of M4 and the input terminal of F8.

7. The ultra-short dead-time frequency and phase detector and the high-speed, ultra-low jitter charge pump circuit according to claim 5 or 6, characterized in that, The first power supply voltage VDD10 is used to provide 1V, the second power supply voltage VDD18 is used to provide 1.8V, and the third power supply voltage VDD09 is used to provide 0.9V.

8. The ultra-short dead-time frequency and phase detector and the high-speed, ultra-low jitter charge pump circuit according to claim 1, characterized in that, The high-speed, low-noise charge pump circuit module includes: a mirror current feedback operational amplifier AMP1, a bias isolation drive operational amplifier AMP2, a clamping operational amplifier AMP3, resistors R1, R2, and R3, a capacitor C05, a low-pass filter LPF1, a low-pass filter LPF2, MOSFETs M11, M12, M15, and M16, a main current source, and a calibration current source. The main current source and the calibration current source are connected in parallel. Both the main current source and the calibration current source are connected to the power supply voltage VDD. Both the main current source and the calibration current source are grounded. The negative input terminal of AMP1 is used to connect to the reference current signal IREF and is simultaneously connected to one end of R1, with the other end of R1 grounded. The positive input terminal of AMP1 is simultaneously connected to the source of M11 and one end of R2, with the other end of R2 grounded. The output terminal of AMP1 is simultaneously connected to the gate of M11, the drain of M11, the drain of M12, the positive input terminal of AMP3, and the negative input terminal of AMP2. The positive input terminal of AMP2 is simultaneously connected to its own output terminal and one end of LPF2. The other end of LPF2 is simultaneously connected to the gate of M16, one end of C05, and the first terminal of the main current source. The AMP3 is connected to the first terminal of the calibration current source. The negative input terminal of AMP3 is connected to both the second terminal of the main current source and the second terminal of the calibration current source, serving as the output terminal of the high-speed low-noise charge pump circuit module. The output terminal of AMP3 is connected to the gate of M12 and one end of LPF1. The source of M12 is connected to one end of R3, and the other end of R3 is grounded. The other end of LPF1 is connected to the gate of M15, the other end of C05, the third terminal of the main current source, and the third terminal of the calibration current source. The control terminals of the first switch in the main current source and the second switch in the calibration current source are both connected to the converted UP signal. The control terminals of the third switch in the main current source and the fourth switch in the calibration current source are both connected to the converted DN signal.

9. The ultra-short dead-time frequency and phase detector and the high-speed, ultra-low jitter charge pump circuit according to claim 8, characterized in that, Both the main current source and the calibration current source are eight-bit current sources. The control terminal of the first switch in the i-th bit circuit structure of the main current source and the control terminal of the second switch in the i-th bit circuit structure of the calibration current source are connected to the i-th bit signal in the converted UP signal; the control terminal of the third switch in the i-th bit circuit structure of the main current source and the control terminal of the fourth switch in the i-th bit circuit structure of the calibration current source are connected to the i-th bit signal in the converted DN signal, where i takes the value of 0~7. The circuit structure of the i-th position of the main current source includes: switch S4, resistor R03, MOSFET M13, MOSFET M14, resistor R02, and switch S5. S4 is the first switch, S5 is the third switch, one end of S4 is connected to the power supply voltage VDD, the other end of S4 is connected to one end of R03, the other end of R03 is connected to the source of M13, the gate of M13 serves as the third terminal of the main current source, the drain of M13 serves as the second terminal of the main current source, and the drain of M13 is connected to the drain of M14. The gate of M14 serves as the first terminal of the main current source, the source of M14 is connected to one end of R02, the other end of R02 is connected to one end of S5, and the other end of S5 is grounded. The circuit structure of the i-th bit of the calibration current source includes: switch S6, resistor R13, MOSFET M17, MOSFET M18, resistor R12, and switch S7. S6 is the second switch, S7 is the fourth switch, one end of S6 is connected to the power supply voltage VDD, the other end of S6 is connected to one end of R13, the other end of R13 is connected to the source of M17, the gate of M17 serves as the third terminal of the calibration current source, the drain of M17 serves as the second terminal of the calibration current source, and the drain of M17 is connected to the drain of M18. The gate of M18 serves as the first terminal of the calibration current source, the source of M18 is connected to one end of R12, the other end of R12 is connected to one end of S7, and the other end of S7 is grounded.

10. A phase-locked loop, characterized in that, It includes the ultra-short dead-zone frequency and phase detector and the high-speed, ultra-low jitter charge pump circuit described in any one of claims 1 to 9.

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