Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate and a ring oscillator circuit disposed thereon. In the ring oscillator circuit, an NMOS (N-channel Metal Oxide Semiconductor) transistor is isolated through a double-diffusion interruption structure, a PMOS (P-channel Metal Oxide Semiconductor) transistor is isolated through a single-diffusion interruption structure, and the single-diffusion interruption structure applies pressure stress to a channel region of the PMOS transistor so as to improve the performance of the PMOS transistor. Meanwhile, a double-diffusion interruption structure configured for the NMOS transistor can avoid the adverse effect of the pressure stress on the performance of the NMOS transistor. Through a design and process collaborative optimization method, on the premise of not causing negative influence on the performance of the NMOS transistor, the performance of the PMOS transistor serving as a performance bottleneck is improved in a targeted manner, so that the overall performance of the ring oscillator circuit is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] In recent years, with the continuous advancement of semiconductor manufacturing processes, the feature size of integrated circuits has continued to shrink, reaching advanced technology nodes of 28 nanometers and below. In these advanced process nodes, to improve transistor integration density and save chip layout area, the industry commonly employs single-diffusion interrupt technology to achieve electrical isolation between transistors. Compared to traditional isolation technologies, single-diffusion interrupt technology can significantly reduce the spacing between transistors in a certain direction (e.g., the X-axis), thereby integrating more functional units within a limited chip space.

[0003] In existing technologies, the application of single-diffused interrupts is typically concentrated in areas with extremely high integration requirements, such as standard cell libraries (e.g., 6-transistor SRAM cells), with the primary design consideration being area saving. However, during the formation of a single-diffused interrupt structure, dielectric materials (such as silicon nitride or silicon oxide) need to be backfilled into the etched isolation trenches. These backfill materials can introduce stress into the active region of the transistor due to their own physical properties and the mismatch in thermal expansion coefficients with the surrounding materials.

[0004] Stress has a significant impact on the performance of field-effect transistors (MOSFETs). Generally speaking, compressive stress can improve the hole mobility of P-channel MOSFETs (PMOS), thereby enhancing their driving capability; while tensile stress is beneficial to the electron mobility of N-channel MOSFETs (NMOS).

[0005] In certain circuit designs, such as ring oscillators, performance is directly related to the combined performance of the NMOS and PMOS transistors that make up the circuit. In traditional designs, the NMOS and PMOS transistors in a ring oscillator circuit are typically isolated using a double-diffusion interruption structure. While this structure provides good isolation, the introduced stress is usually uniform or insignificant, making it impossible to differentiate the stress on the NMOS and PMOS transistors. Since the performance of the PMOS transistor is often the bottleneck for ring oscillators, this indiscriminate design approach limits further optimization of the overall circuit performance.

[0006] Therefore, how to improve the performance of different types of transistors in a ring oscillator circuit by using innovative design and process collaboration methods and stress engineering principles to optimize the overall performance of the circuit is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] The technical problem to be solved by this invention is that, in the prior art, NMOS transistors and PMOS transistors in ring oscillator circuits usually adopt the same isolation structure (e.g., both are double-diffused interrupt structures). This indiscriminate design makes it impossible to perform targeted performance optimization on transistors with different characteristics. In particular, it is difficult to use stress engineering principles to improve the performance of PMOS transistors, which are the bottleneck of circuit performance, while avoiding adverse effects on NMOS transistors, thus limiting the further improvement of the overall performance of the ring oscillator circuit.

[0008] To achieve the above and other related objectives, the present invention provides a semiconductor device comprising:

[0009] Base;

[0010] A ring oscillator circuit is disposed on the substrate, and the ring oscillator circuit includes:

[0011] At least one NMOS transistor, said NMOS transistor being isolated by a double-diffused interrupt structure; and

[0012] At least one PMOS transistor, the PMOS transistor being isolated by a single-diffusion interruption structure, wherein the single-diffusion interruption structure applies compressive stress to the channel region of the PMOS transistor.

[0013] Preferably, the single-diffusion interruption structure includes an isolation groove filled with dielectric material.

[0014] Preferably, the compressive stress generated by the dielectric material is used to improve the carrier mobility of the PMOS transistor.

[0015] Preferably, the dielectric material comprises silicon nitride and / or silicon oxide.

[0016] Preferably, the dual-diffusion interruption structure makes the channel region of the NMOS transistor essentially unaffected by the compressive stress.

[0017] Accordingly, the present invention also provides a method for manufacturing the above-mentioned semiconductor device, comprising:

[0018] Step 1: Provide a substrate on which an area for forming a ring oscillator circuit is defined;

[0019] Step 2: In the region used to form the ring oscillator circuit, at least one first transistor is formed, and a double-diffused interruption structure is formed around at least a portion of the first transistor for electrical isolation.

[0020] Step 3: In the region used to form the ring oscillator circuit, at least one second transistor is formed, and a single-diffusion interruption structure is formed around at least a portion of the second transistor for electrical isolation, wherein the single-diffusion interruption structure applies compressive stress to the channel region of the second transistor.

[0021] Preferably, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

[0022] Preferably, in step three, the step of forming a single-diffusion interruption structure includes: etching an isolation trench next to the active region of the second transistor; and backfilling the isolation trench with dielectric material, and by controlling the deposition process of the dielectric material, causing the dielectric material to generate the compressive stress on the channel region of the second transistor.

[0023] Preferably, in step three, the dielectric material comprises silicon nitride and / or silicon oxide.

[0024] Preferably, in step two, the NMOS transistor is configured with the double diffusion interruption structure to avoid the negative impact of the compressive stress on the performance of the NMOS transistor.

[0025] As described above, the semiconductor device and its manufacturing method of the present invention have the following beneficial effects:

[0026] The solution of this invention simultaneously enhances the performance of PMOS and protects the performance of NMOS, so that both types of transistors constituting the ring oscillator circuit are in a better operating state, thereby significantly improving the overall performance of the ring oscillator circuit, such as achieving higher oscillation frequency, faster operating speed, and better power consumption performance at a specific operating frequency. Attached Figure Description

[0027] Figure 1 The schematic diagram shown illustrates a ring oscillator circuit of the present invention comprising at least one NMOS transistor and at least one PMOS transistor.

[0028] Figure 2 The diagram shown is a schematic representation of the process flow of this invention. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Some embodiments of the present invention provide a semiconductor device. The semiconductor device may include a substrate and a ring oscillator circuit disposed on the substrate. See also... Figure 1 The ring oscillator circuit includes at least one NMOS transistor and at least one PMOS transistor. By using different isolation structures for different types of transistors, targeted optimization of circuit performance is achieved.

[0031] Specifically, the ring oscillator circuit includes at least one NMOS transistor, which is isolated by a double-diffused interrupt structure.

[0032] In some embodiments, the double-diffusion interruption structure makes the channel region of the NMOS transistor essentially unaffected by compressive stress. This double-diffusion interruption structure typically manifests as a standard shallow trench isolation configuration, forming isolation regions on both sides of the active region of the NMOS transistor, thus creating an interruption on the layout. The isolation regions of this structure are filled with an electrically insulating dielectric material, such as silicon oxide deposited by high-density plasma-chemical vapor deposition (HDP-CVD). The process parameters used to form this structure are typically designed to achieve excellent trench filling capability and electrical isolation performance, with a relatively neutral or insignificant impact on the stress generated in the channel region. This contrasts sharply with the strong compressive stress intentionally introduced for PMOS transistors. By employing the double-diffusion interruption structure, the compressive stress intentionally introduced for PMOS regions can be effectively physically isolated from the NMOS regions, thereby avoiding the negative impact of compressive stress on the carrier (electron) mobility of the NMOS transistor. This ensures that the performance of the NMOS transistor does not degrade, thus maintaining the overall stability and reliability of the ring oscillator circuit.

[0033] The ring oscillator circuit also includes at least one PMOS transistor, which is isolated by a single-diffusion interruption structure. This single-diffusion interruption structure applies compressive stress to the channel region of the PMOS transistor. Since the performance of PMOS transistors is typically weaker than that of NMOS transistors at advanced process nodes, it is a bottleneck affecting the performance of circuits like ring oscillators. Therefore, this invention significantly improves the hole mobility and drive current of the PMOS transistor by specifically configuring a single-diffusion interruption structure for the PMOS transistor in the layout design and by applying compressive stress to this structure in conjunction with the process technology. This effectively compensates for its performance shortcomings and ultimately improves the oscillation frequency and operating speed of the entire ring oscillator circuit.

[0034] In some embodiments, the single-diffusion interruption structure includes an isolation trench filled with dielectric material.

[0035] In some embodiments, the compressive stress generated by the dielectric material is used to enhance the carrier mobility of the PMOS transistor. The dielectric material can be silicon nitride, silicon oxide, or a combination thereof. By modulating the deposition process, such as adjusting process parameters (e.g., RF power, gas flow rate ratio, deposition temperature, and pressure) during plasma-enhanced chemical vapor deposition (PECVD), the intrinsic stress of the filled dielectric material can be precisely controlled to exhibit the desired compressive stress characteristics, thereby enhancing PMOS performance.

[0036] Other embodiments of the present invention provide a method for fabricating a semiconductor device, which improves the performance of a ring oscillator circuit through synergistic optimization of design and process.

[0037] In some embodiments, the first transistor formed in the method is an NMOS transistor and the second transistor is a PMOS transistor.

[0038] Please see Figure 2 The method may include the following steps:

[0039] Step 1: Provide a substrate on which a region for forming a ring oscillator circuit is defined. The substrate may be a silicon substrate, a silicon-on-insulator (SOI) substrate, or other materials suitable for semiconductor fabrication.

[0040] Step 2: In the region used to form the ring oscillator circuit, at least one first transistor is formed, and a double-diffused interruption structure is formed around at least a portion of the first transistor for electrical isolation. In some embodiments, the process of forming the double-diffused interruption structure in step 2 may include: forming a shallow trench in a substrate around the active region planned for the NMOS transistor by photolithography and etching processes; then filling the shallow trench with a dielectric material, such as silicon oxide filled using high-density plasma chemical vapor deposition; and finally removing excess dielectric material and planarizing the surface by a chemical mechanical polishing process, thereby completing the fabrication of the isolation structure.

[0041] In some embodiments, step two involves configuring a double-diffusion interruption structure for the NMOS transistor to mitigate the negative impact of compressive stress on its performance. This pre-planning of the layout ensures that subsequent stress engineering introduced to improve PMOS performance will not affect the NMOS transistor's performance, guaranteeing that different types of devices in the circuit can operate at or near their optimal performance states.

[0042] Step 3: In the region used to form the ring oscillator circuit, at least one second transistor is formed, and a single-diffusion interruption structure is formed around at least a portion of the second transistor for electrical isolation, wherein the single-diffusion interruption structure applies compressive stress to the channel region of the second transistor.

[0043] In some embodiments, step three, forming the single-diffusion interruption structure, includes: etching an isolation trench next to the active region of the second transistor; and backfilling the isolation trench with dielectric material, and by controlling the deposition process of the dielectric material, causing the dielectric material to generate the compressive stress on the channel region of the second transistor. This step is a key process step in achieving the core technical effect of the present invention. It closely integrates the layout planning at the design end (using single-diffusion interruption next to PMOS) with the stress control at the process end, ultimately applying the stress effect precisely to the PMOS device that requires performance improvement.

[0044] In some embodiments, in step three, the dielectric material includes silicon nitride and / or silicon oxide. Choosing these common dielectric materials facilitates good compatibility between the fabrication method of this invention and existing semiconductor manufacturing processes (e.g., 28nm and more advanced process platforms), thereby reducing the difficulty and additional cost of process integration when introducing this optimized scheme, and thus giving it better prospects for industrial application.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Base; A ring oscillator circuit is disposed on the substrate, and the ring oscillator circuit includes: At least one NMOS transistor, said NMOS transistor being isolated by a double-diffused interrupt structure; and At least one PMOS transistor, the PMOS transistor being isolated by a single-diffusion interruption structure, wherein the single-diffusion interruption structure applies compressive stress to the channel region of the PMOS transistor.

2. The semiconductor device according to claim 1, characterized in that: The single-diffusion interruption structure includes an isolation trench filled with dielectric material.

3. The semiconductor device according to claim 2, characterized in that: The compressive stress generated by the dielectric material is used to improve the carrier mobility of the PMOS transistor.

4. The semiconductor device according to claim 2, characterized in that: The dielectric material includes silicon nitride and / or silicon oxide.

5. The semiconductor device according to claim 1, characterized in that: The dual-diffusion interruption structure ensures that the channel region of the NMOS transistor is essentially unaffected by the compressive stress.

6. A method for manufacturing a semiconductor device, characterized in that, include: Step 1: Provide a substrate on which an area for forming a ring oscillator circuit is defined; Step 2: In the region used to form the ring oscillator circuit, at least one first transistor is formed, and a double-diffused interruption structure is formed around at least a portion of the first transistor for electrical isolation. Step 3: In the region used to form the ring oscillator circuit, at least one second transistor is formed, and a single-diffusion interruption structure is formed around at least a portion of the second transistor for electrical isolation, wherein the single-diffusion interruption structure applies compressive stress to the channel region of the second transistor.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that: The first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that: In step three, the step of forming a single-diffusion interruption structure includes: etching an isolation trench next to the active region of the second transistor; and backfilling the isolation trench with dielectric material, and by controlling the deposition process of the dielectric material, causing the dielectric material to generate the compressive stress on the channel region of the second transistor.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that: In step three, the dielectric material includes silicon nitride and / or silicon oxide.

10. The method for manufacturing a semiconductor device according to claim 7, characterized in that: In step two, the double-diffusion interruption structure is configured for the NMOS transistor to avoid the negative impact of the compressive stress on the performance of the NMOS transistor.

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