Pipeline type analog-to-digital conversion ADC circuit and sub pipeline level circuit thereof

Abstract

The invention relates to the technical field of power electronics, in particular to a pipelined analog-to-digital conversion ADC circuit and a sub-pipelined circuit thereof. Wherein the sub pipeline stage circuit comprises a sub analog-to-digital conversion circuit and a sub digital-to-analog conversion circuit; wherein in a short pulse control phase of the first clock signal, the sub digital-to-analog conversion circuit is in a reset state; in the effective phase of the first clock signal, the sub digital-to-analog conversion circuit samples the input signal; in the effective phase of the second clock signal, the sub digital-to-analog conversion circuit generates a margin signal according to the input signal and the coded signal input by the sub digital-to-analog conversion circuit, and amplifies the margin signal to obtain a margin amplified signal. By adopting the scheme, the sampling accuracy can be improved, and the accuracy of the pipelined ADC circuit during analog-to-digital conversion is improved.

Description

Technical Field

[0001] This disclosure relates to the field of power electronics technology, and in particular to a pipelined analog-to-digital converter (ADC) circuit and its sub-pipeline circuit. Background Technology

[0002] A pipelined analog-to-digital converter (ADC) circuit consists of several cascaded sub-pipeline stages. Through the processing of each sub-pipeline stage, high-precision analog-to-digital conversion can be achieved. Pipeline ADC circuits reduce their power consumption and area by employing a sample-and-hold-less (SHA-less) structure. However, in the SHA-less structure, when the sub-pipeline stage directly samples the input signal in the current cycle, the residual signal from the previous cycle will discharge, affecting the accuracy of the sampling in the current cycle and resulting in lower accuracy during analog-to-digital conversion. Summary of the Invention

[0003] This disclosure provides a sub-pipeline circuit in a pipelined analog-to-digital converter (ADC) circuit, the main purpose of which is to improve the sampling accuracy and the accuracy of the pipelined ADC circuit when performing analog-to-digital conversion.

[0004] According to one aspect of this disclosure, a sub-pipeline circuit is provided in a pipelined analog-to-digital converter (ADC) circuit. The sub-pipeline circuit is connected to a clock circuit, and the sub-pipeline circuit includes a sub-analog-to-digital converter (ADC) circuit and a sub-digital-to-analog converter (DAC) circuit; wherein...

[0005] The clock circuit is connected to the sub-analog-to-digital converter circuit and the sub-data converter circuit respectively, and is used to output clock signals to the sub-analog-to-digital converter circuit and the sub-digital-to-analog converter circuit. The clock signals include a first clock signal and a second clock signal. The first clock signal includes an active phase and a short pulse control phase inserted before the active phase.

[0006] During the short pulse control phase of the first clock signal, the sub-digital-to-analog converter circuit is in a reset state;

[0007] During the effective phase of the first clock signal, the digital-to-analog converter circuit samples the input signal;

[0008] During the effective phase of the second clock signal, the sub-digital-to-analog converter generates a margin signal based on the input signal and the encoded signal input to the sub-digital-to-analog converter, and amplifies the margin signal to obtain the amplified margin signal.

[0009] Optionally, in one embodiment of this disclosure, the sub-analog-to-digital conversion circuit includes a threshold generation module, a comparator module, and an encoding module, and the input signal includes a positive input signal and a negative input signal; wherein,

[0010] The control terminal of the threshold generation module is connected to the clock circuit, the output terminal of the threshold generation module is connected to the input terminal of the comparator module, the output terminal of the comparator module is connected to the input segment of the encoding module, and the output terminal of the encoding module is connected to the input terminal of the sub-digital-to-analog converter circuit.

[0011] During the effective phase of the second clock signal, the threshold generation module samples the threshold voltage set and performs capacitor voltage division to obtain the first capacitor voltage set and the second capacitor voltage set.

[0012] During the effective phase of the first clock signal, the threshold generation module samples the positive input signal and the negative input signal respectively, and generates a first comparison voltage based on the first capacitor voltage set and the positive input signal, and generates a second comparison voltage based on the second capacitor voltage set and the negative input signal;

[0013] At the end of the effective phase of the first clock signal, the comparator module compares the first comparison voltage and the second comparison voltage, and inputs the comparison result signal to the encoding module.

[0014] Optionally, in one embodiment of this disclosure, the threshold generation module includes a positive input signal threshold generation module and a negative input signal threshold generation module. Both the input signal threshold generation module and the negative input signal threshold generation module include a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a second capacitor. The threshold voltage set includes a first threshold voltage, a second threshold voltage, and a third threshold voltage.

[0015] The connection point between the first terminal of the first switch and the first terminal of the second switch in the positive input signal threshold generation module is used to receive positive input signals, and the connection point between the first terminal of the first switch and the first terminal of the second switch in the negative input signal threshold generation module is used to receive negative input signals.

[0016] The first terminal of the third switch in the positive input signal threshold generation module is used to receive the first threshold voltage, and the first terminal of the fourth switch in the positive input signal threshold generation module is used to receive the second threshold voltage.

[0017] The first terminal of the third switch in the negative input signal threshold generation module is used to receive the third threshold voltage, and the first terminal of the fourth switch in the negative input signal threshold generation module is used to receive the second threshold voltage.

[0018] The second terminal of the first switch is connected to the second terminal of the third switch and the first terminal of the first capacitor. The second terminal of the second switch is connected to the second terminal of the fourth switch and the first terminal of the second capacitor. The second terminal of the first capacitor is connected to the second terminal of the second capacitor, the first terminal of the fifth switch, and the first input terminal of the comparator module. The second terminal of the fifth switch is grounded.

[0019] During the active phase of the first clock signal, the first switch and the second switch are in the closed state.

[0020] During the active phase of the second clock signal, the third and fourth switches are in the closed state;

[0021] During the initial period of the effective phase of the second clock signal, the fifth switch is in the closed state.

[0022] Optionally, in one embodiment of this disclosure, the comparator module includes a first transmission gate, a second transmission gate, a first-stage regenerative comparator, and a latch; wherein,

[0023] The first terminal of the first transmission gate is used to receive the first comparison voltage, the first terminal of the second transmission gate is used to receive the second comparison voltage, the second terminal of the first transmission gate is connected to the first input terminal of the first-stage regenerative comparator, the second terminal of the second transmission gate is connected to the second input terminal of the first-stage regenerative comparator, the first output terminal of the first-stage regenerative comparator is connected to the first input terminal of the latch, the second output terminal of the first-stage regenerative comparator is connected to the second input terminal of the latch, and the output terminal of the latch is connected to the input terminal of the encoding module.

[0024] At the end of the effective phase of the first clock signal, the first and second transmission gates are in the off state.

[0025] Optionally, in one embodiment of this disclosure, the first-stage regenerative comparator includes a first DC power supply, a first P-type switch, a second P-type switch, a third P-type switch, a first N-type switch, a second N-type switch, a third N-type switch, a first NAND gate, a second NAND gate, a first NOT gate, and a second NOT gate; wherein,

[0026] The input of the first NOT gate is used to receive the drive signal. During the last period of the effective phase of the first clock signal, the drive signal is a high-level signal.

[0027] The first DC power supply is connected to the source of the first P-type switch transistor, the gate of the first P-type switch transistor is connected to the output of the first NOT gate and the input of the second NOT gate, and the drain of the first P-type switch transistor is connected to the source of the second P-type switch transistor and the source of the third P-type switch transistor, respectively.

[0028] The drain of the second P-type switch is connected to the gate of the third P-type switch, the drain of the first N-type switch, the gate of the second N-type switch, the output of the second transmission gate, and the first input of the first NAND gate, respectively.

[0029] The drain of the third P-type switch is connected to the gate of the second P-type switch, the drain of the second N-type switch, the gate of the first N-type switch, the output of the first transmission gate, and the first input of the second NAND gate, respectively.

[0030] The drain of the third N-type switch is connected to the source of the first N-type switch and the source of the second N-type switch, respectively. The gate of the third N-type switch is connected to the output of the second NOT gate, the second input of the first NAND gate, and the second input of the second NAND gate. The source of the third N-type switch is grounded.

[0031] The output of the first NAND gate is connected to the first input of the latch, and the output of the second NAND gate is connected to the second input of the latch.

[0032] Optionally, in one embodiment of this disclosure, the sub-digital-to-analog converter circuit includes a capacitor-flipping switched capacitor module and an operational amplifier; wherein,

[0033] The first input terminal of the capacitor-flipping switched capacitor module is used to receive the input signal, and the second input terminal of the capacitor-flipping switched capacitor module is used to receive the encoded signal.

[0034] During the short pulse control phase of the first clock signal, the capacitor-flipping switched capacitor module is in a reset state.

[0035] During the effective phase of the first clock signal, the capacitor-flipping switched capacitor module samples the positive input signal;

[0036] During the effective phase of the second clock signal, the capacitor-flipping switched capacitor module determines the reference signal corresponding to the encoded signal and generates a margin signal based on the input signal and the reference signal. The operational amplifier amplifies the margin signal to obtain the margin amplified signal.

[0037] Optionally, in one embodiment of this disclosure, the capacitor-flipping switched capacitor module includes at least one sixth switch, at least one seventh switch, at least one eighth switch, a ninth switch, a tenth switch, at least one third capacitor, and a fourth capacitor, wherein the input signal includes a positive input signal; wherein,

[0038] The first terminal of the sixth switch is used to receive the positive input signal, the first terminal of the seventh switch is used to receive the reference signal, the second terminal of the sixth switch is connected to the second terminal of the seventh switch, the first terminal of the eighth switch and the first terminal of the third capacitor respectively, the second terminal of the third capacitor is connected to the first terminal of the ninth switch, the first terminal of the fourth capacitor and the positive input terminal of the operational amplifier respectively, the connection point between the second terminal of the fourth capacitor, the first terminal of the tenth switch and the negative output terminal of the operational amplifier is the positive output terminal of the sub-digital-to-analog converter circuit, and the positive output terminal of the operational amplifier is the negative output terminal of the sub-digital-to-analog converter circuit;

[0039] The second terminals of the eighth switch, the ninth switch, and the tenth switch, as well as the negative input terminal of the operational amplifier, are grounded.

[0040] During the short pulse control phase of the first clock signal, the eighth switch is in the closed state;

[0041] During the active phase of the first clock signal, the sixth and tenth switches are in the closed state.

[0042] During the initial time period of the effective phase of the first clock signal, the ninth switch is in the closed state.

[0043] During the active phase of the second clock signal, the seventh switch is in the closed state.

[0044] Optionally, in one embodiment of this disclosure, the input signal includes a positive input signal and a negative input signal, and the capacitor-flipping switched capacitor module includes a first capacitor-flipping switched capacitor module and a second capacitor-flipping switched capacitor module. Both the first and second capacitor-flipping switched capacitor modules include at least one eleventh switch, a twelfth switch, at least one thirteenth switch, at least one fourteenth switch, a fifteenth switch, a sixteenth switch, at least one fifth capacitor, and a sixth capacitor; wherein,

[0045] In the first capacitor-flipping switched capacitor module, the first terminal of the eleventh switch and the first terminal of the twelfth switch are used to receive the positive input signal, and in the second capacitor-flipping switched capacitor module, the first terminal of the eleventh switch and the first terminal of the twelfth switch are used to receive the negative input signal.

[0046] The first terminal of the thirteenth switch is used to receive the reference signal. The second terminal of the eleventh switch is connected to the second terminal of the thirteenth switch, the first terminal of the fourteenth switch, and the first terminal of the fifth capacitor in a corresponding manner. The second terminal of the twelfth switch is connected to the first terminal of the fifteenth switch and the first terminal of the sixth capacitor in a corresponding manner. The second terminal of the sixteenth switch is grounded.

[0047] In the first capacitor-flipping switched capacitor module, the second terminal of the fifth capacitor is connected to the second terminal of the sixth capacitor, the first terminal of the sixteenth switch, and the positive input terminal of the operational amplifier, respectively. In the second capacitor-flipping switched capacitor module, the second terminal of the fifth capacitor is connected to the second terminal of the sixth capacitor, the first terminal of the sixteenth switch, and the negative input terminal of the operational amplifier, respectively.

[0048] In the first capacitor-flipping switched capacitor module, the connection point between the second terminal of the fifteenth switch and the negative output terminal of the operational amplifier is the positive output terminal of the sub-digital-to-analog converter circuit; in the second capacitor-flipping switched capacitor module, the connection point between the second terminal of the fifteenth switch and the positive output terminal of the operational amplifier is the negative output terminal of the sub-digital-to-analog converter circuit.

[0049] During the short pulse control phase of the first clock signal, the fourteenth switch is in the closed state;

[0050] During the active phase of the first clock signal, the eleventh switch and the twelfth switch are in the closed state;

[0051] During the initial time period of the effective phase of the first clock signal, the sixteenth switch is in the closed state;

[0052] During the active phase of the second clock signal, the thirteenth switch and the fifteenth switch are in the closed state.

[0053] Optionally, in one embodiment of this disclosure, the input signal includes a positive input signal and a negative input signal, and the capacitor-flipping switched capacitor module includes a first capacitor-flipping switched capacitor module and a second capacitor-flipping switched capacitor module. Both the first and second capacitor-flipping switched capacitor modules include at least one eleventh switch, a twelfth switch, at least one thirteenth switch, at least one fourteenth switch, a fifteenth switch, a sixteenth switch, at least one fifth capacitor, and a sixth capacitor; wherein,

[0054] In the first capacitor-flipping switched capacitor module, the first terminals of the eleventh switch and the twelfth switch are used to receive positive input signals, and in the second capacitor-flipping switched capacitor module, the first terminals of the eleventh switch and the twelfth switch are used to receive negative input signals.

[0055] The first terminal of the thirteenth switch is used to receive the reference signal. The second terminal of the eleventh switch is connected to the second terminal of the thirteenth switch, the first terminal of the fourteenth switch, and the first terminal of the fifth capacitor in a corresponding manner. The second terminal of the twelfth switch is connected to the first terminal of the fifteenth switch and the first terminal of the sixth capacitor in a corresponding manner. The second terminal of the fifth capacitor is connected to the second terminal of the sixth capacitor, the first terminal of the sixteenth switch, and the positive input terminal of the operational amplifier in a corresponding manner. The first terminal of the seventeenth switch is connected to the negative input terminal of the operational amplifier. The second terminal of the fifteenth switch is connected to the negative output terminal of the operational amplifier. The second terminals of the sixteenth and seventeenth switches are grounded.

[0056] During the short pulse control phase of the first clock signal, the fourteenth switch is in the closed state;

[0057] During the active phase of the first clock signal, the eleventh and twelfth switches are in the closed state;

[0058] During the initial time period of the effective phase of the first clock signal, the sixteenth switch is in the closed state.

[0059] During the active phase of the second clock signal, the thirteenth and fifteenth switches are in the closed state.

[0060] According to another aspect of this disclosure, a pipelined analog-to-digital converter (ADC) circuit is provided, comprising: a clock circuit and any of the sub-pipeline circuits shown in the foregoing embodiments, where N is a positive integer; wherein,

[0061] The clock circuit is connected to N+1 sub-pipeline circuits respectively;

[0062] The input terminal of the (N+1)th sub-pipeline circuit is connected to the output terminal of the Nth sub-pipeline circuit, and the margin amplification signal output by the Nth sub-pipeline circuit is the input signal of the (N+1)th sub-pipeline circuit.

[0063] In summary, the pipelined analog-to-digital converter (ADC) circuit and its sub-pipeline circuit provided in this embodiment first reset the sub-ADC circuit by controlling the short pulse control phase during one working cycle, that is, discharging the residual signal of the previous cycle; then, controlling the sub-ADC circuit to sample the signal. Therefore, it can reduce the situation where the sampling in the current cycle is inaccurate due to the discharge of the residual signal of the previous cycle during the sampling process, and can improve the sampling accuracy and improve the accuracy of the pipelined ADC circuit when performing analog-to-digital conversion.

[0064] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0065] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0066] Figure 1 This is a schematic diagram of the structure of a pipelined ADC circuit provided in an embodiment of the present disclosure;

[0067] Figure 2 This is a schematic diagram of the structure of a sub-pipeline circuit provided in an embodiment of the present disclosure;

[0068] Figure 3 This is a schematic diagram of the structure of a sub-pipeline circuit provided in an embodiment of the present disclosure;

[0069] Figure 4This is a schematic diagram of the structure of a sub-analog-to-digital converter circuit provided in an embodiment of the present disclosure;

[0070] Figure 5 This is a schematic diagram of the structure of a sub-digital-to-analog converter circuit provided in an embodiment of the present disclosure;

[0071] Figure 6 This is a schematic diagram of the structure of a sub-digital-to-analog converter circuit provided in an embodiment of the present disclosure;

[0072] Figure 7 This is a schematic diagram of a gain-enhanced common-source cascode operational amplifier provided in an embodiment of this disclosure. Detailed Implementation

[0073] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are used only to explain this disclosure, and should not be construed as limiting this disclosure. Rather, embodiments of this disclosure include all variations, modifications, and equivalents falling within the spirit and scope of the appended claims.

[0074] The present disclosure will now be described in detail with reference to specific embodiments.

[0075] Figure 1 This is a schematic diagram of a pipelined ADC circuit provided in an embodiment of this disclosure. Figure 1 As shown, this pipelined ADC circuit includes a clock circuit and N+1 sub-pipeline stages, where N is a positive integer; where,

[0076] The clock circuit is connected to N+1 sub-pipeline circuits respectively;

[0077] The input terminal of the (N+1)th sub-pipeline circuit is connected to the output terminal of the Nth sub-pipeline circuit.

[0078] According to some embodiments, when the pipelined ADC circuit is in operation, the input signal of the first sub-pipeline circuit is the analog input signal received by the pipelined ADC circuit. The first sub-pipeline circuit samples the analog input signal and quantizes it into a one-bit digital signal. Then, the first sub-pipeline circuit subtracts the one-bit digital signal from the analog input signal to obtain a margin signal. Finally, the first sub-pipeline circuit amplifies the margin signal to obtain a margin output signal, and uses the margin output signal as an input signal to the second sub-pipeline circuit. That is, the margin amplified signal output by the Nth sub-pipeline circuit is the input signal of the N+1th sub-pipeline circuit.

[0079] In some embodiments, the pipelined ADC circuit further includes an error calibration module, which can calibrate the digital signal output by each sub-pipeline circuit and add the calibrated N+1 digital signals in a staggered manner to obtain the digital output signal corresponding to the analog input signal.

[0080] It's important to note that in traditional pipelined ADC circuits, the sample-and-hold (SUP) structure is located at the very beginning of the pipeline. Under clock control, it samples and holds the analog input signal. The held signal output by the SUP structure is a DC-like signal relative to the first pipeline stage. Its advantages include the first pipeline stage not needing to deal with high-frequency changing input signals, isolation from parasitic interference from chip pins, and consistent signal sampling between the sub-analog-to-digital converters (ADCs) and sub-digital-to-analog converters (DACs). However, the SUP structure results in higher power consumption and larger area requirements for the sub-pipeline stages in the pipelined ADC circuit. Therefore, using a SHA-less structure can reduce the power consumption and area of ​​the pipelined ADC circuit.

[0081] According to some embodiments, Figure 2 This is a schematic diagram of a sub-pipeline circuit provided in an embodiment of this disclosure. Figure 2 As shown, the sub-pipeline circuit includes: a sub-analog-to-digital converter circuit and a sub-digital-to-analog converter circuit; wherein,

[0082] The clock circuit is connected to the sub-analog-to-digital converter circuit and the sub-data converter circuit respectively, and is used to output clock signals to the sub-analog-to-digital converter circuit and the sub-digital-to-analog converter circuit.

[0083] In some embodiments, the clock circuit is used to generate a multiphase non-overlapping clock signal, which refers to a clock signal with multiple phases that do not overlap. In a multiphase clock signal, each clock phase has its own unique phase relationship, typically offset by a certain angle. These clock phases can perform different operations in different time periods, thereby enabling parallel processing and high-speed data transmission. Multiphase non-overlapping clock signals have many advantages. First, they can improve circuit efficiency because multiple operations can be performed simultaneously, reducing latency. Second, multiphase clock signals can reduce circuit power consumption by minimizing unnecessary waiting and idle time. Furthermore, multiphase clock signals can improve circuit stability by reducing timing errors caused by clock signal delays.

[0084] For example, this clock circuit can generate two non-overlapping clock signals, namely a first clock signal and a second clock signal; wherein, the first clock signal includes an active phase Ф1 and a short pulse control phase Ф inserted before the active phase. clear The second clock signal includes the active phase Ф2.

[0085] According to some embodiments, in Ф clear The sub-digital-to-analog converter is in a reset state; at Ф1, the sub-digital-to-analog converter samples the input signal; at Ф2, the sub-digital-to-analog converter generates a margin signal based on the input signal and the encoded signal input to the sub-digital-to-analog converter, and amplifies the margin signal to obtain a margin amplified signal.

[0086] It is easy to understand that in a work cycle, firstly, through Ф clear The control sub-digital-to-analog converter circuit is reset, which discharges the residual signal from the previous cycle. Then, the control sub-digital-to-analog converter circuit samples the signal. Therefore, the inaccuracy of sampling in the current cycle caused by the discharge of the residual signal from the previous cycle during the sampling process can be reduced, thereby improving the sampling accuracy and the accuracy of pipelined ADC circuits in performing analog-to-digital conversion.

[0087] According to some embodiments, the sub-analog-to-digital converter (Sub-ADC) circuit can be, for example, a low-precision Flash ADC.

[0088] Optionally, Figure 3 This is a schematic diagram of a sub-pipeline circuit provided in an embodiment of this disclosure. Figure 3 As shown, the sub-analog-to-digital converter circuit includes a threshold generation module, a comparator module, and an encoding module. The input signals include a positive input signal VIP and a negative input signal VIM; wherein,

[0089] The control terminal of the threshold generation module is connected to the clock circuit, the output terminal of the threshold generation module is connected to the input terminal of the comparator module, the output terminal of the comparator module is connected to the input segment of the encoding module, and the output terminal of the encoding module is connected to the input terminal of the sub-digital-to-analog converter circuit.

[0090] According to some embodiments, in Ф2, the threshold generation module samples the threshold voltage set and performs capacitor voltage division to obtain a first capacitor voltage set and a second capacitor voltage set; in Ф1, the threshold generation module samples the positive input signal and the negative input signal respectively, and generates a first comparison voltage VP based on the first capacitor voltage set and the positive input signal VIP, and generates a second comparison voltage CN based on the second capacitor voltage set and the negative input signal VIM; at the end of the time period in Ф1, the comparator module compares the first comparison voltage CP and the second comparison voltage VN, and inputs the comparison result signal to the encoding module.

[0091] It should be noted that in related technologies, the threshold generation module uses a resistor string voltage divider. This method has several drawbacks, including the presence of quiescent current in the resistor string itself. Furthermore, to drive the capacitive sampling network of the comparator module, this quiescent current needs to be sufficiently large at higher operating frequencies, resulting in significant power consumption. This embodiment of the present disclosure, by employing a capacitor voltage divider, can save power compared to the resistor string voltage divider.

[0092] According to some embodiments, since the sampling of the threshold voltage set and the sampling of the input signal are acquired at two phases, Ф2 and Ф1 respectively, in order to ensure that the sub-analog-to-digital converter (DAC) has prepared the encoded signal before the DAC performs margin amplification, the sampling of the threshold voltage set can be arranged at Ф2 of the previous clock cycle. This avoids occupying the valuable setup time of the DAC and improves the setup accuracy of the DAC.

[0093] In some embodiments, the comparator module operates only during the last period of Ф1, i.e., the final time period, thus further reducing the power consumption of the comparator module. The duration of this final time period can be, for example, 160 ps.

[0094] According to some embodiments, the specific circuitry of the encoding module can be adjusted according to the specific application scenario.

[0095] Optionally, Figure 4 This is a schematic diagram of the structure of a sub-analog-to-digital converter circuit provided in an embodiment of this disclosure. Figure 4 As shown, the threshold generation module includes a positive input signal threshold generation module and a negative input signal threshold generation module. Both the positive and negative input signal threshold generation modules include a first switch S1 (including S1.1 and S1.2), a second switch S2 (including S2.1 and S2.2), a third switch S3 (including S3.1 and S3.2), a fourth switch S4 (including S4.1 and S4.2), a fifth switch S5 (including S5.1 and S5.2), a first capacitor C1 (including C1.1 and C1.2), and a second capacitor C2 (including C2.1 and C2.2). The threshold voltage set includes a first threshold voltage, a second threshold voltage, and a third threshold voltage.

[0096] The connection point between the first terminal of the first switch S1.1 and the first terminal of the second switch S2.1 in the positive input signal threshold generation module is used to receive the positive input signal VIP, and the connection point between the first terminal of the first switch S2.1 and the first terminal of the second switch S2.2 in the negative input signal threshold generation module is used to receive the negative input signal VIM.

[0097] The first terminal of the third switch S3.1 in the positive input signal threshold generation module is used to receive the first threshold voltage, and the first terminal of the fourth switch S4.1 in the positive input signal threshold generation module is used to receive the second threshold voltage.

[0098] The first terminal of the third switch S3.2 in the negative input signal threshold generation module is used to receive the third threshold voltage, and the first terminal of the fourth switch S4.2 in the negative input signal threshold generation module is used to receive the second threshold voltage.

[0099] The second terminal of the first switch S1 is connected to the second terminal of the third switch S3 and the first terminal of the first capacitor C1. The second terminal of the second switch S2 is connected to the second terminal of the fourth switch S4 and the first terminal of the second capacitor C2. The second terminal of the first capacitor C1 is connected to the second terminal of the second capacitor C2, the first terminal of the fifth switch S5 and the first input terminal of the comparator module. The second terminal of the fifth switch S5 is grounded.

[0100] According to some embodiments, at Ф2, the third switch S3 and the fourth switch S4 are in the closed state.

[0101] In some embodiments, when the third switch S3 and the fourth switch S4 are closed at Ф2 in the previous cycle of the current working cycle, the charges stored in the first capacitor C1 (including C1.1 and C1.2) and the second capacitor (including C2.1 and C2.2) are respectively:

[0102] Q 1.1 =VRP*C 1.1 =VRP*kC u

[0103] Q 2.1 =VRG*C 2.1 =VRG*(nk)C u

[0104] Q 1.2 =VRM*C 1.2 =VRM*iC u

[0105] Q 2.2 =VRG*C 2.2 =VRG*(ni)C u

[0106] Among them, C 1.1 This is the capacitance value of C1.1. C 2.1 This is the capacitance value of C2.1. C 1.2 This is the capacitance value of C1.2. C 2.2 This is the capacitance value of C2.2. Q 1.1 Q represents the charge stored in C1.1. 1.2Q represents the charge stored in C1.2. 2.1 Q represents the charge stored in C2.1. 2.2 This represents the charge stored in C2.2. VRP is the voltage value corresponding to the first threshold voltage. VRG is the voltage value corresponding to the second threshold voltage. VRM is the voltage value corresponding to the third threshold voltage.

[0107] Among them, C u is the unit charge. n is a multiple of the unit charge that can be stored in the positive input signal threshold generation module or the negative input signal threshold generation module. k is C 1.1 The multiple of the unit charge that can be stored in C. i is C 1.2 The multiple of the unit charge that can be stored. k and i are both less than n, and the specific values ​​of n, k, and i can be set according to the actual application scenario.

[0108] According to some embodiments, in Ф1, the first switch S1 and the second switch S2 are in a closed state.

[0109] In some embodiments, during the current operating cycle Ф1, the charge stored in the first capacitor C1 (including C1.1 and C1.2) and the second capacitor (including C2.1 and C2.2) satisfies the following formula:

[0110] Q P =(VIP-VP)*(C 1.1 +C 2.1 )=(VIP-VP)*n*C u

[0111] Q N =(VIM-VN)*(C 1.2 +C 2.2 )=(VIM-VN)*n*C u

[0112] Among them, Q P The charge stored in the module is the threshold value for the positive input signal. Q N The charge stored in the negative input signal threshold generation module.

[0113] According to the principle of charge conservation, we can conclude that:

[0114] Q P =Q 1.1 +Q 2.1

[0115] Q N =Q 1.2 +Q 2.2

[0116] Combining the above equations, we get:

[0117]

[0118]

[0119] The flip point of the comparator module can then be determined using the following formula:

[0120]

[0121]

[0122] As can be seen from the above formula, only C needs to be adjusted. 1.1 / C 2.1 And C 1.2 / C 2.2 The size allows you to set the flip point for a relatively strong module.

[0123] For example, when n is 4, setting k to 3 and i to 2, or k to 2 and i to 3, will allow you to set the 5 / 8 flip point;

[0124] For example, when n is 4, setting k to 2 and i to 1, or k to 1 and i to 2, will allow you to set the 3 / 8 flip point;

[0125] For example, by reversing the VRP and VRM connections, the flip points of -3 / 8 and -5 / 8 can be set using the two methods mentioned above.

[0126] For example, if VRM is connected to VRG, then Q N =VRG*n*C u VN = VIM - VRG, therefore, based on charge conservation, the flip point of the comparator module can be obtained as follows:

[0127]

[0128] In this case, setting k to 1 will set the 1 / 8 flip point.

[0129] It's easy to understand that the advantage of the above capacitor sampling method is that it eliminates the need for resistor series voltage division to generate threshold voltages, thus saving power. It only requires setting sufficient drive capability for the threshold voltage set—that is, the first threshold voltage, the second threshold voltage, and the third threshold voltage—and properly matching the capacitors.

[0130] According to some embodiments, during the initial time period of Ф2, the fifth switch S5 is in a closed state, and during the remaining time periods, the fifth switch S5 is in an open state. Therefore, the fifth switch S5 can be in an open state before the third switch S3 and the fourth switch S4, which can reduce the influence of nonlinear factors such as charge injection and clock feedthrough.

[0131] Optionally, such as Figure 4 As shown, the comparator module includes a first transmission gate IC1, a second transmission gate IC2, a first-stage regenerative comparator, and a latch; wherein,

[0132] The first terminal of the first transmission gate IC1 is used to receive the first comparison voltage VP, the first terminal of the second transmission gate IC2 is used to receive the second comparison voltage VN, the second terminal of the first transmission gate IC1 is connected to the first input terminal of the first-stage regenerative comparator, the second terminal of the second transmission gate IC2 is connected to the second input terminal of the first-stage regenerative comparator, the first output terminal of the first-stage regenerative comparator is connected to the first input terminal of the latch, the second output terminal of the first-stage regenerative comparator is connected to the second input terminal of the latch, and the output terminal of the latch is connected to the input terminal of the encoding module.

[0133] It should be noted that in related technologies, high-speed comparators generally adopt a typical structure of a pre-amplifier stage plus a regenerative amplifier. This structure has certain advantages in terms of speed, gain, and kickback noise. However, due to the large number of comparator arrays and channels, the power consumption is relatively high. Therefore, the embodiments of this disclosure differ from the traditional two-stage structure by using only one stage of regenerative comparator, omitting the first stage of pre-amplifier. Reducing the power consumption of each comparator by one stage of pre-amplifier results in significant overall power savings, which is of great significance for power conservation.

[0134] In some embodiments, a higher voltage at the comparator module output node can couple to the input via parasitic capacitance, creating kickback noise that disrupts the input signal. By setting a first transmission gate and a second transmission gate at the input of the comparator module, and controlling the first and second transmission gates to be in an open state at the end of the time interval Ф1, i.e., during the comparison phase of the strong comparison module, the input and output of the comparator module can be isolated, thus reducing the impact of kickback noise.

[0135] In some embodiments, a latch refers to a storage cell circuit that is sensitive to pulse levels and can change its state under the influence of a specific input pulse level. The main function of a latch is to temporarily store signals to maintain a certain level state, especially in digital circuits, where it can record binary digital signals "0" and "1". Its primary function is buffering.

[0136] According to some embodiments, the latch can be, for example, an RS flip-flop. An RS flip-flop, also known as a reset / set flip-flop, is constructed from two cross-feedback gates (e.g., NAND gates) with two inputs R (reset) and S (set), and two outputs Q and Q'.

[0137] In some embodiments, such as Figure 4 As shown, the output of the RS flip-flop and the input of the encoding module can be connected via an NOT gate.

[0138] Optionally, such as Figure 4 As shown, the first-stage regenerative comparator includes a first DC power supply VDD1, a first P-type switch PM1, a second P-type switch PM2, a third P-type switch PM3, a first N-type switch NM1, a second N-type switch NM2, a third N-type switch NM3, a first NAND gate IC3, a second NAND gate IC4, a first NOT gate IC5, and a second NOT gate IC6; wherein,

[0139] The first DC power supply VDD1 is connected to the source of the first P-type switch PM1. The gate of the first P-type switch PM1 is connected to the output of the first NOT gate IC5 and the input of the second NOT gate IC6. The drain of the first P-type switch PM1 is connected to the source of the second P-type switch PM2 and the source of the third P-type switch PM3, respectively.

[0140] The drain of the second P-type switch PM2 is connected to the gate of the third P-type switch PM3, the drain of the first N-type switch NM1, the gate of the second N-type switch NM2, the output of the second transmission gate IC2, and the first input of the first NAND gate IC3.

[0141] The drain of the third P-type switch PM3 is connected to the gate of the second P-type switch PM2, the drain of the second N-type switch NM2, the gate of the first N-type switch NM1, the output of the first transmission gate IC1, and the first input of the second NAND gate IC4.

[0142] The drain of the third N-type switch NM3 is connected to the source of the first N-type switch NM1 and the source of the second N-type switch NM2, respectively. The gate of the third N-type switch NM3 is connected to the output of the second NOT gate IC6, the second input of the first NAND gate IC3 and the second input of the second NAND gate IC4. The source of the third N-type switch NM3 is grounded.

[0143] The output of the first NAND gate IC3 is connected to the first input of the latch, and the output of the second NAND gate IC4 is connected to the second input of the latch.

[0144] According to some embodiments, the input of the first NOT gate IC5 is used to receive the drive signal LAT. At the end of the time period in Ф1, the drive signal LAT is a high-level signal, the output of the first NOT gate IC5 is a low-level signal LATZ, and the output of the second NOT gate IC6 is a high-level signal LATZZ. In this case, the first P-type switch PM1 is in a low-level conducting state, and the third N-type switch NM3 is in a high-level conducting state.

[0145] Conversely, during the time period excluding the end of Ф1, the drive signal LAT is low, the output signal LATZ of the first NOT gate IC5 is high, and the output signal LATZZ of the second NOT gate IC6 is low. In this case, both the first P-type switch PM1 and the third N-type switch NM3 are off, so the comparator module only operates during the last period of Ф1, thus further reducing the power consumption of the comparator module.

[0146] It is easy to understand that by optimizing the structure of the pre-amplification stage and the first-stage regenerator comparator, the impact of kick-back noise, which refers to nonlinear noise caused by quantization error, can also be reduced.

[0147] Optionally, such as Figure 3 As shown, the sub-digital-to-analog converter circuit includes a capacitor-flipping switched capacitor module and an operational amplifier (AMP); wherein,

[0148] The first input terminal of the capacitor-flipping switched capacitor module is used to receive the input signal, and the second input terminal of the capacitor-flipping switched capacitor module is used to receive the encoded signal.

[0149] According to some embodiments, in Ф clear The capacitor-flipping switched capacitor module is in the reset state; at Ф1, the capacitor-flipping switched capacitor module samples the positive input signal VIP; at Ф2, the capacitor-flipping switched capacitor module determines the reference signal corresponding to the encoded signal and generates a margin signal based on the input signal and the reference signal. The operational amplifier AMP amplifies the margin signal to obtain the margin amplified signal.

[0150] In some embodiments, the capacitor-flipping switched capacitor module can precisely control the charging and discharging process of the internal capacitor by controlling internal switching transistors and other components, thereby improving the feedback coefficient of the sub-digital-to-analog converter (MDAC) circuit and thus reducing noise and increasing bandwidth without increasing power consumption.

[0151] According to some embodiments, the operational amplifier can be, for example, a differential amplifier with dual-input dual-output.

[0152] Optionally, when the negative input signal is ground, the capacitor-flipping switched capacitor module includes at least one sixth switch S6, at least one seventh switch S7, at least one eighth switch S8, a ninth switch S9, a tenth switch S10, at least one third capacitor C3, and a fourth capacitor C4; wherein,

[0153] The first terminal of the sixth switch S6 is used to receive the positive input signal VIP, and the first terminal of the seventh switch S7 is used to receive the reference signal. The second terminal of the sixth switch S6 is connected to the second terminal of the seventh switch S7, the first terminal of the eighth switch S8, and the first terminal of the third capacitor C3 in a corresponding manner. The second terminal of the third capacitor C3 is connected to the first terminal of the ninth switch S9, the first terminal of the fourth capacitor C4, and the positive input terminal of the operational amplifier AMP. The connection point between the second terminal of the fourth capacitor C4, the first terminal of the tenth switch S10, and the negative output terminal of the operational amplifier AMP is the positive output terminal VOP of the sub-digital-to-analog converter circuit. The positive output terminal of the operational amplifier is the negative output terminal VOM of the sub-digital-to-analog converter circuit, and the negative output terminal VOM is grounded.

[0154] The second terminal of the eighth switch S8, the second terminal of the ninth switch S9, the second terminal of the tenth switch S10, and the negative input terminal of the operational amplifier AMP are grounded.

[0155] According to some embodiments, the number of the sixth switch S6, the seventh switch S7, the eighth switch S8, and the third capacitor C3 is related to the number of selectable reference signals. For example, in one scenario... Figure 5 This is a schematic diagram of the structure of a sub-digital-to-analog converter circuit provided in an embodiment of this disclosure. Figure 5 As shown, there are only two selectable reference signals, Vrefn and Vrefp, so the number of the sixth switch S6, the seventh switch S7, the eighth switch S8, and the third capacitor C3 is one.

[0156] According to some embodiments, in Ф clear The eighth switch S8 is closed to connect the entire reference voltage to ground (common mode for the fully differential structure) to reset the third capacitor C3. Then, at Ф1, the sixth switch S6 and the tenth switch S10 are closed to sample the positive input signal VIP. Therefore, the third capacitor C3 can be reset before sampling to eliminate the nonlinearity caused by the kick-back, and this structure does not cause a decrease in the feedback coefficient.

[0157] In some embodiments, during the initial time period of Ф1, the ninth switch S9 is in a closed state, thereby reducing the influence of nonlinear factors such as charge injection and clock feedthrough.

[0158] In some embodiments, at Ф2, the seventh switch S7 is in a closed state to generate a margin signal based on the input signal and the encoded signal input by the sub-digital-to-analog converter circuit, and amplify the margin signal to obtain a margin amplified signal.

[0159] Optionally, when the negative input signal is not grounded, the capacitor-flipping switched capacitor module may include a first capacitor-flipping switched capacitor module and a second capacitor-flipping switched capacitor module. Both the first and second capacitor-flipping switched capacitor modules include at least one eleventh switch S11, a twelfth switch S12, at least one thirteenth switch S13, at least one fourteenth switch S14, a fifteenth switch S15, a sixteenth switch S16, at least one fifth capacitor C5, and a sixth capacitor C6; wherein...

[0160] In the first capacitor flip-type switched capacitor module, the first terminal of the eleventh switch S11 and the first terminal of the twelfth switch S12 are used to receive the positive input signal VIP, and in the second capacitor flip-type switched capacitor module, the first terminal of the eleventh switch S11 and the first terminal of the twelfth switch S12 are used to receive the negative input signal VIM.

[0161] The first terminal of the thirteenth switch S13 is used to receive the reference signal. The second terminal of the eleventh switch S11 is connected to the second terminal of the thirteenth switch S13, the first terminal of the fourteenth switch S14, and the first terminal of the fifth capacitor C5 respectively. The second terminal of the twelfth switch S12 is connected to the first terminal of the fifteenth switch S15 and the first terminal of the sixth capacitor C6 respectively. The second terminal of the sixteenth switch S16 is grounded.

[0162] In the first capacitor flip-type switched capacitor module, the second terminal of the fifth capacitor C5 is connected to the second terminal of the sixth capacitor C6, the first terminal of the sixteenth switch S16, and the positive input terminal of the operational amplifier AMP. In the second capacitor flip-type switched capacitor module, the second terminal of the fifth capacitor C5 is connected to the second terminal of the sixth capacitor C6, the first terminal of the sixteenth switch S16, and the negative input terminal of the operational amplifier AMP.

[0163] In the first capacitor-flipping switched capacitor module, the connection point between the second terminal of the fifteenth switch S15 and the negative output terminal of the operational amplifier AMP is the positive output terminal VOP of the sub-digital-to-analog converter circuit. In the second capacitor-flipping switched capacitor module, the connection point between the second terminal of the fifteenth switch S15 and the positive output terminal of the operational amplifier AMP is the negative output terminal VOM of the sub-digital-to-analog converter circuit.

[0164] According to some embodiments, the number of the eleventh switch S11, the thirteenth switch S13, the fourteenth switch S14, and the fifth capacitor C5 is related to the number of selectable reference signals.

[0165] To give an example from a scenario, Figure 6 This is a schematic diagram of the structure of a sub-digital-to-analog converter circuit provided in an embodiment of this disclosure. Figure 6As shown, there are three selectable reference signals: Vrefn, Vrefp, and Vcm. Therefore, the number of eleventh switch S11, thirteenth switch S13, fourteenth switch S14, and fifth capacitor C5 are all three. Figure 6 Only the first capacitor-flipping switched capacitor module and a thirteenth switch S13 in the first capacitor-flipping switched capacitor module are shown, and the fourteenth switch S14 is not shown. The second capacitor-flipping switched capacitor module only shows a sixteenth switch S16.2, and the rest of the structure is the same as the first capacitor-flipping switched capacitor module.

[0166] According to some embodiments, the voltage values ​​corresponding to Vrefn, Vrefp, and Vcm can be set according to the actual application scenario. For example, Vrefn can be 1.6V, Vrefp can be 1.2V, and Vcm can be 0.8V.

[0167] It should be noted that in one operating cycle of this sub-digital-to-analog converter circuit, firstly, at Ф clear The fourteenth switch S14 is closed to connect the entire reference voltage to ground and reset the fifth capacitor C5. Therefore, the fifth capacitor C5 can be reset before sampling to eliminate the nonlinearity caused by the kick-back, and this structure does not cause a decrease in the feedback coefficient.

[0168] Secondly, at Ф1, the eleventh switch S11 and the twelfth switch S12 are in the closed state. The three fifth capacitors C5.1, C5.2, and C5.3, along with the sixth capacitor C6, sample the positive input signal VIP. At the end of the sampling, the charge stored in the sampling capacitors is VIP*(C 5.1 +C 5.2 +C 5.3 +C6); where C 5.1 The capacitance value corresponding to C5.1, C 5.2 The capacitance value corresponding to C5.2, C 5.3 C5.3 is the capacitance value corresponding to C5.3, and C6 is the capacitance value corresponding to C6.

[0169] Next, proceeding to Ф2, the thirteenth switch S13 and the fifteenth switch S15 are closed. The left plate of the sixth capacitor C6 is connected to the negative output terminal of the operational amplifier AMP through the fifteenth switch S15. C5.1, C5.2, and C5.3 are connected to the corresponding reference voltages according to the encoded signal input to the Sub-ADC. At this time, the stored charge Q6 of the sixth capacitor C6 is VOP*C. 5.1 The stored charge Q5.1 of C5.1 is V. 2p *C 5.1 The stored charge Q5.2 of C5.2 is V. 3p *C 5.2The stored charge Q5.3 of C5.3 is V. 3p *C 5.3 According to the principle of charge conservation, the positive output voltage VOP can be expressed as:

[0170]

[0171] Among them, C tot C 5.1 +C 5.2 +C 5.3 +C6, C 5.1 =C 5.2 =C 5.3 =C6,V 2p This refers to the voltage corresponding to C5.1 in the first capacitor-flipping switched capacitor module, V. 3p V represents the voltage corresponding to C5.2 in the first capacitor-flipping switched capacitor module. 4p This is the voltage corresponding to C5.3 in the first capacitor flip-type switched capacitor module.

[0172] Since this sub-analog-to-digital converter circuit is a fully differential structure, the differential output is expressed as:

[0173]

[0174] Among them, V 2n This refers to the voltage corresponding to C5.1 in the second capacitor flip-type switched capacitor module, V. 3n This refers to the voltage corresponding to C5.2 in the second capacitor flip-type switched capacitor module, V. 4n This refers to the voltage corresponding to C5.3 in the second capacitor flip-type switched capacitor module.

[0175] After that, record V ref =VP-VN, then the following relationship can be obtained from the transfer function curve:

[0176]

[0177] In other words, the residual amplification function can be achieved simply by connecting the capacitor plates of C5.1, C5.2, and C5.3 to different reference voltages in the discrimination intervals of different sub-analog-to-digital converter circuits. The decoding logic table is shown in Table (I).

[0178]

[0179]

[0180] Table (1)

[0181] Here, d1 to d6 refer to the encoded signals input to the sub-digital-to-analog converter circuit.

[0182] It should be noted that during the initial time period in Ф1, the sixteenth switch S16 and the seventeenth switch S17 are in the closed state, which can reduce the influence of nonlinear factors such as charge injection and clock feedthrough.

[0183] Alternatively, the operational amplifier can be, for example, a gain-enhanced cascode operational amplifier, thereby achieving high gain, high bandwidth, and large output swing.

[0184] According to some embodiments, Figure 7 This is a schematic diagram of a gain-enhanced cascode operational amplifier provided in an embodiment of this disclosure. Figure 7 As shown, the gain-enhanced cascode operational amplifier includes a second DC power supply VDD2, a fourth P-type switch PM4, a fifth P-type switch PM5, a sixth P-type switch PM6, a seventh P-type switch PM7, a fourth N-type switch NM4, a fifth N-type switch NM5, a sixth N-type switch NM6, a seventh N-type switch NM7, an eighth N-type switch NM8, a ninth N-type switch NM9, a P-side operational amplifier AMP_P, and an N-side operational amplifier AMP_N; wherein,

[0185] The second DC power supply VDD2 is connected to the source of the fourth P-type switch PM4 and the source of the fifth P-type switch PM5, respectively. The gates of the fourth P-type switch PM4 and the fifth P-type switch PM5 are used to receive the first control signal VBP1. The drain of the fourth P-type switch PM4 is connected to the source of the sixth P-type switch PM6 and the negative input terminal of the P-side operational amplifier AMP_P, respectively. The drain of the fifth P-type switch PM5 is connected to the source of the seventh P-type switch PM7 and the positive input terminal of the P-side operational amplifier AMP_P, respectively. The gate of the sixth P-type switch PM6 is connected to the positive output terminal of the P-side operational amplifier AMP_P. The gate of the seventh P-type switch PM7 is connected to the negative output terminal of the P-side operational amplifier AMP_P. The connection point between the drain of the sixth P-type switch PM6 and the drain of the fourth N-type switch NM4 is the negative output terminal Voutn of the gain-enhanced cascode operational amplifier. The connection point between the drain of the seventh P-type switch PM7 and the drain of the fifth N-type switch NM5 is the positive output terminal Voutp of the gain-enhanced cascode operational amplifier.

[0186] The gate of the fourth N-type switch NM4 is connected to the negative output terminal of the N-side operational amplifier AMP_N. The gate of the fifth N-type switch NM5 is connected to the positive output terminal of the N-side operational amplifier AMP_N. The source of the fourth N-type switch NM4 is connected to the positive input terminal of the N-side operational amplifier AMP_N and the drain of the sixth N-type switch NM6. The source of the fifth N-type switch NM5 is connected to the negative input terminal of the N-side operational amplifier AMP_N and the drain of the seventh N-type switch NM7. The gate of the sixth N-type switch NM6 is the positive input terminal of the gain-enhanced cascode operational amplifier. The gate of the seventh N-type switch NM7 is the negative input terminal of the gain-enhanced cascode operational amplifier.

[0187] The source of the sixth N-type switch NM6 is connected to the source of the seventh N-type switch NM7, the drain of the eighth N-type switch NM8, and the drain of the ninth N-type switch NM9, respectively. The gate of the eighth N-type switch NM8 is used to receive the second control signal VBN1, and the gate of the ninth N-type switch NM9 is used to receive the third control signal VCMFB. The sources of the eighth N-type switch NM8 and the ninth N-type switch NM9 are grounded.

[0188] It should be noted that the main body of this gain-enhanced cascode operational amplifier is a sleeve-type cascode operational amplifier, and its gain A V for:

[0189] A V ≈g mn1 [(g mn3 r on3 r on1 )||(g mp3 r op3 r op1 )]

[0190] Among them, g mn1 For the transconductance of the sixth N-type switch NM6, g mn3 For the transconductance of the fourth N-type switch NM4, g mp3 For the transconductance of the sixth P-type switching transistor PM6, r on1 The output resistance of the sixth N-type switching transistor NM6 is r. on3 The output resistance of the fourth N-type switching transistor NM4 is r. op1 The output resistance of the fourth P-type switching transistor PM4 is r. op3 This is the output resistance of the sixth P-type switching transistor PM6.

[0191] Its maximum output signal placement V OFS for:

[0192] V OFS =VDD2-|V dsat,mp1 |-|Vdsat,mp3 |-V dsat,mn1 -V dsat,mn3 -V dsat,mn5

[0193] Among them, V dsat,mp1 V is the saturation drain voltage of the fourth P-type switching transistor PM4. dsat,mp3 V is the saturation drain voltage of the sixth P-type switching transistor PM6. dsat,mn1 V is the saturation drain voltage of the sixth N-type switching transistor NM6. dsat,mn3 V is the saturation drain voltage of the fourth N-type switching transistor NM4. dsat,mn5 This is the saturation drain voltage of the eighth N-type switching transistor, NM8.

[0194] It should be noted that in order to increase the output swing of a gain-enhanced cascode operational amplifier (CABA), the overdrive voltages of multiple switches in the CABA need to be reduced. However, the gain of the CABA decreases as the overdrive voltage decreases. To solve this problem, adjustments can be made to the selection of the switches.

[0195] For example, the first switch in a plurality of switches can be configured to be a core device. The first switch is a switch whose drain-source voltage is less than a first drain-source voltage threshold. Therefore, the overdrive voltage of the switch can be reduced, and the driving capability and speed of the switch can be improved.

[0196] For example, the second switch in a series of multiple switches can be an input / output device (IO device). The second switch is a switch whose drain-source voltage is greater than the second drain-source voltage threshold. Therefore, it can be ensured that the devices in the circuit will not be burned out due to overvoltage.

[0197] In some embodiments, the first drain-source voltage threshold is less than the second drain-source voltage threshold. The first and second drain-source voltage thresholds can be adjusted according to specific application scenarios.

[0198] In summary, the pipelined analog-to-digital converter (ADC) circuit and its sub-pipeline circuit provided in this disclosure, in one working cycle, firstly, through Ф clear The control sub-digital-to-analog converter circuit is reset, which discharges the residual signal from the previous cycle. Then, the control sub-digital-to-analog converter circuit samples the signal. Therefore, the inaccuracy of sampling in the current cycle caused by the discharge of the residual signal from the previous cycle during the sampling process can be reduced, thereby improving the sampling accuracy and the accuracy of pipelined ADC circuits in performing analog-to-digital conversion.

[0199] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms may refer to different embodiments or examples. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0200] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0201] Although embodiments of this disclosure have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A sub-pipeline circuit in a pipelined analog-to-digital converter (ADC) circuit, characterized in that, The sub-pipeline circuit is connected to the clock circuit, and the sub-pipeline circuit includes a sub-analog-to-digital converter circuit and a sub-digital-to-analog converter circuit; wherein... The clock circuit is connected to the sub-analog-to-digital converter circuit and the sub-data converter circuit respectively, and is used to output clock signals to the sub-analog-to-digital converter circuit and the sub-digital-to-analog converter circuit. The clock signal includes a first clock signal and a second clock signal. The first clock signal includes an active phase and a short pulse control phase inserted before the active phase. During the short pulse control phase of the first clock signal, the sub-digital-to-analog converter circuit is in a reset state; During the effective phase of the first clock signal, the sub-digital-to-analog converter circuit samples the input signal; During the effective phase of the second clock signal, the sub-digital-to-analog converter generates a margin signal based on the input signal and the encoded signal input to the sub-digital-to-analog converter, and amplifies the margin signal to obtain a margin amplified signal.

2. The sub-pipeline circuit in the pipelined analog-to-digital converter (ADC) circuit according to claim 1, characterized in that, The sub-analog-to-digital conversion circuit includes a threshold generation module, a comparator module, and an encoding module; the input signal includes a positive input signal and a negative input signal; wherein... The control terminal of the threshold generation module is connected to the clock circuit, the output terminal of the threshold generation module is connected to the input terminal of the comparator module, the output terminal of the comparator module is connected to the input segment of the encoding module, and the output terminal of the encoding module is connected to the input terminal of the sub-digital-to-analog converter circuit. During the effective phase of the second clock signal, the threshold generation module samples the threshold voltage set and performs capacitor voltage division to obtain the first capacitor voltage set and the second capacitor voltage set. During the effective phase of the first clock signal, the threshold generation module samples the positive input signal and the negative input signal respectively, and generates a first comparison voltage based on the first capacitor voltage set and the positive input signal, and generates a second comparison voltage based on the second capacitor voltage set and the negative input signal; At the end of the effective phase of the first clock signal, the comparator module performs a voltage comparison between the first comparison voltage and the second comparison voltage, and inputs the comparison result signal to the encoding module.

3. The sub-pipeline stage circuit in the pipelined analog-to-digital converter (ADC) circuit according to claim 2, characterized in that, The threshold generation module includes a positive input signal threshold generation module and a negative input signal threshold generation module. Both the positive input signal threshold generation module and the negative input signal threshold generation module include a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a second capacitor. The threshold voltage set includes a first threshold voltage, a second threshold voltage, and a third threshold voltage. The connection point between the first end of the first switch and the first end of the second switch in the positive input signal threshold generation module is used to receive the positive input signal, and the connection point between the first end of the first switch and the first end of the second switch in the negative input signal threshold generation module is used to receive the negative input signal. The first terminal of the third switch in the positive input signal threshold generation module is used to receive the first threshold voltage, and the first terminal of the fourth switch in the positive input signal threshold generation module is used to receive the second threshold voltage. The first terminal of the third switch in the negative input signal threshold generation module is used to receive the third threshold voltage, and the first terminal of the fourth switch in the negative input signal threshold generation module is used to receive the second threshold voltage. The second terminal of the first switch is connected to the second terminal of the third switch and the first terminal of the first capacitor, respectively. The second terminal of the second switch is connected to the second terminal of the fourth switch and the first terminal of the second capacitor, respectively. The second terminal of the first capacitor is connected to the second terminal of the second capacitor, the first terminal of the fifth switch and the first input terminal of the comparator module, respectively. The second terminal of the fifth switch is grounded. During the active phase of the first clock signal, the first switch and the second switch are in the closed state; During the active phase of the second clock signal, the third switch and the fourth switch are in the closed state; During the initial time period of the effective phase of the second clock signal, the fifth switch is in the closed state.

4. The sub-pipeline circuit in the pipelined analog-to-digital converter (ADC) circuit according to claim 2, characterized in that, The comparator module includes a first transmission gate, a second transmission gate, a first-stage regenerative comparator, and a latch; wherein... The first terminal of the first transmission gate is used to receive the first comparison voltage, the first terminal of the second transmission gate is used to receive the second comparison voltage, the second terminal of the first transmission gate is connected to the first input terminal of the first-stage regenerative comparator, the second terminal of the second transmission gate is connected to the second input terminal of the first-stage regenerative comparator, the first output terminal of the first-stage regenerative comparator is connected to the first input terminal of the latch, the second output terminal of the first-stage regenerative comparator is connected to the second input terminal of the latch, and the output terminal of the latch is connected to the input terminal of the encoding module. At the end of the effective phase of the first clock signal, the first transmission gate and the second transmission gate are in an open state.

5. The sub-pipeline circuit in the pipelined analog-to-digital converter (ADC) circuit according to claim 4, characterized in that, The first-stage regenerative comparator includes a first DC power supply, a first P-type switch, a second P-type switch, a third P-type switch, a first N-type switch, a second N-type switch, a third N-type switch, a first NAND gate, a second NAND gate, a first NOT gate, and a second NOT gate; wherein, The input terminal of the first NOT gate is used to receive a drive signal, which is a high-level signal at the end of the effective phase of the first clock signal. The first DC power supply is connected to the source of the first P-type switch, the gate of the first P-type switch is connected to the output of the first NOT gate and the input of the second NOT gate, and the drain of the first P-type switch is connected to the source of the second P-type switch and the source of the third P-type switch, respectively. The drain of the second P-type switch is connected to the gate of the third P-type switch, the drain of the first N-type switch, the gate of the second N-type switch, the output of the second transmission gate, and the first input of the first NAND gate, respectively. The drain of the third P-type switch is connected to the gate of the second P-type switch, the drain of the second N-type switch, the gate of the first N-type switch, the output of the first transmission gate, and the first input of the second NAND gate, respectively. The drain of the third N-type switch is connected to the source of the first N-type switch and the source of the second N-type switch, respectively. The gate of the third N-type switch is connected to the output of the second NOT gate, the second input of the first NAND gate, and the second input of the second NAND gate. The source of the third N-type switch is grounded. The output of the first NAND gate is connected to the first input of the latch, and the output of the second NAND gate is connected to the second input of the latch.

6. The sub-pipeline circuit in the pipelined analog-to-digital converter (ADC) circuit according to claim 1, characterized in that, The sub-digital-to-analog converter circuit includes a capacitor-flipping switched capacitor module and an operational amplifier; wherein... The first input terminal of the capacitor-flipping switched capacitor module is used to receive the input signal, and the second input terminal of the capacitor-flipping switched capacitor module is used to receive the encoded signal. During the short pulse control phase of the first clock signal, the capacitor-flipping switched capacitor module is in a reset state; During the effective phase of the first clock signal, the capacitor-flipping switched capacitor module samples the positive input signal; During the effective phase of the second clock signal, the capacitor-flipping switched capacitor module determines the reference signal corresponding to the encoded signal and generates a margin signal based on the input signal and the reference signal. The operational amplifier amplifies the margin signal to obtain a margin amplified signal.

7. The sub-pipeline circuit in the pipelined analog-to-digital converter (ADC) circuit according to claim 6, characterized in that, The capacitor-flipping switched capacitor module includes at least one sixth switch, at least one seventh switch, at least one eighth switch, a ninth switch, a tenth switch, at least one third capacitor, and a fourth capacitor. The input signal includes a positive input signal. The first terminal of the sixth switch is used to receive the positive input signal, the first terminal of the seventh switch is used to receive the reference signal, the second terminal of the sixth switch is connected to the second terminal of the seventh switch, the first terminal of the eighth switch and the first terminal of the third capacitor respectively, the second terminal of the third capacitor is connected to the first terminal of the ninth switch, the first terminal of the fourth capacitor and the positive input terminal of the operational amplifier respectively, the connection point between the second terminal of the fourth capacitor, the first terminal of the tenth switch and the negative output terminal of the operational amplifier is the positive output terminal of the sub-digital-to-analog converter circuit, and the positive output terminal of the operational amplifier is the negative output terminal of the sub-digital-to-analog converter circuit; The second terminal of the eighth switch, the second terminal of the ninth switch, the second terminal of the tenth switch, and the negative input terminal of the operational amplifier are grounded; During the short pulse control phase of the first clock signal, the eighth switch is in the closed state; During the active phase of the first clock signal, the sixth switch and the tenth switch are in the closed state; During the initial time period of the effective phase of the first clock signal, the ninth switch is in the closed state; During the active phase of the second clock signal, the seventh switch is in the closed state.

8. The sub-pipeline stage circuit in the pipelined analog-to-digital converter (ADC) circuit according to claim 6, characterized in that, The input signal includes a positive input signal and a negative input signal. The capacitor-flipping switched capacitor module includes a first capacitor-flipping switched capacitor module and a second capacitor-flipping switched capacitor module. Both the first and second capacitor-flipping switched capacitor modules include at least one eleventh switch, at least one thirteenth switch, at least one fourteenth switch, at least one fifteenth switch, at least one sixteenth switch, at least one fifth capacitor, and at least one sixth capacitor. In the first capacitor-flipping switched capacitor module, the first terminal of the eleventh switch and the first terminal of the twelfth switch are used to receive the positive input signal, and in the second capacitor-flipping switched capacitor module, the first terminal of the eleventh switch and the first terminal of the twelfth switch are used to receive the negative input signal. The first terminal of the thirteenth switch is used to receive the reference signal. The second terminal of the eleventh switch is connected to the second terminal of the thirteenth switch, the first terminal of the fourteenth switch, and the first terminal of the fifth capacitor in a corresponding manner. The second terminal of the twelfth switch is connected to the first terminal of the fifteenth switch and the first terminal of the sixth capacitor in a corresponding manner. The second terminal of the sixteenth switch is grounded. In the first capacitor-flipping switched capacitor module, the second terminal of the fifth capacitor is connected to the second terminal of the sixth capacitor, the first terminal of the sixteenth switch, and the positive input terminal of the operational amplifier, respectively. In the second capacitor-flipping switched capacitor module, the second terminal of the fifth capacitor is connected to the second terminal of the sixth capacitor, the first terminal of the sixteenth switch, and the negative input terminal of the operational amplifier, respectively. In the first capacitor-flipping switched capacitor module, the connection point between the second terminal of the fifteenth switch and the negative output terminal of the operational amplifier is the positive output terminal of the sub-digital-to-analog converter circuit; in the second capacitor-flipping switched capacitor module, the connection point between the second terminal of the fifteenth switch and the positive output terminal of the operational amplifier is the negative output terminal of the sub-digital-to-analog converter circuit. During the short pulse control phase of the first clock signal, the fourteenth switch is in the closed state; During the active phase of the first clock signal, the eleventh switch and the twelfth switch are in the closed state; During the initial time period of the effective phase of the first clock signal, the sixteenth switch is in the closed state; During the active phase of the second clock signal, the thirteenth switch and the fifteenth switch are in the closed state.

9. The sub-pipeline stage circuit in the pipelined analog-to-digital converter (ADC) circuit according to claim 6, characterized in that, The operational amplifier is a gain-enhanced common-source cascode operational amplifier. The sleeve-type common-source cascode operational amplifier includes multiple switching transistors. The first switching transistor among the multiple switching transistors is a core device, and the second switching transistor among the multiple switching transistors is an input / output device. The first switching transistor is a switching transistor with a drain-source voltage less than a first drain-source voltage threshold, and the second switching transistor is a switching transistor with a drain-source voltage greater than a second drain-source voltage threshold. The first drain-source voltage threshold is less than the second drain-source voltage threshold.

10. A pipelined analog-to-digital converter (ADC) circuit, characterized in that, include: A clock circuit and N+1 sub-pipeline circuits as described in any one of claims 1 to 9, where N is a positive integer; wherein, The clock circuit is connected to N+1 sub-pipeline circuits respectively; The input terminal of the (N+1)th sub-pipeline circuit is connected to the output terminal of the Nth sub-pipeline circuit, and the margin amplification signal output by the Nth sub-pipeline circuit is the input signal of the (N+1)th sub-pipeline circuit.

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