Elastic bumper module and method for an elastic bumper module

Abstract

According to the embodiments of the present disclosure, a flexible buffer module and a method for the same are provided. The flexible buffer module comprises a storage module for buffering data between a data receiving clock domain and a local clock domain; a SKP OS symbol deletion circuit for deleting at least one SKP symbol from the received SKP symbols when the storage amount of the storage module exceeds an upper overflow water line; a SKP OS symbol addition circuit for adding at least one SKP symbol to the output SKP symbols when the storage amount of the storage module is lower than a lower overflow water line; a frequency offset measurement module for measuring the frequency offset between the data receiving clock of the data receiving clock domain and the local clock of the local clock domain; and a water line configuration module receiving the frequency offset output by the frequency offset measurement module and dynamically adjusting the position of the median water line according to the frequency offset. The flexible buffer module of the present disclosure can dynamically adjust the water line information according to the frequency offset to reduce the link delay.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of communication technology, and in particular, to a resilient buffer module and a method for the same. BACKGROUND

[0002] In high-speed serial links such as PCIe (Peripheral Component Interconnect Express) or CXL (Compute Express Link), there will be a frequency offset between the local clock and the clock of the received data. To eliminate these deviations, the PCIe / CXL protocol defines the SKP Ordered Set (SKP OS), which plays a key role in clock tolerance compensation. One SKP OS can contain 4 SKP symbols, and each re-timer can add or delete 1-2 SKP symbols to compensate for the frequency offset between the clock of the received data and the local clock. In specific design, the module used to implement this function is usually called a resilient buffer.

[0003] The traditional resilient buffer implementation scheme usually relies on a set of statically configured parameters to manage its operation, including the depth of the buffer, the median waterline, the first and second waterlines for overflow, and the first and second waterlines for underflow. However, this one-time static configuration method performed by firmware at power-on initialization has significant limitations. This method cannot adapt to dynamically changing link states (such as changes in link rate, width, or actual traffic patterns). To meet the tolerance requirements in the worst case, a deep buffer and conservative waterline are usually configured. The general median waterline is set at half the depth of the resilient buffer, thus introducing a delay of half the depth of the resilient buffer, resulting in a relatively large link delay. Since this configuration is independent of the actual frequency offset of the link, the buffer needs to maintain at least half the depth of data to output valid data. This delay is unacceptable for some delay-sensitive applications, such as CXL Type3 memory expansion applications.

[0004] In addition, even if dynamic configuration is used in the prior art, the firmware often reconfigures the waterline by periodically reading the link state, which triggers link retraining and causes temporary interruption of the data path, which is difficult to accept in PCIe re-timers.

[0005] In summary, the prior art lacks a solution that can dynamically adjust the buffer waterline according to the actual frequency offset of the link, reduce data delay, and not disrupt the link state. SUMMARY

[0006] Based on the defects of the prior art, there is an urgent need for an elastic buffer module and method that can reduce link latency.

[0007] A first aspect of the embodiments of the present disclosure provides an elastic buffer module, which comprises a storage module for buffering data between a data receiving clock domain and a local clock domain, the waterline parameters of the storage module at least including a median waterline, an upper overflow waterline and a lower overflow waterline; a SKP OS symbol deletion circuit, an output end of which is connected to an input end of the storage module, for deleting at least one SKP symbol from the received SKP symbols when the storage amount of the storage module exceeds the upper overflow waterline; a SKP OS symbol addition circuit, an input end of which is connected to an output end of the storage module, for adding at least one SKP symbol to the output SKP symbols when the storage amount of the storage module is lower than the lower overflow waterline; a frequency offset measurement module for measuring the frequency offset between the data receiving clock of the data receiving clock domain and the local clock of the local clock domain; a waterline configuration module receiving the frequency offset output by the frequency offset measurement module and dynamically adjusting the position of the median waterline according to the frequency offset, wherein the median waterline is used to indicate the storage amount position when the storage module starts to send the stored data. That is, only when the data stored in the storage module reaches the median waterline for the first time, the data stored in the storage module is allowed to be sent.

[0008] The elastic buffer module of the embodiments of the present disclosure can adjust the waterline parameters, especially the median waterline, according to the size of the frequency offset, thereby reducing the link latency of the link using the elastic buffer module.

[0009] Optionally, according to the elastic buffer module of the first aspect of the embodiments of the present disclosure, the frequency offset measurement module measures the frequency offset between the data receiving clock and the local clock when the link training and the state machine exit the recovery receiver lock state. The waterline configuration module can be implemented by a hardware circuit and does not need the intervention of the firmware program in the chip. The frequency offset measurement when the link training and the state machine exit the recovery receiver lock state does not cause the change of the link state, avoiding triggering the retraining of the link.

[0010] Optionally, according to the elastic buffer module of the first aspect of the embodiments of the present disclosure, the waterline configuration module looks up a predetermined waterline configuration table according to the frequency offset between the data receiving clock and the local clock to determine the waterline parameters. In this embodiment, the waterline configuration module can use the static configuration of the register.

[0011] Embodiments of the present disclosure can use a predetermined and stored water line configuration table, and query the water line parameter corresponding to the measured frequency offset in the water line configuration table as an index. The water line parameter will be output to the SKP OS symbol deletion circuit and the SKP OS symbol addition circuit to update the water line parameter therein. This way occupies less hardware resources and is more efficient.

[0012] Optionally, according to the elastic buffer module of the first aspect of embodiments of the present disclosure, the overflow water line includes an overflow first water line and an overflow second water line, the SKP symbol deletion quantity corresponding to the overflow second water line is greater than the SKP symbol deletion quantity corresponding to the overflow first water line, and the underflow water line includes an underflow first water line and an underflow second water line, the SKP symbol addition quantity corresponding to the underflow second water line is greater than the SKP symbol addition quantity corresponding to the underflow first water line. Each level of the overflow water line and the underflow water line can include two or more levels. The number of SKP symbols deleted or added by each level of water line can be pre-stored in a register.

[0013] Optionally, according to the elastic buffer module of the first aspect of embodiments of the present disclosure, the SKP OS symbol deletion circuit receives the write end water line from the storage module, and judges whether the write end water line exceeds the overflow water line according to the write end water line of the storage module, and the SKP OS symbol addition circuit receives the read end water line from the storage module, and judges whether the read end water line is lower than the underflow water line according to the read end water line of the storage module. The connection mode of the SKP OS symbol deletion circuit, the storage module and the SKP OS symbol addition circuit makes it unnecessary to modify other data signals when deleting or adding SKP OS symbols, which can simplify the circuit design and does not affect the stability of the storage module.

[0014] Optionally, according to the elastic buffer module of the first aspect of embodiments of the present disclosure, the water line configuration module dynamically adjusts the position of the median water line according to the frequency offset, so that the median water line is between the preset maximum median water line and the preset minimum median water line, and the depth of the median water line decreases with the decrease of the frequency offset. The depth of the median water line can decrease with the decrease of the frequency offset, so that the median water line does not have to be fixed at a depth of 50%, but can be set at a position with a smaller depth, while meeting the requirements of avoiding overflow and underflow, so that the link delay can be reduced in the case of low frequency offset.

[0015] Optionally, according to the elastic buffer module of the first aspect of embodiments of the present disclosure, the median water line is calculated by the following method:

[0016] Median water line = Mid min +k˙f offset or Mid max ﹣k˙f offsetwhere k is a pre-trained proportion constant, f offset is the frequency offset, Mid min and Mid max are the preset minimum and maximum midlines in the storage module, respectively.

[0017] Optionally, the waterline configuration module calculates a waterline configuration scheme according to the frequency offset information:

[0018]

[0019] Upper2=D-(Δ sym +M)

[0020] Lower2=Δ sym +M

[0021] where f offset (ppm)=10 6 (f local -f rx ) / f rx , N skp is the maximum number of symbols between two SKP OS insertions allowed by the protocol, f offset (ppm) is the frequency offset between the local clock and the data receiving clock, Δ sym is the maximum number of symbol drift caused by the frequency offset, f local is the local clock frequency, f rx is the data receiving clock, which can be recovered from the received data; Upper2 is the second overflow waterline, Lower2 is the second underflow waterline, D is the depth of the storage module in terms of the number of symbols, and M is a safety margin, which ensures that the storage module will not overflow or underflow even when the worst frequency offset is superimposed with an additional disturbance.

[0022] The above embodiment dynamically selects the corresponding overflow / underflow waterline position according to the frequency offset, so that the compensation strategy is more in line with the actual link state, avoids excessive margin, and improves the utilization rate of the buffer.

[0023] Optionally, according to the elastic buffer module of the first aspect of the embodiments of the present disclosure, the frequency offset measurement module counts the local clock and the data receiving clock using a counter within a preset observation time window, and calculates the frequency offset according to the difference between the number of cycles of the local clock and the number of cycles of the data receiving clock within the observation time window.

[0024] A second aspect of the embodiments of the present disclosure provides a method for the elastic buffer module, which is used in the elastic buffer module, and includes that the frequency offset measurement module measures the frequency offset between the data receiving clock and the local clock; the water line configuration module dynamically adjusts the position of the median water line according to the frequency offset; for valid received data, it is judged whether the data signal is an SKP symbol; if it is an SKP symbol, it is judged whether the water line of the storage module exceeds the upper overflow water line; if the upper overflow water line is exceeded, the first preset number of SKP symbols corresponding to the upper overflow water line are deleted.

[0025] Optionally, the method provided by the second aspect of the embodiments of the present disclosure further includes that for the valid data output by the storage module, it is judged whether the output data signal is an SKP symbol; if it is an SKP symbol, it is judged whether the water line of the storage module is lower than the lower overflow water line; if the lower overflow water line is lower, the second preset number of SKP symbols corresponding to the lower overflow water line are added.

[0026] The elastic buffer module of the present disclosure can dynamically adjust the water line information according to the frequency offset, especially dynamically adjust the position of the median water line, significantly reduce the link delay when the frequency offset is small, and is particularly suitable for delay-sensitive applications such as CXL Type-3. The frequency offset measurement and water line configuration are completed when the link training and the state machine exit the receiver lock state, and the whole process is automatically completed by hardware, without triggering the link retraining.

[0027] The implementation of any device or method of the present disclosure does not necessarily require all the advantages described above to be achieved at the same time. Other features and advantages of the present disclosure will be described in the following embodiments, and some will become apparent from the embodiments, or will be understood by implementing the present disclosure. The purposes and advantages of the embodiments of the present disclosure can be achieved and obtained by the structures indicated in the specification, claims and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure.

[0029] Figure 1 is a structural schematic diagram of an elastic buffer module according to an embodiment of the present disclosure;

[0030] Figure 2 is a schematic diagram of a write operation workflow of an elastic buffer module according to an embodiment of the present disclosure;

[0031] Figure 3 is a schematic diagram of a read operation workflow of an elastic buffer module according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the drawings of the embodiments of the present disclosure to make a clear and complete description of the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. The various different embodiments can be combined with each other to constitute other embodiments which are not shown in the following description. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without any creative effort fall within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, technical terms or scientific terms used herein should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. The terms "first", "second", and similar terms used herein do not necessarily denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one" or "a" or "an" do not necessarily denote a quantity of one. The terms "comprising", "including", and similar terms are intended to encompass the elements listed thereafter, equivalents thereof, and additional elements. The terms "connected", "coupled", and similar terms are not limited to physical or mechanical connections or couplings, but also include electrical connections or couplings, whether direct or indirect. The terms "upper", "lower", "left", "right", and similar terms are used only to indicate relative positions, and when the absolute positions of the described objects are changed, the relative positions may also be changed accordingly.

[0034] Figure 1 A structural diagram of an elastic buffer module according to an embodiment of the present disclosure is shown. As shown, the elastic buffer module of the present embodiment includes a storage module 11, an SKP OS symbol deletion circuit 12, an SKP OS symbol addition circuit 13, a frequency offset measurement module 14, and a waterline configuration module 15. The elastic buffer module receives a received data signal and a received data signal valid indication from the outside in a data receiving clock domain, and sends an output data signal and an output data signal valid indication to the outside in a local clock domain. Figure 1

[0035] The storage module 11 can be implemented using a FIFO (First In First Out buffer), more specifically, an asynchronous FIFO. The storage module 11 is used for data buffering and cross-domain transmission between the data receiving clock domain and the local clock domain. The receiving clock can be recovered from the received data through a clock recovery circuit (CDR).

[0036] ​The SKP OS symbol deletion circuit 12 receives the received data signal and the received data signal valid indication at its input, and is connected to the storage module 11 at its output, for deleting at least one SKP symbol when it detects that the storage module 11 has exceeded the upper watermark, thereby preventing overflow. The upper watermarks can include one or more levels of watermarks. The number of SKP symbols to be deleted is predetermined for each level of the upper watermarks. The SKP OS symbol deletion circuit 12 can send a storage module write enable signal and the received data signal to the storage module 11 to write data to it, and receive the write end watermark from the storage module 11 to detect the watermark level of the storage module 11 to determine whether a certain number of SKP symbols are to be deleted.

[0037] The SKP OS symbol addition circuit 13 is connected to the output of the storage module 11 at its input, and sends the output data signal and the data signal valid indication to the outside at its output. The SKP OS symbol addition circuit 13 is used to add at least one SKP symbol when it detects that the storage module has fallen below the lower watermark, thereby preventing underflow. The lower watermarks can include one or more levels of watermarks. The number of SKP symbols to be added is predetermined for each level of the lower watermarks. The SKP OS symbol addition circuit 13 can send a read enable signal to the storage module 11, and receive the output data signal and the read end watermark from the storage module. The SKP OS symbol addition circuit 13 detects the watermark level of the storage module 11 through the read end watermark.

[0038] The upper watermarks (generally corresponding to the case where the write end frequency of the storage module is higher than the read end frequency) and the lower watermarks (generally corresponding to the case where the output end frequency of the storage module is higher than the write end frequency) can include multiple levels of watermarks, and each level of the watermarks corresponds to a different number of symbols to be deleted or added. For example, the storage module can include a median watermark, an upper first and second watermarks, and a lower first and second watermarks. The median watermark indicates that internal storage data is allowed to be released to the outside only when the data stored in the storage module reaches this watermark or depth for the first time. Therefore, if the depth of the median watermark is large, the resulting link delay will also be large.

[0039] The upper first watermark of the storage module indicates that if the content stored in the storage module exceeds this watermark, a corresponding number of SKP symbols need to be deleted when the SKP OS is written (i.e., when the elastic buffer module receives the SKP OS). The upper second watermark of the storage module indicates that if the content stored in the storage module exceeds this watermark, a corresponding number of SKP symbols need to be deleted when the SKP OS is written at the write end of the buffer. The upper second watermark prevents overflow at the maximum frequency offset, so the number of symbols to be deleted corresponding to the upper second watermark is greater than the number of symbols to be deleted corresponding to the upper first watermark.

[0040] The underflow first watermark of the storage module indicates that if the content stored in the elastic storage module is below this watermark, then a corresponding number of SKP symbols need to be added when outputting the SKP OS. The underflow second watermark of the storage module indicates that if the content stored in the elastic storage module is below this watermark, then a corresponding number of SKP symbols need to be added when outputting the SKP OS. The underflow second watermark prevents overflow at the maximum frequency offset, so the number of symbols that it corresponds to add is greater than the number of symbols that the underflow first watermark corresponds to add.

[0041] The frequency offset measurement module 14 measures the frequency offset between the data receiving clock and the local clock, and outputs the frequency offset information. The input of the watermark configuration module 15 receives the frequency offset information output by the frequency offset measurement module 14, and obtains new watermark parameters according to the frequency offset information. The watermark configuration module 15 can obtain a new set of watermark parameters, for example, including the median watermark, the overflow first watermark, the overflow second watermark, the underflow first watermark and the underflow second watermark, according to the frequency offset information by looking up a table or calculating, and send the new set of parameters to the SKP OS symbol deletion circuit 12 and the SKP OS symbol addition circuit 13.

[0042] The SKP symbol is included in the received data signal. The received data signal valid indication indicates whether the data signal corresponding to it on the clock cycle is a valid data signal. When the received data signal valid indication indicates that the received data signal is valid, the current received data signal will be further judged whether it is a SKP symbol. If it is not a SKP symbol, it will be directly written into the storage module; when the received data signal valid indication indicates that the data is invalid, the data signal corresponding to the time cycle is invalid and will not be written into the storage module. Through the indication of the data valid signal, it is ensured that only valid data signals are stored in the storage module, and invalid signals are avoided to affect the watermark judgment. The process of data input and output elastic buffer module will be described in detail with reference to Figure 2 In the following, it will be described in detail.

[0043] Figure 2 is a schematic diagram of the writing workflow of the elastic buffer module according to an embodiment of the present disclosure. The following will be described in combination with Figure 1The workflow is described as follows. In step S21, the frequency offset measurement module measures the frequency offset between the local clock and the data receiving clock. Alternatively, the local clock and the data receiving clock are counted respectively within a preset observation time window, so as to obtain the number of periods of the local clock and the number of periods of the receiving clock within the observation window. When the observation window ends, the count values of the two counters are compared, the difference between the two is obtained, and the frequency offset between the local clock and the data receiving clock is calculated according to the difference, which can be expressed in ppm (parts per million) for example. Other ways of measuring the frequency offset can also be used in the embodiment, such as obtaining the frequency offset through phase difference, through the sliding window cumulative difference method, or through a phase-locked loop (PLL) or a digital phase-locked loop (DPLL).

[0044] In step S22, the water line configuration module re-determines the water line parameters according to the frequency offset, for example, at least the median water line can be dynamically adjusted, or the median water line, the overflow first water line, the overflow second water line, the underflow first water line and the underflow second water line can be dynamically adjusted. Alternatively, a configuration table can be set in advance, the water line configuration module looks up the internal configuration table according to the frequency offset information to obtain the median water line, the overflow first water line, the overflow second water line, the underflow first water line and the underflow second water line, and then sends the configuration information to the SKP OS symbol deletion circuit and the SKP OS symbol addition circuit.

[0045]

[0046] Table 1 Water line configuration table

[0047] Table 1 is an example of a water line configuration table of the water line configuration module according to an embodiment of the present disclosure, which can be queried with frequency offset information as an index. The water line configuration table can be divided into n schemes (n is an integer) according to the size of the frequency offset, each scheme corresponding to a frequency offset or a range of frequency offsets. Each scheme includes the positions of the corresponding median water line, overflow first water line, overflow second water line, underflow first water line and underflow second water line. When the frequency offset is measured, the water line configuration module looks up the water line configuration table according to the frequency offset to obtain a set of configuration schemes. If the frequency offset changes, the water line configuration module looks up the configuration table with the frequency offset as an index to obtain a new configuration scheme.

[0048] In another embodiment, the water line configuration module can calculate the water line configuration scheme according to the frequency offset information, which can be calculated according to the following formula:

[0049] (Equation 1)

[0050] Where f offset (ppm) = 10 6 (f local -f rx ) / f rxN skp f is the maximum number of symbols that can be intervening between two SKP adjustments. offset (ppm) is the frequency offset between the local clock and the data receiving clock, Δ sym The worst-case sign number drift caused by frequency offset, f local It is the local clock frequency, f rx It is the data receiving clock, which can be recovered from the data stream.

[0051] Upper2=D﹣(Δ sym +M) (Equation 2)

[0052] Lower2=Δ sym +M (Equation 3)

[0053] Upper2 is the second overflow waterline, Lower2 is the second underflow waterline, D is the depth of the storage module (in terms of the number of symbols), and M is the safety margin, which ensures that the storage module will not overflow or underflow even when additional disturbances are added on top of the worst frequency offset.

[0054] To reduce latency, the midline (Mid) can be adjusted based on the frequency offset:

[0055] Mid=Lower2+α(Upper2﹣Lower2)

[0056] α is an adjustment coefficient, and its value can be determined based on the measured frequency offset. When the frequency offset is large, α should be closer to 0.5 to ensure safety; when the frequency offset is small, α can be a smaller value to bring the median waterline closer to the overflow side, thereby reducing the amount of filler required for the first data read and lowering link latency. The maximum value of α can be set. max A value of 0.5 ensures that Mid lies between the upper and lower second waterline. α min The value ensures that the difference between the minimum value of Mid and the second overflow waterline is not less than Δ. sym +M, therefore, based on the frequency offset at the maximum value of the adjustment coefficient α max and minimum value α min The value of the adjustment coefficient α is determined through a linear mapping.

[0057] In yet another embodiment, the median water line Mid can be calculated as follows:

[0058] Mid=Mid min +k˙f offset or Mid=Mid max ﹣k˙f offset ,

[0059] k is a pre-training constant, which is equivalent to a proportionality coefficient, which maps the frequency offset (ppm) to the storage module depth. For example, the minimum median waterline Mid min and the maximum median waterline Mid max may be 20% of the storage module depth and 50% of the storage module depth, respectively. K can be calculated according to the maximum median waterline, the minimum median waterline, and the maximum frequency offset (or the maximum possible frequency offset), or obtained through simulation and linear fitting and fixed in the chip or firmware as a pre-training constant.

[0060] The above embodiments allow the median waterline to be adjusted according to the frequency offset, rather than always being in the middle of the storage module, thereby reducing the link latency and ensuring the stability and low latency characteristics of the system.

[0061] In the above embodiments, the overflow first waterline and the underflow first waterline can be determined according to the overflow second waterline and the underflow second waterline and the number of symbols contained in the SKP OS. The difference between the overflow first waterline and the overflow second waterline and the difference between the underflow first waterline and the underflow second waterline can be set to be not less than Δ sym , so as to avoid frequent add or delete operations near the boundary.

[0062] The above waterline configuration operation of the waterline configuration module can be implemented by a hardware circuit, which measures the frequency offset using a hardware circuit without the need for a firmware program in the chip, so as not to trigger the re-training of the link. In order not to cause the change of the link state, in the embodiments of the present disclosure, the frequency offset measurement circuit preferably works when the PCIe link training and status state machine (LTSSM, Link Training and Status State Machine) exits the Recovery.RcvrLock state, and measures the frequency offset between the data receiving clock and the local clock. The Recovery.RcvrLock state of the link training and status state machine is defined in the PCIe specification. When the state exits, the clock recovery circuit (CDR) of the receiving end has completed the locking, the receiving clock is relatively stable, and the link has not yet entered the normal active state (Normal Active State), so the frequency offset between the local clock and the data receiving clock can be accurately measured at this time.

[0063] The CXL protocol is fully compatible with PCIe at the physical layer, so its link training process also follows the link training and status machine defined in the PCIe specification. Therefore, the frequency offset measurement and waterline configuration method described in the present disclosure is not only applicable to the PCIe protocol, but also applicable to the CXL protocol.

[0064] At step S23, the elastic buffer module receives a valid data signal. When the elastic buffer module receives a data signal, it receives a data signal and a data valid signal at the same time. The elastic buffer module determines whether the received data signal is valid. The validity determination can be achieved by receiving a data valid signal. The data valid signal indicates whether the data signal is valid. When the data valid signal indicates that the data signal is invalid, the data signal is discarded and not processed. When the data valid signal indicates that the data signal is valid, the data signal is received into the elastic buffer module. At step S24, it is determined whether the data signal is an SKP symbol. The determination can be performed by the SKP OS symbol deletion circuit. If the data signal is an SKP symbol, step S25 is performed. If the data signal is not an SKP symbol, step S29 is performed, in which the received data signal is written into the storage module.

[0065] At step S25, it is determined whether the water level of the storage module exceeds the overflow second water level. If the water level of the storage module exceeds the overflow second water level, step S26 is performed, in which the SKP OS symbol deletion circuit deletes a corresponding number of SKP symbols, for example, 2 SKP symbols, according to the frequency offset. After the SKP symbols are deleted, the process returns to step S23 to receive the next valid data signal. If the water level of the buffer does not exceed the overflow second water level, step S27 is performed.

[0066] At step S27, it is determined whether the water level of the storage module exceeds the overflow first water level. If the overflow first water level is not exceeded, no SKP symbol is deleted, and step S29 is performed, in which the received data signal is written into the storage module. If the overflow first water level is exceeded, step S28 is performed, in which the SKP OS symbol deletion circuit deletes a corresponding number of SKP symbols, for example, 1 SKP symbol, according to the frequency offset. After the SKP symbols are deleted, the process returns to step S23 to receive the next valid data signal.

[0067] At step S29, after the data signal is written into the storage module, the process returns to step S23 to receive the next valid data signal.

[0068] Figure 3A schematic diagram of a readout workflow of the elastic buffer module according to an embodiment of the present disclosure is shown. In step S31, a valid data signal is output to the SKP OS symbol adding circuit according to the valid indication of the data signal output by the storage module. It is to be noted that the data stored in the storage module is allowed to be sent only when the waterline of the storage module reaches the midline for the first time. In step S32, it is determined whether the data signal is a SKP symbol, for example, by the SKP OS symbol adding circuit. If it is a SKP symbol, step S33 is performed. If it is not a SKP symbol, step S37 is performed, in which the received data signal is output from the elastic buffer module, and the output signal includes the output data signal and the valid indication thereof.

[0069] In step S33, the SKP OS symbol adding circuit determines whether the waterline of the storage module is below the second underflow waterline. If the waterline of the storage module is below the second underflow waterline, step S34 is entered, in which a corresponding number of SKP symbols, for example, 2 SKP symbols, is added according to the frequency offset. After the SKP symbols are added, the process returns to step S31 to receive the next valid data signal. If the waterline of the storage module is not below the second underflow waterline, step S35 is entered.

[0070] In step S35, the SKP OS symbol adding circuit determines whether the waterline of the storage module is below the first underflow waterline. If it is not below the first underflow waterline, the SKP symbol is not deleted, and step S37 is performed, in which the data signal is output from the elastic buffer module. If it is below the first underflow waterline, step S36 is performed, in which a corresponding number of SKP symbols, for example, 1 SKP symbol, is added according to the frequency offset. After the SKP symbols are added, the process returns to step S31 to receive the next valid data signal.

[0071] According to the above embodiment, the waterline of the storage module can be configured according to the actual state of the link, and the optimal configuration in the actual state can be obtained, thereby reducing the delay of the link and improving the utilization rate of the storage module, and the embodiment is suitable for scenarios sensitive to link delay in high-speed communication.

[0072] The embodiments of the present application can be modified and changed in various ways without departing from the spirit and scope of the present application. Therefore, it should be understood that the scope of protection of the present application should not be limited to the above exemplary embodiments, but should cover the full scope defined by the claims and their equivalents.

Claims

1. A resilient bumper module, characterized by The method comprises: a storage module for buffering data between a data receiving clock domain and a local clock domain, a waterline parameter of the storage module comprising at least a median waterline, an overflow waterline and an underflow waterline; an SKP OS symbol deletion circuit, an output end of which is connected with an input end of the storage module, for deleting at least one SKP symbol from received SKP symbols when a storage amount of the storage module exceeds the overflow waterline; an SKP OS symbol addition circuit, an input end of which is connected with an output end of the storage module, for adding at least one SKP symbol to output SKP symbols when the storage amount of the storage module is lower than the underflow waterline; a frequency offset measurement module for measuring a frequency offset between a data receiving clock of the data receiving clock domain and a local clock of the local clock domain; a waterline configuration module receiving the frequency offset output by the frequency offset measurement module and dynamically adjusting a position of the median waterline according to the frequency offset, wherein the median waterline is used to indicate a storage amount position when the storage module starts to send out stored data.

2. The elastomeric bumper module of claim 1, wherein, The frequency offset measurement module measures the frequency offset between the data receiving clock and the local clock when a receiver lock state of a link training and state machine recovery exits.

3. Elastomeric bumper module according to claim 1 or 2, characterized in that The waterline configuration module looks up a predetermined waterline configuration table according to the frequency offset between the data receiving clock and the local clock to determine the waterline parameter.

4. A module according to claim 1 or 2, wherein The overflow waterline comprises an overflow first waterline and an overflow second waterline, the SKP symbol deletion quantity corresponding to the overflow second waterline being greater than the SKP symbol deletion quantity corresponding to the overflow first waterline, and the underflow waterline comprises an underflow first waterline and an underflow second waterline, the SKP symbol addition quantity corresponding to the underflow second waterline being greater than the SKP symbol addition quantity corresponding to the underflow first waterline.

5. The elastomeric bumper module of claim 1 or 2, wherein, The SKP OS symbol deletion circuit receives a storage module write end waterline from the storage module and judges whether the overflow waterline is exceeded according to the storage module write end waterline, and the SKP OS symbol addition circuit receives a storage module read end waterline from the storage module and judges whether the underflow waterline is lower than the underflow waterline according to the storage module read end waterline.

6. The elastomeric bumper module of claim 1 or 2, wherein, The waterline configuration module dynamically adjusts the position of the median waterline according to the frequency offset, so that the median waterline is between a preset maximum median waterline and a preset minimum median waterline, and a depth of the median waterline decreases with a decrease of the frequency offset.

7. The elastomeric bumper module of claim 1, wherein, The median waterline is calculated by one of the following ways: Median line = Mid min +k˙f offset ; Median line = Mid max -kf offset ; where k is a pre-trained proportionality constant, f offset is the frequency offset, Mid min and Mid max are the pre-set minimum and maximum midlines of the storage module, respectively.

8. The elastomeric bumper module of claim 1, wherein, The frequency offset measurement module counts the local clock and the data receiving clock respectively using a counter within a preset observation time window, and calculates the frequency offset according to a difference between a cycle number of the local clock and a cycle number of the data receiving clock within the observation time window.

9. A method for a resilient bumper module, characterized in that The method is used for the elastic buffer module as claimed in any one of claims 1-8, comprising The frequency offset measurement module measures the frequency offset between the data receiving clock and the local clock; The waterline configuration module dynamically adjusts the position of the median waterline according to the frequency offset; For valid received data, it is judged whether the data signal is an SKP symbol; If the SKP symbol, judge whether the water line of the storage module exceeds the upper overflow water line; If the upper overflow water line is exceeded, the first preset number of SKP symbols corresponding to the upper overflow water line is deleted.

10. The method for a resilient bumper module of claim 9, wherein, Also includes For the valid data output by the storage module, judge whether the output data signal is an SKP symbol; If the SKP symbol, judge whether the water line of the storage module is lower than the lower overflow water line; If lower than the lower overflow water line, add the second preset number of SKP symbols corresponding to the lower overflow water line.

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