Low-power-consumption wireless sensor network communication chip architecture

Abstract

The invention relates to a low-power-consumption wireless sensor network communication chip architecture which is applied to the technical field of electric power sensing. The chip architecture comprises a control circuit, a transmitting circuit, a receiving circuit and a clock circuit, and the control circuit is responsible for logic control, parameter configuration, data forwarding and external interaction of the whole chip; the transmitting circuit is used for processing the data from the MCU and then transmitting the processed data; the receiving circuit realizes the functions of acquisition, amplification, filtering, demodulation and the like of wireless signals; and the clock circuit provides a high-frequency carrier signal and a clock signal for the chip. An analog-to-digital converter and a digital-to-analog converter circuit are not needed, the structures of the transmitting end and the receiving end can be effectively simplified, and meanwhile, the implementation area and the power consumption of a chip are reduced through flexible working mode switching and closing of different functional modules in different modes.

Description

Technical Field

[0001] This invention relates to the field of power sensing technology, and more specifically to a low-power wireless sensor network communication chip architecture. Background Technology

[0002] The current development of energy and power faces the significant tasks of ensuring a safe and reliable supply and accelerating the clean and low-carbon transformation. With the large-scale integration of new energy sources and power electronic equipment into the power grid, the power system is undergoing profound changes in its source-grid-load characteristics, exhibiting complex AC / DC hybrid features. Intelligent sensor technology is a crucial component of this new power system, deploying more intelligent sensors on grid equipment to achieve more precise and detailed monitoring of the grid environment and equipment status. Currently, power sensors have achieved a certain scale of application in transmission and transformation, based on the widespread deployment of various sensors and intelligent terminals, including those for micro-meteorology, temperature, towers, tilt, icing, galloping, sag, wind deflection, partial discharge, dielectric loss, insulation, leakage current, vibration, and pressure, enabling the collection of information on the status of main electrical equipment, the environment, and other auxiliary data.

[0003] With the continuous advancement of the energy internet construction, the power grid is placing higher demands on the depth, breadth, and density of information sensing, leading to an explosive growth in the demand for sensors and sensor networks. Currently, sensor network technologies, represented by low-power wireless communication, offer advantages such as massive connectivity and low cost. However, they also suffer from various technical systems, differing network protocols, and inconsistent interface specifications. When directly applied to the power grid, these technologies exhibit mismatches with the needs of power sensing services in terms of communication speed, transmission distance, and module power consumption. In field applications, sensor modules lack continuous wired power supply and are primarily powered by batteries. Furthermore, the installation environment for sensors is often limited in space, thus placing high demands on low power consumption, complexity, and size.

[0004] Currently, wireless sensor network communication chip architectures generally include traditional layered architectures, system-on-a-chip (SoC) architectures, and multi-mode communication architectures. Traditional layered architectures divide the network into different layers, each responsible for a specific function, with layers interacting through standard interfaces. This architecture borrows from the layered approach of computer networks, offering good modularity and scalability, but generally only includes wireless communication functionality, making its functionality relatively limited. SoC architecture integrates multiple functional modules such as a microprocessor, memory, wireless communication module, and sensor interface onto a single chip, forming a complete system. Multi-mode communication architecture chips support multiple wireless communication protocols and can switch between different communication modes. This architecture allows for the selection of the most suitable communication protocol based on different application scenarios and requirements, improving the flexibility and adaptability of wireless sensor networks; however, integrating multiple communication methods results in higher power consumption. Summary of the Invention

[0005] To address the aforementioned problems in existing technologies, this invention proposes a low-power wireless sensor network communication chip architecture, characterized in that the communication chip architecture includes: a receiving circuit, a clock circuit, a transmitting circuit, and a control circuit; the control circuit is connected to the receiving circuit, the clock circuit, the transmitting circuit, and an external processor, respectively, and the clock circuit is also connected to the receiving circuit and the transmitting circuit, respectively.

[0006] The control circuit is used to detect the power-on signal sent by the external processor, and based on the power-on signal, switch the working state of the communication chip from sleep mode to wait mode, receive and parse the signal instructions sent by the external processor, and generate configuration data and mode switching instructions; it is also used to switch the working state of the communication chip from the wait mode to receive mode or transmit mode according to the clock signal generated by the clock circuit and the mode switching instructions corresponding to the clock signal.

[0007] The clock circuit is used to generate the clock signal and upload it to the control circuit according to the configuration data transmitted by the control circuit when the working state is in waiting mode.

[0008] The receiving circuit is used to receive and process external communication signals when the communication chip is in receiving mode;

[0009] The transmitting circuit is used to transmit communication signals according to the configuration data transmitted by the control circuit when the communication chip is in transmitting mode.

[0010] Optionally, the clock circuit includes a frequency synthesizer and a clock control circuit connected in sequence; the frequency synthesizer is connected to the receiving circuit and the transmitting circuit respectively;

[0011] The frequency synthesizer is used to generate a current high-frequency clock signal based on the current reference clock signal, and to send the current high-frequency clock signal to the receiving circuit or the transmitting circuit. The current high-frequency clock signal is either a first high-frequency clock signal or a second high-frequency clock signal.

[0012] The clock control circuit is used to provide the clock signal corresponding to the mode switching command to the timing control module of the control circuit according to the current high-frequency clock signal.

[0013] Optionally, the clock control circuit includes a frequency divider and a clock pulse shaper connected in sequence; the frequency divider is connected to the frequency synthesizer, and the clock pulse shaper is connected to the control circuit.

[0014] The frequency divider is used to divide the current high-frequency clock signal according to the first clock parameter in the configuration data to obtain the frequency-divided current high-frequency clock signal.

[0015] The clock pulse shaper is used to suppress the current high-frequency clock signal after frequency division according to the second clock parameter in the configuration data, so as to obtain the clock signal corresponding to the mode switching command.

[0016] Optionally, the transmitting circuit includes a power amplifier and a transmitting control circuit connected in sequence; the transmitting control circuit is also connected to the control circuit.

[0017] The transmission control circuit is used to convert the communication signal into a high-frequency signal according to the first high-frequency clock signal and generate an adjustment signal according to the configuration data when the communication chip is in the transmission mode.

[0018] The power amplifier is used to adjust the high-frequency signal according to the adjustment signal.

[0019] Optionally, the adjustment signal includes an amplitude adjustment signal and a waveform adjustment signal;

[0020] The transmission control circuit includes a power amplifier driver, a power controller, a buck circuit, a pulse shaper, and an LDO circuit; the buck circuit is connected to the power controller and the LDO circuit, and the LDO circuit is also connected to the pulse shaper.

[0021] The power amplifier driver and the LDO circuit are respectively connected to the power amplifier;

[0022] The power amplifier driver is used to convert the communication signal into a high-frequency signal according to the first high-frequency clock signal;

[0023] The power controller is used to adjust the input reference voltage of the buck circuit according to the first input signal in the configuration data to obtain the amplitude adjustment signal;

[0024] The pulse shaper is used to adjust the rise time of the input reference level of the LDO circuit according to the second input signal in the configuration data to obtain the waveform adjustment signal.

[0025] Optionally, the power amplifier driver is specifically configured to output the first high-frequency clock signal when the communication signal is bit 1, and not output a signal when the communication signal is bit 0.

[0026] Optionally, the transmission control circuit is specifically configured to reduce the amplitude of the first input signal to reduce the power of the communication signal when the signal transmission rate of the transmission control circuit is greater than a first preset transmission rate; and to increase the amplitude of the first input signal to increase the power of the communication signal when the signal transmission rate of the transmission control circuit is less than a second preset transmission rate, wherein the first preset transmission rate is greater than the second preset transmission rate.

[0027] Optionally, the control circuit is specifically configured to switch the operating state of the communication chip to the transmission mode when the mode switching instruction corresponding to the current clock signal is the transmission mode switching instruction, control the power amplifier and the transmission control circuit to turn on, send the communication data to be transmitted to the transmission circuit in the form of a communication signal, generate a first interrupt signal after the transmission circuit has sent the communication signal, send the first interrupt signal to the external processor, control the power amplifier and the transmission control circuit to turn off, and convert the operating state of the communication chip to the waiting mode.

[0028] Optionally, the control circuit includes a timing control module, an interface driver module, a configuration circuit module, and a data cache module, wherein the interface driver module is connected to the timing control module, the configuration circuit module, and the data cache module, respectively.

[0029] The data cache module is also connected to the receiving circuit and the transmitting circuit respectively, and the interface driver module is also connected to the external processor through a specified interface;

[0030] The timing control module is used to detect the enable signal sent by the external processor, and based on the enable signal, switch the working state of the communication chip from sleep mode to wait mode; it is also used to switch the working state of the communication chip from wait mode to receive mode or transmit mode according to the clock signal generated by the clock circuit and the mode switching instruction corresponding to the clock signal.

[0031] The interface driver module is used to receive and parse the signal command through the designated interface when the communication chip is in a waiting mode, and generate the configuration data and the mode switching command.

[0032] The configuration circuit module is used to extract configuration parameters from the configuration data and send the configuration parameters to the receiving circuit, the clock circuit, and the transmitting circuit;

[0033] The data caching module is used to cache the processed external communication signals or the communication signals sent by the transmitting circuit.

[0034] Optionally, the timing control module is specifically used to switch the working state of the communication chip to a standby mode when the enable signal is high, and to keep the communication chip in a sleep mode when the enable signal is low.

[0035] Optionally, the receiving circuit includes a low-noise amplifier, a mixer, a cascaded filter amplifier module, a demodulator, a programmable low-pass filter, a limiter, and a data synchronization module connected in sequence; the data synchronization module is connected to the control circuit.

[0036] The low-noise amplifier is used to amplify the external communication signal when the communication chip is in receiving mode, so as to obtain an amplified external communication signal.

[0037] The mixer is used to receive the second high-frequency clock signal and, based on the second high-frequency clock signal, down-frequency the amplified external communication signal to obtain the down-frequency external communication signal.

[0038] The cascaded filtering and amplification module is used to filter and amplify the down-frequency external communication signal to obtain the filtered external communication signal.

[0039] The demodulator is used to analyze the filtered external communication signal to obtain the analyzed external communication signal.

[0040] The programmable low-pass filter is used to perform low-pass filtering on the parsed external communication signal to obtain a low-pass filtered external communication signal.

[0041] The limiter is used to convert the low-pass filtered external communication signal into a digital signal;

[0042] The data synchronization module is used to find the start position of the data frame from the digital signal, and based on the start position of the data frame, store the communication data in the processed external communication signal into the control circuit.

[0043] Optionally, the control circuit is specifically configured to switch the operating state of the communication chip to the receiving mode when the mode switching instruction corresponding to the current clock signal is the receiving mode switching instruction, control the receiving circuit to turn on, use the receiving circuit to receive the external communication signal, amplify, filter, demodulate and convert the external communication signal, generate a second interrupt signal after the external communication signal is received, store the communication data in the processed external communication signal in the control circuit, send the second interrupt signal to the external processor, control the receiving circuit to turn off, and switch the operating state of the communication chip to the waiting mode.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0045] This invention provides a low-power wireless sensor network communication chip architecture. By shutting down the clock circuit, transmitting circuit, and receiving circuit when the communication chip is in sleep mode, the power consumption of the communication chip is reduced. When the control circuit receives an enable signal, it switches the communication chip from sleep mode to standby mode. According to the mode switching instruction and the clock signal generated by the clock circuit, the working state of the communication chip is switched to transmitting mode or receiving mode. This allows for flexible switching between sleep, standby, transmitting, and receiving working modes of the communication chip. Furthermore, the control circuit can turn on the transmitting circuit or the receiving circuit when the communication chip is in different working modes, which can reduce the overall power consumption of the chip. Attached Figure Description

[0046] Figure 1 A block diagram of a low-power wireless sensor network communication chip architecture provided by the present invention;

[0047] Figure 2 A schematic diagram of a clock control circuit provided by the present invention;

[0048] Figure 3 A schematic diagram of a transmission control circuit provided by the present invention;

[0049] Figure 4 A flowchart of the working mode switching of a low-power wireless sensor network communication chip is provided for this invention;

[0050] Figure 5 A control flowchart of a low-power wireless sensor network communication chip in transmission mode provided by the present invention;

[0051] Figure 6 A control flowchart of a low-power wireless sensor network communication chip in receiving mode provided by the present invention;

[0052] Figure 7 This is a block diagram of a low-power wireless sensor network communication chip architecture provided by the present invention. Detailed Implementation

[0053] Example 1:

[0054] Figure 1 A block diagram of a low-power wireless sensor network communication chip architecture provided by the present invention is shown below. Figure 1As shown, the low-power wireless sensor network communication chip architecture may include: a receiving circuit 101, a clock circuit 102, a transmitting circuit 103, and a control circuit 104; the control circuit 104 is connected to the receiving circuit 101, the clock circuit 102, the transmitting circuit 103, and an external processor, respectively; the clock circuit 102 is also connected to the receiving circuit 101 and the transmitting circuit 103, respectively; the control circuit 104 is used to detect the enable signal sent by the external processor, and based on the enable signal, switch the working state of the communication chip from sleep mode to standby mode, receive and parse the signal commands sent by the external processor, and generate configuration data and mode switching parameters. The circuit 103 is configured to switch the operating state of the communication chip from the waiting mode to the receiving mode or the transmitting mode according to the clock signal generated by the clock circuit 102 and the mode switching instruction corresponding to the clock signal; the clock circuit 102 is configured to generate the clock signal and upload it to the control circuit 104 according to the configuration data transmitted by the control circuit 104 when the operating state is in the waiting mode; the receiving circuit 101 is configured to receive and process external communication signals when the communication chip is in the receiving mode; the transmitting circuit 103 is configured to transmit communication signals according to the configuration data transmitted by the control circuit 104 when the communication chip is in the transmitting mode.

[0055] The enable signal can be a voltage signal, a current signal, a level signal, or a digital signal.

[0056] It should be noted that when the control circuit does not detect an enable signal, the communication chip is in sleep mode, and the clock circuit, receiving circuit, and transmitting circuit are all off. Some modules in the control circuit are also off, such as the timing control module, configuration circuit module, and data buffer module, while the interface driver module is on to detect enable signals sent by the external processor, which helps reduce the power consumption of the communication chip. When the control circuit detects an enable signal, the communication chip switches from sleep mode to waiting mode. The modules in the control circuit that were off are turned on, and the clock circuit is turned on. The control circuit begins to receive and parse signal commands so that the receiving circuit can receive external communication signals or the transmitting circuit can send communication signals. In this invention, the receiving circuit and control circuit do not require analog-to-digital converters, and the transmitting circuit and control circuit do not require digital-to-analog converters. This invention proposes a low-power wireless sensor network communication chip architecture that eliminates the need for ADCs (Analogue-to-Digital Converters) and DACs (Digital-to-Analogue Converters), effectively simplifying the transmitter and receiver structures and reducing chip implementation area and power consumption. The communication chip includes operating modes such as sleep, wait, transmit, and receive, and proposes a corresponding workflow for each operating mode, which makes mode switching flexible. Furthermore, different functional modules can be shut down in different operating modes, which can reduce the overall power consumption of the chip.

[0057] Optionally, the clock circuit includes a frequency synthesizer and a clock control circuit connected in sequence; the frequency synthesizer is connected to the receiving circuit and the transmitting circuit respectively; the frequency synthesizer is used to generate a current high-frequency clock signal based on the current reference clock signal, and send the current high-frequency clock signal to the receiving circuit or the transmitting circuit, wherein the current high-frequency clock signal is a first high-frequency clock signal or a second high-frequency clock signal; the clock control circuit is used to provide the clock signal corresponding to the mode switching command to the timing control module of the control circuit based on the current high-frequency clock signal.

[0058] The clock control circuit includes a frequency divider and a clock pulse shaper connected in sequence. The frequency divider is connected to the frequency synthesizer, and the clock pulse shaper is connected to the control circuit. The frequency divider is used to divide the current high-frequency clock signal according to a first clock parameter in the configuration data to obtain a divided current high-frequency clock signal. The clock pulse shaper is used to suppress the divided current high-frequency clock signal according to a second clock parameter in the configuration data to obtain the clock signal corresponding to the mode switching command. The frequency divider adjusts the clock frequency and clock signal rise time based on the first clock parameter, and the clock pulse shaper adjusts the clock frequency based on the second clock parameter, thereby suppressing the harmonic components of the clock signal, reducing the impact of the clock on the communication signal, and improving the data transmission success rate.

[0059] It should be noted that the clock circuit provides the chip with a high-frequency carrier signal (i.e., the current high-frequency clock signal) and a clock signal, mainly including a frequency synthesizer and a clock control circuit. The frequency synthesizer receives an external reference clock signal REF_CLK, providing a high-frequency carrier signal for the transmit control circuit and the receive mixer. Simultaneously, the frequency synthesizer generates a high-frequency clock signal, which, after passing through the clock control circuit, provides a stable clock signal (i.e., the clock signal corresponding to the mode switching command) for the logic circuits in the control circuit and other components of the chip. The low-power wireless sensor network communication chip clock circuit proposed in this invention allows for adjustment of the clock frequency and clock signal rise time through parameter configuration, thereby suppressing harmonic components of the clock signal (i.e., the clock signal corresponding to the mode switching command), reducing the impact of the clock on the communication signal, and improving the data transmission success rate.

[0060] For example, a clock control circuit such as Figure 2 As shown, the circuit includes a frequency divider and a pulse shaper. The frequency divider divides the clock signal (i.e., the current high-frequency clock signal) CLK_PLL input to the clock control circuit. The division factor can be adjusted by the configuration parameter (i.e., the first clock parameter) DIV_SET, thereby adjusting the clock frequency. By configuring the pulse shaper parameter (i.e., the second clock parameter) PLS_SET, the rise time of the clock signal (i.e., the clock signal corresponding to the mode switching command) CLK_DIV can be increased, thereby suppressing harmonic components of the clock signal (i.e., the clock signal corresponding to the mode switching command), reducing the impact of the clock on the communication signal, and improving the data transmission success rate.

[0061] Optionally, the transmitting circuit includes a power amplifier and a transmitting control circuit connected in sequence; the transmitting control circuit is also connected to the control circuit; the transmitting control circuit is used to convert the communication signal into a high-frequency signal according to the first high-frequency clock signal when the communication chip is in transmitting mode, and to generate an adjustment signal according to the configuration data; the power amplifier is used to adjust the high-frequency signal according to the adjustment signal.

[0062] The adjustment signals include amplitude adjustment signals and waveform adjustment signals.

[0063] It should be noted that the low-power wireless sensor network communication chip transmitting circuit proposed in this invention can adjust the output signal amplitude and rise time through parameter configuration, adapting to different channel environments, suppressing out-of-band spectrum leakage of the output signal, effectively improving spectrum utilization, and reducing interference to signals in other frequency bands. The transmitting circuit processes the data from the MCU (Micro-controller Unit) and transmits it, including a PA (Power Amplifier) ​​and a transmitting control circuit. The PA amplifies the power of the signal to be transmitted, and the transmitting control circuit adjusts the amplitude and waveform of the transmitted signal.

[0064] Optionally, the transmission control circuit includes a power amplifier driver, a power controller, a buck circuit, a pulse shaper, and an LDO (Low Dropout Regulator) circuit; the buck circuit is connected to the power controller and the LDO circuit respectively, and the LDO circuit is also connected to the pulse shaper; the power amplifier driver and the LDO circuit are respectively connected to the power amplifier; the power amplifier driver is used to convert the communication signal into a high-frequency signal according to the first high-frequency clock signal; the power controller is used to adjust the input reference voltage of the buck circuit according to the first input signal in the configuration data to obtain the amplitude adjustment signal; the pulse shaper is used to adjust the rise time of the input reference level of the LDO circuit according to the second input signal in the configuration data to obtain the waveform adjustment signal.

[0065] Specifically, the power amplifier driver is used to output the first high-frequency clock signal when the communication signal is bit 1, and not output a signal when the communication signal is bit 0.

[0066] It should be noted that the transmission control circuit is specifically used to reduce the amplitude of the first input signal to reduce the power of the communication signal when the signal transmission rate of the transmission control circuit is greater than a first preset transmission rate; and to increase the amplitude of the first input signal to increase the power of the communication signal when the signal transmission rate of the transmission control circuit is less than a second preset transmission rate, wherein the first preset transmission rate is greater than the second preset transmission rate. Based on a first high-frequency clock signal, the transmission control circuit adjusts the amplitude and rise time of the output signal, adapting to different channel environments, suppressing out-of-band spectrum leakage of the output signal, effectively improving spectrum utilization, reducing interference to other frequency band signals, and eliminating the need for a digital-to-analog converter, thus simplifying the transmitting end and reducing chip implementation area and power consumption.

[0067] For example, the transmission control circuit structure is as follows: Figure 3 As shown, the circuit consists of a PA driver (power amplifier driver), a power controller, a BUCK circuit (step-down circuit), a pulse shaper, and an LDO circuit. The PA driver converts the data TX_D (communication signal) read from the data buffer (data buffer module) into a high-frequency signal TX_S: when TX_D is bit "0", the PA driver does not output a signal; when TX_D is bit "1", the PA driver outputs the signal TX_CLK, where TX_CLK is the high-frequency signal generated by the frequency synthesizer (i.e., the first high-frequency clock signal). The BUCK circuit provides power to the LDO circuit, which in turn provides power VDD_PA (adjustment signal) to the PA (power amplifier). By configuring the input signal (i.e., the first input signal) PWR_SET of the power controller, the input reference voltage of the BUCK circuit can be adjusted, thereby affecting the amplitude of the adjustment signal VDD_PA, and ultimately adjusting the power of the PA output signal. In environments with good wireless channels, the power of the PA output signal can be reduced by configuring PWR_SET to decrease transmission power consumption; conversely, in environments with poor wireless channels, the power of the PA output signal can be increased by configuring PWR_SET to improve data transmission success rate. By configuring the input signal (i.e., the second input signal) TRMP_SET of the pulse shaper, the rise time of the LDO circuit's input reference level can be adjusted, thereby affecting the rise time of the adjustment signal VDD_PA, and ultimately shaping the waveform of the PA output signal, i.e., adjusting the rise time of the PA output signal. Increasing the rise time of the PA output signal can suppress out-of-band spectral leakage, reduce interference to other frequency bands, and improve spectrum utilization.

[0068] Optionally, the control circuit is specifically configured to switch the operating state of the communication chip to the transmission mode when the mode switching instruction corresponding to the current clock signal is the transmission mode switching instruction, control the power amplifier and the transmission control circuit to turn on, send the communication data to be transmitted to the transmission circuit in the form of a communication signal, generate a first interrupt signal after the transmission circuit has sent the communication signal, send the first interrupt signal to the external processor, control the power amplifier and the transmission control circuit to turn off, and convert the operating state of the communication chip to the waiting mode.

[0069] It should be noted that the communication signal is continuously transmitted until it is completely transmitted.

[0070] For example, in wait mode, when the chip receives a mode switching instruction from an external processor, it switches from wait mode to transmit mode and begins transmitting data. The specific process is as follows: Figure 4 As shown:

[0071] Step 1: Switch from waiting mode to sending mode;

[0072] Step 2: Turn on the PA and transmit control circuit;

[0073] Step 3: Read data from the data buffer and send it to the transmitting circuit to start transmitting data;

[0074] Step 4: Wait for the data to be sent completely. If it is complete, proceed to Step 5; otherwise, proceed to Step 3 to continue sending data.

[0075] Step 5: Generate an interrupt signal (i.e., the first interrupt signal) to notify the external processor that the data transmission operation has been completed;

[0076] Step 6: Turn off the PA and transmit control circuit to reduce power consumption;

[0077] Step 7: Switch from send mode to wait mode;

[0078] Step 8: End a data transmission operation.

[0079] Optionally, the control circuit includes a timing control module, an interface driver module, a configuration circuit module, and a data cache module. The interface driver module is connected to the timing control module, the configuration circuit module, and the data cache module, respectively. The data cache module is also connected to the receiving circuit and the transmitting circuit, respectively. The interface driver module is also connected to the external processor through a designated interface. The timing control module is used to detect the enable signal sent by the external processor and, based on the enable signal, switch the working state of the communication chip from sleep mode to wait mode. It is also used to switch the working state of the communication chip from wait mode to receive mode or transmit mode according to the clock signal generated by the clock circuit and the mode switching instruction corresponding to the clock signal. The interface driver module is used to receive and parse the signal instruction through the designated interface when the communication chip is in wait mode, and generate the configuration data and the mode switching instruction. The configuration circuit module is used to extract configuration parameters from the configuration data and send the configuration parameters to the receiving circuit, the clock circuit, and the transmitting circuit. The data cache module is used to cache the processed external communication signal or the communication signal sent by the transmitting circuit.

[0080] Specifically, the timing control module is used to switch the working state of the communication chip to a standby mode when the enable signal is high, and to keep the communication chip in a sleep mode when the enable signal is low.

[0081] It should be noted that the control circuit is responsible for the entire chip's logic control, parameter configuration, data forwarding, and external interaction, including four sub-modules: interface driver, configuration circuit, data buffer, and timing control. The chip can use different interface methods to achieve external data interaction, including but not limited to SPI, UART, and I2C. 2 C, etc. Following the specified interface method, the interface driver parses the signal instructions from the external processor. The configuration circuit extracts configuration parameters from the parsed data and configures the parameters of the corresponding sub-modules within the chip. The data buffer buffers the data bits to be sent and received. The entire chip includes four operating states: sleep, wait, send, and receive. The timing control module controls the chip to switch between these operating modes and enables / disables specific sub-modules in different operating states.

[0082] For example, to reduce overall power consumption, the chip is in sleep mode during idle periods and shuts down most submodules. In sleep mode, if the chip receives a signal from an external processor, it exits sleep mode, and its workflow is as follows: Figure 5 As shown, the specific steps are as follows:

[0083] Step 1: Detect the NSS signal pin. If it is low, maintain sleep mode; if it is high, proceed to Step 2.

[0084] Step 2: Switch the working status from sleep mode to wait mode;

[0085] Step 3: Turn on the frequency synthesizer and clock control circuit;

[0086] Step 4: Enable the interface driver module;

[0087] Step 5: Activate the configuration circuit module;

[0088] Step Six: End.

[0089] Optionally, the receiving circuit includes a low-noise amplifier, a mixer, a cascaded filter amplification module, a demodulator, a programmable low-pass filter, a limiter, and a data synchronization module connected in sequence; the data synchronization module is connected to the control circuit; the low-noise amplifier is used to amplify the external communication signal when the communication chip is in receiving mode to obtain an amplified external communication signal; the mixer is used to receive the second high-frequency clock signal and, according to the second high-frequency clock signal, down-convert the amplified external communication signal to obtain a down-converted external communication signal; the cascaded filter amplification module is used to... The external communication signal is filtered and amplified to obtain a filtered external communication signal; the demodulator is used to analyze the filtered external communication signal to obtain an analyzed external communication signal; the programmable low-pass filter is used to perform low-pass filtering on the analyzed external communication signal to obtain a low-pass filtered external communication signal; the limiter is used to convert the low-pass filtered external communication signal into a digital signal; the data synchronization module is used to find the start position of the data frame from the digital signal, and based on the start position of the data frame, store the communication data in the processed external communication signal into the control circuit.

[0090] It should be noted that the receiving circuit performs functions such as wireless signal acquisition, amplification, filtering, and demodulation, including modules such as a low-noise amplifier, mixer, cascaded filter amplifier, demodulator, programmable low-pass filter, limiter, and data synchronization. Specifically, the low-noise amplifier amplifies the signal in the wireless channel; the mixer down-converts the amplified high-frequency signal to a low-frequency signal; the cascaded filter amplifier filters the down-converted signal, removing any mirrored signals, and further amplifies the filtered signal; then, demodulation is performed to extract the useful signal from the low-frequency signal, and further low-pass filtering is applied by the programmable low-pass filter; the limiter converts the filtered analog signal into a data signal, and the data synchronization module locates the start position of the data frame and stores the valid data in the data buffer.

[0091] Optionally, the control circuit is specifically configured to switch the operating state of the communication chip to the receiving mode when the mode switching instruction corresponding to the current clock signal is the receiving mode switching instruction, control the receiving circuit to turn on, use the receiving circuit to receive the external communication signal, amplify, filter, demodulate and convert the external communication signal, generate a second interrupt signal after the external communication signal is received, store the communication data in the processed external communication signal in the control circuit, send the second interrupt signal to the external processor, control the receiving circuit to turn off, and switch the operating state of the communication chip to the waiting mode.

[0092] It should be noted that, while the external communication signal has not been fully received, the reception of the external communication signal continues until the reception of the external communication signal is completed.

[0093] For example, in wait mode, when the chip receives a mode switching instruction from an external processor, it switches from wait mode to receive mode and begins receiving data. The specific process is as follows: Figure 6 As shown:

[0094] Step 1: Switch from wait mode to receive mode;

[0095] Step 2: Turn on the receiving circuits such as the low-noise amplifier and mixer;

[0096] Step 3: Collect data from the wireless channel and send it to the receiving circuit for processing;

[0097] Step 4: Determine if the data is synchronized. If synchronized, proceed to Step 5; otherwise, proceed to Step 3 to continue receiving signals.

[0098] Step 5: Store the valid data in the data cache;

[0099] Step 6: Generate an interrupt signal (i.e., the second interrupt signal) to notify the external processor that the data reception operation has been completed and the received data can be read from the data buffer;

[0100] Step 7: Turn off the low-noise amplifier, mixer, and other receiving circuits to reduce power consumption;

[0101] Step 8: Switch from receive mode to wait mode;

[0102] Step 9: End the data receiving operation.

[0103] This invention proposes a low-power wireless sensor network communication chip architecture, such as... Figure 7As shown, the chip comprises four main circuits: a control circuit, a transmitting circuit, a receiving circuit, and a clock circuit. The control circuit is responsible for the chip's logic control, parameter configuration, data forwarding, and external interaction. The transmitting circuit processes and transmits data from the MCU. The receiving circuit performs wireless signal acquisition, amplification, filtering, and demodulation. The clock circuit provides the chip with a high-frequency carrier signal and a clock signal. The low-power wireless sensor network communication chip's sleep mode exit process ensures the chip remains in sleep mode during idle periods and can exit sleep mode normally, reducing overall chip power consumption. The transmitting control circuit consists of a PA driver, power controller, BUCK circuit, pulse shaper, and LDO circuit. Its signal transmission process effectively reduces overall chip power consumption while ensuring normal data transmission. The receiving circuit includes modules such as a low-noise amplifier, mixer, cascaded filter amplification, demodulator, programmable low-pass filter, limiter, and data synchronization module. Its signal receiving process effectively reduces overall chip power consumption while ensuring normal data reception. The clock control circuit includes a frequency divider and a pulse shaper.

[0104] For example, still using Figure 7 For example, the clock circuit receives the reference clock signal REF_CLK from the frequency synthesizer, generates a high-frequency carrier signal, and sends the high-frequency carrier signal to the mixer of the receiving circuit or the transmit control circuit of the transmitting circuit. The clock control circuit generates a clock signal based on the high-frequency carrier signal and uploads the clock signal to the control circuit. In receive mode, the receiving circuit receives the external communication signal RX_SIG and processes the external communication signal RX_SIG based on the high-frequency carrier signal to obtain the processed external communication signal. The control circuit stores the processed external communication signal through a data buffer. In transmit mode, the transmitting circuit generates and transmits the communication signal TX_SIG based on the high-frequency carrier signal. The control circuit uses timing control to receive the enable signal NSS and / or enable signal INT to switch the communication chip from sleep mode to wait mode. In wait mode, the control circuit controls the receiving circuit to receive the external communication signal RX_SIG or controls the transmitting circuit to transmit the communication signal TX_SIG. The control circuit receives SPI and I signals through the interface driver. 2 Interaction data using protocols such as C.

[0105] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of the claims of the present invention pending approval.

Claims

1. A low-power wireless sensor network communication chip architecture, characterized in that, The communication chip architecture includes: a receiving circuit, a clock circuit, a transmitting circuit, and a control circuit; the control circuit is connected to the receiving circuit, the clock circuit, the transmitting circuit, and an external processor, respectively; the clock circuit is also connected to the receiving circuit and the transmitting circuit, respectively. The control circuit is used to detect the power-on signal sent by the external processor, and based on the power-on signal, switch the working state of the communication chip from sleep mode to wait mode, receive and parse the signal instructions sent by the external processor, and generate configuration data and mode switching instructions; it is also used to switch the working state of the communication chip from the wait mode to receive mode or transmit mode according to the clock signal generated by the clock circuit and the mode switching instructions corresponding to the clock signal. The clock circuit is used to generate the clock signal and upload it to the control circuit according to the configuration data transmitted by the control circuit when the working state is in waiting mode. The receiving circuit is used to receive and process external communication signals when the communication chip is in receiving mode; The transmitting circuit is used to transmit communication signals according to the configuration data transmitted by the control circuit when the communication chip is in transmitting mode.

2. The communication chip architecture according to claim 1, characterized in that, The clock circuit includes a frequency synthesizer and a clock control circuit connected in sequence; the frequency synthesizer is connected to the receiving circuit and the transmitting circuit respectively. The frequency synthesizer is used to generate a current high-frequency clock signal based on the current reference clock signal, and to send the current high-frequency clock signal to the receiving circuit or the transmitting circuit. The current high-frequency clock signal is either a first high-frequency clock signal or a second high-frequency clock signal. The clock control circuit is used to provide the clock signal corresponding to the mode switching command to the timing control module of the control circuit according to the current high-frequency clock signal.

3. The communication chip architecture according to claim 2, characterized in that, The clock control circuit includes a frequency divider and a clock pulse shaper connected in sequence; the frequency divider is connected to the frequency synthesizer, and the clock pulse shaper is connected to the control circuit. The frequency divider is used to divide the current high-frequency clock signal according to the first clock parameter in the configuration data to obtain the frequency-divided current high-frequency clock signal. The clock pulse shaper is used to suppress the current high-frequency clock signal after frequency division according to the second clock parameter in the configuration data, so as to obtain the clock signal corresponding to the mode switching command.

4. The communication chip architecture according to claim 2, characterized in that, The transmitting circuit includes a power amplifier and a transmitting control circuit connected in sequence; the transmitting control circuit is also connected to the control circuit. The transmission control circuit is used to convert the communication signal into a high-frequency signal according to the first high-frequency clock signal and generate an adjustment signal according to the configuration data when the communication chip is in the transmission mode. The power amplifier is used to adjust the high-frequency signal according to the adjustment signal.

5. The communication chip architecture according to claim 4, characterized in that, The adjustment signals include amplitude adjustment signals and waveform adjustment signals; The transmission control circuit includes a power amplifier driver, a power controller, a buck circuit, a pulse shaper, and an LDO circuit; the buck circuit is connected to the power controller and the LDO circuit, and the LDO circuit is also connected to the pulse shaper. The power amplifier driver and the LDO circuit are respectively connected to the power amplifier; The power amplifier driver is used to convert the communication signal into a high-frequency signal according to the first high-frequency clock signal; The power controller is used to adjust the input reference voltage of the buck circuit according to the first input signal in the configuration data to obtain the amplitude adjustment signal; The pulse shaper is used to adjust the rise time of the input reference level of the LDO circuit according to the second input signal in the configuration data to obtain the waveform adjustment signal.

6. The communication chip architecture according to claim 5, characterized in that, The power amplifier driver is specifically used to output the first high-frequency clock signal when the communication signal is bit 1, and not output a signal when the communication signal is bit 0.

7. The communication chip architecture according to claim 5, characterized in that, The transmission control circuit is specifically configured to reduce the amplitude of the first input signal to reduce the power of the communication signal when the signal transmission rate of the transmission control circuit is greater than a first preset transmission rate; and to increase the amplitude of the first input signal to increase the power of the communication signal when the signal transmission rate of the transmission control circuit is less than a second preset transmission rate, wherein the first preset transmission rate is greater than the second preset transmission rate.

8. The communication chip architecture according to claim 4, characterized in that, The control circuit is specifically used to switch the working state of the communication chip to the transmission mode when the mode switching instruction corresponding to the current clock signal is the transmission mode switching instruction, control the power amplifier and the transmission control circuit to turn on, send the communication data to be transmitted to the transmission circuit in the form of a communication signal, and after the transmission circuit has completed sending the communication signal, generate a first interrupt signal, send the first interrupt signal to the external processor, control the power amplifier and the transmission control circuit to turn off, and switch the working state of the communication chip to the waiting mode.

9. The communication chip architecture according to claim 2, characterized in that, The control circuit includes a timing control module, an interface driver module, a configuration circuit module, and a data cache module. The interface driver module is connected to the timing control module, the configuration circuit module, and the data cache module, respectively. The data cache module is also connected to the receiving circuit and the transmitting circuit respectively, and the interface driver module is also connected to the external processor through a specified interface; The timing control module is used to detect the enable signal sent by the external processor, and based on the enable signal, switch the working state of the communication chip from sleep mode to wait mode; it is also used to switch the working state of the communication chip from wait mode to receive mode or transmit mode according to the clock signal generated by the clock circuit and the mode switching instruction corresponding to the clock signal. The interface driver module is used to receive and parse the signal command through the designated interface when the communication chip is in a waiting mode, and generate the configuration data and the mode switching command. The configuration circuit module is used to extract configuration parameters from the configuration data and send the configuration parameters to the receiving circuit, the clock circuit, and the transmitting circuit; The data caching module is used to cache the processed external communication signals or the communication signals sent by the transmitting circuit.

10. The communication chip architecture according to claim 9, characterized in that, The timing control module is specifically used to switch the working state of the communication chip to standby mode when the enable signal is high, and to keep the communication chip in sleep mode when the enable signal is low.

11. The communication chip architecture according to any one of claims 2-10, characterized in that, The receiving circuit includes a low-noise amplifier, a mixer, a cascaded filter amplifier module, a demodulator, a programmable low-pass filter, a limiter, and a data synchronization module connected in sequence; the data synchronization module is connected to the control circuit. The low-noise amplifier is used to amplify the external communication signal when the communication chip is in receiving mode, so as to obtain an amplified external communication signal. The mixer is used to receive the second high-frequency clock signal and, based on the second high-frequency clock signal, down-frequency the amplified external communication signal to obtain the down-frequency external communication signal. The cascaded filtering and amplification module is used to filter and amplify the down-frequency external communication signal to obtain the filtered external communication signal. The demodulator is used to analyze the filtered external communication signal to obtain the analyzed external communication signal. The programmable low-pass filter is used to perform low-pass filtering on the parsed external communication signal to obtain a low-pass filtered external communication signal. The limiter is used to convert the low-pass filtered external communication signal into a digital signal; The data synchronization module is used to find the start position of the data frame from the digital signal, and based on the start position of the data frame, store the communication data in the processed external communication signal into the control circuit.

12. The communication chip architecture according to claim 11, characterized in that, Specifically, when the mode switching instruction corresponding to the current clock signal is a receive mode switching instruction, the control circuit switches the working state of the communication chip to receive mode, controls the receiving circuit to turn on, uses the receiving circuit to receive the external communication signal, amplifies, filters, demodulates and converts the external communication signal, generates a second interrupt signal after the external communication signal is received, stores the communication data in the processed external communication signal in the control circuit, sends the second interrupt signal to the external processor, controls the receiving circuit to turn off, and switches the working state of the communication chip to standby mode.

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