Semiconductor device

Abstract

A semiconductor device having improved integration density and electrical characteristics is provided. The semiconductor device includes a first peripheral gate structure on a substrate; an active pattern spaced apart from the substrate in the first direction and including a first surface and a second surface opposite to each other in the first direction; a peripheral active pattern spaced apart from the substrate in the first direction and including a first surface and a second surface opposite to each other in the first direction; a second peripheral gate structure on the first surface of the peripheral active pattern; a bit line electrically connected to a first surface of the active pattern and extending in a second direction intersecting the first direction; and a data storage pattern electrically connected to the second surface of the active pattern.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0063085, filed on May 14, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including a vertical channel transistor (VCT). Background Technology

[0003] Increasing the integration density of semiconductor memory devices helps meet consumer demands for superior performance and lower prices. In the case of semiconductor memory devices, increasing integration density is particularly beneficial because it is a crucial factor in determining product price.

[0004] For two-dimensional or planar semiconductor memory devices, the integration density is primarily determined by the area occupied by a single memory cell, and therefore is largely influenced by the level of fine patterning technology. However, due to the need for expensive devices to miniaturize the patterns, the integration density of two-dimensional semiconductor memory devices, while continuously increasing, remains limited. Accordingly, semiconductor memory devices, including vertical channel transistors whose channels extend in the vertical direction, have been proposed. Summary of the Invention

[0005] This disclosure provides a semiconductor device with improved integration density and electrical characteristics.

[0006] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0007] According to some aspects of this disclosure, a semiconductor device is provided, comprising: an active pattern including a first surface and a second surface opposite to each other in a first direction; a peripheral active pattern including the first surface and the second surface opposite to each other in the first direction, wherein the peripheral active pattern is spaced apart from the active pattern in a second direction intersecting the first direction; a bit line electrically connected to the first surface of the active pattern and extending in the second direction; a data storage pattern electrically connected to the second surface of the active pattern; and a first peripheral gate structure on the first surface of the peripheral active pattern.

[0008] According to some aspects of this disclosure, a semiconductor device is provided, comprising: a first peripheral gate structure on a substrate; an active pattern spaced apart from the substrate in a first direction and including a first surface and a second surface opposite to each other in the first direction; a peripheral active pattern spaced apart from the substrate in a first direction and including a first surface and a second surface opposite to each other in the first direction; a second peripheral gate structure on the first surface of the peripheral active pattern; a bit line electrically connected to the first surface of the active pattern and extending in a second direction intersecting the first direction; and a data storage pattern electrically connected to the second surface of the active pattern.

[0009] According to some aspects of this disclosure, a semiconductor device is provided, comprising: an active pattern spaced apart from a substrate in a first direction and including a first surface and a second surface opposite to each other in the first direction; a peripheral active pattern spaced apart from the substrate in a first direction and including a first surface and a second surface opposite to each other in the first direction; a bit line electrically connected to the first surface of the active pattern, extending in a second direction intersecting the first direction, and including a conductive bit line comprising a conductive material; a data storage pattern electrically connected to the second surface of the active pattern; a peripheral gate structure on the first surface of the peripheral active pattern and including a peripheral gate electrode, wherein the thickness of the peripheral gate electrode is equal to the thickness of the conductive bit line; a peripheral field insulating film contacting a sidewall of the peripheral active pattern, wherein the sidewall of the peripheral active pattern connects the first surface of the peripheral active pattern to the second surface of the peripheral active pattern; a peripheral contact plug electrically connected to the peripheral gate structure; a peripheral field through plug extending into the peripheral field insulating film; a peripheral wiring line on the first surface of the peripheral active pattern and electrically connected to the peripheral contact plug and the peripheral field through plug; and a peripheral connection structure on a substrate and electrically connected to the peripheral wiring line. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0011] Figure 1 It is a layout diagram of a semiconductor device according to some embodiments.

[0012] Figure 2 yes Figure 1 The layout diagram of the boundary between the cell array region and the peripheral circuit region of a semiconductor device.

[0013] Figure 3 It is along Figure 2 The cross-sectional view taken from line AA.

[0014] Figure 4 It is along Figure 2The cross-sectional view taken from lines BB and CC.

[0015] Figure 5 yes Figure 3 A magnified view of part P.

[0016] Figure 6 yes Figure 3 A magnified view of part of Q.

[0017] Figure 7 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0018] Figures 8 to 10 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0019] Figure 11 and Figure 12 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0020] Figure 13 and Figure 14 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0021] Figures 15 to 18 These are diagrams used to illustrate semiconductor devices according to some embodiments.

[0022] Figures 19 to 26 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments.

[0023] Figures 27 to 30 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments.

[0024] Figures 31 to 34 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0025] Figure 1 It is a layout diagram of a semiconductor device according to some embodiments. Figure 2 yes Figure 1 The layout diagram of the boundary between the cell array region and the peripheral circuit region of a semiconductor device. Figure 3 It is along Figure 2 The cross-sectional view taken from line AA. Figure 4 It is along Figure 2 The cross-sectional view taken from lines BB and CC. Figure 5 yes Figure 3 A magnified view of part P. Figure 6 yes Figure 3 A magnified view of part of Q.

[0026] Semiconductor devices according to exemplary embodiments of this disclosure may include memory cells having vertical channel transistors (VCTs).

[0027] refer to Figures 1 to 6 According to some embodiments, a semiconductor device may include a first peripheral gate structure PG1, a second peripheral gate structure PG2, a peripheral active pattern P_ACT, a bit line BL, word lines WL1 and WL2, a back gate electrode BG, a shielded conductive pattern SL, active patterns AP1 and AP2, and a data storage pattern DSP.

[0028] The first substrate 100 may be a silicon substrate, or may include other materials, such as, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0029] The first substrate 100 may include a cell array region (CAR) in which a data storage pattern (DSP) is disposed, and a peripheral circuit region (PCR) defined around the cell array region (CAR). A peripheral field insulating film (STI) may be disposed on the peripheral circuit region (PCR) of the first substrate 100. From a planar view perspective, the peripheral field insulating film (STI) may define the cell array region (CAR) of the first substrate 100.

[0030] The peripheral active pattern P_ACT can be disposed on the peripheral circuit region PCR of the first substrate 100. The peripheral active pattern P_ACT can be spaced apart from the first substrate 100 on the third-direction DR3. The peripheral active pattern P_ACT may not be in contact with the first substrate 100.

[0031] From a planar perspective, the peripheral active pattern P_ACT can be positioned around the cell array region CAR. The peripheral active pattern P_ACT can be positioned spaced apart from the cell array region CAR in either the first direction DR1 or the second direction DR2. The peripheral active pattern P_ACT can be spaced apart from the first active pattern AP1 and the second active pattern AP2 positioned within the cell array region CAR in either the first direction DR1 or the second direction DR2. The peripheral active pattern P_ACT does not overlap with the first active pattern AP1 and the second active pattern AP2 in the third direction DR3. As used herein, "element A overlaps with element B in the X direction" (or similar language) means that there exists at least one straight line extending along the X direction that intersects both element A and element B.

[0032] For example, a peripheral field insulating film (STI) can be disposed around a peripheral active pattern P_ACT. From a plan view perspective, the STI can be on the outer edge of the peripheral active pattern P_ACT (e.g., it can cover the outer edge of the peripheral active pattern P_ACT). The peripheral active pattern P_ACT can include a first surface P_S1 and a second surface P_S2 opposite to each other on a third-direction DR3. The peripheral active pattern P_ACT can include a sidewall P_SS connecting the first surface P_S1 and the second surface P_S2 of the peripheral active pattern. The STI can be on the sidewall P_SS of the peripheral active pattern (e.g., it can cover the sidewall P_SS of the peripheral active pattern). For example, the STI can be in contact with the sidewall P_SS of the peripheral active pattern.

[0033] A first peripheral gate structure PG1 may be disposed on the first substrate 100. For example, the first peripheral gate structure PG1 may be disposed on the upper surface of the first substrate 100. The first peripheral gate structure PG1 may be disposed on the cell array region CAR and the peripheral circuit region PCR. In other words, a portion of the first peripheral gate structure PG1 may be disposed in the cell array region CAR of the first substrate 100, and the remaining portion of the first peripheral gate structure PG1 may be disposed in the peripheral circuit region PCR of the first substrate 100.

[0034] The first peripheral gate structure PG1 may be included in a sensing transistor, a transmission transistor, a driving transistor, etc. It goes without saying that the types of transistors in the peripheral circuits located in the cell array region CAR and the peripheral circuit region PCR can vary depending on the design and layout of the semiconductor device.

[0035] The first peripheral gate structure PG1 may include a first peripheral gate insulating film 215, a first peripheral lower conductive pattern 223, and a first peripheral upper conductive pattern 225. The first peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high dielectric constant insulating film may include, for example, but not limited to, at least one of metal oxide, metal oxynitride, metal silicon oxide, or metal silicon oxynitride.

[0036] The first peripheral lower conductive pattern 223 and the first peripheral upper conductive pattern 225 may each include a conductive material. The first peripheral gate structure PG1 may include a first peripheral gate electrode containing a conductive material. The first peripheral gate electrode may include the first peripheral lower conductive pattern 223 and the first peripheral upper conductive pattern 225. For example, the first peripheral lower conductive pattern 223 and the first peripheral upper conductive pattern 225 may each include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, or a metal. In the semiconductor device according to some embodiments, the two-dimensional material may be a metallic material and / or a semiconductor material. The two-dimensional material may include 2D allotropes or 2D compounds, and may include, but is not limited to, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), or tungsten disulfide (WS2). That is, since the above two-dimensional materials are listed only as examples, the two-dimensional materials that may be included in the semiconductor device of this disclosure are not limited to the above materials. Although the first peripheral gate structure PG1 is shown as including multiple conductive patterns, this disclosure is not limited thereto.

[0037] Although not shown, peripheral gate spacers may be provided on the sidewalls of the first peripheral gate structure PG1. The peripheral gate spacers comprise an insulating material. Additionally, the first peripheral gate structure PG1 may also include a first peripheral gate mask pattern disposed on a conductive pattern 225 on the first periphery. The first peripheral gate mask pattern is made of an insulating material.

[0038] A first peripheral interlayer insulating film 265 is disposed on the first substrate 100. The first peripheral interlayer insulating film 265 includes an insulating material.

[0039] The first peripheral contact plug 241a and the first peripheral wiring line 241b can be disposed in the first peripheral interlayer insulating film 265. The first peripheral contact plug 241a can be connected to a first source / drain region disposed on at least one side of the first peripheral gate structure PG1. For example, the first source / drain region can be, but is not limited to, a region in the first substrate 100 doped with impurities. Although not shown, the first peripheral contact plug 241a can be connected to the first peripheral gate electrodes 223 and 225 of the first peripheral gate structure PG1. The first peripheral wiring line 241b can be disposed on the first peripheral contact plug 241a. The first peripheral wiring line 241b is connected to the first peripheral contact plug 241a. For example, the first peripheral wiring line 241b can be the wiring line on the third-direction DR3 closest to the first peripheral gate structure PG1.

[0040] Although the first peripheral contact plug 241a and the first peripheral wiring line 241b are shown as different films, this disclosure is not limited thereto. In some embodiments, the boundary between the first peripheral contact plug 241a and the first peripheral wiring line 241b may not be distinguished. The first peripheral contact plug 241a and the first peripheral wiring line 241b each comprise a conductive material.

[0041] The first peripheral connection structure 260 can be disposed on the first peripheral wiring line 241b. The first peripheral connection structure 260 can be connected to the first peripheral wiring line 241b. The first peripheral connection structure 260 can be disposed in the first peripheral interlayer insulating film 265.

[0042] The first peripheral connection structure 260 may include first peripheral connection wirings 261b and 262b and first peripheral connection vias 261a and 262a. Although the first peripheral connection structure 260 is shown as including a plurality of first peripheral connection wirings 261b and 262b disposed on different metal layers, this is only for illustrative purposes and the present disclosure is not limited thereto.

[0043] The first peripheral connection wirings 261b and 262b and the first peripheral connection vias 261a and 262a may each include a conductive material. Although the first peripheral connection wirings 261b and 262b and the first peripheral connection vias 261a and 262a are shown as different films, this disclosure is not limited thereto.

[0044] The first bonding pad BP1 can be disposed on the first peripheral gate structure PG1. The first peripheral connection structure 260 can be disposed between the first peripheral gate structure PG1 and the first bonding pad BP1. The first bonding pad BP1 can be connected to the first peripheral connection structure 260.

[0045] The first bonding pad plug 263 can be disposed between the first bonding pad BP1 and the first peripheral connection structure 260. The first bonding pad plug 263 can connect the first bonding pad BP1 and the first peripheral connection structure 260.

[0046] The first bonding pad BP1 and the first bonding pad plug 263 may be disposed within the first peripheral interlayer insulating film 265. The first bonding pad plug 263 and the first bonding pad BP1 may each comprise a conductive material containing metal. Although the first bonding pad BP1 is shown as a single-layer film, this is for illustrative purposes only, and the present disclosure is not limited thereto.

[0047] Shielding structures 171, SL, and 175 may be disposed on the first substrate 100. For example, shielding structures 171, SL, and 175 may be disposed on the first bonding pad BP1. Shielding structures 171, SL, and 175 may be spaced apart from the first bonding pad BP1 on a third-direction DR3.

[0048] The shielding structures 171, SL, and 175 may include a shielding conductive pattern SL and shielding insulating films 171 and 175. For example, shielding insulating films 171 and 175 may include a shielding insulating pad 171 and a shielding insulating capping film 175.

[0049] In a semiconductor device according to some embodiments, the shielding conductive pattern SL may include a plurality of shielding conductive line patterns having a linear shape (see [reference]). Figure 9 Each shielding conductive pattern SL can extend in the second direction DR2. The shielding conductive patterns SL can be adjacent to each other in the first direction DR1. For example, each of the first direction DR1 and the second direction DR2 can be a horizontal direction that is horizontal (i.e., parallel) to the upper surface of the first substrate 100. The first direction DR1 and the second direction DR2 can intersect each other.

[0050] Each shielded conductive pattern SL can extend from the cell array region CAR to the peripheral circuit region PCR. The end of each shielded conductive pattern SL can be positioned on the peripheral circuit region PCR.

[0051] The shielding conductive pattern SL includes a conductive material. The shielding conductive pattern SL may include at least one of, for example, conductive metal nitrides, conductive metal silicon nitrides, metal carbonitrides, conductive metal silicides, conductive metal oxides, two-dimensional materials, or metals.

[0052] A shielding insulating capping film 175 may be disposed on the first bonding pad BP1. The shielding insulating capping film 175 may be disposed between the first bonding pad BP1 and the shielding conductive pattern SL. For example, the shielding insulating capping film 175 may be in contact with the shielding conductive pattern SL.

[0053] The shielding insulating capping film 175 may have a linear shape extending along the shielding conductive pattern SL in the second direction DR2. Unlike the example shown, the shielding insulating capping film 175 may have a flat shape. In other words, the shielding insulating capping film 175 may overlap with the bit line BL in the third direction DR3. For example, the third direction DR3 may be a vertical direction perpendicular to the upper surface of the first substrate 100. The third direction DR3 may intersect with the first direction DR1 and the second direction DR2.

[0054] The shielding insulating pad 171 can be disposed on the shielding conductive pattern SL. The shielding insulating pad 171 can extend along the outline of the shielding conductive pattern SL.

[0055] The shielding insulating pad 171 can be disposed between the bit line BL and the first bonding pad BP1. Unlike the example shown, from the perspective of the cross-sectional view, the shielding insulating pads 171 that are adjacent to each other on the first direction DR1 and formed along the contour of the shielding conductive pattern SL can be connected to each other.

[0056] The shielding insulating pad 171 and the shielding insulating cover film 175 can each be made of insulating material. When the shielding insulating pad 171 and the shielding insulating cover film 175 are made of the same material, the boundary between the shielding insulating pad 171 and the shielding insulating cover film 175 does not need to be distinguished.

[0057] Since shielding structures 171, SL and 175 are disposed between adjacent bit lines BL along the first direction DR1, coupling noise between bit lines BL can be reduced.

[0058] Bit line BL can be disposed on the first substrate 100. For example, bit line BL can be disposed on the first bonding pad BP1.

[0059] Bit lines BL can extend longitudinally in the second direction DR2. Adjacent bit lines BL can be spaced apart from each other in the first direction DR1. Bit lines BL include long sidewalls extending along the second direction DR2 and short sidewalls extending along the first direction DR1.

[0060] Bit line BL can be configured to be adjacent to the shielding conductive pattern SL. Bit line BL can be configured to be adjacent to the shielding conductive pattern SL in a first direction DR1. In other words, the shielding conductive pattern SL can extend along the long sidewall of bit line BL in a second direction DR2.

[0061] Bit lines BL can be disposed between adjacent shielding conductive patterns SL along the first direction DR1. Bit lines BL can be disposed on shielding insulating pads 171. For example, shielding insulating pads 171 can be in contact with bit lines BL.

[0062] Each bit line BL can extend from the cell array region CAR to the peripheral circuit region PCR. The end of each bit line BL can be positioned on the peripheral circuit region PCR.

[0063] Bit line BL may include an upper surface BL_US and a bottom surface opposite each other on a third-direction DR3. The upper surface BL_US of the bit line may face (i.e., confront) the first active pattern AP1 and the second active pattern AP2, which will be described later. In a semiconductor device according to some embodiments, the shielding conductive pattern SL may not be disposed on the bottom surface of the bit line BL.

[0064] Each bit line BL may include a semiconductor pattern 161, a metal pattern 163, and a bit line mask pattern 165 stacked in sequence. Unlike the example shown, by way of example, the bit line BL may include either the semiconductor pattern 161 or the metal pattern 163. By way of another example, the bit line BL may not include the bit line mask pattern 165.

[0065] Bit line BL may include conductive bit lines comprising conductive material. The conductive bit line includes a film made of conductive material within the bit line BL. The conductive bit line may include a semiconductor pattern 161 and a metal pattern 163.

[0066] Semiconductor pattern 161 may include a conductive semiconductor material. The conductive semiconductor material may be, for example, a semiconductor material doped with impurities. Semiconductor pattern 161 may include at least one of polycrystalline silicon, polycrystalline silicon germanium, polycrystalline germanium, amorphous silicon, amorphous silicon germanium, or amorphous germanium.

[0067] The metal pattern 163 may include a conductive material comprising a metal. The metal pattern 163 may include at least one of, for example, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, or a metal.

[0068] Bit line mask pattern 165 may include insulating material. Bit line mask pattern 165 may include, but is not limited to, silicon nitride, silicon oxynitride, etc.

[0069] The second peripheral gate structure PG2 can be disposed on the peripheral active pattern P_ACT. For example, the second peripheral gate structure PG2 can be disposed on the first surface P_S1 of the peripheral active pattern.

[0070] In a semiconductor device according to some embodiments, a first surface P_S1 of a peripheral active pattern may face a first substrate 100. A second peripheral gate structure PG2 may face a first peripheral gate structure PG1.

[0071] The second peripheral gate structure PG2 may be included in a sensing transistor, a transmission transistor, a driving transistor, etc. Semiconductor devices may require various peripheral circuit transistors for operation. In a semiconductor device according to some embodiments, some peripheral circuit transistors may be disposed on the first substrate 100, and the remaining peripheral circuit transistors may be disposed on the peripheral active pattern P_ACT. Since the peripheral circuit transistors are separately disposed on the first substrate 100 and the peripheral active pattern P_ACT, the area on which the peripheral circuit transistors are disposed can be reduced. Accordingly, the integration density of the semiconductor device can be increased, and the size of the semiconductor device can be reduced.

[0072] The second peripheral gate structure PG2 may include a second peripheral gate insulating film 315, a second peripheral lower conductive pattern 323, a second peripheral upper conductive pattern 325, and a second peripheral gate mask pattern 326. The second peripheral gate insulating film 315 may include a silicon oxide film, a silicon oxynitride film, a high-dielectric-constant insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high-dielectric-constant insulating film may include, for example, but not limited to, at least one of metal oxides, metal oxynitrides, metal silicon oxides, or metal silicon oxynitrides.

[0073] In the second peripheral gate structure PG2, the second peripheral lower conductive pattern 323, the second peripheral upper conductive pattern 325, and the second peripheral gate mask pattern 326 can be formed simultaneously with the bit line BL. The stacked structure of the second peripheral gate structure PG2, excluding the second peripheral gate insulating film 315, can have the same stacked structure as the bit line BL. That is, the second peripheral lower conductive pattern 323 comprises the same material as the semiconductor pattern 161. The second peripheral upper conductive pattern 325 comprises the same material as the metal pattern 163. The second peripheral gate mask pattern 326 comprises the same material as the bit line mask pattern 165.

[0074] The second peripheral gate structure PG2 may include a second peripheral gate electrode containing conductive material. The second peripheral gate electrode may include a second peripheral lower conductive pattern 323 and a second peripheral upper conductive pattern 325. The thickness T22 of the second peripheral gate electrode in the second peripheral gate structure PG2 may be the same as the thickness T11 of the conductive bit line in the bit line BL. For example, thicknesses T11 and T22 may be taken on the third direction DR3.

[0075] Although not shown, the peripheral etch stop film may extend along the contours of the second peripheral gate structure PG2, the first surface P_S1 of the peripheral active pattern, and the bit line BL. The peripheral etch stop film may extend along one surface of the peripheral field insulating film STI. This one surface of the peripheral field insulating film STI may face the first substrate 100.

[0076] The second peripheral interlayer insulating film 365 can be disposed on the first surface P_S1 of the peripheral active pattern. The second peripheral interlayer insulating film 365 can be disposed on one surface of the peripheral field insulating film STI. The second peripheral interlayer insulating film 365 can be disposed on the first bonding pad BP1. The second peripheral interlayer insulating film 365 can be on the bit line BL and the second peripheral gate structure PG2 (e.g., it can cover the bit line BL and the second peripheral gate structure PG2). The second peripheral interlayer insulating film 365 includes an insulating material.

[0077] The second peripheral contact plug 341a and the second peripheral wiring line 341b can be disposed in the second peripheral interlayer insulating film 365. The second peripheral contact plug 341a can be connected to the second source / drain region disposed on at least one side of the second peripheral gate structure PG2. Although not shown, the second peripheral contact plug 341a can be connected to the second peripheral gate electrodes 323 and 325 of the second peripheral gate structure PG2. The second peripheral contact plug 341a can be connected to the conductive bit lines 161 and 163 of the bit line BL. Although not shown, the second peripheral contact plug 341a can be connected to the first word line WL1 and the second word line WL2.

[0078] The second peripheral wiring line 341b may be disposed on the second peripheral contact plug 341a. The second peripheral wiring line 341b is connected to the second peripheral contact plug 341a. For example, the second peripheral wiring line 341b may be the wiring line on the third-direction DR3 that is closest to the second peripheral gate structure PG2. The second peripheral contact plug 341a and the second peripheral wiring line 341b each include a conductive material.

[0079] The second peripheral connection structure 360 ​​may be disposed on the second peripheral gate structure PG2. In a semiconductor device according to some embodiments, the second peripheral connection structure 360 ​​may be disposed on the first surface P_S1 of the peripheral active pattern.

[0080] The second peripheral connection structure 360 ​​can be disposed on the second peripheral wiring line 341b. The second peripheral connection structure 360 ​​can be connected to the second peripheral wiring line 341b. The second peripheral connection structure 360 ​​can be connected to the second peripheral gate structure PG2. The second peripheral connection structure 360 ​​can be disposed in the second peripheral interlayer insulating film 365.

[0081] The second peripheral connection structure 360 ​​may include second peripheral connection wirings 361b and 362b, second peripheral connection vias 361a and 362a, and a first peripheral via 362c. Although the second peripheral connection structure 360 ​​is shown as including a plurality of second peripheral connection wirings 361b and 362b disposed at different metal layers, this is for illustrative purposes only, and the disclosure is not limited thereto. The first peripheral via 362c may be connected to one of the second peripheral connection wirings 361b and 362b. The first peripheral via 362c may penetrate the peripheral field insulating film STI (i.e., extend into the peripheral field insulating film STI). The first peripheral via 362c may extend to the height level of the second surface P_S2 of the peripheral active pattern.

[0082] The second peripheral connection wirings 361b and 362b, the second peripheral connection vias 361a and 362a, and the first peripheral through-hole 362c may each include conductive material.

[0083] The second bonding pad BP2 can be disposed on the second peripheral gate structure PG2. The second bonding pad BP2 can also be disposed on the first surface P_S1 of the peripheral active pattern. The second peripheral connection structure 360 ​​can be disposed between the second peripheral gate structure PG2 and the second bonding pad BP2. The second bonding pad BP2 can be connected to the second peripheral connection structure 360.

[0084] The second bonding pad BP2 can be connected to the first bonding pad BP1. The first bonding pad BP1 and the second bonding pad BP2 can be disposed between the first peripheral gate structure PG1 and the second peripheral gate structure PG2.

[0085] The second bonding pad plug 363 can be disposed between the second bonding pad BP2 and the second peripheral connection structure 360. The second bonding pad plug 363 can connect the second bonding pad BP2 and the second peripheral connection structure 360.

[0086] The second bonding pad BP2 and the second bonding pad plug 363 can be disposed within the second peripheral interlayer insulating film 365. The second bonding pad plug 363 and the second bonding pad BP2 can each comprise a conductive material containing metal.

[0087] The first active pattern AP1 and the second active pattern AP2 can be disposed on each bit line BL. The first active pattern AP1 and the second active pattern AP2 can be disposed alternately along the second direction DR2. The first active pattern AP1 and the second active pattern AP2 are spaced apart from the first substrate 100 on the third direction DR3.

[0088] The first active pattern AP1 can be spaced apart from each other in the first direction DR1. The first active pattern AP1 can be spaced apart at regular intervals. The second active pattern AP2 can be spaced apart from each other in the first direction DR1. The second active pattern AP2 can be spaced apart at regular intervals. The first active pattern AP1 can be spaced apart from the second active pattern AP2 in the second direction DR2. The first active pattern AP1 and the second active pattern AP2 can be arranged in two dimensions along the intersecting first direction DR1 and second direction DR2.

[0089] exist Figure 2 In this configuration, the first active pattern AP1 and the second active pattern AP2 may be spaced apart from the peripheral active pattern P_ACT in the second direction DR2. Although not shown, the first active pattern AP1 and the second active pattern AP2 may be spaced apart from the peripheral active pattern P_ACT in the first direction DR1.

[0090] For example, the first active pattern AP1 and the second active pattern AP2 can each be made of a single-crystal semiconductor material. As an example, the first active pattern AP1 and the second active pattern AP2 can each be made of single-crystal silicon.

[0091] Each of the first active pattern AP1 and the second active pattern AP2 may have a length in the first direction DR1, a width in the second direction DR2, and a height in the third direction DR3. Each of the first active pattern AP1 and the second active pattern AP2 may have a substantially uniform width. That is, each of the first active pattern AP1 and the second active pattern AP2 may have substantially the same width in the first surface S1 and the second surface S2. Furthermore, the width of the first active pattern AP1 may be equal to the width of the second active pattern AP2.

[0092] The widths of the first active pattern AP1 and the second active pattern AP2 on the second direction DR2 can range from several nanometers (nm) to tens of nanometers. For example, the widths of the first active pattern AP1 and the second active pattern AP2 can be in the range of 1 nm to 30 nm, and more preferably, in the range of 1 nm to 10 nm, but are not limited thereto. The length of each of the first active pattern AP1 and the second active pattern AP2 can be greater than the linewidth of the bit line BL. That is, the length of each of the first active pattern AP1 and the second active pattern AP2 on the first direction DR1 can be greater than the width of the bit line BL on the first direction DR1.

[0093] exist Figure 5 In the first active pattern AP1 and the second active pattern AP2, each includes a first surface S1 and a second surface S2 opposite to each other on a third-direction DR3. For example, the first surface S1 of the first active pattern AP1 and the second active pattern AP2 may face the bit line BL. In a semiconductor device according to some embodiments, the first surface S1 of the first active pattern AP1 and the second active pattern AP2 may face the first substrate 100. The second surface S2 of the first active pattern AP1 and the second active pattern AP2 may face the contact pattern BC.

[0094] The first surfaces S1 of the first active pattern AP1 and the second active pattern AP2 are connected to the bit line BL. For example, the first surfaces S1 of the first active pattern AP1 and the second active pattern AP2 can be connected to the semiconductor pattern 161 of the bit line BL. Unlike the example shown, if the semiconductor pattern 161 is omitted, the first surfaces S1 of the first active pattern AP1 and the second active pattern AP2 can be connected to the metal pattern 163. The second surfaces S2 of the first active pattern AP1 and the second active pattern AP2 can be connected to the contact pattern BC.

[0095] Each of the first active pattern AP1 and the second active pattern AP2 may include a first sidewall SS1 and a second sidewall SS2 that are opposite to each other in the second direction DR2. The first sidewall SS1 of the first active pattern AP1 may face the second sidewall SS2 of the second active pattern AP2.

[0096] The second sidewall SS2 of the first active pattern AP1 may be adjacent to the first letter line WL1. The first sidewall SS1 of the second active pattern AP2 may be adjacent to the second letter line WL2.

[0097] Although not shown, as an example, each of the first active pattern AP1 and the second active pattern AP2 may include a first doped region adjacent to the bit line BL and a second doped region adjacent to the contact pattern BC. Each of the first active pattern AP1 and the second active pattern AP2 may include a channel region between the first doped region and the second doped region. The first doped region and the second doped region are regions in the first active pattern AP1 and the second active pattern AP2 that are doped with dopant. Unlike the example above, each of the first active pattern AP1 and the second active pattern AP2 may not include at least one of the first doped region and the second doped region.

[0098] During semiconductor device operation, the channel regions of the first active pattern AP1 and the second active pattern AP2 can be controlled by the first word line WL1, the second word line WL2, and the back gate electrode BG. Because the first active pattern AP1 and the second active pattern AP2 are made of single-crystal semiconductor material, the leakage current characteristics of the semiconductor device can be improved.

[0099] The back gate electrode BG can be disposed on the bit line BL and the shielding conductive pattern SL. The back gate electrodes BG can be spaced apart from each other in the second direction DR2. The back gate electrodes BG can be spaced apart at regular intervals. Each back gate electrode BG can extend across the bit line BL in the first direction DR1.

[0100] Each back gate electrode BG can be disposed between a first active pattern AP1 and a second active pattern AP2 that are adjacent to each other along the second direction DR2. That is, the first active pattern AP1 can be disposed on one side of each back gate electrode BG, and the second active pattern AP2 can be disposed on the other side of each back gate electrode BG. The height of the back gate electrode BG on the third direction DR3 can be less than the height of the first active pattern AP1 and the second active pattern AP2.

[0101] Each back gate electrode BG can be disposed between the first sidewall SS1 of the first active pattern AP1 and the second sidewall SS2 of the second active pattern AP2. Each back gate electrode BG can be disposed on the first sidewall SS1 of the first active pattern AP1 and the second sidewall SS2 of the second active pattern AP2.

[0102] A first active pattern AP1 can be disposed between a first word line WL1 and a back gate electrode BG. A second active pattern AP2 can be disposed between a second word line WL2 and a back gate electrode BG. A pair of first word lines WL1 and second word lines WL2 can be disposed between back gate electrodes BG that are adjacent to each other along the second direction DR2.

[0103] The back gate electrode BG may include a first surface BG_S1 and a second surface BG_S2 opposite to each other on a third-direction DR3. The first surface BG_S1 of the back gate electrode is closer to the bit line BL than the second surface BG_S2 of the back gate electrode. The first surface BG_S1 of the back gate electrode may face the bit line BL.

[0104] The back gate electrode (BG) comprises a conductive material and may include at least one of, for example, a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, or a metal.

[0105] When a semiconductor device is operating, a voltage can be applied to the back gate electrode (BG) to adjust the threshold voltage of the vertical channel transistor. Because the threshold voltage of the vertical channel transistor is adjusted, leakage current characteristics can be prevented from deteriorating.

[0106] The back gate isolation pattern 111 can be disposed between the first active pattern AP1 and the second active pattern AP2 that are adjacent to each other along the second direction DR2. The back gate isolation pattern 111 can extend parallel to the back gate electrode BG in the first direction DR1. The back gate isolation pattern 111 can be disposed on the second surface BG_S2 of the back gate electrode.

[0107] The back gate isolation pattern 111 can be made of an insulating material. The back gate isolation pattern 111 can be, but is not limited to, a silicon oxide film, a silicon oxynitride film, or a silicon nitride film.

[0108] The back gate insulating pattern 113 can be disposed between the back gate electrode BG and the first active pattern AP1, and between the back gate electrode BG and the second active pattern AP2. The back gate insulating pattern 113 can also be disposed between the back gate isolation pattern 111 and the first active pattern AP1, and between the back gate isolation pattern 111 and the second active pattern AP2.

[0109] The back grid insulating pattern 113 can be made of an insulating material. The back grid insulating pattern 113 may include, for example, a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than a silicon oxide film, or a combination thereof.

[0110] A back gate capping pattern 115 can be disposed between the bit line BL and the back gate electrode BG. The back gate capping pattern 115 can be disposed between a first active pattern AP1 and a second active pattern AP2 that are adjacent to each other along the second direction DR2. The back gate capping pattern 115 can extend parallel to the bit line BL and the back gate electrode BG in the first direction DR1. The back gate capping pattern 115 and the bit line BL can be disposed on the first surface BG_S1 of the back gate electrode.

[0111] The back gate cover pattern 115 may be made of an insulating material. The back gate cover pattern 115 may include, but is not limited to, at least one of a silicon oxide film, a silicon oxynitride film, or a silicon nitride film.

[0112] The first word line WL1 and the second word line WL2 are disposed on the bit line BL and the shielding conductive pattern SL. Each of the first word line WL1 and the second word line WL2 may extend in the first direction DR1. The first word line WL1 and the second word line WL2 may be arranged alternately in the second direction DR2.

[0113] The first character line WL1 can be disposed on the second sidewall SS2 of the first active pattern AP1. The second character line WL2 can be disposed on the first sidewall SS1 of the second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 can be disposed between the first character line WL1 and the second character line WL2 that are adjacent to each other along the second direction DR2.

[0114] The first word line WL1 and the second word line WL2 can be spaced apart from the bit line BL and the contact pattern BC on the third direction DR3. The first word line WL1 and the second word line WL2 can be located between the bit line BL and the contact pattern BC.

[0115] Each of the first word line WL1 and the second word line WL2 may have a width in the second direction DR2. The width of the first word line WL1 and the width of the second word line WL2 on the bit line BL may be different from the width of the first word line WL1 and the width of the second word line WL2 on the shielded conductive pattern SL.

[0116] For example, each of the first word line WL1 and the second word line WL2 may include a first portion WLa and a second portion WLb of the word line. The width of the first portion WLa of the word line in the second direction DR2 may be smaller than the width of the second portion WLb of the word line in the second direction DR2. As an example, the first portion WLa of the word line may be disposed on the bit line BL. The second portion WLb of the word line may be disposed on the shielded conductive pattern SL.

[0117] Each of the first word line WL1 and the second word line WL2 may include a first portion WLa and a second portion WLb of the word line alternately arranged along a first direction DR1. In the first word line WL1, each first active pattern AP1 may be disposed between adjacent second portions WLb of the word line along the first direction DR1. In the second word line WL2, each second active pattern AP2 may be disposed between adjacent second portions WLb of the word line along the first direction DR1.

[0118] Unlike the example shown, the width of the first part WLa of the word line in the second direction DR2 can be equal to the width of the second part WLb of the word line in the second direction DR2.

[0119] The first word line WL1 and the second word line WL2 may include a first surface WL_S1 and a second surface WL_S2 opposite to each other on a third-party DR3. The first surface WL_S1 of the first word line and the second word line is closer to the bit line BL than the second surface WL_S2 of the first word line and the second word line. The first surface WL_S1 of the first word line and the second word line faces the bit line BL.

[0120] The following explanation will use the first word line WL1 as an example. As an example, the height of the first word line WL1 on the third-direction DR3 can be equal to the height of the back gate electrode BG on the third-direction DR3. As another example, the height of the first word line WL1 on the third-direction DR3 can be greater than the height of the back gate electrode BG on the third-direction DR3. As yet another example, the height of the first word line WL1 on the third-direction DR3 can be less than the height of the back gate electrode BG on the third-direction DR3.

[0121] Furthermore, as an example, with the upper surface BL_US of the bit line as a reference, the height of the first surface WL_S1 of the first word line can be equal to the height of the first surface BG_S1 of the back gate electrode. As another example, the first surface WL_S1 of the first word line can be higher than the first surface BG_S1 of the back gate electrode. As yet another example, the first surface WL_S1 of the first word line can be lower than the first surface BG_S1 of the back gate electrode.

[0122] Additionally, as an example, with the upper surface BL_US of the bit line as a reference, the height of the second surface WL_S2 of the first word line can be equal to the height of the second surface BG_S2 of the back gate electrode. As another example, the second surface WL_S2 of the first word line can be higher than the second surface BG_S2 of the back gate electrode. As yet another example, the second surface WL_S2 of the first word line can be lower than the second surface BG_S2 of the back gate electrode.

[0123] The first surface WL_S1 of the first character line WL1 and the second character line WL2 can be planar (i.e., flat). Unlike the example shown, by way of example, the first surface WL_S1 of the first character line WL1 and the second character line WL2 can be concave. As another example, each of the first character line WL1 and the second character line WL2 can have the form of a spacer. In other words, the first surface WL_S1 of the first character line WL1 and the second character line WL2 can be convex.

[0124] The second surface WL_S2 of the first word line WL1 and the second word line WL2 can be planar (i.e., flat). Unlike the example shown, the second surface WL_S2 of the first word line WL1 and the second word line WL2 can have a concave surface. The first surface BG_S1 and the second surface BG_S2 of the back gate electrode are shown as planar (i.e., flat), but this disclosure is not limited thereto.

[0125] The gate insulating pattern GOX can be disposed between the first word line WL1 and the first active pattern AP1, and between the second word line WL2 and the second active pattern AP2. The gate insulating pattern GOX can extend in a first direction DR1 parallel to the first word line WL1 and the second word line WL2.

[0126] The gate insulating pattern (GOX) may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high dielectric constant insulating film may include, for example, but not limited to, at least one of a metal oxide, a metal oxynitride, a metal silicon oxide, or a metal silicon oxynitride.

[0127] The gate insulating pattern GOX may extend along the second sidewall SS2 of the first active pattern AP1 and along the first sidewall SS1 of the second active pattern AP2. In a semiconductor device according to some embodiments, from a cross-sectional view, the gate insulating pattern GOX between the first active pattern AP1 and the first word line WL1 may be separated from the gate insulating pattern GOX between the second active pattern AP2 and the second word line WL2.

[0128] A gate isolation pattern GSS can be disposed on bit line BL. The gate isolation pattern GSS can be disposed between adjacent first word lines WL1 and WL2 along the second direction DR2. The first word lines WL1 and WL2 can be separated by the gate isolation pattern GSS. The gate isolation pattern GSS can extend along the first direction DR1 between the first word lines WL1 and WL2.

[0129] The first word line WL1 can be disposed between the gate isolation pattern GSS and the first active pattern AP1. The second word line WL2 can be disposed between the gate isolation pattern GSS and the second active pattern AP2.

[0130] The gate isolation pattern GSS can be made of an insulating material. Although the gate isolation pattern GSS is shown as a single-layer film, this is only for illustrative purposes and the present disclosure is not limited thereto.

[0131] The first interlayer insulating film 271 may be disposed on the peripheral active pattern P_ACT and the peripheral field insulating film STI. The first interlayer insulating film 271 may be disposed on the second surface P_S2 of the peripheral active pattern. The first interlayer insulating film 271 comprises an insulating material. Although the first interlayer insulating film 271 is shown as a single-layer film, this is only for illustrative purposes and the present disclosure is not limited thereto.

[0132] The contact pattern BC can be disposed in the first interlayer insulating film 271. The contact pattern BC can be connected to each of the first active pattern AP1 and the second active pattern AP2. The contact pattern BC can be connected to the second surface S2 of the first active pattern AP1 and the second active pattern AP2. From a planar perspective, each contact pattern BC can have various shapes such as circular, elliptical, rectangular, square, rhomboid, and hexagonal.

[0133] The contact pattern BC may include a conductive material. The contact pattern BC may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, or metal.

[0134] The bonding pad LP can be disposed on the contact pattern BC. The bonding pad LP can be disposed in the first interlayer insulating film 271. From a planar perspective, the bonding pad LP can have various shapes such as circular, elliptical, rectangular, square, rhomboid and hexagonal.

[0135] The bonding pad LP may include a conductive material, and may include at least one of, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material or metal.

[0136] The connection buffer conductive pattern 285 can be disposed in the first interlayer insulating film 271. The connection buffer conductive pattern 285 can be disposed on the second surface P_S2 of the peripheral active pattern. For example, the connection buffer conductive pattern 285 can be disposed on the peripheral field insulating film STI.

[0137] The connection buffer conductive pattern 285 can be connected to the second peripheral connection structure 360. In a semiconductor device according to some embodiments, the connection buffer conductive pattern 285 can be directly connected to the second peripheral connection structure 360. For example, the connection buffer conductive pattern 285 can be in contact with the second peripheral connection structure 360.

[0138] For example, the connecting buffer conductive pattern 285 can be connected to the first peripheral through-hole 362c. The connecting buffer conductive pattern 285 can contact the first peripheral through-hole 362c. The connecting buffer conductive pattern 285 may include a first connecting buffer pattern 286 and a second connecting buffer pattern 287. For example, the first connecting buffer pattern 286 can contact the first peripheral through-hole 362c.

[0139] The first connection buffer pattern 286 may be made of the same material as the contact pattern BC, but is not limited to. The second connection buffer pattern 287 may be made of the same material as the bonding pad LP, but is not limited to.

[0140] The data storage pattern DSP can be disposed on each bonding pad LP. The data storage pattern DSP can be electrically connected to each of the first active pattern AP1 and the second active pattern AP2. The data storage pattern DSP can be arranged in a matrix form along the first direction DR1 and the second direction DR2, such as... Figure 2 As shown. The data storage pattern DSP can fully or partially overlap with the bonding pad LP on the third-party DR3. The data storage pattern DSP can make full or partial contact with the upper surface of the bonding pad LP.

[0141] As an example, the data storage pattern DSP can be a capacitor. The data storage pattern DSP may include a capacitor dielectric film 253 between the storage electrode 251 and the plate electrode 255. For example, the storage electrode 251 may contact the bonding pad LP. From a planar perspective, the storage electrode 251 may have various shapes such as circular, elliptical, rectangular, square, rhomboid, and hexagonal. The data storage pattern DSP may contact all or part of the upper surface of the bonding pad LP.

[0142] Storage electrode 251 and plate electrode 255 may each include at least one of, for example, a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, or a metal. Capacitor dielectric film 253 may include at least one of a ferroelectric material, an antiferroelectric material, or a paraelectric material. For example, capacitor dielectric film 253 may include one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of ferroelectric and antiferroelectric materials, a combination of ferroelectric and paraelectric materials, a combination of paraelectric and antiferroelectric materials, and / or a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0143] In other embodiments, the data storage pattern DSP can be a variable resistance pattern that can be switched between two resistance states by an electrical pulse applied to the storage element. For example, the data storage pattern DSP may include phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials.

[0144] The second interlayer insulating film 272 may be disposed on the first interlayer insulating film 271. The second interlayer insulating film 272 may be on the sidewall of the data storage pattern DSP (e.g., may cover the sidewall of the data storage pattern DSP). The second interlayer insulating film 272 includes an insulating material.

[0145] The third interlayer insulating film 273 can be disposed on the second interlayer insulating film 272 and the data storage pattern DSP. The third interlayer insulating film 273 includes insulating material.

[0146] The bonding pad 280 can be disposed on the third interlayer insulating film 273. The bonding pad 280 can also be disposed on the second surface P_S2 of the peripheral active pattern.

[0147] Connection pad 280 can be connected to the data storage pattern DSP. Connection pad 280 can be connected to the second peripheral connection structure 360.

[0148] The connecting pad connector 281 can be disposed in the second interlayer insulating film 272 and the third interlayer insulating film 273. The connecting pad connector 281 can connect the connecting pad 280 to the connecting buffer conductive pattern 285. The connecting pad connector 281 can contact the connecting buffer conductive pattern 285.

[0149] The connection pad plug 282 can be disposed in the third interlayer insulating film 273. The connection pad plug 282 can connect the board electrode 255 of the data storage pattern DSP to the connection pad 280.

[0150] The connecting pad 280, the connecting pad connecting plug 281, and the connecting pad plug 282 may each include at least one of conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal oxide, or metal.

[0151] Figure 7 This is a diagram used to illustrate a semiconductor device according to some embodiments. Figures 8 to 10 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main focus will be on the description and use. Figures 1 to 6 The differences in the content of the explanation.

[0152] For reference only. Figure 7 and Figure 8 It is along Figure 2 The cross-sectional view taken from line AA. Figure 9 It is along Figure 2 The cross-sectional view taken from lines BB and CC. Figure 10 yes Figure 8 A magnified view of part P.

[0153] refer to Figure 7 The semiconductor device according to some embodiments may also include a second peripheral field through plug 341c.

[0154] The second peripheral field through-hole plug 341c can be connected to the second peripheral wiring line 341b. The second peripheral field through-hole plug 341c can penetrate the peripheral field insulating film STI. The second peripheral field through-hole plug 341c can extend to the second surface P_S2 of the peripheral active pattern (e.g., see...). Figure 6 ) at a high level.

[0155] The second peripheral field through plug 341c can be connected to the connection buffer conductive pattern 285. The second peripheral field through plug 341c can contact the connection buffer conductive pattern 285.

[0156] The second peripheral connection structure 360 ​​can be connected to the second peripheral field through plug 341c. The second peripheral connection structure 360 ​​can be connected to the connection buffer conductive pattern 285 through the second peripheral field through plug 341c.

[0157] refer to Figures 8 to 10 In a semiconductor device according to some embodiments, the shielding conductive pattern SL may include a shielding conductive plate SLh and a plurality of shielding conductive line patterns SLp.

[0158] The shielding conductive plate SLh can be flat. The shielding conductive line pattern SLp can protrude from the shielding conductive plate SLh on the third-direction DR3. The shielding conductive line pattern SLp is directly connected to the shielding conductive plate SLh.

[0159] The shielding insulating pad 171 may extend along the outline of the shielding conductive plate SLh and the shielding conductive wire pattern SLp.

[0160] The shielding insulating cover film 175 can be disposed between the shielding conductive plate SLh and the first substrate 100. The shielding insulating cover film 175 can be in contact with the shielding conductive plate SLh.

[0161] Bit line BL can be disposed on the shielded conductive pattern SL. Bit line BL can be disposed on the shielded conductive plate SLh. Shielded conductive pattern SL can be disposed on the bottom surface of bit line BL. For example, shielded conductive plate SLh can be disposed on the bottom surface of bit line BL.

[0162] Bit line BL can be positioned adjacent to shielded conductive line pattern SLp. Bit line BL can be positioned adjacent to shielded conductive line pattern SLp in a first direction DR1. Shielded conductive line pattern SLp can extend along the long sidewall of bit line BL in a second direction DR2. Bit line BL can be positioned between shielded conductive line patterns SLp that are adjacent to each other along the first direction DR1.

[0163] Figure 11 and Figure 12 This is a diagram used to illustrate a semiconductor device according to some embodiments. Figure 13 and Figure 14 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main focus will be on the description and use. Figures 1 to 10 The differences in the content of the explanation.

[0164] refer to Figures 11 to 14 In a semiconductor device according to some embodiments, a first active pattern AP1, a second active pattern AP2, and a peripheral active pattern P_ACT can be formed on a second substrate 200.

[0165] The second substrate 200 may include a cell array region CAR in which a data storage pattern DSP is disposed, and a peripheral circuit region PCR defined around the cell array region CAR (e.g., see...). Figure 1 and Figure 2 The peripheral active pattern P_ACT can be set on the peripheral circuit region PCR of the second substrate 200.

[0166] The second substrate 200 may be a silicon substrate, or may include other materials, such as, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0167] No first peripheral gate structure is disposed on the second substrate 200 (see Figure 3 (PG1). Various peripheral circuit transistors can be placed on the peripheral active pattern P_ACT to enable the semiconductor device to operate.

[0168] According to some embodiments, the semiconductor device may not include a first peripheral gate structure (see [reference]). Figure 3 PG1) and the first peripheral connection structure (see PG1) and the first peripheral connection structure (see PG1) Figure 3 (260). Additionally, according to some embodiments, the semiconductor device may not include the first bonding pad BP1 and the second bonding pad BP2 (see 260). Figure 3 and Figure 4 ).

[0169] The connection buffer conductive pattern 345 can be disposed in the first interlayer insulating film 271. The connection buffer conductive pattern 345 can be disposed on the second surface P_S2 of the peripheral active pattern. For example, the connection buffer conductive pattern 345 can be disposed on the peripheral field insulating film STI.

[0170] The connection buffer conductive pattern 345 may include a first connection buffer pattern 346 and a second connection buffer pattern 347. The first connection buffer pattern 346 may be made of, but is not limited to, the same material as the contact pattern BC. The second connection buffer pattern 347 may be made of, but is not limited to, the same material as the bonding pad LP.

[0171] The second peripheral field through plug 341c can be connected to the connection buffer conductive pattern 345. The second peripheral field through plug 341c can contact the connection buffer conductive pattern 345.

[0172] exist Figure 11 and Figure 12 In the second substrate 200, the first surface P_S1 of the peripheral active pattern does not face the second substrate 200. The second surface P_S2 of the peripheral active pattern may face the second substrate 200. The second peripheral gate structure PG2 does not face the second substrate 200.

[0173] The first surfaces of the first active pattern AP1 and the second active pattern AP2 (see...) Figure 5 S1) is not facing the second substrate 200. The second surfaces of the first active pattern AP1 and the second active pattern AP2 (see...) Figure 5 S2) can be oriented toward the second substrate 200.

[0174] The data storage pattern DSP can be disposed between the first active pattern AP1 and the second substrate 200, and between the second active pattern AP2 and the second substrate 200. A fourth interlayer insulating film 274 can be disposed between the data storage pattern DSP and the second substrate 200. The fourth interlayer insulating film 274 comprises an insulating material.

[0175] The connecting buffer conductive pattern 345 can be connected to the data storage pattern DSP. For example, the connecting buffer conductive pattern 345 can be connected to the plate electrode 255 of the data storage pattern DSP. The second peripheral field through plug 341c can be connected to the data storage pattern DSP.

[0176] The second peripheral connection structure 360 ​​can be disposed on the first surface P_S1 of the peripheral active pattern. The second peripheral connection structure 360 ​​can be connected to the second peripheral wiring line 341b. The second peripheral connection structure 360 ​​may include second peripheral connection wirings 361b, 362b, 363b and 364b, and second peripheral connection vias 361a, 362a, 363a and 364a.

[0177] The connection pad 280 can be disposed on the first surface P_S1 of the peripheral active pattern. The connection pad 280 can be connected to the second peripheral connection structure 360. The connection pad plug 282 can connect the connection pad 280 to the second peripheral connection structure 360.

[0178] exist Figure 13 and Figure 14 In this configuration, the first surface P_S1 of the peripheral active pattern can face the second substrate 200. The second peripheral gate structure PG2 can also face the second substrate 200. The second peripheral gate structure PG2 can be disposed between the peripheral active pattern P_ACT and the second substrate 200.

[0179] The second peripheral contact plug 341a and the second peripheral wiring line 341b can be disposed in the lower peripheral interlayer insulating film 366. The lower peripheral interlayer insulating film 366 can be disposed between the peripheral active pattern P_ACT and the second substrate 200. The lower peripheral interlayer insulating film 366 includes an insulating material.

[0180] A bonding insulating film 275 may be disposed on the second substrate 200. The bonding insulating film 275 may be disposed between the second substrate 200 and the lower peripheral interlayer insulating film 366. The bonding insulating film 275 may include, but is not limited to, silicon carbonitride (SiCN). A second peripheral wiring line 341b may be disposed on the bonding insulating film 275.

[0181] Unlike the example shown, the bonding insulating film 275 may not be disposed on the second substrate 200.

[0182] In some embodiments, the bonding insulating film 275 may be disposed on Figure 3 Between the first peripheral interlayer insulating film 265 and the second peripheral interlayer insulating film 365. In this case, the bonding insulating film 275 may be disposed along the boundary between the first bonding pad BP1 and the second bonding pad BP2.

[0183] The second peripheral connection structure 360 ​​can be disposed on the second surface P_S2 of the peripheral active pattern. The second peripheral connection structure 360 ​​can also be disposed on the data storage pattern DSP.

[0184] The second peripheral connection structure 360 ​​may include second peripheral connection wirings 361b, 362b, 363b and 364b, second peripheral connection vias 361a, 362a, 363a and 364a, and a second peripheral through-hole 361c. The second peripheral through-hole 361c may be disposed in the second peripheral interlayer insulating film 365 and the second interlayer insulating film 272.

[0185] The second peripheral connection structure 360 ​​can be connected to the data storage pattern DSP. The second peripheral connection structure 360 ​​can be connected to the second peripheral field through plug 341c.

[0186] The second peripheral connection structure 360 ​​can be connected to the connection buffer conductive pattern 345. For example, the second peripheral through-hole 361c can be connected to the connection buffer conductive pattern 345. The second peripheral through-hole 361c can be connected to the second peripheral field through-plug 341c.

[0187] The connection pad 280 can be disposed on the second surface P_S2 of the peripheral active pattern. The connection pad 280 can be connected to the second peripheral connection structure 360.

[0188] Figures 15 to 18 These are figures used to illustrate semiconductor devices according to some embodiments. For ease of explanation, the main focus will be on description and use. Figures 1 to 14 The differences in the content of the explanation.

[0189] refer to Figure 15 In a semiconductor device according to some embodiments, a first active pattern AP1 and a second active pattern AP2 may be alternately arranged in a diagonal direction relative to the first direction DR1 and the second direction DR2. Here, the diagonal direction may be parallel to the first substrate (see...). Figure 3 The upper surface of (100).

[0190] From a planar perspective, each of the first active pattern AP1 and the second active pattern AP2 can have a parallelogram shape or a rhombus shape. Since the first active pattern AP1 and the second active pattern AP2 are arranged in a diagonal direction, the coupling between the first active pattern AP1 and the second active pattern AP2 facing each other in the second direction DR2 can be reduced.

[0191] refer to Figure 16 In a semiconductor device according to some embodiments, from a planar perspective, the bonding pads LP and the data storage pattern DSP can be arranged in a sawtooth or honeycomb shape.

[0192] refer to Figure 17 In a semiconductor device according to some embodiments, from a planar perspective, the data storage pattern DSP can be configured to be offset from the bonding pad LP.

[0193] Each data storage pattern DSP can contact a portion of the bonding pad LP.

[0194] refer to Figure 18In a semiconductor device according to some embodiments, each contact pattern BC disposed on the first active pattern AP1 and the second active pattern AP2 may have a semi-circular shape or a semi-elliptical shape when viewed from a planar perspective.

[0195] From a planar perspective, the contact pattern BC can be symmetrically arranged with the back gate electrode BG in between.

[0196] Figures 19 to 26 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments. Accordingly, a reference [device] can be manufactured. Figures 1 to 10 Explanation of semiconductor devices.

[0197] refer to Figure 19 The sub-substrate structure can be configured to include a sub-substrate 300, a buried insulating layer 301, and an active layer.

[0198] For example, the sub-substrate structure can be a silicon-on-insulator substrate (i.e., an SOI substrate).

[0199] Sub-substrate 300 may include a cell array region (see Figure 2 CAR) and peripheral circuitry area (see Figure 2 (PCR). Substrate 300 can be, for example, a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate.

[0200] The buried insulating layer 301 may be a buried oxide (BOX) formed by a SIMOX (separation by oxygen injection) method or a bonding and layer transfer method. In other embodiments, the buried insulating layer 301 may be an insulating film formed by chemical vapor deposition (CVD). The buried insulating layer 301 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric constant insulating film.

[0201] The active layer can be a single-crystal semiconductor film. The active layer can be, for example, a single-crystal silicon substrate, a germanium substrate, and / or a silicon-germanium substrate.

[0202] A peripheral field insulating film (STI) can be formed on the sub-substrate 300. The STI can be formed within the active layer. The STI can be formed to define the cell array region (see [link]). Figure 2 (CAR). In addition, a peripheral field insulating film STI can be formed to form a peripheral active pattern P_ACT.

[0203] Next, a first active pattern AP1, a second active pattern AP2, a first word line WL1, and a second word line WL2 can be formed in the cell array region CAR.

[0204] refer to Figure 20A second peripheral gate insulating film 315 can be formed on the peripheral active pattern P_ACT. A semiconductor film 161p, a metal film 163p, and a mask film 165p can be sequentially formed on the second peripheral gate insulating film 315.

[0205] refer to Figure 20 and Figure 21 It can pattern the semiconductor film 161p, the metal film 163p and the mask film 165p, and can form bit lines BL on the first active pattern AP1 and the second active pattern AP2.

[0206] The second peripheral gate insulating film 315, semiconductor film 161p, metal film 163p and mask film 165p can be patterned, and the second peripheral gate structure PG2 can be formed on the peripheral active pattern P_ACT.

[0207] refer to Figure 22 and Figure 23 A second peripheral contact plug 341a and a second peripheral wiring line 341b can be formed on the second peripheral gate structure PG2 and the bit line BL.

[0208] Next, a second peripheral connection structure 360 ​​can be formed on the second peripheral wiring line 341b. A second bonding pad BP2 and a second bonding pad plug 363 can be formed on the second peripheral connection structure 360.

[0209] exist Figure 22 In this process, a first peripheral through-hole 362c that penetrates the peripheral field insulating film STI can be formed simultaneously with the formation of the second peripheral connection structure 360.

[0210] exist Figure 23 In this process, a second peripheral field through plug 341c that penetrates the peripheral field insulating film STI can be formed simultaneously with the formation of the second peripheral contact plug 341a.

[0211] Will be described in Figure 22 The following manufacturing method will then be carried out.

[0212] refer to Figure 24 A first peripheral gate structure PG1, a first peripheral connection structure 260, and a first bonding pad BP1 can be formed on the first substrate 100.

[0213] A sub-substrate 300, on which a second peripheral gate structure PG2, bit line BL, first active pattern AP1, second active pattern AP2, first word line WL1, and second word line WL2 are formed, can be bonded to a first substrate 100. The first substrate 100 and the sub-substrate 300 can be bonded such that the first peripheral gate structure PG1 and the second peripheral gate structure PG2 face each other. The first bonding pad BP1 and the second bonding pad BP2 can be connected to bond the sub-substrate 300 to the first substrate 100.

[0214] Next, after bonding the first substrate 100 to the sub-substrate 300, a back-side grinding process can be performed to remove the sub-substrate 300 and the buried insulating layer 301. The sub-substrate 300 and the buried insulating layer 301 can be removed to expose the first peripheral via 362c.

[0215] refer to Figure 25 Contact patterns BC and bonding pads LP can be formed in the first interlayer insulating film 271.

[0216] The contact pattern BC can be connected to the first active pattern AP1 and the second active pattern AP2.

[0217] A connection buffer conductive pattern 285 can be formed in the first interlayer insulating film 271. The connection buffer conductive pattern 285 can be connected to the exposed first peripheral via 362c.

[0218] refer to Figure 26 A data storage pattern DSP can be formed on the contact pattern BC. The data storage pattern DSP can be connected to the first active pattern AP1 and the second active pattern AP2.

[0219] Then, a second interlayer insulating film 272 can be formed on the first interlayer insulating film 271.

[0220] Next, return to the reference. Figure 3 Connection pads 280 can be formed on the data storage pattern DSP.

[0221] Figures 27 to 30 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments. Accordingly, a reference [device] can be manufactured. Figure 13 and Figure 14 The semiconductor device described.

[0222] For reference only. Figure 27 It can be in Figure 21 Subsequent manufacturing processes. (See reference) Figure 27 A second peripheral contact plug 341a and a second peripheral wiring line 341b can be formed on the second peripheral gate structure PG2 and the bit line BL.

[0223] The second peripheral contact plug 341a and the second peripheral wiring line 341b can be formed in the lower peripheral interlayer insulating film 366. The lower peripheral interlayer insulating film 366 can be on the bit line BL and the second peripheral gate structure PG2 (e.g., it can cover the bit line BL and the second peripheral gate structure PG2). During the formation of the second peripheral contact plug 341a, the second peripheral field through plug 341c can be formed in the peripheral field insulating film STI and the lower peripheral interlayer insulating film 366.

[0224] refer to Figure 28 The sub-substrate 300, on which the second peripheral gate structure PG2, bit line BL, first active pattern AP1, second active pattern AP2, first word line WL1 and second word line WL2 are formed, can be bonded to the second substrate 200.

[0225] The sub-substrate 300 can be bonded to the second substrate 200 using the bonding insulating film 275.

[0226] Then, after bonding the second substrate 200 to the sub-substrate 300, a back-side grinding process can be performed to remove the sub-substrate 300 and the buried insulating layer 301. Removing the sub-substrate 300 and the buried insulating layer 301 exposes the second peripheral field through-hole 341c.

[0227] refer to Figure 29 Contact patterns BC and bonding pads LP can be formed in the first interlayer insulating film 271.

[0228] A connection buffer conductive pattern 345 can be formed in the first interlayer insulating film 271. The connection buffer conductive pattern 345 can be connected to the exposed second peripheral field through plug 341c.

[0229] Next, a data storage pattern DSP can be formed on the contact pattern BC and the connection buffer conductive pattern 345. The data storage pattern DSP can be connected to the first active pattern AP1 and the second active pattern AP2.

[0230] Next, a second interlayer insulating film 272 can be formed on the first interlayer insulating film 271.

[0231] refer to Figure 30 A second peripheral connection structure 360 ​​can be formed on the data storage pattern DSP.

[0232] The second peripheral connection structure 360 ​​can be connected to the data storage pattern DSP. The second peripheral connection structure 360 ​​can be connected to the connection buffer conductive pattern 345.

[0233] Next, return to the reference. Figure 13 A connection pad 280 can be formed on the second peripheral connection structure 360.

[0234] Figures 31 to 34 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments. Accordingly, a reference [device] can be manufactured. Figure 11 and Figure 12 The semiconductor device described.

[0235] For reference only. Figure 31 It can be in Figure 21 The subsequent manufacturing process.

[0236] refer to Figure 31 A second peripheral contact plug 341a and a second peripheral wiring line 341b can be formed on the second peripheral gate structure PG2 and the bit line BL.

[0237] The second peripheral contact plug 341a and the second peripheral wiring line 341b can be formed in the second peripheral interlayer insulating film 365. During the formation of the second peripheral contact plug 341a, the second peripheral field through plug 341c can be formed in the peripheral field insulating film STI and the second peripheral interlayer insulating film 365.

[0238] refer to Figure 32 The sub-substrate 300, on which the second peripheral gate structure PG2, bit line BL, first active pattern AP1, second active pattern AP2, first word line WL1 and second word line WL2 are formed, can be bonded to the support substrate 400.

[0239] Next, after bonding the support substrate 400 to the sub-substrate 300, the sub-substrate 300 and the buried insulating layer 301 can be removed to expose the second peripheral field through plug 341c.

[0240] refer to Figure 33 Contact pattern BC, bonding pad LP and connection buffer conductive pattern 345 can be formed in the first interlayer insulating film 271.

[0241] Then, a data storage pattern DSP can be formed on the contact pattern BC and the connection buffer conductive pattern 345.

[0242] A fourth interlayer insulating film 274 can be formed on the data storage pattern DSP.

[0243] refer to Figure 34 The support substrate 400, on which the data storage pattern DSP, the second peripheral gate structure PG2, the bit line BL, the first active pattern AP1, the second active pattern AP2, the first word line WL1 and the second word line WL2 are disposed, can be bonded to the second substrate 200.

[0244] After the second substrate 200 is bonded to the support substrate 400, the support substrate 400 can be removed.

[0245] After removing the support substrate 400, a second peripheral connection structure 360 ​​can be formed on the second peripheral wiring line 341b.

[0246] Next, return to the reference. Figure 11 A connection pad 280 can be formed on the second peripheral connection structure 360.

[0247] Although exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, but can be implemented in various different forms. Those skilled in the art will understand that the present disclosure can be implemented in other specific forms without changing its scope. Therefore, it should be understood that the above embodiments are illustrative in all respects rather than limiting.

[0248] As used herein, the terms “comprising,” “including,” “including,” “having,” “containing,” and any other variations thereof indicate the presence of the described features, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. Furthermore, it will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. Rather, these terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

Claims

1. A semiconductor device, comprising: An active pattern includes a first surface and a second surface that are opposite to each other in a first direction; The peripheral active pattern includes a first surface and a second surface that are opposite to each other in the first direction, wherein the peripheral active pattern is spaced apart from the active pattern in a second direction that intersects with the first direction; Bit lines are electrically connected to the first surface of the active pattern and extend in the second direction; Data storage pattern, electrically connected to the second surface of the active pattern; and A first peripheral gate structure is located on a first surface of the peripheral active pattern.

2. The semiconductor device according to claim 1, further comprising: A peripheral field insulating film contacts the sidewall of the peripheral active pattern, wherein the sidewall of the peripheral active pattern connects the first surface of the peripheral active pattern to the second surface of the peripheral active pattern; The peripheral contact plug is electrically connected to the first peripheral gate structure; A peripheral field through-plug extends into the peripheral field insulating film; and The peripheral wiring is on the first surface of the peripheral active pattern and is electrically connected to the peripheral contact plug and the peripheral field through plug.

3. The semiconductor device according to claim 2, further comprising: The peripheral connection structure is on the first surface of the peripheral active pattern and is electrically connected to the peripheral wiring line.

4. The semiconductor device according to claim 2, wherein, The peripheral field through plug is electrically connected to the data storage pattern.

5. The semiconductor device according to claim 2, further comprising: A peripheral connection structure is located on the second surface of the peripheral active pattern and is electrically connected to the data storage pattern. The peripheral field through plug is electrically connected to the peripheral connection structure.

6. The semiconductor device according to claim 5, further comprising: Connect the buffer conductive pattern on the second surface of the peripheral active pattern. The peripheral connection structure and the peripheral field through plug are electrically connected to the connection buffer conductive pattern.

7. The semiconductor device according to claim 1, further comprising: The substrate is spaced apart from the active pattern and the peripheral active pattern in the first direction; as well as A second peripheral gate structure is located on the substrate.

8. The semiconductor device according to claim 7, wherein, The first surface of the peripheral active pattern faces the substrate.

9. The semiconductor device according to claim 7, further comprising: The first peripheral connection structure is electrically connected to the first peripheral gate structure; The first bonding pad is electrically connected to the first peripheral connection structure; The second peripheral connection structure is electrically connected to the second peripheral gate structure; as well as The second bonding pad is electrically connected to the second peripheral connection structure and the first bonding pad.

10. The semiconductor device according to claim 1, further comprising: A first peripheral connection structure is located on the first surface of the peripheral active pattern and is electrically connected to the first peripheral gate structure. as well as Connect the pads on the second surface of the peripheral active pattern. The connecting pads are electrically connected to the data storage pattern and the first peripheral connection structure.

11. The semiconductor device of claim 10, further comprising: A buffer conductive pattern is connected to the second surface of the peripheral active pattern; as well as Connect the pads and plugs to electrically connect the conductive pattern of the connection buffer to the pads. The first peripheral connection structure is electrically connected to the connection buffer conductive pattern.

12. The semiconductor device according to claim 1, wherein, The bit lines include conductive bit lines containing conductive material. Wherein, the first peripheral gate structure includes a first peripheral gate electrode, and The thickness of the conductive bit line is equal to the thickness of the first peripheral gate electrode.

13. A semiconductor device, comprising: The first peripheral gate structure is on the substrate; An active pattern is spaced apart from the substrate in a first direction and includes a first surface and a second surface that are opposite to each other in the first direction; The peripheral active pattern is spaced apart from the substrate in the first direction and includes a first surface and a second surface that are opposite to each other in the first direction; The second peripheral gate structure is on the first surface of the peripheral active pattern; Bit lines are electrically connected to a first surface of the active pattern and extend in a second direction intersecting the first direction; as well as The data storage pattern is electrically connected to the second surface of the active pattern.

14. The semiconductor device according to claim 13, wherein, The first surface of the active pattern and the first surface of the peripheral active pattern face the substrate.

15. The semiconductor device according to claim 13, further comprising: A peripheral connection structure is located on the first surface of the peripheral active pattern and is electrically connected to the second peripheral gate structure. Connecting pads on the second surface of the peripheral active pattern; A buffer conductive pattern is connected to the second surface of the peripheral active pattern; as well as Connect the pads and plugs to electrically connect the conductive pattern of the connection buffer to the pads. The connecting buffer conductive pattern is electrically connected to the peripheral connecting structure.

16. The semiconductor device according to claim 15, wherein, The peripheral connection structure is in contact with the connection buffer conductive pattern.

17. The semiconductor device of claim 15, further comprising: A peripheral field insulating film contacts the sidewall of the peripheral active pattern, wherein the sidewall of the peripheral active pattern connects the first surface of the peripheral active pattern to the second surface of the peripheral active pattern; The peripheral contact plug is electrically connected to the second peripheral gate structure; A peripheral field through-plug extends into the peripheral field insulating film and is electrically connected to the connection buffer conductive pattern; and The peripheral wiring is on the first surface of the peripheral active pattern and is electrically connected to the peripheral contact plug and the peripheral field through plug.

18. The semiconductor device of claim 13, further comprising: The first peripheral connection structure is electrically connected to the first peripheral gate structure; The first bonding pad is electrically connected to the first peripheral connection structure; The second peripheral connection structure is on the first surface of the peripheral active pattern and is electrically connected to the second peripheral gate structure; as well as The second bonding pad is electrically connected to the second peripheral connection structure and the first bonding pad.

19. A semiconductor device, comprising: An active pattern is spaced apart from a substrate in a first direction and includes a first surface and a second surface that are opposite to each other in the first direction; The peripheral active pattern is spaced apart from the substrate in the first direction and includes a first surface and a second surface that are opposite to each other in the first direction; Bit lines, electrically connected to a first surface of the active pattern, extend in a second direction intersecting the first direction, and include conductive bit lines comprising conductive material; Data storage pattern, electrically connected to the second surface of the active pattern; A peripheral gate structure is provided on a first surface of the peripheral active pattern and includes a peripheral gate electrode, wherein the thickness of the peripheral gate electrode is equal to the thickness of the conductive bit line. A peripheral field insulating film contacts the sidewall of the peripheral active pattern, wherein the sidewall of the peripheral active pattern connects the first surface of the peripheral active pattern to the second surface of the peripheral active pattern; The peripheral contact plug is electrically connected to the peripheral gate structure; The peripheral field through-plug extends into the peripheral field insulating film; Peripheral wiring lines are located on the first surface of the peripheral active pattern and are electrically connected to the peripheral contact plug and the peripheral field-through plug; and A peripheral connection structure is located on the substrate and is electrically connected to the peripheral wiring lines.

20. The semiconductor device of claim 19, further comprising: Connect the buffer conductive pattern on the second surface of the peripheral active pattern. The peripheral connection structure and the peripheral field through plug are electrically connected to the connection buffer conductive pattern.

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