Memory cell structure and forming method of memory cell structure

Abstract

The invention discloses a memory cell structure and a forming method of the memory cell structure. The forming method comprises the following steps: providing a substrate; the substrate is etched, a source line structure and a bit line structure are formed, and a first opening is formed between the bit line structure and the source line structure; forming a floating gate dielectric layer on the bottom surface of the first opening and the surface of the bit line structure; forming a floating gate layer on the floating gate dielectric layer; forming a first photoresist layer with a control gate pattern on the floating gate layer; part of the floating gate layer is etched with the first photoresist layer as a mask, a floating gate is formed, and a second opening is formed between the floating gate and the source line structure; forming a control gate dielectric layer on the bottom surface of the second opening, the side wall surface of the source line structure and the side wall surface of the floating gate; and forming a control gate on the control gate dielectric layer. By omitting a word line structure and an erase gate, the area of the memory cell is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a memory cell structure and a method for forming the memory cell structure. Background Technology

[0002] With the increasing intelligence of automobiles and industries, as well as the trend of in-memory computing, higher requirements are being placed on the area and storage density of individual storage cells in memory.

[0003] Currently, in order to reduce the area of ​​memory cells, the size of the floating gate, the size of the conductive plugs in the word line structure and the control gate structure, or the size of the peripheral control circuit are compressed. However, the area reduction is limited and affects the performance of the memory cells, which is not conducive to memory integration. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a memory cell structure and a method for forming the memory cell structure, so as to improve the integration of memory.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a memory cell structure, comprising: providing a substrate; etching the substrate to form a source line structure and a bit line structure, wherein a first opening is provided between the bit line structure and the source line structure; forming a floating gate dielectric layer on the bottom surface of the first opening and the surface of the bit line structure; forming a floating gate layer on the floating gate dielectric layer; forming a first photoresist layer having a control gate pattern on the floating gate layer; etching a portion of the floating gate layer using the first photoresist layer as a mask to form a floating gate, wherein a second opening is provided between the floating gate and the source line structure; forming a control gate dielectric layer on the bottom surface of the second opening, the sidewall surface of the source line structure, and the sidewall surface of the floating gate; and forming a control gate on the control gate dielectric layer.

[0006] Optionally, the steps of forming the source line structure and the bit line structure include: performing ion implantation on the substrate surface to form a well region located within the substrate; forming a second photoresist layer having source line structure patterns and bit line structure patterns on the well region; and etching the well region using the second photoresist layer as a mask to form the bit line structure and the source line structure.

[0007] Optionally, the ion type for the ion implantation treatment is P-type or N-type, and the concentration range of the ion implantation treatment is 1E11 atom / cm³. 3 Up to 1E14atom / cm 3 .

[0008] Optionally, the method for etching the trap region is dry etching, and the process parameters for dry etching are as follows: the etching gas is at least three of the following: fluorine, hydrogen, nitrogen, argon and ammonia, the flow rate of each gas is in the range of 0 mL / min to 2000 mL / min, the reaction pressure is in the range of 0 mT to 3000 mT, the reaction temperature is in the range of 0 degrees Celsius to 250 degrees Celsius, and the etching power is in the range of 0 W to 1000 W.

[0009] Optionally, the method for forming the floating gate dielectric layer and the floating gate layer is a chemical vapor deposition process, wherein the parameters of the chemical vapor deposition process are that the deposition gas includes hydrogen and silane, and the reaction temperature range is 400 degrees Celsius to 800 degrees Celsius.

[0010] Optionally, the method for etching the floating gate layer is dry etching, and the process parameters for dry etching are as follows: the etching gas is at least three of the following: fluorine, hydrogen, nitrogen, argon and ammonia, the flow rate of each gas is in the range of 0 mL / min to 2000 mL / min, the reaction pressure is in the range of 0 mT to 3000 mT, the reaction temperature is in the range of 0 degrees Celsius to 250 degrees Celsius, the etching power is in the range of 0 W to 1000 W, and the thickness of the floating gate is in the range of 1000 angstroms to 3000 angstroms.

[0011] Optionally, the step of forming the control gate dielectric layer includes: forming a first dielectric layer on the bottom surface of the second opening, the sidewall surface of the source line structure, and the sidewall surface of the floating gate; forming a second dielectric layer on the first dielectric layer; and forming a third dielectric layer on the second dielectric layer, wherein the material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer.

[0012] Optionally, the method for forming the control gate dielectric layer and the control gate is a chemical vapor deposition process, wherein the parameters of the chemical vapor deposition process are that the deposition gas includes hydrogen and silane, the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius, and the thickness of the control gate ranges from 700 angstroms to 2700 angstroms.

[0013] Optionally, after forming the control gate, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the source line structure, the bit line structure, the floating gate, and the control gate surface; and forming a conductive plug extending through the thickness of the dielectric layer within the dielectric layer.

[0014] Accordingly, the present invention also provides a memory cell structure, comprising: a substrate; a source line structure located within the substrate; a bit line structure located within the substrate, wherein a first opening is formed between the bit line structure and the source line structure; a floating gate dielectric layer located on the bottom surface of the first opening and the surface of the bit line structure; a floating gate located on the floating gate dielectric layer, wherein a second opening is formed between the floating gate and the source line structure; a control gate dielectric layer located on the bottom surface of the second opening, the sidewall surface of the source line structure, and the sidewall surface of the floating gate; and a control gate located on the control gate dielectric layer.

[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0016] This invention reduces the area of ​​the memory cell by omitting the word line structure and erase gate. During write operations, pressure is applied to the control gate to allow electrons to enter the floating gate. During erase operations, the electrons written are pulled into the source line structure, thus clearing the electrons stored in the floating gate. This ensures the basic operation of the memory cell. Furthermore, by forming a floating gate and control gate between the bit line structure and the source line structure, a vertical electron transport channel is created in the memory cell structure, reducing the lateral dimensions of the memory cell structure. Additionally, the tops of the floating gate and control gate are flush, increasing the vertical thickness of the floating gate and ensuring the storage capacity of the memory cell structure. This, in turn, ensures the read window and the cyclic characteristics of write and erase operations, improving the performance of the memory cell. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a memory cell structure;

[0018] Figures 2 to 13 This is a schematic diagram of the formation process of a memory cell structure in one embodiment of the present invention;

[0019] Figure 14 This is a schematic diagram of a storage array structure in one embodiment of the present invention. Detailed Implementation

[0020] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0021] The current formation of memory cell structures can be referenced. Figure 1The system includes: a substrate 100, the substrate 100 including a plurality of first regions I arranged along a first direction, and a second region II located between adjacent first regions I, the adjacent first regions I being axially symmetrically distributed along the second region II; a memory cell located in the first region I, the memory cell including a floating gate structure 105 located on the surface of the substrate 100, a control gate structure 106 located on the surface of the floating gate structure 105, a bit line structure 101 located on the surface of the substrate 100, a word line structure 108 located between the bit line structure 101 and the floating gate structure 105, and a channel region 102 located on the bottom surface of the word line structure 108; an erase gate structure 104 located in the second region II, and a source line structure 103 located on the bottom surface of the erase gate structure 104.

[0022] In this embodiment, the storage cell structure further includes a conductive plug structure 109 located on the surface of the bit line structure 101, the word line structure 108, the control gate structure 106, and the erase gate structure 104.

[0023] In this embodiment, the surface of the control gate structure 106 further includes a first dielectric layer 107, and the conductive plug structure 109 penetrates the first dielectric layer 107.

[0024] In this embodiment, the storage cell structure further includes: an erase gate structure 104 and a second dielectric layer 110 of conductive plug structure 109 in the second region II.

[0025] In the above schemes, in order to reduce the area of ​​the storage cell structure, the size of the conductive plugs of the word line structure and control gate structure in the storage cell and the size of the peripheral control circuit are compressed. However, the size of the floating gate structure 105 cannot be reduced significantly because the total electronic storage capacity must be guaranteed. Too low a storage capacity of the floating gate structure 105 will reduce the data read window and the cyclic characteristics of write and erase operations, thereby reducing the performance of the memory. Therefore, the area reduction of the above schemes is limited and affects the performance of the storage cell, which is not conducive to the integration of the memory.

[0026] To address the aforementioned technical problems, the present invention provides a semiconductor structure and its formation method. Without affecting the basic operation of the memory cell, the word line structure and erase gate are omitted, reducing the area of ​​the memory cell. Furthermore, by utilizing the transposed structure of the floating gate and the control gate, a vertical electron transport channel is realized in the memory cell structure, reducing the lateral dimension of the memory cell structure and increasing the size of the floating gate, thereby ensuring the storage capacity of the memory cell structure and improving the performance of the memory cell.

[0027] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] Figures 2 to 13 This is a schematic diagram of the formation process of a memory cell structure in one embodiment of the present invention.

[0029] Please refer to Figure 2 A substrate 200 is provided; a first ion implantation process is performed on the substrate 200 to form a well region 201 located within the substrate 200.

[0030] In this embodiment, the substrate 200 is made of silicon.

[0031] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0032] The ion implantation type of the first ion implantation treatment is P-type or N-type.

[0033] In this embodiment, the ion implantation type of the first ion implantation treatment is P-type, and the concentration range of the first ion implantation treatment is 1E11atom / cm³. 3 Up to 1E14atom / cm 3 .

[0034] Please refer to Figure 3 A photoresist layer (not shown in the figure) with a source line structure 203 pattern and a bit line structure 204 pattern is formed on the well region 201. The well region 201 is etched using the photoresist layer (not shown in the figure) as a mask to form the bit line structure 204 and the source line structure 203. A first opening 202 is provided between the bit line structure 204 and the source line structure 203.

[0035] The first opening 202 is used to accommodate the subsequently formed floating gate 2101 structure and control gate 212.

[0036] The method of forming the first opening 202 includes one or a combination of wet etching and dry etching processes.

[0037] The wet etching process parameters include: the etching solution includes at least two of the following: ammonia, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration of each solution ranges from 0 wt% to 30 wt%, and the reaction temperature ranges from 0 degrees Celsius to 80 degrees Celsius.

[0038] The process parameters of the dry etching process include: the etching gas includes at least three gases selected from fluorine, hydrogen, nitrogen, argon and ammonia, and the flow rate of each gas ranges from 0 mL / min to 2000 mL / min; the reaction pressure ranges from 0 mT to 3000 mT; the reaction temperature ranges from 0 degrees Celsius to 250 degrees Celsius; and the etching power ranges from 0 W to 1000 W.

[0039] In the above scheme, the bit line structure 204 has a source line structure 203 on each side, that is, adjacent memory cells share a bit line structure 204, thereby reducing the size of the memory cell structure in the horizontal direction.

[0040] Furthermore, the bit line structure 204 in the technical solution of this invention can be flexibly adjusted according to the technology node. Taking nodes below 14 nanometers as an example, by compressing the size of the bit line structure 204, the longitudinal channel of the bit line structure 204 is controlled, thereby improving the control capability of the memory cell structure over the channel, reducing charge leakage, and thus improving the performance of the memory cell.

[0041] Please refer to Figure 4 After the source line structure 203 is formed, a second ion implantation process is performed on the sidewall surface and top surface of the source line structure 203 to form the source line doped region 205.

[0042] The ion type of the second ion implantation treatment is N-type or P-type, and the ion type of the first ion implantation treatment is the opposite of the ion type of the second ion implantation treatment.

[0043] In this embodiment, the ion type for the second ion implantation treatment is N-type, and the concentration range of the second ion implantation treatment is 1E13 atom / cm³. 3 Up to 5E15atom / cm 3 .

[0044] Please refer to Figure 5 A protective layer 206 is formed on the substrate 200. The protective layer 206 is located inside the first opening 202, on the top surface of the source line structure 203, and on the top surface of the bit line structure 204.

[0045] The protective layer 206 is formed by one or more of the following processes: chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition. The deposition gas includes hydrogen and silane, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0046] The protective layer 206 is made of one or more of the following materials: silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0047] Please refer to Figure 6A gate structure 207 is formed in the first opening 202 and on the substrate 200; the gate structure 207 is planarized until the top surface of the protective layer 206 is exposed, thus forming the gate structure 207.

[0048] The materials of the gate structure 207 include: monocrystalline silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0049] The method for forming the gate structure 207 includes one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition, wherein the deposition gas includes hydrogen and silane, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0050] In this embodiment, the planarization method includes mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical mechanical polishing, through the combined action of chemicals and machinery, avoids the surface damage caused by purely mechanical polishing and the drawbacks of purely chemical polishing, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nanoscale.

[0051] Please refer to Figure 7 A second photoresist layer 208 is formed on the top surface of the protective layer 206 on the source line structure 203; using the second photoresist layer 208 as a mask, the bottom surface of the first opening 202 and the protective layer 206 on the surface of the bit line structure 204 are etched until the surface of the well region 201 is exposed.

[0052] In this embodiment, a dry etching process is used to remove the protective layer 206 on the bottom surface of the first opening 202 and the surface of the bit line structure 204. The process parameters of the dry etching process are: chamber pressure of 5mT to 15mT, source power of 350W to 1200W, bias voltage of 150V to 600V, gas flow rate of 20sccm to 200sccm, and etching time of 8s to 60s.

[0053] Please refer to Figure 8 Using the second photoresist layer as a mask, a floating gate dielectric layer 209 is formed on the bottom surface of the first opening 202 and the surface of the bit line structure 204.

[0054] The material of the floating gate dielectric layer 209 is one or more combinations of silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0055] The method for forming the floating gate dielectric layer 209 includes one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition, wherein the deposition gas includes hydrogen and silane, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0056] Please refer to Figure 9 Using the second photoresist layer as a mask, a floating gate layer 210 is formed on the floating gate dielectric layer 209.

[0057] The materials of the floating gate layer 210 include: monocrystalline silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0058] The method for forming the floating gate layer 210 includes one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition, wherein the deposition gas includes hydrogen and silane, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0059] Please refer to Figure 10 A first photoresist layer 2081 with a control gate 212 pattern is formed on the floating gate layer 210; a portion of the floating gate layer 210 is etched using the first photoresist layer 2081 as a mask to form a floating gate 2101, and a second opening is provided between the floating gate 2101 and the source line structure 203.

[0060] The thickness of the floating grid 2101 ranges from 1000 angstroms to 3000 angstroms.

[0061] In this embodiment, the floating gate 2101 is L-shaped.

[0062] In this embodiment, a dry etching process is used to remove the protective layer 206 on the bottom surface of the first opening 202 and the surface of the bit line structure 204. The process parameters of the dry etching process are: chamber pressure of 5mT to 15mT, source power of 350W to 1200W, bias voltage of 150V to 600V, gas flow rate of 20sccm to 200sccm, and etching time of 8s to 60s.

[0063] Please refer to Figure 11 A control gate dielectric layer 211 is formed on the bottom surface of the second opening, the side wall surface of the source line structure 203, and the side wall surface of the floating gate 2101 structure.

[0064] The method of forming the control gate dielectric layer 211 includes: forming a first dielectric layer 2111 in the second opening and on the surface of the protective layer 206; forming a second dielectric layer 2112 on the first dielectric layer 2111; and forming a third dielectric layer 2113 on the second dielectric layer 2112.

[0065] In this embodiment, the control gate dielectric layer 211 has an ONO structure, the first dielectric layer 2111 is made of silicon oxide, the second dielectric layer 2112 is made of silicon nitride, and the third dielectric layer 2113 is made of silicon oxide.

[0066] The process for forming the control gate dielectric layer 211 is one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition. The deposition gas includes hydrogen and silane, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0067] Please refer to Figure 12 The control gate dielectric layer 211 is planarized until the top surface of the protective layer 206 and the surface of the floating gate layer 210 are exposed.

[0068] In this embodiment, the planarization method includes mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical mechanical polishing, through the combined action of chemicals and machinery, avoids the surface damage caused by purely mechanical polishing and the drawbacks of purely chemical polishing, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nanoscale.

[0069] In this embodiment, a control gate 212 is also formed on the control gate dielectric layer 211.

[0070] The materials of the control gate 212 include: monocrystalline silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0071] The method of forming the control gate 212 includes one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition, wherein the deposition gas includes hydrogen and silane, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0072] The thickness of the control gate 212 ranges from 700 angstroms to 2700 angstroms.

[0073] Please refer to Figure 13A first interlayer dielectric layer 2131 is formed on the top surface of the control gate 212, the floating gate 2101, the source line structure 203, and the bit line structure 204; a second interlayer dielectric layer 2132 is formed on the first interlayer dielectric layer 2131; the first interlayer dielectric layer 2131, the second interlayer dielectric layer 2132, and the floating gate dielectric layer 209 on the top surface of the bit line structure 204 are etched until the surface of the bit line structure 204 is exposed, forming an opening (not shown in the figure); a conductive plug 214 is formed in the opening (not shown in the figure), and the conductive plug 214 is located on the top surface of the bit line structure 204.

[0074] In other embodiments, the method further includes: etching the first interlayer dielectric layer 2131 and the second interlayer dielectric layer 2132 on the top surface of the control gate 212 structure until the top surface of the control gate 212 is exposed to form an opening; forming a conductive plug 214 in the opening (not shown in the figure), the conductive plug 214 being located on the top surface of the bit line structure 204.

[0075] The materials of the first interlayer dielectric layer 2131 and the second interlayer dielectric layer 2132 are one or more combinations of silicon oxide, nitrogen-doped silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0076] The etching process for the opening includes dry etching, wherein the process parameters for dry etching are as follows: the etching gas is at least three of the following: fluorine, hydrogen, nitrogen, argon and ammonia, the flow rate of each gas is in the range of 0 mL / min to 2000 mL / min, the reaction pressure is in the range of 0 mT to 3000 mT, the reaction temperature is in the range of 0 degrees Celsius to 250 degrees Celsius, and the etching power is in the range of 0 W to 1000 W.

[0077] In this embodiment, the conductive plug 214 is made of aluminum and copper.

[0078] In the above scheme, the area of ​​the memory cell is reduced by omitting the word line structure and the erase gate. Furthermore, the floating gate 2101 structure and the control gate 212 structure are formed between the bit line structure 204 and the source line structure 203, realizing a vertical electron transport channel in the memory cell structure and reducing the lateral size of the memory cell structure. Taking a 55-nanometer node as an example, the area of ​​the memory cell structure can be reduced to 0.04 square micrometers. In addition, the increased thickness of the floating gate 2101 structure in the vertical direction ensures the storage capacity of the memory cell structure, thereby ensuring the read window and the cyclic characteristics of write and erase operations, and improving the performance of the memory cell.

[0079] The following will combine Figure 13The working principle of the writing and erasing processes of the storage cell structure in this embodiment is explained.

[0080] Specifically, during the writing process, the memory cell structure applies a high voltage (greater than 10V) to the control gate 212, which couples the voltage to the floating gate 2101. This causes the channel below the floating gate 2101 to open and form a strong vertical electric field. A large voltage difference is applied between the source line structure 203 and the bit line structure 204 to generate a conduction current. Due to the large voltage difference and high carrier energy, the strong vertical electric field accelerates the hot carriers in the channel in the vertical direction, allowing them to pass through the floating gate dielectric layer 209 and be injected into the floating gate 2101. The source-side hot electron injection (SSHEI) principle is used to tunnel electrons from the channel into the floating gate 2101, thereby achieving signal writing.

[0081] As can be seen, the storage cell of the present invention can realize the write operation of the storage cell without the need for a word line structure, which ensures the performance of the storage cell and reduces the area of ​​the storage cell.

[0082] Specifically, during the erasure process, the memory cell structure applies a high voltage (greater than 10V) to the source structure. Due to the coupling capacitor, a potential difference is formed on the protective layer 206, which is sufficient to pull the electrons written in the floating gate 2101 to the source structure through the tunneling mechanism, thereby clearing the electrons stored in the floating gate 2101.

[0083] Please continue to refer to this. Figure 13 The erasure sites are mainly located at the junction of the floating gate 2101 and the source structure. The electrons in the floating gate 2101 are erased by using the tunneling principle.

[0084] As can be seen, in the storage cell of the present invention, the erasure operation of the storage cell can be realized without erasing the gate, which ensures the performance of the storage cell and reduces the area of ​​the storage cell.

[0085] Figure 14 This is a schematic diagram of a storage array structure in an embodiment of the present invention.

[0086] Please refer to Figure 14 The storage array structure includes several storage cell structures 301, with each row of storage cell structures connected to a bit line and each column of storage cell structures connected to a source line.

[0087] In this embodiment, the storage cell structure in the second row and second column is selected for write, read, or erase operations.

[0088] In this embodiment, the voltage and current values ​​in the memory cell structure are shown in Tables 1, 2, and 3:

[0089]

[0090] Table 1

[0091]

[0092] Table 2

[0093]

[0094] Table 3

[0095] In Table 1, the values ​​in each column represent the voltage or current values ​​of source line 1 (SL1), source line 2 (SL2), and source line 3 (SL3) under different operating types.

[0096] The values ​​in each column of Table 2 represent the voltage or current values ​​of bit line 1 (BL1), bit line 2 (BL2), bit line 3 (BL3), and bit line 4 (BL4) under different operating types.

[0097] The values ​​in each column of Table 3 represent the voltage or current values ​​of the control gate (CG1) and control gate (CG2) under different operating types.

[0098] In the above scheme, since the storage cell structure in the second row and second column is the selected storage cell structure, that is, source line 2 (SL2), bit line 2 (BL2) and control gate (CG1) are read ends.

[0099] Accordingly, embodiments of the present invention also provide a storage unit structure, please refer to [the relevant documentation]. Figure 13 The system includes: a substrate 200; a source line structure 203 located within the substrate 200; a bit line structure 204 located within the substrate 200, with a first opening between the bit line structure 204 and the source line structure 203; a floating gate dielectric layer 209 located on the bottom surface of the first opening and the surface of the bit line structure 204; a floating gate 2101 located on the floating gate dielectric layer 209, with a second opening between the floating gate 2101 and the source line structure 203; a control gate dielectric layer 211 located on the bottom surface of the second opening, the sidewall surface of the source line structure 203, and the sidewall surface of the floating gate 2101; and a control gate 212 located on the control gate dielectric layer 211.

[0100] In summary, the memory cell structure of this invention reduces the area of ​​the memory cell by omitting the word line structure and the erase gate. During write operations, pressure is applied to the control gate to allow electrons to enter the floating gate. During erase operations, the electrons written are pulled into the source line structure, thereby clearing the electrons stored in the floating gate. This ensures the basic operation process of the memory cell. Furthermore, by forming a floating gate and a control gate between the bit line structure and the source line structure, a vertical electron transport channel is created in the memory cell structure, reducing the lateral dimensions of the memory cell structure. In addition, the tops of the floating gate and the control gate are flush, increasing the vertical thickness of the floating gate and ensuring the storage capacity of the memory cell structure. This, in turn, ensures the read window and the cyclic characteristics of write and erase operations, improving the performance of the memory cell.

[0101] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a storage cell structure, characterized in that, include: Provide substrate; The substrate is etched to form a source line structure and a bit line structure, wherein a first opening is provided between the bit line structure and the source line structure. A floating gate dielectric layer is formed on the bottom surface of the first opening and on the surface of the bit line structure; A floating gate layer is formed on the floating gate dielectric layer; A first photoresist layer with a control gate pattern is formed on the floating gate layer; Using the first photoresist layer as a mask, a portion of the floating gate layer is etched to form a floating gate, and a second opening is provided between the floating gate and the source line structure; A control gate dielectric layer is formed on the bottom surface of the second opening, the sidewall surface of the source line structure, and the sidewall surface of the floating gate; A control gate is formed on the control gate dielectric layer.

2. The method for forming a storage cell structure as described in claim 1, characterized in that, The steps for forming the source line structure and the bit line structure include: Ion implantation is performed on the surface of the substrate to form a well region located within the substrate; A second photoresist layer with source line structure pattern and bit line structure pattern is formed on the well region; the well region is etched using the second photoresist layer as a mask to form the bit line structure and the source line structure.

3. The method for forming a storage cell structure as described in claim 2, characterized in that, The ion type for the ion implantation treatment is P-type or N-type, and the concentration range for the ion implantation treatment is 1E11 atom / cm³. 3 Up to 1E14atom / cm 3 .

4. The method for forming a storage cell structure as described in claim 2, characterized in that, The method for etching the well region is dry etching. The process parameters for dry etching are as follows: the etching gas is at least three of the following: fluorine, hydrogen, nitrogen, argon and ammonia; the flow rate of each gas ranges from 0 mL / min to 2000 mL / min; the reaction pressure ranges from 0 mT to 3000 mT; the reaction temperature ranges from 0 degrees Celsius to 250 degrees Celsius; and the etching power ranges from 0 W to 1000 W.

5. The method for forming a storage cell structure as described in claim 1, characterized in that, The method for forming the floating gate dielectric layer and the floating gate layer is chemical vapor deposition (CVD). The parameters of the CVD process are as follows: the deposition gas includes hydrogen and silane, and the reaction temperature range is 400 degrees Celsius to 800 degrees Celsius.

6. The method for forming a memory cell structure as described in claim 1, characterized in that, The method for etching the floating gate layer is dry etching. The process parameters for dry etching are as follows: the etching gas is at least three of the following: fluorine, hydrogen, nitrogen, argon and ammonia; the flow rate of each gas ranges from 0 mL / min to 2000 mL / min; the reaction pressure ranges from 0 mT to 3000 mT; the reaction temperature ranges from 0 degrees Celsius to 250 degrees Celsius; the etching power ranges from 0 W to 1000 W; and the thickness of the floating gate ranges from 1000 angstroms to 3000 angstroms.

7. The method for forming a storage cell structure as described in claim 1, characterized in that, The steps for forming the control gate dielectric layer include: A first dielectric layer is formed on the bottom surface of the second opening, the sidewall surface of the source line structure, and the sidewall surface of the floating gate; A second dielectric layer is formed on the first dielectric layer; A third dielectric layer is formed on the second dielectric layer, wherein the material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer.

8. The method for forming a memory cell structure as described in claim 1, characterized in that, The method for forming the control gate dielectric layer and the control gate is a chemical vapor deposition process, wherein the parameters of the chemical vapor deposition process are: the deposition gas includes hydrogen and silane, the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius, and the thickness of the control gate ranges from 700 angstroms to 2700 angstroms.

9. The method for forming a storage cell structure as described in claim 1, characterized in that, Following the step of forming the control barrier, the following is also included: A dielectric layer is formed on the substrate, the dielectric layer covering the source line structure, the bit line structure, the floating gate, and the control gate surface; A conductive plug extending through the thickness of the dielectric layer is formed within the dielectric layer.

10. A storage cell structure, characterized in that, include: Substrate; The source line structure is located within the substrate; A bit line structure is located within the substrate, and a first opening is provided between the bit line structure and the source line structure. A floating gate dielectric layer is located on the bottom surface of the first opening and the surface of the bit line structure; A floating gate is located on the floating gate dielectric layer, and a second opening is provided between the floating gate and the source line structure; A control gate dielectric layer is located on the bottom surface of the second opening, the sidewall surface of the source line structure, and the sidewall surface of the floating gate; A control gate is located on the control gate dielectric layer.

Images