Trench MOSFET and manufacturing method thereof

Abstract

The invention provides a trench MOSFET and a manufacturing method thereof, and the method comprises the steps: forming a trench, a shield gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shield gate, a control gate, a body region, a source region, and a dielectric layer; a first contact hole penetrating through the dielectric layer and the source region and extending into the body region and a second contact hole penetrating through the dielectric layer, the control gate and the isolation oxide layer and exposing the shield gate are formed, a subsequently formed source metal layer is electrically connected with the source region and the body region through the first contact hole, and a gate metal layer is electrically connected with the control gate and the shield gate through the second contact hole. When the trench MOSFET provided by the invention is in forward conduction, because the shield grid is connected to the control grid, an electron accumulation layer is formed on the side wall of the shield grid, so that the conduction resistance is reduced. Besides, in the manufacturing process of the trench MOSFET, the number of photomasks can be reduced, for example, only three photomasks corresponding to the trench, the contact hole and the metal layer respectively are needed, and the production cost can be reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power transistor technology, and relates to a trench MOSFET and its manufacturing method. Background Technology

[0002] Power transistors are generally used to control the proper operation of power electronic devices, enabling them to provide high-power output to loads. Power transistors are widely used for controlling power output; high-frequency, high-power transistors are used in scanning circuits of electronic devices, such as color TVs, monitors, oscilloscopes, horizontal scanning circuits in large-scale game consoles, video amplifier circuits, and power amplifiers in transmitters.

[0003] Generally speaking, power devices typically operate under high voltage and high current conditions, and generally possess characteristics such as high withstand voltage, large operating current, and high self-dissipation power. Therefore, their usage differs somewhat from that of general low-power devices. To ensure the optimal functioning of switching devices, power semiconductor field-effect transistors (FETs) must meet two basic requirements: 1. When the device is in the on-state, it must possess very low on-resistance to minimize its own power loss; 2. When the device is in the off-state, it must possess sufficiently high reverse breakdown voltage.

[0004] Existing power transistors generally employ superjunction transistor structures. However, the fabrication process of superjunction transistors is complex. Due to the influence of processes such as annealing, the interdiffusion of ions within the superjunction can easily lead to a significant deviation between the actual doping concentration and the actual value. Furthermore, the breakdown voltage of superjunction transistors is highly sensitive to ion doping concentration, greatly increasing the difficulty of fabrication, especially for devices with high doping concentration and low junction width. Moreover, superjunction power transistors are generally used in high-voltage or medium-high-voltage circuits. Because the width of superjunction power transistors is limited, it is difficult to implement conventional superjunction power transistors for circuits with voltages less than 180V. Additionally, the continuous reduction in semiconductor device size limits the increase in the distance between deep trench electrodes in transistors with side-on-the-edge (OB) structures, further increasing the complexity of the trench gate structure and source contact electrode formation, ultimately leading to increased device fabrication difficulty and cost.

[0005] Therefore, how to provide a trench MOSFET and its manufacturing method to achieve sufficiently high reverse breakdown voltage and sufficiently low on-resistance, while reducing process difficulty and production cost, has become an important technical problem that urgently needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench MOSFET and its manufacturing method, so as to solve the problems of high process difficulty and high production cost in the preparation of high-performance power transistors in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a method for manufacturing a trench MOSFET, comprising the following steps:

[0009] A preliminary structure is provided, the preliminary structure including a substrate, a trench formed on the upper surface of the substrate, and a shielding gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shielding gate, and a control gate located in the trench. The control gate oxide layer is located above the shielding gate oxide layer, the isolation oxide layer is located between the control gate and the shielding gate, the shielding gate oxide layer is located between the outer wall of the shielding gate and the inner wall of the trench, and the control gate oxide layer is located between the sidewall of the shielding gate and the sidewall of the trench.

[0010] A body region is formed on the upper surface of the substrate, and a source region is formed on the upper surface of the body region;

[0011] A dielectric layer is formed on the substrate and a first contact hole and a second contact hole are formed. The first contact hole penetrates the dielectric layer and the source region and extends into the body region. The second contact hole penetrates the dielectric layer, the control gate and the isolation oxide layer and exposes the shielding gate.

[0012] A source metal layer and a gate metal layer are formed on the dielectric layer with spacing between them. The source metal layer is electrically connected to the source region and the body region through the first contact hole, and the gate metal layer is electrically connected to the control gate and the shielding gate through the second contact hole.

[0013] Optionally, the formation of the preceding structure includes the following steps:

[0014] The trench is formed in the substrate;

[0015] A first oxide layer is formed, which conformally covers the inner wall of the trench and the upper surface of the substrate;

[0016] A first polysilicon layer is deposited, which fills the trench and covers the surface of the first oxide layer outside the trench;

[0017] The first polysilicon layer is etched back to obtain the shielding gate;

[0018] Remove the portion of the first oxide layer above the shielding gate to obtain the shielding gate oxide layer;

[0019] The control gate oxide layer and the isolation oxide layer are formed;

[0020] A second polysilicon layer is deposited and etched back to obtain the control gate.

[0021] Optionally, a photomask was not used during the deposition and etch-back of the first polysilicon layer.

[0022] Optionally, in the preceding structure, the upper surface of the control gate is lower than or flush with the upper surface of the substrate, and the distance between the upper surface of the control gate and the upper surface of the substrate is in the range of 0 to 0.2 micrometers.

[0023] Optionally, the first contact hole and the second contact hole are etched simultaneously.

[0024] Optionally, the simultaneous etching includes dry etching. When simultaneously etching to the control gate and the substrate, the etching gases used include HBr, Cl2, and O2, and the etching selectivity ratio of polysilicon to silicon ranges from 1.5:1 to 4:1. When simultaneously etching to the isolation oxide layer and the substrate, the etching gases used include CHF3, O2, and Ar, and the etching selectivity ratio of silicon oxide to silicon ranges from 10:1 to 20:1.

[0025] Optionally, the depth of the first contact hole ranges from 0.3 micrometers to 0.6 micrometers, and the depth of the second contact hole ranges from 0.8 micrometers to 2 micrometers.

[0026] Optionally, in the extending direction of the trench, the length of the first contact hole is greater than the length of the second contact hole.

[0027] The present invention also provides a trench MOSFET, comprising:

[0028] The preceding structure includes a substrate, a trench formed on the upper surface of the substrate, and a shielding gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shielding gate, and a control gate located in the trench. The control gate oxide layer is located above the shielding gate oxide layer, the isolation oxide layer is located between the control gate and the shielding gate, the shielding gate oxide layer is located between the outer wall of the shielding gate and the inner wall of the trench, and the control gate oxide layer is located between the sidewall of the shielding gate and the sidewall of the trench.

[0029] The body region is located on the upper surface layer of the substrate;

[0030] The source region is located on the upper surface layer of the body region;

[0031] A dielectric layer is located on the substrate;

[0032] The first contact hole penetrates the dielectric layer and the source region and extends into the body region;

[0033] The second contact hole penetrates the dielectric layer, the control gate, and the isolation oxide layer, and exposes the shielding gate.

[0034] A source metal layer is located on the dielectric layer and electrically connected to the source region and the body region through the first contact hole.

[0035] A gate metal layer is located on the dielectric layer and electrically connected to the control gate and the shielding gate through the second contact hole.

[0036] Optionally, the depth of the first contact hole ranges from 0.3 micrometers to 0.6 micrometers, and the depth of the second contact hole ranges from 0.8 micrometers to 2 micrometers.

[0037] As described above, the trench MOSFET manufacturing method of the present invention, after forming a trench, a shielding gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shielding gate, a control gate, a body region, a source region, and a dielectric layer, forms a first contact hole and a second contact hole. The first contact hole penetrates the dielectric layer and the source region and extends into the body region. The second contact hole penetrates the dielectric layer, the control gate, and the isolation oxide layer and exposes the shielding gate. Then, a source metal layer and a gate metal layer, spaced apart, are formed on the dielectric layer. The source metal layer is electrically connected to the source region and the body region through the first contact hole, and the gate metal layer is electrically connected to the control gate and the shielding gate through the second contact hole. In the trench MOSFET of the present invention, the shielding gate and the control gate in the trench are electrically connected through the second contact hole. When the device is forward-biased, because the shielding gate is connected to the control gate, an electron accumulation layer is formed on the sidewall of the shielding gate, thereby reducing the on-resistance. Furthermore, the number of photomasks can be reduced during the manufacturing process of the trench MOSFET of the present invention; for example, only three photomasks are needed, corresponding to the trench, the contact hole, and the metal layer respectively, which helps to reduce production costs. Attached Figure Description

[0038] Figure 1 The diagram shown is a process flow diagram of the trench MOSFET manufacturing method of the present invention.

[0039] Figure 2 This is a layout of a trench MOSFET that will be manufactured.

[0040] Figure 3The diagram shows a preliminary structure provided by the method for manufacturing a trench MOSFET according to the present invention.

[0041] Figure 4 The diagram shows a schematic of the structure obtained after forming a trench in a substrate according to the trench MOSFET manufacturing method of the present invention.

[0042] Figure 5 The diagram shown is a schematic of the structure obtained after forming the first oxide layer in the trench MOSFET manufacturing method of the present invention.

[0043] Figure 6 The diagram shows the structure obtained after depositing a first polysilicon layer in the trench MOSFET manufacturing method of the present invention.

[0044] Figure 7 The diagram shows a schematic of the structure obtained after etching back the first polysilicon layer to obtain a shielding gate in the manufacturing method of the trench MOSFET of the present invention.

[0045] Figure 8 The diagram shows the structure obtained after forming a shielding gate oxide layer, a control gate oxide layer, and an isolation oxide layer in the trench MOSFET manufacturing method of the present invention.

[0046] Figure 9 The diagram shown is a schematic of the structure obtained after forming the body region in the manufacturing method of the trench MOSFET of the present invention.

[0047] Figure 10 The diagram shown is a schematic of the structure obtained after forming the source region in the trench MOSFET manufacturing method of the present invention.

[0048] Figure 11 The diagram shown is a schematic diagram of the structure obtained after forming the first contact hole and the second contact hole in the trench MOSFET manufacturing method of the present invention, in section S.

[0049] Figure 12 The diagram shown is a schematic diagram of the structure obtained after forming the first contact hole and the second contact hole in the trench MOSFET manufacturing method of the present invention, in section G.

[0050] Figure 13 The diagram shown is a schematic diagram of the structure obtained after forming the source metal layer and the gate metal layer in the trench MOSFET manufacturing method of the present invention, in section S.

[0051] Figure 14 The diagram shown is a schematic diagram of the structure obtained after forming the source metal layer and the gate metal layer in the trench MOSFET manufacturing method of the present invention, in section G.

[0052] Figure 15The image shown is a simulation diagram of a trench MOSFET manufactured using the trench MOSFET manufacturing method of the present invention.

[0053] Figure 16 The image shown is a simulation diagram of a trench MOSFET as a comparative example.

[0054] Explanation of reference numerals in the attached figures

[0055] Steps S1 to S4 100 substrate

[0056] 101 Trench

[0057] 102 Source Metal Layer

[0058] 103 Gate metal layer

[0059] 104 First contact hole

[0060] 105 Second Contact Hole

[0061] 106 Shielding gate oxide layer

[0062] 106a First Oxide Layer

[0063] 107 Control gate oxide layer

[0064] 108 Isolation Oxide Layer

[0065] 109 Shielding fence

[0066] 109a First polycrystalline silicon layer

[0067] 110 Control gate

[0068] 111 Body Area

[0069] 112 source region

[0070] 113 Dielectric Layer

[0071] 114 Electron Accumulation Layer Detailed Implementation

[0072] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0073] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0074] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0075] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0076] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0077] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0078] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0079] This invention provides a method for manufacturing a trench MOSFET. Please refer to [link / reference]. Figure 1 The diagram shows the process flow of this method, which includes the following steps:

[0080] S1: A preceding structure is provided, the preceding structure including a substrate, a trench formed on the upper surface of the substrate, and a shielding gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shielding gate, and a control gate located in the trench. The control gate oxide layer is located above the shielding gate oxide layer, the isolation oxide layer is located between the control gate and the shielding gate, the shielding gate oxide layer is located between the outer wall of the shielding gate and the inner wall of the trench, and the control gate oxide layer is located between the sidewall of the shielding gate and the sidewall of the trench.

[0081] S2: A body region is formed on the upper surface of the substrate, and a source region is formed on the upper surface of the body region;

[0082] S3: A dielectric layer is formed on the substrate and a first contact hole and a second contact hole are formed. The first contact hole penetrates the dielectric layer and the source region and extends into the body region. The second contact hole penetrates the dielectric layer, the control gate and the isolation oxide layer and exposes the shielding gate.

[0083] S4: A source metal layer and a gate metal layer are formed on the dielectric layer with a spacing between them. The source metal layer is electrically connected to the source region and the body region through the first contact hole, and the gate metal layer is electrically connected to the control gate and the shielding gate through the second contact hole.

[0084] For example, please refer to Figure 2 The diagram shows a layout of the trench MOSFET to be manufactured, illustrating multiple trenches 101, a source metal layer 102, a gate metal layer 103, multiple first contact holes 104, and multiple second contact holes 105. The trenches 101 are arranged sequentially and at intervals in the X direction, and all trenches 101 extend in the Y direction. The source metal layer 102 and the gate metal layer 103 are arranged sequentially and at intervals in the Y direction, and both the source metal layer 102 and the gate metal layer 103 extend in the X direction. The source metal layer 102 is electrically connected to the source region and the body region through the first contact holes 104 disposed on both sides of the trenches 101. The gate metal layer 103 is electrically connected to the control gate and the shield gate through the second contact holes 105 disposed on the trenches 101.

[0085] As an example, in the extending direction (Y direction) of the groove 101, the length of the first contact hole 104 is greater than the length of the second contact hole 105.

[0086] The following describes in detail each step of the trench MOSFET manufacturing method of the present invention with reference to the structural diagram.

[0087] Please refer to the following first. Figure 3Step S1 is performed: a preliminary structure is provided, the preliminary structure including a substrate 100, a trench 101 formed on the upper surface of the substrate 100, and a shielding gate oxide layer 106, a control gate oxide layer 107, an isolation oxide layer 108, a shielding gate 109, and a control gate 110 located in the trench 101. The control gate oxide layer 107 is located above the shielding gate oxide layer 106, the isolation oxide layer 108 is located between the control gate 110 and the shielding gate 109, the shielding gate oxide layer 106 is located between the outer wall of the shielding gate 109 and the inner wall of the trench 101, and the control gate oxide layer 107 is located between the sidewall of the shielding gate 109 and the sidewall of the trench 101.

[0088] In some embodiments, the substrate 100 includes an epitaxial layer, and the trench 101 is formed in the epitaxial layer.

[0089] In some embodiments, the formation of the pre-structure includes the following steps:

[0090] (1) Please refer to Figure 4 The trench 101 is formed in the substrate 100 by dry etching and / or wet etching. The depth of the trench 101 can be in the range of 2 micrometers to 20 micrometers, and the width of the trench 101 can be in the range of 0.8 micrometers to 6 micrometers.

[0091] (2) Please refer to Figure 5 A first oxide layer 106a is formed by growth or deposition. The first oxide layer 106a conformally covers the inner wall of the trench 101 and the upper surface of the substrate 100. The thickness of the first oxide layer 106a can be in the range of 100nm to 700nm, and can be adjusted according to actual needs.

[0092] (3) Please refer to Figure 6 A first polysilicon layer 109a is deposited, which fills the trench 101 and covers the surface of the first oxide layer 106a outside the trench 101. The thickness of the first polysilicon layer 109a can be 1 micrometer to 5 micrometers.

[0093] (4) Please refer to Figure 7 The first polysilicon layer 109a is etched back to obtain the shielding gate 109. Before etching back the first polysilicon layer 109a, a chemical mechanical polishing process can be performed to remove the first polysilicon layer 109a above the substrate 100. After etching back, the upper surface of the shielding gate 109 is lower than the upper surface of the substrate 100 by a predetermined distance. The predetermined distance can be in the range of 0.6 micrometers to 2 micrometers.

[0094] (5) Please refer to Figure 8 The portion of the first oxide layer 106a above the shielding gate 109 is removed to obtain the shielding gate oxide layer 106. Then, the control gate oxide layer 107 and the isolation oxide layer 108 are formed. The control gate oxide layer 107 can be grown by thermal oxidation. The thickness of the control gate oxide layer 107 can be in the range of 300 angstroms to 1000 angstroms. The thickness of the isolation oxide layer 108 is greater than the thickness of the control gate oxide layer 107.

[0095] (6) Please refer to Figure 3 The control gate 110 is obtained by depositing a second polysilicon layer and etching back the second polysilicon layer. Before etching back the second polysilicon layer, a chemical mechanical polishing process can be performed to remove the second polysilicon layer above the substrate 100. After etching back, the upper surface of the control gate 110 is flush with or lower than the upper surface of the substrate 100. For example, the distance between the upper surface of the control gate 110 and the upper surface of the substrate 100 is in the range of 0 micrometers to 0.2 micrometers.

[0096] It should be noted that in the manufacturing process of trench MOSFETs, a shielding gate is usually required to be brought out in a specific area of ​​the trench. Therefore, when etching back the first polysilicon layer in the trench, the aforementioned specific area needs to be shielded to prevent the first polysilicon layer in the trench in that specific area from being etched back. In other words, a photomask corresponding to the first polysilicon layer is required. However, in the manufacturing process of the trench MOSFET of the present invention, since the shielding gate 109 will be electrically connected to the control gate 110 through the second contact hole 105 penetrating the control gate 110 and the isolation oxide layer 108, it is not necessary to bring out the shielding gate 109 separately in a specific area. Therefore, a photomask can be omitted during the deposition of the first polysilicon layer 109a and the etching back of the first polysilicon layer 109a in the trench. In other words, compared to the conventional trench MOSFET manufacturing process which requires four photomasks corresponding to the trench, the first polysilicon layer, the contact hole, and the metal layer respectively, the trench MOSFET manufacturing process of the present invention can reduce the number of photomasks. For example, only three photomasks corresponding to the trench, the contact hole, and the metal layer are needed, which is beneficial to reducing production costs.

[0097] Please refer to the following. Figure 9 and Figure 10 Perform step S2: First, implant first-type ions from the structural surface and perform high-temperature diffusion to form a bulk region 111 on the upper surface layer of the substrate 100 (e.g., Figure 9 As shown), a second type of ions is then implanted from the surface of the structure and subjected to high-temperature diffusion to form a source region 112 on the upper surface layer of the body region 111 (as shown). Figure 10 (As shown).

[0098] As an example, when forming the body region 111, the first type of ion can be boron (B) ions or other suitable ions, with an implantation dose range of 6e12-2e13 ions / cm². 2 (Ions / cm²), the implantation energy range is 70 keV-300 keV; when forming the source region 112, the first type of ion can be arsenic (As) ions or other suitable ions, and the implantation dose range is 1e15-2e16 ions / cm². 2 The energy range for injection is 60keV-200keV.

[0099] Please refer to the following. Figure 11 and Figure 12 Step S3 is performed: a dielectric layer 113 is formed on the substrate 100, and a first contact hole 104 and a second contact hole 105 are formed. The first contact hole 104 penetrates the dielectric layer 113 and the source region 112 and extends into the body region 111. The second contact hole 105 penetrates the dielectric layer 113, the control gate 110, and the isolation oxide layer 108 and exposes the shielding gate 109. Figure 11 Corresponding to Figure 2 Section S in Figure 12 Corresponding to Figure 2 Section G in the middle.

[0100] In some embodiments, the dielectric layer 113 is a silicon oxide layer.

[0101] In some embodiments, the first contact hole 104 and the second contact hole 105 are etched simultaneously.

[0102] In some embodiments, the synchronous etching includes dry etching, wherein the bottom surface of the second contact hole 105 can be made higher than the bottom surface of the second contact hole 105 by controlling the etching atmosphere.

[0103] In some embodiments, when simultaneously etching to the control gate 110 (polysilicon layer) and the substrate 100 (silicon layer), the etching gases used include HBr, Cl2 and O2, wherein HBr is used as the main etching agent to form silicon bromide, Cl2 is used as an auxiliary etching agent to improve the etching rate, and O2 can form a passivation layer to protect silicon.

[0104] As an example, when simultaneously etching the control gate 110 (polysilicon layer) and the substrate 100 (silicon layer), the etching selectivity ratio of polysilicon to silicon ranges from 1.5:1 to 4:1.

[0105] As an example, when the etching gases used include HBr, Cl2, and O2, the flow rate of HBr is 80 sccm to 150 sccm, the flow rate of Cl2 is 10 sccm to 40 sccm, the flow rate of O2 is 2 sccm to 10 sccm, the pressure in the etching chamber is 5 mTorr to 20 mTorr, the power of inductively coupled plasma (ICP) is 600 W to 1200 W, the bias power is 20 W to 70 W (the lower the value, the higher the selectivity), the temperature is 40 °C to 70 °C (often with back-side He cooling), and the etching rate of polysilicon is 100 nm / min to 300 nm / min.

[0106] In some embodiments, when simultaneously etching the isolation oxide layer 108 (silicon oxide layer) and the substrate 100 (silicon layer), the etching gases used include CHF3, O2 and Ar.

[0107] As an example, when simultaneously etching the isolation oxide layer 108 (silicon oxide layer) and the substrate 100 (silicon layer), the etching selectivity ratio of silicon oxide to silicon ranges from 10:1 to 20:1.

[0108] As an example, when the etching gases used include CHF3, O2, and Ar, the flow rate range of CHF3 is 35 sccm to 50 sccm, the flow rate range of O2 is 3 sccm to 8 sccm, the flow rate range of Ar is 10 sccm to 30 sccm, the pressure range within the etching chamber is 10 mTorr to 30 mTorr, the ICP power range is 600 W to 1200 W, the Bias power range is 30 W to 80 W, the temperature range is 20 °C to 30 °C, the etching rate range of silicon oxide is 150 nm / min to 250 nm / min, and the etching rate range of silicon is 10 nm / min to 20 nm / min.

[0109] As an example, the depth range of the first contact hole 104 is 0.3 micrometers to 0.6 micrometers, and the depth range of the second contact hole 105 is 0.8 micrometers to 2 micrometers.

[0110] Please refer to the following. Figure 13 and Figure 14 Execute step S4: Form a source metal layer 102 with spacing (e.g., Figure 13 (as shown) and gate metal layer 103 (as shown) Figure 14 As shown, on the dielectric layer 113, the source metal layer 102 is electrically connected to the source region 112 and the body region 111 through the first contact hole 104, and the gate metal layer 103 is electrically connected to the control gate 110 and the shielding gate 109 through the second contact hole 105.

[0111] As an example, a top surface metal layer is first deposited, the thickness of which ranges from 2 micrometers to 8 micrometers, and then the top surface metal layer is patterned to obtain the source metal layer 102 and the SS gate metal layer 103.

[0112] For example, please refer to Figure 15 and Figure 16 Simulation diagrams of trench MOSFETs formed using the trench MOSFET manufacturing method of the present invention are shown (e.g., Figure 15 Simulation diagrams of a trench MOSFET (as shown) and a comparative example (e.g.) Figure 16 As shown in the figure, in the trench MOSFET formed by the manufacturing method of the present invention, since the gate metal layer is electrically connected to the control gate and the shield gate through the second contact hole, when the device is forward conducting, an electron accumulation layer 114 is also formed on the sidewall of the shield gate, thereby reducing the on-resistance of the device.

[0113] In addition, the number of photomasks can be reduced during the manufacturing process of the trench MOSFET of the present invention. For example, only three photomasks are needed, corresponding to the trench, the contact hole and the metal layer respectively, which helps to reduce production costs.

[0114] The present invention also provides a trench MOSFET, which can be formed using the manufacturing method described in any of the above embodiments or other suitable methods. The trench MOSFET includes a preceding structure, a body region, a source region, a dielectric layer, a first contact hole, a second contact hole, a source metal layer, and a gate metal layer. The preceding structure includes a substrate, a trench formed on the upper surface of the substrate, and a shielding gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shielding gate, and a control gate located within the trench. The control gate oxide layer is located above the shielding gate oxide layer, the isolation oxide layer is located between the control gate and the shielding gate, and the shielding gate oxide layer is located on the outer wall of the shielding gate and the... Between the inner walls of the trench, the control gate oxide layer is located between the sidewall of the shielding gate and the sidewall of the trench. The body region is located on the upper surface layer of the substrate, the source region is located on the upper surface layer of the body region, and the dielectric layer is located on the substrate. The first contact hole penetrates the dielectric layer and the source region and extends into the body region. The second contact hole penetrates the dielectric layer, the control gate, and the isolation oxide layer and exposes the shielding gate. The source metal layer is located on the dielectric layer and is electrically connected to the source region and the body region through the first contact hole. The gate metal layer is located on the dielectric layer and is electrically connected to the control gate and the shielding gate through the second contact hole.

[0115] As an example, the depth range of the first contact hole is 0.3 micrometers to 0.6 micrometers, and the depth range of the second contact hole is 0.8 micrometers to 2 micrometers.

[0116] In the trench MOSFET of the present invention, the shielding gate and the control gate in the trench are electrically connected through a second contact hole. When the device is forward-biased, an electron accumulation layer can be formed on the sidewall of the shielding gate, thereby reducing the on-resistance.

[0117] In summary, the trench MOSFET manufacturing method of the present invention, after forming a trench, a shielding gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shielding gate, a control gate, a body region, a source region, and a dielectric layer, forms a first contact hole and a second contact hole. The first contact hole penetrates the dielectric layer and the source region and extends into the body region. The second contact hole penetrates the dielectric layer, the control gate, and the isolation oxide layer and exposes the shielding gate. Then, a source metal layer and a gate metal layer, spaced apart, are formed on the dielectric layer. The source metal layer is electrically connected to the source region and the body region through the first contact hole, and the gate metal layer is electrically connected to the control gate and the shielding gate through the second contact hole. In the trench MOSFET of the present invention, the shielding gate and the control gate in the trench are electrically connected through the second contact hole. When the device is forward-biased, because the shielding gate is connected to the control gate, an electron accumulation layer is formed on the sidewall of the shielding gate, thereby reducing the on-resistance. Furthermore, the manufacturing process of the trench MOSFET of the present invention can reduce the number of photomasks; for example, only three photomasks are needed, corresponding to the trench, the contact hole, and the metal layer respectively, which helps to reduce production costs. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0118] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a trench MOSFET, characterized in that, Includes the following steps: A preliminary structure is provided, the preliminary structure including a substrate, a trench formed on the upper surface of the substrate, and a shielding gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shielding gate, and a control gate located in the trench. The control gate oxide layer is located above the shielding gate oxide layer, the isolation oxide layer is located between the control gate and the shielding gate, the shielding gate oxide layer is located between the outer wall of the shielding gate and the inner wall of the trench, and the control gate oxide layer is located between the sidewall of the shielding gate and the sidewall of the trench. A body region is formed on the upper surface of the substrate, and a source region is formed on the upper surface of the body region; A dielectric layer is formed on the substrate and a first contact hole and a second contact hole are formed. The first contact hole penetrates the dielectric layer and the source region and extends into the body region. The second contact hole penetrates the dielectric layer, the control gate and the isolation oxide layer and exposes the shielding gate. A source metal layer and a gate metal layer are formed on the dielectric layer with spacing between them. The source metal layer is electrically connected to the source region and the body region through the first contact hole, and the gate metal layer is electrically connected to the control gate and the shielding gate through the second contact hole.

2. The method for manufacturing a trench MOSFET according to claim 1, characterized in that, The formation of the preceding structure includes the following steps: The trench is formed in the substrate; A first oxide layer is formed, which conformally covers the inner wall of the trench and the upper surface of the substrate; A first polysilicon layer is deposited, which fills the trench and covers the surface of the first oxide layer outside the trench; The first polysilicon layer is etched back to obtain the shielding gate; Remove the portion of the first oxide layer above the shielding gate to obtain the shielding gate oxide layer; The control gate oxide layer and the isolation oxide layer are formed; A second polysilicon layer is deposited and etched back to obtain the control gate.

3. The method for manufacturing a trench MOSFET according to claim 2, characterized in that: No photomask was used during the deposition and etch-back of the first polysilicon layer.

4. The method for manufacturing a trench MOSFET according to claim 1, characterized in that: In the preceding structure, the upper surface of the control gate is lower than or flush with the upper surface of the substrate, and the distance between the upper surface of the control gate and the upper surface of the substrate is in the range of 0 to 0.2 micrometers.

5. The method for manufacturing a trench MOSFET according to claim 1, characterized in that: The first contact hole and the second contact hole were etched simultaneously.

6. The method for manufacturing a trench MOSFET according to claim 5, characterized in that: The simultaneous etching includes dry etching. When simultaneously etching to the control gate and the substrate, the etching gases used include HBr, Cl2 and O2, and the etching selectivity ratio of polysilicon to silicon ranges from 1.5:1 to 4:

1. When simultaneously etching to the isolation oxide layer and the substrate, the etching gases used include CHF3, O2 and Ar, and the etching selectivity ratio of silicon oxide to silicon ranges from 10:1 to 20:

1.

7. The method for manufacturing a trench MOSFET according to claim 1, characterized in that: The depth of the first contact hole ranges from 0.3 micrometers to 0.6 micrometers, and the depth of the second contact hole ranges from 0.8 micrometers to 2 micrometers.

8. The method for manufacturing a trench MOSFET according to claim 1, characterized in that: In the extending direction of the trench, the length of the first contact hole is greater than the length of the second contact hole.

9. A trench MOSFET, characterized in that, include: The preceding structure includes a substrate, a trench formed on the upper surface of the substrate, and a shielding gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shielding gate, and a control gate located in the trench. The control gate oxide layer is located above the shielding gate oxide layer, the isolation oxide layer is located between the control gate and the shielding gate, the shielding gate oxide layer is located between the outer wall of the shielding gate and the inner wall of the trench, and the control gate oxide layer is located between the sidewall of the shielding gate and the sidewall of the trench. The body region is located on the upper surface layer of the substrate; The source region is located on the upper surface layer of the body region; A dielectric layer is located on the substrate; The first contact hole penetrates the dielectric layer and the source region and extends into the body region; The second contact hole penetrates the dielectric layer, the control gate, and the isolation oxide layer, and exposes the shielding gate. A source metal layer is located on the dielectric layer and electrically connected to the source region and the body region through the first contact hole. A gate metal layer is located on the dielectric layer and electrically connected to the control gate and the shielding gate through the second contact hole.

10. The trench MOSFET according to claim 9, characterized in that: The depth of the first contact hole ranges from 0.3 micrometers to 0.6 micrometers, and the depth of the second contact hole ranges from 0.8 micrometers to 2 micrometers.

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