3kV asymmetric super-junction trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a 3kV asymmetric super-junction trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type region; removing the barrier layer, and performing epitaxial growth on the drift layer to form an epitaxial layer; forming a barrier layer above the epitaxial layer, and performing etching and ion implantation to form a P + region, a low-resistance region, a shielding layer, a P-type well region and an N-type source region; etching and oxidizing to form an insulating dielectric layer which is internally provided with a groove; depositing metal to form a gate metal layer; etching the epitaxial layer, then depositing metal to form a source metal layer, and removing the barrier layer to complete preparation; through the design of asymmetric super junction cells of the device, small cells, high current density and low on-resistance of the device under a 3kV withstand voltage condition are realized.

Description

Technical Field

[0001] This invention relates to a 3kV asymmetric superjunction trench gate silicon carbide VDMOS and its fabrication method. Background Technology

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally have high voltage withstand capability compared to Si VDMOS devices. However, in fields such as high-voltage power transmission, the structure of traditional silicon carbide VDMOS devices is difficult to achieve both high voltage withstand capability of 3kV and low on-resistance. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a 3kV asymmetric superjunction trench gate silicon carbide VDMOS and its fabrication method. By designing the asymmetric superjunction cell of the device, the device can achieve small cell size, high current density and low on-resistance under 3kV withstand voltage conditions.

[0004] In a first aspect, the present invention provides a method for fabricating a 3kV asymmetric superjunction trench gate silicon carbide VDMOS, comprising the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; grow an epitaxial layer on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a barrier layer above the drift layer, etch the barrier layer to form vias, and implant ions to form a P-type region; Step 3: Remove the blocking layer from Step 2, and perform epitaxial growth on the drift layer to form an epitaxial layer; Step 4: Form a barrier layer above the epitaxial layer, etch the barrier layer to form vias, and implant ions to form P+ regions; Step 5: Ion implantation to form a low-resistivity region; Step 6: Ion implantation to form a shielding layer; Step 7: Ion implantation to form a P-type well region; Step 8: Ion implantation to form an N-type source region; Step 9: Etch the epitaxial layer and P+ region to form grooves, oxidize the grooves, and form an insulating dielectric layer, wherein the insulating dielectric layer has trenches. Step 10: Deposit metal to form a gate metal layer; Step 11: Etch the epitaxial layer, then deposit metal to form the source metal layer, remove the barrier layer, and complete the fabrication; Before steps 5 to 11, the barrier layer from the previous step needs to be removed, and the barrier layer is etched to form a through hole.

[0005] Secondly, the present invention provides a 3kV asymmetric superjunction trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the preparation method of the 3kV asymmetric superjunction trench gate silicon carbide VDMOS described in the first aspect.

[0006] The advantages of this invention are: I. This invention constructs a breakdown voltage region with alternating P-type region, drift region, and P-type region. This region constitutes a superjunction structure, which can achieve comprehensive breakdown voltage of the lateral and vertical pn junctions, and effectively improve the doping concentration of the drift region, achieving both high breakdown voltage and low on-resistance. 2. The present invention constructs an asymmetric superjunction trench gate structure, which constructs a P+ region enclosing half of the gate structure and a shielding layer corresponding to the insulating dielectric layer on one side of the device, which can effectively improve the gate reliability of the trench gate device. Third, the top of the P-type region of this invention is distributed with P+ regions, which can realize the transmission of potential and electric field in the P-type region. The withstand voltage structure is distributed longitudinally in the entire structure of the device. Fourth, this invention constructs a low-resistance region, which in turn constructs a low-resistance JFET region, thereby reducing the on-resistance of the device and avoiding current concentration. Fifth, the present invention adopts an asymmetric structure, which is narrower in the non-gate-controlled region, thereby increasing the current density of the device. Attached Figure Description

[0007] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0008] Figure 1 This is a schematic diagram of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention.

[0009] Figure 2 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 1 .

[0010] Figure 3 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 2 .

[0011] Figure 4 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 3 .

[0012] Figure 5 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 4 .

[0013] Figure 6This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 5 .

[0014] Figure 7 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 6 .

[0015] Figure 8 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 7 .

[0016] Figure 9 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 8 .

[0017] Figure 10 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 9 .

[0018] Figure 11 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 10 .

[0019] Figure 12 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 10 one.

[0020] Figure 13 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 10 two.

[0021] Figure 14 This is a cross-sectional view of the process of a 3kV asymmetric superjunction trench gate silicon carbide VDMOS according to the present invention. Figure 10 three. Detailed Implementation

[0022] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0024] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0025] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0026] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0027] like Figures 1 to 14 As shown in the figure, this application provides a method for fabricating a 3kV asymmetric superjunction trench gate silicon carbide VDMOS, including the following steps: Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 7; grow epitaxially on the upper side of silicon carbide substrate 1 to form drift layer 2; Step 2: Form a barrier layer 100 above the drift layer 2, etch the barrier layer to form a via, and implant ions to form a P-type region; Step 3: Remove the barrier layer 100 from step 2, and perform epitaxial growth on the drift layer 2 to form an epitaxial layer 200; Step 4: Form a barrier layer 100 above the epitaxial layer 200, etch the barrier layer 100 to form a via, and implant ions to form the P+ region 3; Step 5: Ion implantation to form a low-resistivity region 31; Step 6: Ion implantation to form shielding layer 32; Step 7: Ion implantation to form a P-type well region 33; Step 8: Ion implantation to form N-type source region 34; Step 9: Etch the epitaxial layer 200 and P+ region 3 to form groove 35, oxidize the groove 35, and form an insulating dielectric layer 4. The insulating dielectric layer 4 has a trench 41. Step 10: Deposit metal to form gate metal layer 5; Step 11: Etch epitaxial layer 200, then deposit metal to form source metal layer 6, remove barrier layer 100, and complete the fabrication; Before steps 5 to 11, the barrier layer 100 from the previous step needs to be removed, and the barrier layer 100 is etched to form a through hole.

[0028] In this embodiment, preferably, the doping concentration of the P-type region 21 is greater than or equal to the doping concentration of the drift layer 2, and the doping concentration of the P+ region 3 is greater than the doping concentration of the P-type region 21.

[0029] In this embodiment, preferably, the doping concentration of the shielding layer 32 is greater than or equal to that of the drift layer 2, and the doping concentration of the shielding layer 32 is greater than that of the P-type well region 33.

[0030] In this embodiment, preferably, the doping concentration of the low-resistivity region 31 is greater than the doping concentration of the shielding layer 32.

[0031] In this embodiment, preferably, the silicon carbide substrate 1, the drift layer 2, and the low-resistivity region 31 are all N-type, and the shielding layer 32 is P-type.

[0032] In this embodiment, preferably, the low-resistance region 31 is L-shaped, and the width of the low-resistance region 31 is equal to the sum of the width of the P-type well region 33 and the width of the shielding layer 32.

[0033] like Figure 13 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 1, Drift layer 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1, and a P-type region 21 is provided in the drift layer 2; P+ region 3, the lower side of which is connected to the upper side of the drift layer 2 and the upper side of the P-type region 21, is provided with a low-resistivity region 31, a shielding layer 32, a P-type well region 33 and an N-type source region 34. The lower side of the low-resistivity region 31 is connected to the upper side of the drift layer 2, the shielding layer 32 is connected to the low-resistivity region 31, the lower side of the P-type well region 33 is connected to the low-resistivity region 31, and the lower side of the N-type source region 34 is connected to the P-type well region 33. A groove 35 is provided in P+ region 3. An insulating dielectric layer 4 is disposed in the groove 35 at its lower part. One side of the insulating dielectric layer 4 is connected to a low-resistivity region 31, a P-type well region 33, and an N-type source region 34, respectively. The lower side of the insulating dielectric layer 4 is connected to a shielding layer 32 and a P+ region 3, respectively. A groove 41 is provided in the insulating dielectric layer 4. Gate metal layer 5, the gate metal layer 5 being disposed within the trench 41; Source metal layer 6, which is connected to P+ region 3 and N-type source region 34 respectively; And a drain metal layer 7, which is connected to the lower side of the silicon carbide substrate 1.

[0034] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 2 is 6-10e16cm. -3 The doping concentration of P-type region 21 is 1-5e17cm. -3 The doping concentration of P+ region 3 is 1-5e18cm. -3 The doping concentration of the N-type low-resistivity region 31 is 6-10e17cm. -3 The doping concentration of the P-type shielding layer 32 is 1-5e17cm. -3 The doping concentration of the P-type well region 33 is 1-5e16cm. -3 The insulating dielectric layer 4 can be made of silicon dioxide, and the doping concentration of the N-type source region 34 is 2-8e18cm. -3 ; The doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 7, reducing the overall on-resistance of the device. The doping concentrations of the N-type drift layer 2 and the P-type region 21 represent a trade-off between reverse breakdown voltage and on-resistance. Their concentration relationship ensures the lateral and vertical diffusion relationship of the space charge region of the pn junction, realizing a superjunction structure and thus ensuring both breakdown voltage and low on-resistance. The doping concentration of the P+ region 3 is to ensure the formation of a gradually changing junction near the source and gate regions during reverse breakdown, improving the source resistance of the device. The doping concentration of the N-type low-resistivity region 31 is to reduce the on-resistance from the N-type source region 34 through the gate-controlled region to the JFET region of the device. The doping concentration of the P-type shielding layer 32 can ensure the protective effect of the P-type shielding layer 32 on the insulating dielectric layer 4 of the device, improve the reliability of the bottom of the insulating dielectric layer 4, ensure that the leakage current is small enough when the device is reverse withstand voltage, shield the capacitance from the gate to the drain of the device, and reduce the Miller capacitance of the device. The P-type well region 33 is to form the gate-controlled structure of the device to realize the trench gate control of the device. Because the 3kV trench-gate silicon carbide VDMOS device requires thick epitaxy, the silicon carbide substrate 1 is designed to be 1.2μm thick to ensure support during device fabrication. The N-type drift layer 2 is 80μm thick, the device withstand voltage is 3kV, the source metal layer 6 is 300nm thick, with a width of 800nm ​​on the side with the conductive channel and 500nm on the side without the conductive channel. The N-type source region 34 is 200nm thick and 300nm wide. This is because the width of the gate-controlled P-type well region 33 is limited, and the 300nm width of the N-type source region 34 is sufficient to support the formation of the conductive channel. The P-type well region 33 is 400nm thick and 300nm wide to ensure a low off-state current. The maximum width of the N-type low-resistivity region 31 is 800nm, and the maximum thickness is 1.7μm. This is related to the structure of the P-type shielding layer 32 for gate protection. The overall design incorporates a P-type shielding layer 32 with a width of 500nm and a thickness of 400nm. This is because the device gate withstands a high voltage under 3kV withstand conditions, requiring sufficient thickness to ensure gate reliability. The device insulating dielectric layer 4 has a maximum width of 1μm and a maximum thickness of 1.1μm. The insulating dielectric layer 4 at the bottom of the gate metal layer 5 has a thickness of 100nm, and the insulating dielectric layers 4 on the left and right sides of the gate metal layer 5 have a width of 50nm. This is to ensure control of the conductive channel on the left side of the device. The gate metal layer 5 has a width of 900nm and a thickness of 1μm. The P+ region 3 on the conductive channel side of the device has a width of 500nm and a thickness of 2.3μm. The P+ region on the side without a conductive channel has a width of 1μm and a thickness of 2.3μm. This is to ensure the device's withstand voltage and that the current on the left and right sides is symmetrical when the device's body diode is freewheeling.

[0035] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a 3kV asymmetric superjunction trench gate silicon carbide VDMOS, characterized in that: Includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; grow an epitaxial layer on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a barrier layer above the drift layer, etch the barrier layer to form vias, and implant ions to form a P-type region; Step 3: Remove the blocking layer from Step 2, and perform epitaxial growth on the drift layer to form an epitaxial layer; Step 4: Form a barrier layer above the epitaxial layer, etch the barrier layer to form vias, and implant ions to form P+ regions; Step 5: Ion implantation to form a low-resistivity region; Step 6: Ion implantation to form a shielding layer; Step 7: Ion implantation to form a P-type trap region; Step 8: Ion implantation to form an N-type source region; Step 9: Etch the epitaxial layer and P+ region to form grooves, oxidize the grooves, and form an insulating dielectric layer, wherein the insulating dielectric layer has trenches. Step 10: Deposit metal to form a gate metal layer; Step 11: Etch the epitaxial layer, then deposit metal to form the source metal layer, remove the barrier layer, and complete the fabrication; Before steps 5 to 11, the barrier layer from the previous step needs to be removed, and the barrier layer is etched to form a through hole.

2. The method for fabricating a 3kV asymmetric superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type region is greater than or equal to the doping concentration of the drift layer, and the doping concentration of the P+ region is greater than the doping concentration of the P-type region.

3. The method for fabricating a 3kV asymmetric superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration is greater than or equal to that of the drift layer, and the doping concentration of the shielding layer is greater than that of the P-type well region.

4. The method for fabricating a 3kV asymmetric superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration in the low-resistivity region is greater than that in the shielding layer.

5. The method for fabricating a 3kV asymmetric superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The silicon carbide substrate, drift layer, and low-resistivity region are all N-type, and the shielding layer is P-type.

6. The method for fabricating a 3kV asymmetric superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The low-resistance region is L-shaped, and the width of the low-resistance region is equal to the sum of the width of the P-type well region and the width of the shielding layer.

7. A 3kV asymmetric superjunction trench gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

Images