Metal oxide semiconductor wafer device

Abstract

The invention provides a metal oxide semiconductor chip device which comprises a semiconductor substrate, and first source electrode structures and second source electrode structures are arranged on a first side of the semiconductor substrate in pairs. The drain structure is disposed on a second side of the semiconductor substrate opposite to the first source structure and the second source structure. The first channel structure is disposed therebetween and separates the first source structure and the semiconductor substrate, and the second channel structure is disposed therebetween and separates the second source structure and the semiconductor substrate. The gate structure is disposed on the first side of the semiconductor substrate. Wherein the first channel structure and the second channel structure are configured in a mirror image mode, and at least one wide area and at least one narrow area are formed between the first channel structure and the second channel structure according to different distances between the first channel structure and the second channel structure. According to the invention, the effective sectional area of the channel can be improved, the current density is effectively improved under the same wafer size, the sectional area of the junction field type region can be increased, and the effective sectional area and the current density are further improved.

Description

Technical Field

[0001] This invention relates to a metal-oxide-semiconductor (MOS) wafer device, and more particularly to a MOS wafer device having a channel design that increases current density and reduces on-resistance. Background Technology

[0002] In the field of power electronics, power devices responsible for switching control are crucial to performance. For a long time, silicon has dominated this field. However, with increasing power density, higher switching speeds (frequency), and more stringent power consumption requirements in applications, the design performance of silicon devices is approaching its theoretical limits. Therefore, industry professionals often focus on materials to find new semiconductor materials that can replace silicon. Based on this, silicon carbide and gallium nitride, two wide-bandgap semiconductor materials (also known as third-generation semiconductors), have gradually come into focus. Among them, silicon carbide, with its numerous properties, possesses unparalleled advantages in power semiconductor devices.

[0003] In automotive applications, replacing silicon-based devices with silicon carbide in electric drive inverters can reduce driver energy efficiency losses by 80% at the device level. It is estimated that using silicon carbide power devices in electric vehicle inverters can reduce overall vehicle power consumption by 5%-10%. Considering all factors, although the cost of the inverter module will increase, battery costs, heat dissipation costs, and space utilization costs will be significantly reduced. Furthermore, besides inverters, silicon carbide power devices can also be used in many other areas of electric vehicles, such as on-board chargers (OBC) and power conversion systems (DC / DC).

[0004] Material improvements have not yet yielded further breakthroughs in the market. In existing technologies, the effective current density and wafer size reduction of conventional inline channel metal-oxide-semiconductor wafer devices have reached their limits. Since the effective current density cannot be increased, the cost-performance ratio becomes less competitive. Summary of the Invention

[0005] The main objective of this invention is to provide a metal-oxide-semiconductor (MOS) wafer device, comprising a semiconductor substrate, on which a first source structure, a second source structure, a first channel structure, a second channel structure, and a gate structure are disposed. The first source structure and the second source structure are disposed in pairs on a first side of the semiconductor substrate. The drain structure is disposed on a second side of the semiconductor substrate opposite to the first source structure and the second source structure. The first channel structure and the second channel structure are disposed therebetween and spaced apart from the first source structure and the semiconductor substrate, and the second channel structure is disposed therebetween and spaced apart from the second source structure and the semiconductor substrate. The gate structure is disposed on the first side of the semiconductor substrate and contacts the first channel structure, the first source structure, the second channel structure, and the second source structure. The first channel structure and the second channel structure are mirror images of each other, and at least one wide region and at least one narrow region are formed between the first channel structure and the second channel structure depending on their spacing.

[0006] Furthermore, the semiconductor substrate sequentially includes an n+ substrate and an n epitaxial layer from the second side of the semiconductor substrate to the first side of the semiconductor substrate.

[0007] Furthermore, the first source structure includes a first n+ well region and a first metal silicide layer disposed on the first n+ well region; the second source structure includes a second n+ well region and a second metal silicide layer disposed on the second n+ well region.

[0008] Furthermore, the metal oxide semiconductor wafer device further includes an electrode structure that is connected at both ends to the first metal silicide layer of the first source structure and the second metal silicide layer of the second source structure, respectively.

[0009] Furthermore, the first channel structure includes a first p channel region disposed on the side of the first n+ well region closer to the second n+ well region, and a first p+ doping region disposed on the side of the first n+ well region away from the second n+ well region; the second channel structure includes a second p channel region disposed on the side of the second n+ well region closer to the first n+ well region, and a second p+ doping region disposed on the side of the second n+ well region away from the first n+ well region.

[0010] Furthermore, the gate structure includes an insulating layer disposed on the first side of the semiconductor substrate and a conductive layer disposed on the insulating layer.

[0011] Furthermore, the insulating layer contacts the surface of the first side of the semiconductor substrate, and from one end to the other, it contacts the first n+ well region, the first p channel region, the n epitaxial layer, the second p channel region, and the second n+ well region, respectively.

[0012] Furthermore, the first channel structure and the second channel structure are mirror images of each other, forming a serrated structure.

[0013] Furthermore, the first channel structure and the second channel structure are mirror images of each other in a wave-like structure.

[0014] Furthermore, the first channel structure and the second channel structure are comb-shaped structures that are mirror images of each other.

[0015] Therefore, compared with the prior art, the present invention can increase the effective cross-sectional area of ​​the channel and effectively increase the current density under the same wafer size. Furthermore, in addition to increasing the effective cross-sectional area of ​​the channel, it can also increase the cross-sectional area of ​​the junction field-type region (JFET region), further improving the effective cross-sectional area and current density. Attached Figure Description

[0016] Figure 1 This is a schematic diagram showing the appearance and partial cross-section of the metal oxide semiconductor wafer device in this invention.

[0017] Figure 2 This is an exploded view of the structure of the first embodiment of the metal-oxide-semiconductor wafer device of the present invention.

[0018] Figure 3 This is a top view schematic diagram of the channel shape in the first embodiment of the metal-oxide-semiconductor wafer device of the present invention.

[0019] Figure 4 This is a top view schematic diagram of the channel shape in the second embodiment of the metal-oxide-semiconductor wafer device of the present invention.

[0020] Figure 5 This is a top view schematic diagram of the channel shape in the third embodiment of the metal-oxide-semiconductor wafer device of the present invention.

[0021] Figure 6 This is a top view schematic diagram of the channel shape in the fourth embodiment of the metal-oxide-semiconductor wafer device of the present invention.

[0022] Figure 7 This is a top view schematic diagram of the channel shape in the fifth embodiment of the metal-oxide-semiconductor wafer device of the present invention.

[0023] The diagram is marked as follows:

[0024] 100 Metal Oxide Semiconductor Wafer Device

[0025] 10 Semiconductor substrates

[0026] 11-junction field region

[0027] 12n+ base

[0028] 13n epitaxial layer

[0029] 21 First source structure

[0030] 211 First n+ Well Area

[0031] 212 First metal silicide layer

[0032] 22 Second source structure

[0033] 221 Second n+ Well Area

[0034] 222 Second metal silicide layer

[0035] 23 Electrode Structure

[0036] 231 empty slot

[0037] 31 First Channel Structure

[0038] 311 First P Channel Area

[0039] 312 First p+ Mixed Zone

[0040] 32 Second Channel Structure

[0041] 321 Second P Channel Area

[0042] 322 Second p+ Mixed Zone

[0043] 40 drain structure

[0044] 50 gate structure

[0045] 51 Insulation Layer

[0046] 52 conductive layers

[0047] P1 First side

[0048] P2 Second Side

[0049] UW wide area

[0050] NW narrow area

[0051] 31A First Channel Structure

[0052] 32A Second Channel Structure

[0053] 31B First Channel Structure

[0054] 32B Second Channel Structure

[0055] 31C First Channel Structure

[0056] 32C Second Channel Structure

[0057] 31D First Channel Structure

[0058] 32D Second Channel Structure

[0059] MW1 width marker

[0060] MW2 width marking Detailed Implementation

[0061] To make the technical content of the present invention more detailed and complete, the following describes the embodiments and specific embodiments of the present invention. However, the following description is not the only form of implementing or using the specific embodiments of the present invention. If those skilled in the art can easily understand the necessary technical content of the present invention through the following description, and can change and modify the invention in various ways to adapt to different uses and situations without violating its spirit and scope, then the embodiments also fall within the scope of the patent application of the present invention.

[0062] In the description of this invention, unless the context otherwise requires, “a” and “the” may also be interpreted as plural. Furthermore, in this specification and the appended claims, unless otherwise stated, “placed on something” can be considered as direct or indirect contact with a surface of something, whether attached or otherwise, and the definition of that surface should be determined based on the context of the preceding / following paragraphs and common knowledge in the art to which this description pertains.

[0063] In the description of this invention, unless the context otherwise requires, the words “comprising,” “including,” “having,” or “containing” have inclusiveness or openness and do not exclude other elements or method steps not set forth.

[0064] In the description of this invention, terms such as "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," used to indicate orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings. They are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. It should be particularly noted that although this application uses exploded structural diagrams to represent structural features for ease of explanation, this does not mean that the product can actually be disassembled.

[0065] The metal oxide semiconductor wafer device of the present invention can be used in high-frequency, high-voltage products, such as inverters, rectifiers, electric vehicles, plug-in hybrid electric vehicles (PHEVs), charging stations, smart grids, energy storage devices, or rail transit and other high-frequency, high-power related electronic products. The scope of use of these devices is not limited in the present invention.

[0066] The metal-oxide-semiconductor (MOS) wafer devices used in this invention may include, but are not limited to, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond power semiconductor material (Diamond C), or other similar materials, and are not limited thereto in this invention. The element type of the MOS wafer devices used in this invention may be, for example, a vertically diffused MOS (VDMOS), a MOSFET (Metal-O-Metal Field-Effect Transistor), an insulated-gate bipolar transistor (IGBT), or other similar devices, and is not limited thereto in this invention. The gate structure design used in this invention may be, for example, a planar or trench design, and is not limited thereto in this invention.

[0067] The following is a detailed description of one embodiment of the present invention, which please refer to in advance. Figure 1 and Figure 2 Figure 100 shows the appearance, partial cross-sectional view, and structural exploded view of the metal oxide semiconductor wafer device of the present invention. As shown in the figure, this embodiment provides a metal oxide semiconductor wafer device 100, which mainly includes a semiconductor substrate 10, a first source structure 21 and a second source structure 22 disposed on the semiconductor substrate 10, a first channel structure 31 and a second channel structure 32 disposed on the semiconductor substrate 10, a drain structure 40 and a gate structure 50 disposed on the semiconductor substrate 10.

[0068] The first source structure 21 and the second source structure 22 are disposed in pairs on the first side P1 of the semiconductor substrate 10, and the drain structure 40 is disposed on the second side P2 of the semiconductor substrate 10 opposite to the first source structure 21 and the second source structure 22. Here, the first side P1 and the second side P2 refer to... Figure 1 The middle corresponds to the surface in the upper direction (first side P1) and Figure 1 The surface corresponding to the lower direction (second side P2) is described in terms of direction only. These directional descriptions are only for the purpose of clearly illustrating the content of the present invention. It is understood that these orientational relationships will change when the device is placed in a different orientation. These changes in orientation are not limited in the present invention.

[0069] The first channel structure 31 is disposed between the first source structure 21 and the semiconductor substrate 10, thereby separating the first source structure 21 and the semiconductor substrate 10 to form a well structure. The second channel structure 32 is disposed between the second source structure 22 and the semiconductor substrate 10, thereby separating the second source structure 22 and the semiconductor substrate 10 to form a well structure. The gate structure is disposed on the first side P1 of the semiconductor substrate 10 and contacts the first channel structure 31, the first source structure 21, the second channel structure 32, and the second source structure 22. This allows an electron layer (or hole layer) to be formed on the first channel structure 31 and the second channel structure 32 when an external electric field is applied to the gate, thereby allowing the first source structure 21 to conduct through the semiconductor substrate 10 to the drain structure 40 and the second source structure 22 to conduct through the semiconductor substrate 10 to the drain structure 40.

[0070] In this embodiment, on the semiconductor substrate 10, the region between the first channel structure 31 and the second channel structure 32 is the junction field-type region 11 (JFET region). The junction field-type region 11 (JFET region) mentioned here does not mean that the metal-oxide-semiconductor wafer device used in this invention is a JFET, but rather that the first channel structure 31 and the second channel structure 32 on both sides of the semiconductor substrate 10 form a symmetrical architecture, so that the semiconductor substrate 10 is sandwiched in the middle by the first channel structure 31 and the second channel structure 32 to form a region with JFET-like characteristics.

[0071] Next, please refer to the following: Figure 3 This is a top view schematic diagram of the channel shape in the first embodiment of the metal-oxide-semiconductor wafer device of the present invention. As shown in the figure, the first channel structure 31 and the second channel structure 32 in the present invention are arranged in a mirror image configuration. Here, "mirror" refers to... Figure 2 In the top view shown, the first channel structure 31 and the second channel structure 32 are configured in a mirror shape relative to each other (not in the direction of the cross section, such as...). Figure 1At least one wide region UW and at least one narrow region NW are formed between the first channel structure 31 and the second channel structure 32 according to their different spacing; in one embodiment, the longest distance of the wide region UW is 2.1μm~2.3μm, for example, but not limited to 2.10μm, 2.11μm, 2.12μm, 2.13μm, 2.14μm, 2.15μm, 2.16μm, 2.17μm, 2.18μm, 2.19μm, 2.20μm, 2.21μm, 2.22μm, 2.23μm, 2.24μm, 2.25μm, 2.26μm, 2.27μm, 2.28μm, 2.2 The distance may be 9 μm or 2.30 μm, which is not limited in this invention; in one embodiment, the shortest distance of the narrow region NW is 1.1 μm to 1.3 μm, for example, but not limited to 1.10 μm, 1.11 μm, 1.12 μm, 1.13 μm, 1.14 μm, 1.15 μm, 1.16 μm, 1.17 μm, 1.18 μm, 1.19 μm, 1.20 μm, 1.21 μm, 1.22 μm, 1.23 μm, 1.24 μm, 1.25 μm, 1.26 μm, 1.27 μm, 1.28 μm, 1.29 μm, or 1.30 μm, which is not limited in this invention. The narrow-range NW is configured such that when an external electric field is applied, the narrow-range NW is clamped at its location, while the source-to-drain current (ISD) can pass through the wide-range UW. To achieve this configuration, the actual widths of the wide-range UW and the narrow-range NW are related to the doping concentrations of the first p-channel region 311 in the first channel structure 31 and the second p-channel region 321 in the second channel structure 32. Therefore, the distance between the wide-range UW and the narrow-range NW is not limited in this invention and should be determined based on whether the configuration allows the wide-range UW current to pass through and the narrow-range NW to be clamped when an external electric field is applied. Furthermore, it should be specifically noted that the regions forming the wide-range UW and the narrow-range NW in the first channel structure 31 and the second channel structure 32 mainly refer to the regions on both sides of the junction field-type region 11 (JFET region). The shapes of the remaining structures of the first channel structure 31 and the second channel structure 32 are not limited in this invention.

[0072] Although only the first channel structure 31 and the second channel structure 32 are described herein as non-equidistant straight-line mirror structures, in conjunction with the design of the first channel structure 31 and the second channel structure 32, the conductive layers (e.g., metal silicide layers) on the first source structure 21 and the second source structure 22 and / or the first source structure 21 and the second source structure 22 are also designed to match the shape of the first channel structure 31 and the second channel structure 32; similarly, the gate structure 50 can also be designed to match the shape of the first channel structure 31 and the second channel structure 32 to form regions of varying widths, which is not limited in this invention.

[0073] Please refer to the following: Figure 1 In the following embodiments, the structural features of the present invention are illustrated using an npn architecture. In one embodiment, the semiconductor substrate 10 sequentially includes an n+ substrate 12 and an n epitaxial layer 13 from the second side to the first side; the first source structure 21 includes a first n+ well region 211 and a first metal silicide layer 212 disposed on the first n+ well region 211; the second source structure 22 includes a second n+ well region 221 and a second metal silicide layer 222 disposed on the second n+ well region 221; in one embodiment, the metal oxide semiconductor wafer device 100 further includes an electrode structure 23 that spans the first metal silicide layer 212 of the first source structure 21 and the second metal silicide layer 222 of the second source structure 22 at both ends; the electrode structure 23 forms a slot 231 at the middle position so that the electrode structure 23 does not contact the gate structure 50. In one embodiment, the material of the electrode structure 23 may be aluminum or other conductive materials, which are not limited in the present invention. It should be noted that although an NPN architecture is used in this embodiment, it can also be configured as a PNP architecture in practice. These variations are not limited in this invention.

[0074] In one embodiment, the first channel structure 31 includes a first p-channel region 311 disposed on the side of the first n+ well region 211 near the second n+ well region 221 (i.e., near the junction field region 11), and a first p+ doping region 312 disposed on the side of the first n+ well region 211 away from the second n+ well region (i.e., away from the junction field region 11). The first p-channel region 311 and the first p+ doping region 312 surround the bottom side of the first n+ well region 211. The second channel structure 32 includes a first p-channel region 311 disposed on the side of the second n+ well region 221 near the first n+ well region 221. The second p-channel region 321 is located on one side of the first n+ well region 211 (i.e., near the junction field-type region 11), and the second p+ doped region 322 is located on the side of the second n+ well region 221 away from the first n+ well region 211 (i.e., away from the junction field-type region 11). The second p-channel region 321 and the second p+ doped region 322 surround the bottom side of the second n+ well region 221. The gate structure 50 includes an insulating layer 51 disposed on the first side P1 of the semiconductor substrate 10 (i.e., the upper surface of the junction field-type region 11) and a conductive layer 52 disposed on the insulating layer 51. According to the above configuration, the insulating layer 51 contacts the surface of the first side P1 of the semiconductor substrate 10 from one end to the other (e.g., ...). Figure 1 From left to right, the first n+ well region 211, the first p channel region 311, the n epitaxial layer 13 (including the junction field region 11), the second p channel region 321 and the second n+ well region 221 are respectively in contact with the first n+ well region 211, the first p channel region 311, the n epitaxial layer 13 (including the junction field region 11), the second p channel region 321 and the second n+ well region

[0075] In one embodiment, the first p-channel region 311 is L-shaped, extending from the first n+ well region 211 to the area between the first n+ well region 211 and the junction field-type region 11, and contacts the insulating layer 51 of the gate structure 50 on its top side; the second p-channel region 321 is L-shaped, extending from the second n+ well region 221 to the area between the second n+ well region 221 and the junction field-type region 11, and contacts the insulating layer 51 of the gate structure 50 on its top side. In one embodiment, the widths of the first p-channel region 311 and the second p-channel region 321 are 0.35 μm to 0.45 μm; the "width" of the first p-channel region 311 and the second p-channel region 321 mentioned here refers only to the areas on the first p-channel region 311 and the second p-channel region 321 where channels can be generated, i.e. Figure 1 The regions marked with width MW1 and width MW2 in the figure; the width may be, for example, but not limited to, 0.35μm, 0.36μm, 0.37μm, 0.38μm, 0.39μm, 0.40μm, 0.41μm, 0.42μm, 0.43μm, 0.44μm, or 0.45μm, and is not limited in this invention.

[0076] For different embodiments of the channel structure in this invention, please refer to the following: Figures 2 to 7 Figure 1 is a top view schematic diagram of the channel shape in the first to fifth embodiments of the metal-oxide-semiconductor wafer device of the present invention, as shown in the figure: Regarding Figures 2 to 7 For ease of explanation, it should be noted that the figures described are simplified to show only the shape of the channels and are not intended to limit the actual appearance of the metal oxide semiconductor wafer device 100 in this invention. This will be stated in advance.

[0077] In one embodiment, the first channel structure 31 and the second channel structure 32 may be, but are not limited to, mutually mirror-image sawtooth structures (e.g., Figure 2 As shown); in another embodiment, the first channel structure 31A and the second channel structure 32A may be, but are not limited to, wavy structures that are mirror images of each other (e.g., Figure 3 As shown in the figure, the wavy structure is in the form of a chain wave, with its sharp ends facing inwards; in another embodiment, the first channel structure 31B and the second channel structure 32B can be, but are not limited to, wavy structures that are mirror images of each other (e.g., Figure 4 As shown in the diagram, the wavy structure is in the form of a chain wave, and... Figure 3 The difference in one embodiment is that its sharp ends face outwards; in another embodiment, the first channel structure 31C and the second channel structure 32C can be, but are not limited to, mirror-image wavy structures (such as...). Figure 5 As shown), the wave-like structure in this embodiment is a sine wave; in one embodiment, the first channel structure 31D and the second channel structure 32D can be, but are not limited to, mirror images of each other square wave structures (such as...). Figure 6(As shown); the above description of the shapes is only used to illustrate a few specific embodiments of the present invention, and simple changes to these shapes should also fall within the scope of protection of the present invention.

[0078] In summary, compared with the prior art, the present invention can increase the effective cross-sectional area of ​​the channel and effectively improve the current density under the same wafer size. Furthermore, in addition to increasing the effective cross-sectional area of ​​the channel, it can also increase the cross-sectional area of ​​the junction field-type region (JFET region), further improving the effective cross-sectional area and current density.

[0079] The present invention has been described in detail above. The above description is only one preferred embodiment of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should still fall within the patent coverage of the present invention.

Claims

1. A metal-oxide-semiconductor wafer device, characterized in that, It includes: A semiconductor substrate; A first source structure and a second source structure are disposed in pairs on the first side of the semiconductor substrate; A drain structure is disposed on a second side of the semiconductor substrate opposite to the first source structure and the second source structure; A first channel structure and a second channel structure are provided therebetween and separate the first source structure and the semiconductor substrate, and the second channel structure is provided therebetween and separate the second source structure and the semiconductor substrate. as well as A gate structure is disposed on the first side of the semiconductor substrate and contacts the first channel structure, the first source structure, the second channel structure, and the second source structure; The first channel structure and the second channel structure are configured in a mirror image, and at least one wide area and at least one narrow area are formed between the first channel structure and the second channel structure according to their different spacing.

2. The metal-oxide-semiconductor wafer device according to claim 1, characterized in that, The semiconductor substrate includes an n+ substrate and an n epitaxial layer sequentially from the second side of the semiconductor substrate to the first side of the semiconductor substrate.

3. The metal-oxide-semiconductor wafer device according to claim 2, characterized in that, The first source structure includes a first n+ well region and a first metal silicide layer disposed on the first n+ well region; the second source structure includes a second n+ well region and a second metal silicide layer disposed on the second n+ well region.

4. The metal-oxide-semiconductor wafer device according to claim 2, characterized in that, It further includes an electrode structure with its two ends respectively connected to the first metal silicide layer of the first source structure and the second metal silicide layer of the second source structure.

5. The metal-oxide-semiconductor wafer device according to claim 3 or 4, characterized in that, The first channel structure includes a first p channel area disposed on the side of the first n+ well area close to the second n+ well area, and a first p+ doping area disposed on the side of the first n+ well area away from the second n+ well area; the second channel structure includes a second p channel area disposed on the side of the second n+ well area close to the first n+ well area, and a second p+ doping area disposed on the side of the second n+ well area away from the first n+ well area.

6. The metal-oxide-semiconductor wafer device according to claim 5, characterized in that, The gate structure includes an insulating layer disposed on the first side of the semiconductor substrate and a conductive layer disposed on the insulating layer.

7. The metal-oxide-semiconductor wafer device according to claim 6, characterized in that, The insulating layer contacts the surface of the first side of the semiconductor substrate, and from one end to the other, it contacts the first n+ well region, the first p channel region, the n epitaxial layer, the second p channel region, and the second n+ well region, respectively.

8. The metal-oxide-semiconductor wafer device according to claim 1, characterized in that, The first channel structure and the second channel structure are serrated structures that are mirror images of each other.

9. The metal-oxide-semiconductor wafer device according to claim 1, characterized in that, The first channel structure and the second channel structure are mirror images of each other in a wave-like structure.

10. The metal-oxide-semiconductor wafer device according to claim 1, characterized in that, The first channel structure and the second channel structure are comb-shaped structures that are mirror images of each other.

Images