A pixel unit structure and a preparation method thereof

Abstract

The application discloses a pixel unit structure and a preparation method, relates to the technical field of image sensors, and has the advantages that the PD region is used for transmitting internal electrons to the FD region; the first P-type ion region is used for changing the potential trend inside the PD region; the first P-type ion region is arranged around the PD region; the second P-type ion region is used for separating the PD region and changing the potential trend inside the PD region; the second P-type ion region extends into the PD region from the first P-type ion region; the scheme is improved on the basis of the traditional pixel unit structure, the potential trend inside the PD region is changed by adding the second P-type ion region, and the transmission of the electrons in the PD region is facilitated; the second P-type ion region also separates the PD region, reduces the ion concentration on the lower side of the PD region, changes the potential trend in the vertical direction of the PD region, makes the electrons on the lower side of the PD region more easily transmit, and further improves the electron transmission efficiency.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and specifically to a pixel unit structure and its fabrication method. Background Technology

[0002] In the design and manufacturing of CMOS image sensors, increasing the full-well capacity (FWC) of pixels is one of the key indicators for improving dynamic range and image quality. Full-well capacity determines the maximum number of photogenerated electrons a single pixel can hold before saturation. A larger FWC is crucial for high dynamic range imaging, avoiding overexposure, and improving the signal-to-noise ratio.

[0003] Traditionally, the most direct and widely used method to increase the full-well capacity of a pixel is to increase the ion implantation concentration of n-type doping in the photodiode (PD) region. The principle is that a higher n-type doping concentration can form a larger potential well depth and width in the PD depletion region, thereby physically providing more space to accommodate more photogenerated electrons.

[0004] However, as technology nodes continue to shrink and pixel sizes continue to miniaturize, this method of simply increasing the n-type ion implantation concentration in the PD region faces increasingly severe technical bottlenecks and side effects:

[0005] Decreased electron transport efficiency: Increasing the n-type doping concentration reduces the built-in electric field strength within the PD. A weaker electric field significantly weakens the driving force and speed of photogenerated electrons transferring to the floating diffusion (FD) node during the transport phase; this directly leads to a decrease in charge transfer efficiency.

[0006] The problem of residual electrons becomes prominent: due to insufficient transmission drive force and slower speed, it is impossible to completely and quickly transfer all photogenerated electrons in the PD depletion region to the FD region during the pixel reset and readout cycles. After each transfer, a large number of electrons remain inside the PD.

[0007] Severely impacting image quality: Residual electrons can cause serious image quality problems, mainly manifested in the following ways: Residual electrons from the previous frame are superimposed on the signal of subsequent frames, causing moving objects to appear as trails or artifacts, especially noticeable in high-speed shooting or high-brightness scenes; Residual electrons blur the signal boundaries between pixels, reducing image sharpness and detail resolution; The amount of residual electrons may vary between different pixels, resulting in a fixed image noise pattern; Residual electrons are essentially a form of background noise, reducing the effective utilization of the signal and the signal-to-noise ratio, thus limiting further improvement in dynamic range.

[0008] Therefore, with the continuous shrinking of pixel size and the increasing demands for imaging performance, the traditional method of increasing the n-type ion implantation concentration in the PD region to improve full-well capacity is becoming increasingly ineffective due to declining electron transport efficiency and worsening residual electron problems. This issue has become one of the key bottlenecks restricting the performance of advanced CMOS image sensors, especially for high dynamic range, low noise, and small pixel designs. There is an urgent need to develop new technical solutions that can effectively improve full-well capacity while ensuring efficient and thorough charge transfer, eliminating or significantly reducing residual electrons, in order to overcome the limitations of existing technologies and meet the demands for higher image quality. Summary of the Invention

[0009] The technical problem to be solved by this invention is that the traditional method of increasing the full-well electron concentration mainly involves increasing the n-type ion implantation concentration in the PD region. However, as the concentration increases, electron transport problems become prominent, resulting in a large number of residual electrons that affect image quality. The purpose of this invention is to provide a pixel unit structure and preparation method that improves the traditional pixel unit structure by adding a second P-type ion region to change the potential trend inside the PD region, making it easier for electrons in the PD region to be transported to the FD region. At the same time, the second P-type ion region also separates the PD region, reducing the ion concentration on the lower side of the PD region and changing the potential trend in the vertical direction of the PD region, making it easier for electrons on the lower side of the PD region to be transported to the FD region, thereby further improving electron transport efficiency.

[0010] This invention is achieved through the following technical solution:

[0011] This solution provides a pixel unit structure, including:

[0012] The FD region and the PD region, wherein the PD region transfers internal electrons to the FD region;

[0013] The first P-type ion region is used to isolate the PD region; the first P-type ion region is disposed around the PD region.

[0014] The second P-type ion region is used to separate the PD region and change the potential trend inside the PD region; the second P-type ion region extends into the PD region from the first P-type ion region.

[0015] A further optimized solution is that the PD region includes a deep n-type region and a shallow n-type region;

[0016] Both the deep n-type region and the shallow n-type region are cuboid structures; the length, width, and height of the shallow n-type region are smaller than those of the deep n-type region, respectively.

[0017] The shallow n-shaped region is superimposed on the deep n-shaped region, and the geometric center of the shallow n-shaped region and the geometric center of the deep n-shaped region are on the same straight line.

[0018] A further optimized approach involves implanting phosphorus ions into the deep n-type region at a concentration of 0.2e⁻¹. 12 ~5.0e 12 ;

[0019] Arsenic ions were implanted into the shallow n-type region at a concentration of 0.2e⁻¹. 12 ~5.0e 12 ;

[0020] The ion implantation energy in the deep n-type region is greater than that in the shallow n-type region.

[0021] A further optimized approach involves implanting boron ions into the first P-type ion region at an implantation energy of 30K~950K and an implantation concentration of 0.2e⁻¹. 12 ~5.0e 12 ;

[0022] Boron ions were implanted into the second P-type ion region at an implantation energy of 250 K ~ 600 K and an implantation concentration of 0.2 e⁻¹. 12 ~5.0e 12 .

[0023] A further optimization scheme also includes a P-type substrate;

[0024] The PD region, the first P-type ion region, and the FD region are all completely embedded in the P-type substrate along the surface of the P-type substrate.

[0025] The surface of the shallow n-type region is on the surface of the P-type substrate;

[0026] The FD region is formed by n-type ions implanted inward along the surface of the P-type substrate;

[0027] The second P-type ion region extends from the first P-type ion region and passes through the P-type substrate before being vertically embedded into the deep n-type region. After being embedded into the deep n-type region, the second P-type ion region points in the direction where the FD region is located.

[0028] The geometric center of the deep n-type region is located within the second p-type ion region.

[0029] A further optimization is that the depth to which the first P-type ion region is embedded in the P-type substrate along the surface of the P-type substrate is greater than the depth to which the PD region is embedded in the P-type substrate along the surface of the P-type substrate.

[0030] The depth to which the shallow n-type region is embedded in the P-type substrate along the surface of the P-type substrate is greater than the depth to which the FD region is embedded in the P-type substrate along the surface of the P-type substrate.

[0031] The further optimized solution also includes polysilicon and a pinning region;

[0032] A raised polysilicon layer is formed outward along the surface of a P-type substrate, the polysilicon being used to control the connection between the FD region and the PD region;

[0033] The Pinning region is a P-type implantation region disposed on the surface of the PD region, and boron ions are implanted in the Pinning region.

[0034] A further optimization scheme includes an STI isolation trench; an active region and a shallow trench isolation region are divided on the surface of the P-type substrate, wherein the STI isolation trench (8) is a trench formed in the shallow trench isolation region.

[0035] A further optimized scheme is as follows: the inner ring region of the first P-type ion region is the active region, and the outer ring region of the first P-type ion region is the shallow trench isolation region; the inner ring region includes all regions within the inner wall of the first P-type ion region, and the region extending from the inner wall to the outer wall but not reaching the outer wall; the outer ring region includes all regions outside the outer wall of the first P-type ion region, and the region extending from the outer wall to the inner wall but not reaching the inner wall.

[0036] This solution also provides a method for fabricating a pixel unit structure, used to fabricate the aforementioned pixel unit structure; the method includes:

[0037] S1, an STI isolation trench is formed on a P-type substrate;

[0038] S2, with the first energy, injects deep n-type ions into the P-type substrate to form a cuboid deep n-type region;

[0039] S3, P-type ions are injected into the P-type substrate along the surface of the P-type substrate to form a first P-type ion region, which surrounds the deep n-type region.

[0040] S4, P-type ions are injected into the region extending along the first P-type ion region and passing through the P-type substrate and then vertically embedded into the deep n-type region to form a cuboid-shaped second P-type ion region.

[0041] S5, shallow n-type ions are injected with a second energy into a cuboid region above the deep n-type region and extending to the surface of the p-type substrate to form a shallow n-type region; the length, width, and height of the shallow n-type region are smaller than those of the deep n-type region, respectively; the first energy is greater than the second energy;

[0042] S6, p-type injection is performed on the surface of the shallow n-type region to form a pinning region;

[0043] S7, n-type ions are implanted inward along the surface of the P-type substrate to form an FD region, and protruding polysilicon is generated outward along the surface of the P-type substrate; the polysilicon is used to control the connection between the FD region and the PD region; the second P-type ion region is embedded into the deep n-type region and points in the direction of the FD region.

[0044] S8, used to manufacture the reset tube.

[0045] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0046] 1. The present invention provides a pixel unit structure and preparation method, which improves the structure based on the traditional pixel unit structure by adding a second P-type ion region to change the potential trend inside the PD region, promoting the easy transfer of electrons in the PD region to the FD region. At the same time, the second P-type ion region also separates the PD region, reducing the ion concentration on the lower side of the PD region and changing the potential trend in the vertical direction of the PD region, making it easier for electrons on the lower side of the PD region to transfer to the FD region, thereby further improving the electron transfer efficiency.

[0047] 2. The pixel unit structure and fabrication method provided by the present invention can also form two PN junctions in the PD to increase the capacitance of the PD region and improve the electron transport efficiency by using the second P-type ion region and the first P-type ion region.

[0048] 3. The pixel unit structure and preparation method provided by the present invention can also force the center of the PD region to move up and closer to the FD region by adding a second P-type ion region, making it easier for electrons to be transported to the FD region. Compared with the traditional method, the clamping voltage of the PD region is smaller, thereby making the electron transport efficiency of the pixel unit structure higher. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0050] Figure 1 This is a schematic diagram of the pixel unit structure;

[0051] Figure 2 This is a top view of the pixel unit structure;

[0052] Figure 3 This is a schematic diagram of a traditional pixel structure;

[0053] Figure 4 A schematic diagram illustrating the formation process of a deep n-type region in a pixel unit structure;

[0054] Figure 5 A schematic diagram of the formation process of the first P-type ion region in the pixel unit structure;

[0055] Figure 6 A schematic diagram of the formation process of the second P-type ion region in the pixel unit structure;

[0056] Figure 7 A schematic diagram illustrating the formation process of a shallow n-type region in a pixel unit structure;

[0057] Figure 8 This is a schematic diagram of the pinning region of the pixel unit structure and the polysilicon formation process.

[0058] The attached diagram shows the markings and corresponding component names:

[0059] 1-PD region, 11-deep n-type region, 12-shallow n-type region; 2-first P-type ion region, 3-second P-type ion region, 4-FD region, 5-P-type substrate, 6-polysilicon, 7-Pining region, 8-STI isolation trench, 9-electron transport path, 100-active region, 101-shallow trench isolation region. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0061] A simplified diagram of the traditional pixel structure is shown below. Figure 3 As shown, increasing the number of electrons in the full-well requires either increasing the area of ​​the PD region 1 or the concentration of n-type ions implanted. However, as the full-well size increases, such as... Figure 3 In the electron transport path 9, electrons below PD region 1 are not easily transported to FD region 4, resulting in a large number of residual electrons, which in turn affects image quality. Therefore, this solution provides the following embodiments to address the above-mentioned technical problems:

[0062] Example 1

[0063] This embodiment provides a pixel unit structure, such as Figure 1 and Figure 2 As shown, it includes:

[0064] FD region 4 and PD region 1, wherein the PD region transfers internal electrons to FD region 4;

[0065] The first P-type ion region 2 is used to isolate the PD region 1; the first P-type ion region 2 is disposed around the PD region 1.

[0066] The second P-type ion region 3 is used to separate the PD region 1 and change the potential trend inside the PD region; the second P-type ion region 3 extends into the PD region from the first P-type ion region 2.

[0067] The first P-type ion region 2 and the second P-type ion region 3 change the potential trend inside the PD region, making it easier for electrons in the PD region to be transported to the FD region 4. At the same time, the second P-type ion region 3 also separates the PD region 1, reducing the ion concentration on the lower side of the PD region 1 and changing the potential trend in the vertical direction of the PD region, making it easier for electrons on the lower side of the PD region to be transported to the FD region, thereby further improving the electron transport efficiency.

[0068] In this scheme, the main function of the first P-type ion region 2 is to isolate the PD region and prevent crosstalk between two pixel units.

[0069] The PD region in this scheme mainly functions to collect photons and convert them into electrons, and is the most important structure of the pixel unit.

[0070] The FD region is a key structure in the pixel unit. Its main function is to store photogenerated charge. The FD region collects the photogenerated charge generated by the PD region and converts it into a voltage signal.

[0071] The pinning region is a boron ion region, and its main function is to eliminate surface defects.

[0072] The PD region 1 includes a deep n-type region 11 and a shallow n-type region 12;

[0073] Both the deep n-type region 11 and the shallow n-type region 12 are cuboid structures; the length, width and height of the shallow n-type region 12 are smaller than those of the deep n-type region 11, respectively; the volume of the deep n-type region 11 is larger than that of the shallow n-type region 12, and the injected energy is also greater than that of the shallow n-type region 12, so as to expand the area of ​​the PD region.

[0074] The shallow n-shaped region 12 is superimposed on the deep n-shaped region 11, and the geometric center of the shallow n-shaped region 12 and the geometric center of the deep n-shaped region 11 are on the same straight line.

[0075] Phosphorus ions were injected into the deep n-type region 11 at a concentration of 0.2e. 12 ~5.0e 12 In addition to phosphorus ions, other pentavalent elements can also be injected into the deep n-type region 11. In this embodiment, phosphorus ions are mainly injected.

[0076] Arsenic ions were implanted into the shallow n-type region 12 at a concentration of 0.2e⁻¹. 12 ~5.0e 12 In addition to arsenic ions, other pentavalent elements can also be injected into the shallow n-type region 12. In this embodiment, arsenic ions are mainly injected.

[0077] The ion implantation energy of the deep n-type region 11 is greater than that of the shallow n-type region 12.

[0078] Boron ions were implanted into the first P-type ion region 2 at an implantation energy of 30K~950K and an implantation concentration of 0.2e⁻¹. 12 ~5.0e 12 ;

[0079] Boron ions were implanted into the second P-type ion region 3 at an implantation energy of 250 K ~ 600 K and an implantation concentration of 0.2 e⁻¹. 12 ~5.0e 12 .

[0080] It also includes a P-type substrate 5; in addition to boron ions, other trivalent elements can also be implanted in the first P-type ion region 2 and the second P-type ion region 3. In this embodiment, boron ions are mainly implanted.

[0081] The PD region 1, the first P-type ion region 2, and the FD region 4 are all completely embedded in the P-type substrate along the surface of the P-type substrate.

[0082] The surface of the shallow n-type region 12 is on the surface of the p-type substrate;

[0083] The FD region 4 is formed by n-type ions implanted inward along the surface of the P-type substrate 5;

[0084] The second P-type ion region 3 extends from the first P-type ion region 1 and passes through the P-type substrate before being vertically embedded into the deep n-type region 11. After being embedded into the deep n-type region 11, the second P-type ion region 3 points in the direction where the FD region 4 is located.

[0085] The geometric center of the deep n-type region 11 is located within the second p-type ion region 3.

[0086] The geometric center of the deep n-type region is within the second P-type ion region, indicating that the horizontal extension of the second P-type ion region exceeds the centerline of the deep n-type region, and it is embedded in the middle of the deep n-type region in the vertical direction to form a PD region for isolation.

[0087] The depth to which the first P-type ion region 2 is embedded in the P-type substrate along the surface of the P-type substrate is greater than the depth to which the PD region 1 is embedded in the P-type substrate along the surface of the P-type substrate.

[0088] The depth to which the shallow n-type region 12 is embedded in the P-type substrate along the surface of the P-type substrate is greater than the depth to which the FD region 4 is embedded in the P-type substrate along the surface of the P-type substrate.

[0089] The second P-type ion region 3 connects to the first P-type ion region 2, partially dividing the deep n-type region 11. This reduces the n-type concentration on the lower side of the PD region, causing the electron concentration on the lower side of the PD region to increase sequentially from left to right, creating a potential difference that facilitates electron transport. Furthermore, the connection between the second P-type ion region 3 and the first P-type ion region 2 allows the formation of two PN junctions in the PD, increasing the PD region capacitance. By controlling the injection concentration of the shallow n-type region 12, the concentration on the upper side of the PD region can be made greater than that on the lower side, making it easier for electrons to transport upwards. The deep n-type region 11 and the shallow n-type region 12 contribute to the formation of a complete PD region for photoelectric conversion.

[0090] It also includes polysilicon 6 and pinning region 7;

[0091] A raised polysilicon 6 is formed outward along the surface of the P-type substrate. The polysilicon 6 is used to control the connection between the FD region 4 and the PD region 1. The polysilicon 6 and the FD region transmit the electrons formed by photoelectric conversion in the PD region to the subsequent transistors for processing.

[0092] The Pinning region 7 is a P-type implantation region disposed on the surface of the PD region, and boron ions are implanted in the Pinning region 7; the Pinning region 7 mainly functions to eliminate surface defects.

[0093] It also includes an STI isolation trench 8; the inner ring region of the first P-type ion region is the active region 100, and the outer ring region of the first P-type ion region is the shallow trench isolation region 101; the inner ring region includes all regions within the inner wall of the first P-type ion region, and the region extending from the inner wall to the outer wall but not reaching the outer wall; the outer ring region includes all regions outside the outer wall of the first P-type ion region, and the region extending from the outer wall to the inner wall but not reaching the inner wall; the STI isolation trench 8 is a groove formed around the shallow trench isolation region.

[0094] This embodiment achieves PD region segmentation by implanting a second P-type ion region 3, resulting in a decrease in the n-type ion concentration on the lower side of the PD region and an increasing potential trend from bottom to top within the PD region, thus facilitating electron transport from the lower side of the PD region. Due to the presence of the first P-type ion region 2, the ion concentration in the PD region increases from left to right, and the horizontal potential of the PD region also increases from left to right, making it easier for electrons on the left to transport to the right. The increasing potential trend from bottom to top within the PD region further facilitates electron transport from the lower side of the PD region.

[0095] The implantation of the second P-type ion region 3 can also force the center of the PD region to move upward and closer to the FD region, making it easier for electrons to be transported to the FD region, forming... Figure 1As shown in the electron transport path 9, the potential inside the PD region gradually increases with the direction of the arrow in the electron transport path 9. Electrons will move to the place with higher potential, thus achieving the purpose of improving electron transport efficiency. Compared with the traditional method, the clamping voltage of the PD region is smaller, which makes the electron transport efficiency of the pixel unit structure higher.

[0096] Example 2

[0097] This embodiment provides a method for preparing a pixel unit structure, used to prepare the pixel unit structure of Embodiment 1; the method includes:

[0098] S1, STI isolation trenches are formed on the P-type substrate; the STI isolation trenches surround the active region;

[0099] S2, using the first energy, implants deep n-type ions into a p-type substrate to form a cuboid-shaped deep n-type region, such as... Figure 4 As shown;

[0100] S3, P-type ions are implanted into the P-type substrate along the surface of the P-type substrate to form a first P-type ion region, which surrounds the deep n-type region. Figure 5 As shown;

[0101] S4, P-type ions are injected into a region extending from the first P-type ion region and passing through the P-type substrate, then vertically embedded into the deep n-type region to form a cuboid-shaped second P-type ion region; as shown... Figure 6 As shown;

[0102] S5, shallow n-type ions are injected with a second energy into a cuboid region above the deep n-type region and extending to the surface of the p-type substrate, forming a shallow n-type region; the length, width, and height of the shallow n-type region are smaller than those of the deep n-type region, respectively; the first energy is greater than the second energy; as... Figure 7 As shown;

[0103] S6, p-type injection is performed on the surface of the shallow n-type region to form a pinning region;

[0104] S7, n-type ions are implanted inward along the surface of the P-type substrate 5 to form an FD region 4, and protruding polysilicon 6 is generated outward along the surface of the P-type substrate; the polysilicon 6 is used to control the connection between the FD region 4 and the PD region 1; the second P-type ion region is embedded into the deep n-type region and points in the direction of the FD region; as shown... Figure 8 As shown;

[0105] S8 is used to fabricate a series of MOSFETs, including reset transistors, row and column selection transistors, to obtain a complete pixel unit structure.

[0106] This embodiment divides the PD region by adding a second P-type ion region, thereby reducing the concentration of n-type ions on the lower side of the PD region. The potential inside the PD region increases from bottom to top and from left to right, making it easier for electrons to be transported out from the lower side of the PD region. The addition of the second P-type ion region also forces the center of the PD region to move upward and closer to the FD region, making it easier for electrons to be transported to the FD region. Compared with the traditional method, the clamping voltage of the PD region is smaller, which in turn makes the electron transport efficiency of the pixel unit structure higher.

[0107] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A pixel cell structure, characterized by, The pixel unit structure comprises: an FD region (4) and a PD region (1), the PD region (1) being used to transmit electrons inside to the FD region (4); a first P-type ion region (2) used to isolate the PD region (1), the first P-type ion region (2) being arranged around the PD region (1); a second P-type ion region (3) used to separate the PD region (1) and change the potential trend inside the PD region (1), the second P-type ion region (3) extending into the PD region (1) from the first P-type ion region (2); the PD region (1) comprising a deep n-type region (11) and a shallow n-type region (12); the deep n-type region (11) and the shallow n-type region (12) both being cuboid structures, the length, width and height of the shallow n-type region (12) being smaller than those of the deep n-type region (11); the shallow n-type region (12) being superimposed on the deep n-type region (11), and the geometric center of the shallow n-type region (12) being on the same straight line as the geometric center of the deep n-type region (11); the second P-type ion region (3) being connected with the first P-type ion region (2), partially cutting the deep n-type region (11), reducing the n-type concentration on the lower side of the PD region, making the electron concentration on the lower side of the PD region increase from left to right, forming a potential difference, and making the electrons on the lower side more easily transmit out.

2. The pixel unit structure according to claim 1, wherein the ion implantation energy of the deep n-type region (11) is greater than that of the shallow n-type region (12). The deep n-type region (11) is implanted with phosphorus ions at an implantation concentration of 0.2e 12 5.0e 12 ; The n- region (12) is implanted with arsenic ions at an implantation concentration of 0.2e 12 5.0e 12 ; 3. The pixel unit structure according to claim 2, further comprising a P-type substrate (5); the PD region (1), the first P-type ion region (2) and the FD region (4) all being completely embedded in the P-type substrate along the surface of the P-type substrate (5); the surface of the shallow n-type region (12) being on the surface of the P-type substrate (5); the FD region (4) being formed by n-type ions implanted inward along the surface of the P-type substrate (5); the second P-type ion region (3) extending from the first P-type ion region (2) and being vertically embedded in the deep n-type region (11) after penetrating through the P-type substrate (5), the second P-type ion region (3) being directed to the direction where the FD region (4) is located after being embedded in the deep n-type region (11); the geometric center of the deep n-type region (11) being in the second P-type ion region (3); the depth of the first P-type ion region (2) embedded in the P-type substrate along the surface of the P-type substrate being greater than the depth of the PD region (1) embedded in the P-type substrate along the surface of the P-type substrate; the depth of the shallow n-type region (12) embedded in the P-type substrate (5) along the surface of the P-type substrate (5) being greater than the depth of the FD region embedded in the P-type substrate (5) along the surface of the P-type substrate (5). The pixel unit structure further comprises polysilicon (6) and a Pining region (7); the polysilicon (6) is generated outward along the surface of the P-type substrate, and is used to control the connection between the FD region (4) and the PD region (1); the Pining region is a P-type implantation region arranged on the surface of the PD region (1), and boron ions are implanted in the Pining region (7). The first P-type ion region (2) is injected with boron ions, the injection energy is 30K ~ 950K, the injection concentration is 0.2e 12 ~5.0e 12 ; The second P-type ion region (3) is implanted with boron ions, with an implantation energy of 250K ~ 600K and an implantation concentration of 0.2e 12 ~5.0e 12 .

4. The pixel cell structure of claim 1, wherein, ​ ​ ​ ​ ​ ​ 5. A pixel cell structure according to claim 4, wherein, ​ ​ 6. A pixel cell structure according to claim 5, wherein, ​ ​ ​ 7. A pixel cell structure according to claim 6, wherein, The STI isolation groove (8) is formed in the shallow trench isolation region.

8. A pixel cell structure according to claim 7, wherein, The inner ring region of the first P-type ion region (2) is the active region (100), and the outer ring region of the first P-type ion region (2) is the shallow trench isolation region (101). The inner ring region includes all regions within the inner wall of the first P-type ion region (2) and regions extending from the inner wall to the outer wall but not reaching the outer wall. The outer ring region includes all regions outside the outer wall of the first P-type ion region (2) and regions extending from the outer wall to the inner wall but not reaching the inner wall.

9. A method for fabricating a pixel unit structure, characterized in that, The method comprises: S1, forming an STI isolation groove (8) on the P-type substrate (5); S2, injecting deep n-type ions into the P-type substrate (5) at a first energy to form a cuboid-shaped deep n-type region (11); S3, injecting P-type ions into the P-type substrate (5) along the surface of the P-type substrate (5) to form a first P-type ion region (2), which surrounds the deep n-type region (11); S4, injecting P-type ions into the region formed by extending along the first P-type ion region and vertically embedding into the deep n-type region (11) after passing through the P-type substrate (5) to form a cuboid-shaped second P-type ion region (3); S5, injecting n-type ions into the cuboid region above the deep n-type region (11) to the surface of the P-type substrate at a second energy to form a n-type region (12); the length, width and height of the n-type region (12) are smaller than those of the deep n-type region (11); the first energy is greater than the second energy; S6, performing p-type injection on the surface of the n-type region (12) to form a Pining region (7); S7, injecting n-type ions into the P-type substrate (5) along the surface to form an FD region (4), and generating a protruding polysilicon (6) outward along the surface of the P-type substrate; the polysilicon (6) is used to control the connection between the FD region (4) and the PD region (1); the second P-type ion region (3) is embedded in the deep n-type region (11) and points to the direction of the FD region (4); S8, manufacturing a reset tube.

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