Memory array of three-dimensional NOR memory strings with word line selection devices

Abstract

A memory circuit includes an array of thin film ferroelectric memory transistors formed of an array of NOR memory strings intersecting local word line structures, where global word lines are arranged orthogonally to the array of NOR memory strings and aligned with a set of local word line structures provided across a plurality of NOR memory string stacks. The memory circuit includes a word line selection transistor associated with each local word line structure to isolate each local word line structure from an associated global word line. The word line selection transistor selectively couples a selected local word line structure to the associated global word line upon startup. The remaining local word line structures associated with the same global word line remain disconnected and thus are not selected. In this manner, parasitic capacitance on the global word line is reduced, and unintended interference to other unselected memory transistors is also reduced.

Description

Technical Field

[0001] This invention relates to memory circuits and high-density memory structures, as well as methods for manufacturing the same. Specifically, this invention relates to memory arrays of NOR memory strings with word line selection devices. Background Technology

[0002] NOR memory strings comprise memory transistors sharing a common source and a common drain region, wherein each memory transistor can be individually addressed and accessed. U.S. Patent 10,121,553 ('553 Patent), published November 6, 2018, entitled "Capacitive-Coupled Non-Volatile Thin-film Transistor NOR Strings in Three-Dimensional Arrays," discloses memory transistors (or memory transistors) organized as a three-dimensional array of NOR memory strings formed above a flat surface of a semiconductor substrate. The '553 Patent is hereby incorporated by reference in its entirety for all purposes. In the '553 Patent, the NOR memory string comprises a large number of thin-film memory transistors sharing a common bit line and a common source line. Specifically, the '553 Patent discloses a NOR memory string comprising (i) a common source and a common drain region, both extending longitudinally along a horizontal direction, and (ii) gate electrodes for the memory transistors, each extending vertically. In this specification, the term "vertical" refers to a direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of the semiconductor substrate. In a 3D array, NOR memory strings are provided on multiple planes (e.g., 8 or 16 planes) above the semiconductor substrate, with the NOR memory strings on each plane arranged in rows. For charge trap type memory transistors, a charge storage film is used as the gate dielectric material to store data in each memory transistor. For example, the charge storage film may comprise a tunneling dielectric layer, a charge trapping layer, and a barrier layer, which may be implemented as a multilayer comprising silicon oxide or oxynitride, silicon-rich nitride, and silicon oxide, arranged in this order and referred to as an ONO layer. An electric field applied across the charge storage film adds or removes charge from the charge trapping layer, thereby changing the threshold voltage of the memory transistor to encode a given logic state in the memory transistor.

[0003] Electrically polarizable materials (“ferroelectric materials”), particularly those used in semiconductor manufacturing processes, have advanced theorized new potential applications in ferroelectric memory circuits. For example, U.S. Patent Application No. 17 / 936,320 (“320 Application”), filed September 28, 2022, entitled “Memory Structure Including Three-Dimensional NOR Memory Strings Of Junctionless Ferroelectric Memory Transistors And Method Of Fabrication,” discloses a high-density memory array implemented using a three-dimensional NOR memory string array of ferroelectric memory transistors. The entire contents of '320 Application are hereby incorporated by reference for all purposes. '320 Application describes a memory structure comprising randomly accessible ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in a plurality of scalable memory stacks of thin-film memory transistors. In some instances, the three-dimensional memory stack is fabricated in a process that includes forming operational trenches for vertical local word lines and forming auxiliary trenches to facilitate back-alley metal replacement and channel separation via a back-side selective etching process. For example, a three-dimensional NOR memory string array of thin-film ferroelectric transistors is also disclosed in U.S. Patent Application No. 17 / 812,375, filed July 13, 2022, entitled “3-Dimensional Memory String Array of Thin-Film Ferroelectric Transistors,” which is incorporated herein by reference in its entirety. Summary of the Invention

[0004] This disclosure discloses a memory circuit or structure comprising a three-dimensional NOR memory string including a thin-film ferroelectric memory transistor, and a method for manufacturing thereof, substantially as shown in at least one of the figures and / or described below, for example, in conjunction with at least one of the figures, as further elaborated in the claims.

[0005] In some embodiments, a memory circuit includes an array of thin-film ferroelectric memory transistors formed by a plurality of NOR memory strings intersecting with a plurality of local word line structures. The NOR memory strings are arranged as a plurality of stacked, vertically aligned NOR memory strings, each memory string including a common drain line and a common source line. The local word line structures of the memory circuit include groups of local word line structures, with the local word line structures in each respective group arranged along at least one stack of the NOR memory strings. Each local word line structure extends vertically along the at least one stack of vertically aligned NOR memory strings and includes a channel and a gate conductor separated by a ferroelectric gate dielectric layer. The ferroelectric memory transistors are formed at each intersection point of the respective local word line structure with the common drain line and the common source line of the respective NOR memory string. The gate conductor of each local word line structure serves as a common gate terminal of the memory transistors in the respective stack of vertically aligned NOR memory strings intersecting with the respective local word line structure.

[0006] The memory circuitry includes global word lines arranged orthogonally to the NOR memory strings, each global word line aligned with a set of local word line structures provided across the plurality of stacks. The memory circuitry further includes word line select transistors, comprising groups of word line select transistors, each group arranged along the NOR memory strings of the stacks. Each word line select transistor is disposed between a corresponding local word line structure and an associated global word line, and includes a source terminal for the gate conductor of the associated local word structure, a drain terminal coupled to the associated global word line, and a gate terminal coupled to receive a corresponding select gate signal. Each group of word line select transistors is controlled by the same select gate signal. In response to a global word line being asserted to select its associated set of local word line structures, the corresponding group of word line select transistors is activated by a corresponding select gate signal to electrically connect the asserted global word line to the common gate terminal of the associated local word line structure to activate one of the local word line structures in the set of local word line structures.

[0007] In other embodiments, a three-dimensional memory structure formed above a flat surface of a semiconductor substrate includes: a thin-film ferroelectric memory transistor array organized as a stack of NOR memory strings, each stack being separated from each of its adjacent stacks by trenches along a first direction, the stacks extending along a second direction substantially parallel to the flat surface of the semiconductor substrate, and the NOR memory strings of each stack being stacked on top of each other along a third direction substantially perpendicular to the flat surface. Each NOR memory string includes a common drain layer spaced apart from a common source layer, local word line structures configured to contact the NOR memory string stacks and spaced apart in the second direction, each local word line structure extending upward in the third direction and including a channel layer contacting the NOR memory strings in the associated stack, a ferroelectric gate dielectric layer formed adjacent to the channel layer, and a gate conductor layer disposed adjacent to the ferroelectric gate dielectric layer in the local word line structure. The gate conductor layer of each local word line structure serves as a common gate terminal for the ferroelectric memory transistors in the NOR memory strings in the corresponding stack associated with the local word line structure.

[0008] The memory structure further includes word line select transistors, each word line select transistor associated with a given local word line structure. Each word line select transistor includes a source terminal for the gate conductor layer of the associated local word line structure, a drain terminal coupled to one of a plurality of global word lines, and a gate terminal coupled to receive a corresponding select gate signal. In response to a first global word line being asserted to select its associated set of local word line structures, the first word line select transistor is activated by a first select gate signal to electrically connect the asserted first global word line to the common gate terminal of the associated local word line structures to activate one of the local word line structures in the set of local word line structures.

[0009] These and other advantages, aspects, and novel features of the invention, as well as details of the embodiments shown therein, will be more fully understood from the following description and accompanying drawings. Attached Figure Description

[0010] Various embodiments of the present invention are disclosed in the following detailed description and accompanying drawings. Although the drawings depict various examples of the invention, the invention is not limited to the depicted examples. It should be understood that similar reference numerals in the drawings indicate similar structural elements. Furthermore, it should be understood that the depictions in the drawings are not necessarily drawn to scale.

[0011] Figure 1 ,Include Figure 1 (a) is a perspective view of a memory structure including a 3D NOR memory string array in some embodiments.

[0012] Figure 2 To illustrate, in some embodiments and with usability Figure 1 A schematic diagram of a memory circuit with a local word line selection transistor constructed from the memory structure.

[0013] Figure 3 To illustrate in some embodiments Figure 2 A perspective view of a three-dimensional memory device as part of an implementation of a memory circuit.

[0014] Figure 4 To illustrate in some embodiments Figure 3 A top view of a portion of a three-dimensional memory device. Figure 3 and 4 The same components are given the same component symbol.

[0015] Figure 5 To illustrate the alternative embodiments Figure 2 A perspective view of a three-dimensional memory device as part of an implementation of a memory circuit.

[0016] Figure 6 This is a cross-sectional view of a memory device with a string of NOR memory and word line select transistors in some embodiments.

[0017] Figures 7(a) to 7(o) ,Include Figure 7(c1) , 7(c2) 7(k1) and 7(k2) illustrate the manufacturing process of a memory structure in some embodiments that includes word line select transistors formed as integrated with a three-dimensional memory array of memory transistors.

[0018] Figures 8(a) to 8(f) This describes an alternative process for performing selected gate separation in an alternative embodiment. Detailed Implementation

[0019] In an embodiment of the invention, a memory circuit includes an array of thin-film ferroelectric memory transistors formed by an array of NOR memory strings intersecting with local word line structures, wherein global word lines are arranged orthogonally to the NOR memory string array and aligned with a set of local word line structures provided across a stack of multiple NOR memory strings. The memory circuit includes word line selection transistors associated with each local word line structure to isolate each local word line structure from its associated global word line. Upon startup, the word line selection transistor selectively couples a selected local word line structure to the associated global word line. The remaining local word line structures associated with the same global word line remain disconnected and are therefore unselected. By connecting only a subset of local word lines to the asserted global word line, parasitic capacitance on the global word line is reduced, and unintended interference to other unselected memory transistors is also reduced. By reducing parasitic capacitance on the global word line, the charging time for the global word line is reduced, thereby shortening the latency of the memory device.

[0020] In some embodiments, the word line select device is a vertical thin-film transistor formed above the memory stack array, and is referred to herein as a "word line select transistor". Furthermore, in some embodiments, the word line select transistor is a non-memory transistor and has a gate electrode formed using a conductive layer for forming a common bit line of a NOR memory string.

[0021] In embodiments of the present invention, the ferroelectric memory transistor is a thin-film ferroelectric field-effect transistor (FeFET) having a ferroelectric polarization layer as the gate dielectric layer. The ferroelectric polarization layer (also referred to as the "ferroelectric gate dielectric layer") is formed adjacent to the oxide semiconductor layer as a channel region. The ferroelectric memory transistor includes a source region and a drain region, both formed of a metallic conductive material in electrical contact with the oxide semiconductor channel region. Each ferroelectric memory transistor thus formed is a junctionless transistor, which does not have a p / n junction in the channel, and wherein the threshold voltage is changed by the polarization of the ferroelectric dielectric layer, which in turn modulates the mobile carriers in the oxide semiconductor channel layer. In the memory structure of the present invention, the ferroelectric memory transistors in each NOR memory string are controlled by individual control gate electrodes formed in a local word line structure to allow individual addressing and access to each memory transistor. In some embodiments, the ferroelectric polarization layer is formed of a hafnium oxide-doped material, and the oxide semiconductor channel region is formed of an amorphous metal oxide semiconductor material.

[0022] In this specification, the terms "memory transistor" and "memory transistor" are used interchangeably to refer to a transistor device formed in the memory device described herein. In some instances, the memory device of this disclosure, comprising a string of NOR memory containing random access memory transistors (or memory transistors), can be used as main memory in a computing system, where the memory location is directly accessible by the processor of the computer system, for example, the role played by conventional random access memory (RAM) (e.g., dynamic RAM (DRAM) and static RAM (SRAM)) in the prior art. For example, the memory structure of this disclosure can be applied in a computing system as random access memory to support the operation of microprocessors, graphics processors, and artificial intelligence processors. In other instances, the memory structure of this disclosure is also suitable for forming storage systems, such as solid-state drives or alternatives to hard disk drives, for providing long-term data storage in a computing system.

[0023] In this specification, as used herein, the term "oxide semiconductor layer" (sometimes also referred to as "semiconductor oxide layer" or "metal oxide semiconductor layer") means a thin film semiconducting material made of conductive metal oxides such as zinc oxide and indium oxide, or any suitable conductive metal oxide whose charge carrier mobility can be modified or modulated by appropriate preparation or by including suitable impurities.

[0024] In embodiments of the invention, the memory device includes a memory stack (also referred to as a "stack"), wherein each memory stack contains a plurality of NOR memory strings formed stacked on top of each other in a vertical direction. In some embodiments, the NOR memory string stack is formed by a group of thin films successively deposited above a flat surface of a semiconductor substrate, each group of thin films referred to herein as an "active layer". The active layers in each NOR memory string stack are disposed stacked on top of each other, and each active layer is separated from other active layers by interlayer isolation layers. Each active layer includes a common drain line and a common source line, the common drain line and the common source line being arranged to be spaced apart in a vertical direction by a channel spacer isolation layer. Both the common source line and the common drain line extend in a horizontal direction.

[0025] The memory transistors in each NOR memory string share a common source line and a common drain line. In some instances, the channel layer, gate dielectric layer, and gate conductor layer of the memory transistors are formed vertically, contacting the common source line and common drain line of each NOR memory string. The memory transistors are thus formed in multiple parallel planes in each stack, with the memory transistors formed at each intersection of the gate conductor layer and the common source line and common drain line of the memory string. The gate conductor layer is referred to herein as a local word line (LWL). As mentioned above, the term "vertical" refers to a direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of the semiconductor substrate. Furthermore, as used herein and described in more detail below, a "local word line structure" refers to a columnar structure in which the channel layer, gate dielectric layer, and gate conductor are formed. Memory transistors are formed at each intersection of the local word line structure and the common source line and common drain line of the memory string. In some instances, local word lines are formed in operational trenches between memory stacks, and these operational trenches are sometimes referred to herein as "local word line trenches" or "LWL trenches." That is, an operational trench or local word line trench is a trench in which local word line gate conductors are formed and memory transistors are fabricated.

[0026] In embodiments of the invention, the memory transistors in the NOR memory string are ferroelectric field-effect transistors (FeFETs), which include a ferroelectric thin film as a gate dielectric layer, also referred to as a ferroelectric polarization layer, ferroelectric gate dielectric layer, or ferroelectric dielectric layer. In a ferroelectric field-effect transistor (FeFET), the polarization direction in the ferroelectric gate dielectric layer is controlled by an electric field applied between the transistor drain terminal and the transistor gate electrode, wherein a change in the polarization direction alters the threshold voltage of the FeFET. In some embodiments, the electric field is applied to both the transistor drain terminal and the source terminal relative to the transistor gate electrode. For example, the FeFET can be programmed to have either of two threshold voltages, wherein each threshold voltage of the FeFET can be used to encode a given logic state. For example, the two threshold voltages of the FeFET can be used to encode a “programmed” state and an “erase” state, each representing a specified logic value. In one instance, the programmed state is associated with the higher threshold voltage, and the erase state is associated with the lower threshold voltage. In some embodiments, more than two threshold voltages can be established to represent more than two memory states at each FeFET.

[0027] In this specification, for ease of reference to the figures, a Cartesian coordinate system is used, where the Z-direction is perpendicular to the flat surface of the semiconductor substrate, and the X and Y directions are orthogonal to the Z-direction and to each other, as indicated in the figures. Furthermore, the figures provided herein are idealized representations to illustrate embodiments of this disclosure and are not intended to be actual views of any particular component, structure, or device. The figures are not drawn to scale, and for clarity, the thickness and dimensions of some layers may be exaggerated. The shapes illustrated will vary. For example, areas illustrated as box shapes may generally have rough and / or non-linear characteristics. Acute angles illustrated may be rounded. The same numbers always refer to the same components or elements.

[0028] Figure 1 ,Include Figure 1 (a) is a perspective view of a memory structure including a 3D NOR memory string array in some embodiments. In some instances, the memory structure can be used to implement a portion of a semiconductor memory device. In some embodiments, a semiconductor memory device is constructed using a 3D NOR memory string array of ferroelectric memory transistors formed over a semiconductor substrate, as described in the aforementioned '320 application. See also Figure 1 The memory structure 10 includes a plurality of active layers 16 formed on a flat surface of a semiconductor substrate 12. An insulating layer 14 may be disposed between the semiconductor substrate 12 and the active layers 16 formed on the substrate. The active layers 16 are stacked on top of each other in the Z direction (i.e., along a direction perpendicular to the flat surface of the substrate 12) and separated from each other by an interlayer isolation layer 15. The active layers 16 are divided into narrow strips (“active strips”) in the X direction, and the narrow strips are stacked on top of each other to form a stack 17 (“active stack”) of active strips extending in the Y direction. In this specification, the active stack 17 is also referred to as a memory stack.

[0029] In this embodiment, the active stack 17 of the memory structure 10 is separated by narrow trenches including operating trenches 18 (also referred to as "LWL trenches") and auxiliary trenches 19. Specifically, the active stack 17 is separated by alternating operating trenches 18 and auxiliary trenches 19. In this specification, the operating trench 18 is a narrow trench between the active stacks 17, in which local word line structures are provided and memory transistors are formed. The auxiliary trench 19 is a narrow trench between the active stacks 17, in which no memory transistors are formed.

[0030] Each active layer 16 includes a first low-resistivity conductive layer and a second low-resistivity conductive layer (e.g., a tungsten (W) layer lined with titanium nitride (TiN)) separated by a channel spacer dielectric layer (e.g., silicon oxide). During intermediate processing steps, the active layers may include a sacrificial layer (e.g., silicon nitride) to be subsequently replaced by the conductive layers. Subsequent processing steps form a channel layer, a gate dielectric layer, and a gate conductor layer in an operating trench 18 between the separated active stacks. The gate conductor layer, the gate dielectric layer, and sometimes the channel layer are formed as columnar structures extending in the Z direction. In this specification, the gate conductor layer is also referred to as a “local word line,” and the gate conductor layer, along with the gate dielectric layer and the channel layer, are collectively referred to as a local word line (LWL) structure 13. The first and second conductive layers of each active stripe form the drain region (“common drain line” or “common bit line”) and source region (“common source line”) of the memory transistor, respectively. In this embodiment, memory transistors are formed along the vertical side of the active stack 17 facing the operating trench 18. Specifically, memory transistors 20 are formed at the intersection of the active strip and the LWL structure 13. The local word line structures 13 in each trench 18 are separated from each other in the Y direction by dielectric-filled shafts.

[0031] Figure 1 (a) A detailed description of the construction of the memory transistor 20 formed in the memory structure 10 in some embodiments is provided. Specifically, Figure 1 (a) Illustrate a pair of memory transistors 20-1 and 20-2 in two adjacent planes of the active stack 17 (also known as a memory stack). Reference Figure 1 (a) The memory transistor 20 includes a first conductive layer 22 forming a drain region (common drain line or common bit line) and a second conductive layer 24 forming a source region (common source line), the conductive layers being spaced apart by a channel spacer dielectric layer 23. The memory transistor 20 further includes a channel layer 26, a gate dielectric layer 27, and a gate conductor layer 28 formed on the sidewalls of the memory stack. The channel layer 26 is formed vertically along the sidewalls of the memory stack and contacts both the first conductive layer 22 and the second conductive layer 24. The memory transistor 20 is isolated from adjacent memory transistors in the memory stack by an interlayer isolation layer 15. In this configuration, memory transistors sharing a common source line and a common bit line form a NOR memory string (referred to herein as a "horizontal NOR memory string" or "HNOR memory string") along each active stripe (in the Y direction).

[0032] In embodiments of the present invention, the memory transistors in the memory structure 10 are junctionless ferroelectric memory transistors. Therefore, each memory transistor 20 contains only conductive layers as source and drain regions, without any semiconductor layers. The first and second conductive layers are formed using low-resistivity metallic conductive materials. In some embodiments, the first and second conductive layers are metal layers, such as a tungsten (W) layer lined with titanium nitride (TiN), a molybdenum (Mo) layer lined with titanium nitride (TiN), a tungsten (W) layer lined with tungsten nitride (WN), a molybdenum (Mo) layer lined with molybdenum nitride (MoN), or an unlined tungsten, molybdenum, or cobalt layer, or other metal layers. The channel spacer dielectric layer 23 between the first and second conductive layers may be a silicon dioxide (SiO2) layer. The channel layer 26 is an oxide semiconductor layer. In some instances, the channel layer 26 is formed using an amorphous oxide semiconductor material, such as indium gallium zinc oxide (InGaZnO or IGZO), indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO), or other such oxide semiconductor materials. Oxide semiconductor channel regions offer the advantage of high mobility for better switching performance without the need to consider electron or hole tunneling. For example, depending on the relative composition of indium, gallium, zinc, and oxygen, the IGZO film has a mobility ranging from 10.0 to 100.0 cm⁻¹. 2 / V electron mobility.

[0033] To form a ferroelectric memory transistor, memory transistor 20 includes a ferroelectric gate dielectric layer or ferroelectric polarization layer 27 in contact with channel layer 26. Ferroelectric polarization layer 27 acts as the memory layer of the memory transistor. The ferroelectric polarization layer can be deposited using atomic layer deposition (ALD) technology and can have a thickness between 1 nm and 14 nm. In some embodiments, an interface layer 25 may be disposed between oxide semiconductor channel layer 26 and ferroelectric polarization layer 27. Interface layer 25 is a thin layer and can be 0.5 nm to 4 nm thick. In some embodiments, the interface layer is formed using a material with a high dielectric constant (K) (also referred to as a "high-K" material). In some embodiments, interface layer 25 may be a silicon nitride (Si3N4) layer, or a silicon oxynitride layer, or an aluminum oxide (Al2O3) layer. In one example, the interface layer (if present) may have a thickness of 1.5 nm, while the ferroelectric polarization layer has a thickness of 4 nm to 5 nm. Figure 1 The inclusion of interface layer 25 in (a) is illustrative only and is not intended to be limiting. Interface layer 25 is optional and may be omitted in other embodiments of the invention. In other embodiments, interface layer 25 may be formed as a multilayer of different dielectric materials when included. In this specification, a material with a high dielectric constant or a high-K material refers to a material with a dielectric constant greater than that of silicon dioxide (SiO2).

[0034] In some embodiments, the ferroelectric polarization layer is formed of a doped hafnium oxide material (e.g., zirconium-doped hafnium oxide (HfZrO or "HZO")). In other embodiments, the hafnium oxide may be doped with silicon (Si), iridium (Ir), or lanthanum (La). In some embodiments, the ferroelectric polarization layer is a material selected from the following: zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum-zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium zirconium nitride oxide (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and any hafnium oxide containing zirconium impurities.

[0035] The ferroelectric polarization layer contacts the channel layer 26 on one side and the gate conductor layer 28 on the opposite side. In some embodiments, the gate conductor layer 28 includes a conductive liner 28a as an adhesion layer and a low-resistivity conductor 28b. In some instances, the conductive liner 28a is a titanium nitride (TiN) layer, a tungsten nitride (WN) layer, or a molybdenum nitride (MoN) layer, and the conductor 28b is formed using tungsten, molybdenum, or other metals. In some cases, the conductive liner 28a is not required, and the gate conductor layer 28 only includes the low-resistivity conductor 28b, such as an unlined tungsten or molybdenum layer. In another instance, the gate conductor layer 28 may be formed using titanium nitride (TiN) alone as the low-resistivity conductor 28b. In other instances, the conductor 28b may be heavily doped n-type or p-type polysilicon, which may be used with or without a conductive liner. The gate conductor layer 28, which includes a conductive liner 28a (if present) and a conductor 28b, together forms the control gate electrode of the memory transistor and serves as a local word line in the memory structure.

[0036] In this configuration, the oxide semiconductor channel layer 26 forms an N-type, unipolar channel region, in which the conductive layers 22 and 24, forming the drain and source terminals, directly contact the channel region. The ferroelectric memory transistor thus formed is a depletion-type device, where the transistor is normally on (i.e., conductive) and can be turned off (i.e., non-conductive) by depleting the N-type carriers in the channel region. The threshold voltage of the ferroelectric memory transistor varies with the thickness (X direction) of the oxide semiconductor channel layer 26. That is, the threshold voltage of the ferroelectric memory transistor is the amount of voltage necessary to deplete the carriers within the thickness of the oxide semiconductor channel region to turn off the ferroelectric memory transistor.

[0037] Each memory transistor 20 is isolated from adjacent memory transistors along the active stack (in the Z direction) by an interlayer isolation layer 15. In this embodiment, the interlayer isolation layer 15 is a dielectric layer, such as silicon dioxide (SiO2) or other dielectric materials having a similar dielectric constant. In some cases, the interlayer isolation layer 15 may include an optional liner 15b to cover or passivate the exposed surfaces of the active strips, and then fill the remaining volume with the dielectric layer 15a. In some embodiments, the air gap liner 15b is a silicon nitride layer or an aluminum oxide (Al2O3) layer. The air gap liner 15b may be 1 nm to 3 nm thick. Figure 1 In (a), the elements are sometimes exaggerated in size for illustrative purposes only. It should be understood that the depictions in this and other figures are not necessarily drawn to scale. In embodiments of the invention, the interlayer isolation layer 15 also serves to provide physical separation between the channel layer 26 of one memory transistor in the same memory stack and the channel layers of memory transistors above or below it, thereby providing isolation for each memory transistor in the memory stack.

[0038] In other embodiments of the invention, the interlayer isolation layer 15 is implemented as an air gap isolation formed by an air gap cavity and an optional air gap liner. For example, the interlayer isolation layer 15 may include an air gap liner 15b, wherein the remaining cavity forms an air gap isolation cavity 15a. The air gap liner 15b is a dielectric layer used to cover or passivate the exposed surfaces of the air gap cavity 15a. Thus formed, the air gap cavity 15a acts as the interlayer isolation layer 15 to provide effective isolation between adjacent memory transistors 20 along the memory stack.

[0039] Return to Figure 1 In the exemplary embodiment shown, the memory structure 10 includes a dielectric layer 44 that fills an auxiliary trench 19 outside the interlayer isolation layer 15. In some embodiments, the dielectric layer 44 is, for example, a silicon dioxide (SiO2) layer. In other embodiments, the auxiliary trench 19 may be capped by a dielectric capping layer, wherein the remaining cavity is used to form an air gap cavity.

[0040] In embodiments of the present invention, a three-dimensional NOR memory string array of ferroelectric memory transistors can be used to implement a non-volatile memory device or a quasi-volatile memory device. For example, a quasi-volatile memory has an average retention time greater than 100 ms (e.g., about 10 minutes or several hours), while a non-volatile memory device can have a minimum data retention time of more than 5 years. As a quasi-volatile memory, the ferroelectric memory transistor 20 may need to be refreshed periodically to restore the intended programming and erasing polarization states. For example, the ferroelectric memory transistor 20 in the memory structure 10 may be refreshed every few minutes or hours. Specifically, the ferroelectric memory transistors of this disclosure can form a quasi-volatile memory device, wherein the refresh interval can be about several hours, significantly longer than the refresh interval of DRAM, which requires much more frequent refreshes, such as once every tens of milliseconds.

[0041] It is worth noting that the memory structures described herein are provided as exemplary memory structures for three-dimensional NOR memory string arrays of ferroelectric memory transistors. Figure 1 and Figure 1 The memory structure 10 shown in (a) is illustrative only and is not intended to be limiting. Those skilled in the art will understand upon receiving this disclosure that the word line selection device of this disclosure can be applied to other memory structures of three-dimensional NOR memory string arrays of ferroelectric memory transistors.

[0042] Refer again Figure 1 To complete the memory circuitry, various types of circuit systems are formed in or on the surface of the semiconductor substrate 12 to support the operation of the HNOR memory string. Such circuitry is referred to as “array-under-circuit” (“CuA”) and may include digital and analog circuit systems such as decoders, drivers, sense amplifiers, sequencers, state machines, XOR circuits, memory caches, multiplexers, voltage level shifters, voltage sources, latches and registers, and connectors, which perform repetitive local operations, such as processing random addresses with the memory array formed above the semiconductor substrate 12 and executing boot, erase, program, read, and refresh commands. In some embodiments, the transistors in the CuA are constructed using processes optimized for control circuitry, such as advanced manufacturing processes optimized for forming low-voltage and faster logic circuitry. In some embodiments, the CuA is constructed using fin field-effect transistors (FinFETs) or gate-all-around field-effect transistors (GAAFETs) to achieve compact circuit layers and enhanced transistor performance.

[0043] In some embodiments, the CuA provides a data path to and from the memory array and further to a memory controller that can be built on the same semiconductor substrate as the CuA. Alternatively, the memory controller may reside on a separate semiconductor substrate, in which case the CuA and the associated data path are electrically connected to the memory controller using various bonding techniques. In some instances, the memory controller includes control circuitry for accessing and operating memory transistors in the memory array connected thereto, performing other memory control functions such as data delivery and error correction, and providing interface functionality for the system interacting with the memory array.

[0044] Figure 1 The memory structure 10 illustrates the construction of a 3D NOR memory string array in some embodiments. In some embodiments, the memory structure 10 is manufactured using a process that implements advantageous features of the memory structure. First, the memory structure 10 is formed such that the memory transistors in the 3D NOR memory string array are individually isolated from other memory transistors. Specifically, as Figure 1 As shown, each memory transistor is vertically isolated by an interlayer isolation layer and horizontally isolated by isolating the channel layer from each local word line structure 13. The performance characteristics of the memory transistors can be enhanced by individually isolating each memory transistor. Second, the channel layer is conformally deposited as part of the local word line structure 13, and then the channel backside is etched through a contact opening formed via a sacrificial layer to achieve channel separation between the active layers in the memory stack. This results in a simplified and more reliable process for forming the channel layer. Third, after removing the interlayer sacrificial layer for channel separation, the remaining cavities between the active layers can form an air gap isolation between the active layers, thereby achieving better isolation than most dielectric materials.

[0045] In embodiments of this disclosure, the memory structure includes a memory array portion constructed as described above to form a 3D NOR memory string array. To complete the memory device, the memory structure includes a stepped portion disposed at the end (in the Y direction) of the memory string. Thin-film memory transistors of the NOR memory string are formed in the memory array portion, while the stepped portion on the opposite side of the array portion includes a stepped structure to provide connections to a common bit line and optionally a common source line of the NOR memory string via conductive vias. In some embodiments, the common source line is pre-charged to serve as a virtual voltage reference source during programming, reading, and erasing operations, thereby avoiding the need for continuous electrical connections to the supporting circuitry during such operations. In this specification, the common source line is described as electrically floating to indicate the absence of continuous electrical connections to the common source line. In embodiments of this disclosure, various processing steps for forming the stepped structure in the memory structure can be used. The processing steps for forming the stepped structure can precede, follow, or interleave with the processing steps for forming the memory array portion.

[0046] Figure 1 The memory structure 10 illustrates the construction of a memory array comprising a three-dimensional NOR memory string array. The memory structure 10 can be used as a building block for forming high-capacity, high-density memory devices. In embodiments of this disclosure, the memory structure 10 represents modular memory cells referred to as “tiles,” and an array of modular memory cells is used to form a memory device. In one exemplary embodiment, the memory device is organized as a two-dimensional tile array arranged along the X and Y directions, wherein each tile comprises a three-dimensional ferroelectric memory transistor array, and a supporting circuitry system for each tile is formed beneath the respective tile. More specifically, the memory device comprises a plurality of memory arrays of thin-film ferroelectric memory transistors, organized as a two-dimensional array of “tiles” formed above a flat semiconductor substrate (i.e., the tiles are arranged in rows and columns). Each tile can be configured to be addressed individually and independently, or it can generate larger memory segments (e.g., a row of tiles or a two-dimensional block of tiles) and be configured to be addressed together.

[0047] Therefore, the memory device described herein implements a block-based architecture comprising: an arrangement of independently and simultaneously operable arrays or blocks of memory transistors, wherein each block contains memory transistors arranged in a three-dimensional array, the memory transistors being supported by locally modular control circuitry operating the memory transistors within the block. The block-based architecture enables simultaneous memory access to multiple blocks within the memory device, allowing independent and simultaneous memory operations to be performed across multiple blocks. Block-based simultaneous access to the memory device has the benefit of increasing memory bandwidth and reducing tail latency of the memory device by ensuring high availability of memory transistors.

[0048] In embodiments of the invention, the memory device is configured to include word line selection transistors that connect local word lines (i.e., gate conductor layers in the local word line structure) to global word lines. The word line selection transistors are used to select or activate only the relevant local word lines among all local word lines connected to the global word lines. In this way, parasitic capacitance on the global word lines is reduced, and the latency of the memory device is improved.

[0049] Figure 2 To illustrate, in some embodiments and with usability Figure 1 The diagram shows a schematic of a memory circuit with a local word line selection transistor constructed using the memory structure. Figure 3 To illustrate in some embodiments Figure 2 A perspective view of a three-dimensional memory device as part of an implementation of a memory circuit. Figure 2 and 3 Identical components are given the same component symbol. First refer to... Figure 2 The memory circuit 30 includes an array of active stacks 32 (active stacks 32-0 to 32-n) forming an array of NOR memory strings 38 spanning multiple active stacks. In each active stack 32, the NOR memory strings 38 of ferroelectric memory transistors 34 are formed in multiple layers (layers 0 to p), that is, in each active stack, the NOR memory strings 38-0 to 38-p are stacked on top of each other. Each NOR memory string 38 includes m+1 ferroelectric memory transistors 34 connected in parallel between bit lines BLx,y and source lines SLx,y. The ferroelectric memory transistors 34 have their gate terminals connected to corresponding local word lines LWL0 to LWLm.

[0050] More specifically, in each active stack 32, the memory transistors 34 in the vertically aligned NOR memory strings 38 across multiple layers 0 to p have their gate terminals connected to the same local word line LWLx (i.e., one of LWL0 to LWLm). The local word lines LWLx across the array of active stacks 32 are connected to the same global word line GWLx (i.e., one of GWL0 to GULM). In the memory circuitry 30, the n+1 NOR memory strings 38 in each layer are organized into k memory pages, such that each memory page has (n+1) / k memory transistors or (n+1) / k bits. Each memory access operation is performed on a per-memory-page basis, such that each memory access operation is performed on the selected memory transistor associated with a given memory page.

[0051] Figure 3 This description can be used to implement memory circuit 30 ( Figure 2 An exemplary memory device 40 is a part of [the above]. Reference Figure 3 The memory device 40 includes memory transistors formed on a substrate 41. The substrate 41 may contain a logic circuit system for operating the memory transistors, referred to as under-array circuitry, as described above. Figure 3 In the illustration, memory device 40 includes active stacks 32-0 and 32-1 formed adjacent to a first set of local word line structures 43. Memory device 40 further includes active stacks 32-2 and 32-3 formed adjacent to a second set of local word line structures 43. Each active stack 32 includes an array of NOR memory strings 38, i.e., memory strings 38-0 to 38-p, formed by stacking NOR memory strings on top of each other in a p+1 layer. A conductive layer 46 in each NOR memory string forms a common drain layer or bit line for the memory string. Each local word line structure 43 includes a local word line LWLx, which is a gate conductor layer of a vertically aligned memory transistor in the memory string 38 formed in the p+1 layer. Figure 3 The diagram shows local word lines LWL0 and LWL1. Global word lines are formed above the memory stack and extend in a direction traversing the memory string. Local word lines LWLx aligned in the Y direction will connect to the same corresponding global word line GWLx. For example, local word line LWL0 in the first and second group local word line structures will connect to global word line GWL0, and local word line LWL1 in the first and second group local word line structures will connect to global word line GWL1.

[0052] refer to Figure 2In operation, a given global word line GWLx is activated to select a segment (also called a "segment of memory transistors") that spans p+1 memory strings 38 across multiple layers and n+1 active stacks connected to the local word line LWLx. For example, global word line GWL1 is activated to select a segment of memory transistors 34 that spans memory strings 38-0 to 38-p and memory stacks 32-0 to 32-n connected to the local word line LWL1. Specifically, bit lines BLx,y associated with the selected memory page within the segment of memory transistors are activated to perform memory operations.

[0053] In embodiments of the invention, memory circuitry 30 includes word line selection transistors 36 disposed at each local word line LWLx to connect the corresponding local word line to the corresponding global word line GWLx. For example, word line selection transistor 36-0,m connects the local word line LWLm in the active stack 32-0 to the global word line GWLm. In another example, word line selection transistor 36-n,0 connects the local word line LWL0 in the active stack 32-n to the global word line GWL0. In this way, each global word line GWLx is selectively connected to the associated local word line LWLx in a segment of memory transistors. Specifically, word line selection transistors 36 are controlled by corresponding select gate signals SGx (e.g., SG0 to SGn) to selectively connect a subset of local word lines in a segment of memory transistors to the associated global word line. That is, a subset of word line selection transistors 36 is selected by the corresponding select gate signal SGx to turn on the local word line LWLx associated with the selected memory page and connect it to the activated global word line GWLx. Other unselected word line select transistors 36 remain off, and their corresponding local word lines are disconnected from their associated global word lines. Therefore, the parasitic capacitance experienced by each activated global word line is significantly reduced, which decreases the latency of the memory circuitry.

[0054] In other words, when implementing memory circuitry without word line select transistors, whenever a global word line is activated, it must drive all local word lines connected to it (i.e., LWL0 to LWLn), only a portion of which are associated with the selected memory page. Local word lines associated with unselected memory pages contribute to parasitic capacitances experienced by the global word line. Furthermore, activating the local word line of an unselected memory page may interfere with the stored data values ​​of the unselected memory transistors. According to an embodiment of the invention, memory circuitry 30 includes word line select transistors to selectively connect global word lines to corresponding local word lines. Therefore, at each memory access operation, only the local word line of the selected memory page is connected to the activated global word line. Local word lines associated with unselected memory pages are not connected to the global word line and do not contribute to parasitic capacitances experienced by the global word line. Furthermore, interference with the unselected memory transistors is avoided by not activating their gate terminals. In this scheme, only the unselected memory transistors of the unselected memory pages associated with the activated local word lines may experience interference, but these examples will be limited.

[0055] In one example, the memory circuitry has 2048 memory stacks or bit lines (n+1 = 2048), and each memory stack has 16 layers or memory strings (p+1 = 16). Each bit line is divided into 4 memory pages (k = 4), and each page has 512 bit lines. Each NOR memory string has 4096 memory transistors, and therefore 4096 global word lines (m+1 = 4096). In this embodiment, the memory device is configured with a local word line structure shared by two adjacent memory stacks. Therefore, each global word line is selectively connected to 1024 local word lines. When each global word line is initiated, one of the four memory pages is selected, and the word line selection transistor connects the local word line of the selected memory page to the initiated global word line. In this way, during each memory access operation, the initiated global word line is connected to only 512 local word lines to access 512 memory transistors. The other 512 local word lines are not connected to the initiated global word line. In this configuration, the parasitic capacitance traversed by the global word line is reduced by half.

[0056] In an embodiment of the invention, the word line select transistor 36 is a vertical thin-film transistor. In this embodiment, the word line select transistor 36 is used to transmit the word line voltage and does not need to have a large drive capability because the ferroelectric memory transistor can operate at low voltage values. For example, the word line voltage for a ferroelectric memory transistor can be 3V. In this case, the word line select transistor only needs to be a 4V transistor to transmit a 3V word line voltage. In another example, when the bit line is biased to -1V, the word line voltage can be 2V. In this case, the word line select transistor only needs to be a 3V transistor to transmit a 3V word line voltage. Referring again... Figure 2 and 3 In some embodiments, each word line selector transistor 36 connects its source terminal to the corresponding local word line LWLx (i.e., the gate conductor layer in the corresponding local word line structure) and its drain terminal to the corresponding global word line GWLx. For example, in Figure 3 In the exemplary embodiment shown, the drain terminal of each word line select transistor may include a via 44 to connect to a conductive line 45 forming the corresponding global word line. Figure 3 Each word line select transistor 36 includes a gate terminal formed by a gate conductor layer 37. In this embodiment, the gate conductor layer 37 extends in the same direction as the common drain layer (or bit line) 46 of the NOR memory string 38. In some embodiments, the gate conductor layer 37 is formed in the same manner as the conductor layer forming the common drain layer. In this embodiment, the gate dielectric layer 48 and the channel layer 49 of the word line select transistor 36 are formed above the respective pillar-shaped local word line structure. The word line select transistor 36 is formed at the intersection of the gate conductor layer 37 and the gate dielectric layer 48 with the channel layer 49.

[0057] Figure 4 To illustrate in some embodiments Figure 3 A top view of a portion of a three-dimensional memory device. Figure 3 and 4 Identical components are given the same component symbol. (Reference) Figure 4 The memory device 40 includes NOR memory strings, which are formed as portions of a memory stack spaced apart in the X direction and extending in the Y direction. Figure 4 In the diagram, bit line 46 is shown to represent one of the NOR memory strings in the memory stack. Specifically, the topmost bit line of the memory stack is shown in... Figure 4 middle.

[0058] In this embodiment, local word line structures are formed in alternating trenches between adjacent pairs of memory stacks, and are spaced apart in the Y direction within the respective trenches. Memory transistors are formed at the intersection points of each memory string in the memory stack and the local word line structures. In this illustration, the local word line structures for local word lines LWL0 to LWL4 are shown.

[0059] According to an embodiment of the present invention, a word line select transistor is formed above the memory stack and on a pillar-shaped partial word line structure. In this embodiment, the gate conductor layer 37 of the word line select transistor is formed using the same conductor layer as the bit lines or source lines of the NOR memory string. Therefore, the gate conductor layer 37 overlaps with the bit lines 46 of the memory stack, as shown below. Figure 4 As shown in the diagram. The gate conductor layer 37 carries corresponding select gate signals SG0 to SGn to control the corresponding word line select transistor, that is, to turn the word line select transistor on or off. Word line select transistors are provided to connect local word lines to corresponding global word lines. Global word lines GWL are formed in conductive layer 45 (e.g., a metal layer). Global word lines GWL extend in the X direction and traverse the bit lines of the word line select transistors and the gate conductor layer 37. In this configuration, each global word line GWL is connected in the Y direction to the same local word line in each trench. That is, global word line GWL0 is connected to local word line LWL0 across the memory stack, and global word line GWL4 is connected to local word line LWL4 across the memory stack.

[0060] In memory device 40, the n+1 bit lines in each layer are divided into k memory pages. In this illustration, each layer of bit lines is divided into 4 memory pages. Therefore, each memory access will initiate a bit line associated with one memory page. Figure 4 In the example shown, bit lines BL0 to BL3 are assigned to corresponding memory pages 0 to 3. Bit lines BL0 to BL3 may be the first data bits in each of the memory pages, and the bit lines are selectively connected to the first sense amplifier SA0. Similarly, bit lines BL4 to BL7 are assigned to corresponding memory pages 0 to 3. Bit lines BL4 to BL7 may be the second data bits in each of the memory pages, and the bit lines are selectively connected to the second sense amplifier SA1.

[0061] In the above embodiment, the gate terminals of the word line select transistors are disposed in individual gate conductor layers 37. The word line select transistors are formed at the intersection of the gate conductor layer 37 and the gate dielectric / channel layer structure. Therefore, the select gate signal SGx activates the word line select transistor associated with only one memory stack. In an alternative embodiment, the select gate signal SGx can be configured to activate word line select transistors associated with a pair of adjacent memory stacks.

[0062] Figure 5To illustrate the alternative embodiments Figure 2 A perspective view of a three-dimensional memory device as part of an implementation of a memory circuit. Figure 3 and 5 Identical components are given the same component symbol. (Reference) Figure 5 The memory device 40a includes word line select transistors 36 associated with a pair of adjacent memory stacks having a shared gate conductor layer 37a. That is, each gate conductor layer 37a controls the word line select transistors 36 formed on both sides of the gate dielectric / channel layer structure. Figure 5 The configuration of the gate conductor layer 37a achieves specific manufacturing simplicity without sacrificing the benefits of word line select transistors. Specifically, because adjacent memory stacks share the same local word line, word line select transistors in adjacent memory stacks can be controlled by the same select gate signal without altering the functionality of memory operations. In practice, bit lines in adjacent memory stacks are typically assigned to different memory pages and are not selected in the same memory operations.

[0063] Figure 6 This is a cross-sectional view of a memory device with a NOR memory string and word line select transistors in some embodiments. (Refer to...) Figure 6In some embodiments, a memory structure 50 including word line select transistors is formed above a three-dimensional memory array 53. In embodiments of the invention, the three-dimensional memory array 53 includes NOR memory strings formed in a memory stack array. In some embodiments, the memory array 53 is manufactured using the memory structure described in co-application and commonly assigned U.S. Patent Application No. 17 / 936,320, filed September 28, 2022, entitled “Memory Structure Incloding Three-Dimensional NOR Memory Strings of Junctionless Ferroelectric Memory Transistors and Method of Fabrication,” which is incorporated herein by reference in its entirety. In another embodiment, memory array 53 is manufactured using the memory structure described in U.S. Patent Application No. 18 / 419,385, filed January 22, 2024, entitled “Fabrication method for a three-dimensional memory array of thin-film ferroelectric transistors using a high-aspect-ratio local word line damaskene process,” which is incorporated herein by reference in its entirety. In the embodiments, memory array 53 may be manufactured in various ways, and the process used to manufacture memory array 53 is not critical to the practice of this invention.

[0064] In this exemplary embodiment, the memory array 53 includes an array of memory stacks formed on a semiconductor substrate 52, which may have circuitry formed therein, referred to above as under-array circuitry or CuA. An insulating layer 54 may be disposed between the semiconductor substrate 52 and the memory array formed on the substrate. The insulating layer 54 may also serve as an etch stop layer for the manufacturing process used to form the memory array. The memory array 53 includes active layers 51 and interlayer isolation layers 60 that are alternately stacked on top of each other. Each active layer 51 includes a first conductive layer 62 forming a common drain layer or bit line of a NOR memory string and a second conductive layer 64 forming a common source layer or source line of a NOR memory string. The first conductive layer 62 is separated from the second conductive layer 64 by a channel spacer dielectric layer 63. The memory array 53 may include one or more dummy layers formed as the bottom or top layer of the memory stack. In this illustration, the memory array 53 includes a conductive layer 61a as the bottom dummy layer. The dummy layer 61a may also serve as an anchoring layer for the memory stack formed thereon. In this illustration, the memory array 53 further includes a conductive layer 61b as a topmost dummy layer. One or more insulating layers are disposed on the memory array as array isolation layers. In this example, the array isolation layer includes an oxide layer 71 and a silicon carbide (SiOC) layer 72.

[0065] The memory array 53 further includes trenches separating the memory stack. Specifically, the memory array 53 includes local word line trenches LWT in which local word line structures are formed and auxiliary trenches AXT in which no active structures are formed. The local word line structures are formed at regular intervals in the Y direction to form ferroelectric memory transistors at their intersections with the active layer 51. In each local word line trench LWT, each local word line structure includes a channel layer 66, a ferroelectric gate dielectric layer 67, and a gate conductor layer 68. In some examples, the gate conductor layer 68 may include a conductive liner 68a (e.g., titanium nitride TiN) as an adhesive layer and a low-resistivity conductor 68b. In some embodiments, an interface layer 65 may be disposed between the channel layer 66 and the ferroelectric gate dielectric layer 67. The channel layer 66 is isolated from each active layer 51, for example, by separation in the Z direction. Ferroelectric memory transistors 34 are formed at each intersection of the active layer 51 and the local word line structure.

[0066] In embodiments of the invention, word line select transistors are formed over memory array 53. After processing of memory array 53 is completed, additional processing is performed to form vertical thin-film transistors to act as word line select transistors for local word lines formed in local word line structures. Specifically, word line select transistors are formed over array isolation layers (layers 71 and 72). In some embodiments, word line select transistors are formed using a multilayer structure 55 similar to the layers forming memory array 53. In this embodiment, word line select transistors are formed in a multilayer structure 55 comprising a conductive layer 75 sandwiched between insulating layers 74 and 76. Conductive layer 75 forms a gate conductor layer that serves as the gate terminal of the word line select transistor. In some embodiments, conductive layer 75 is formed using the same material as common drain layer 62 and common source layer 64. For example, conductive layer 75 may be a tungsten layer with a titanium nitride liner. Insulating layers 74 and 76 may be any dielectric layer, such as silicon dioxide (SiO2). Multilayer structure 55 may further comprise a capping dielectric layer 78. For example, the capping dielectric layer 78 can be a silicon oxycarbide (SiOC) layer.

[0067] The channel structure of the local word line select transistor is formed over the local word line structure of the memory array 53 and has the same periodicity as the local word line structure. Each channel structure includes a gate dielectric layer 92 adjacent to the multilayer structure 55 and a channel layer 93 adjacent to the gate dielectric layer. The remaining volume of the channel structure is filled by a dielectric layer 94 (e.g., a silicon oxide layer (SiO2)). The channel layer 93 of each word line select transistor is electrically contacted with the gate conductor layer 68 of the associated local word line structure. The gate conductor layer of the local word line structure associated with the corresponding channel structure serves as the source terminal of the word line select transistor. The multilayer structure 55 includes a top insulating layer 96 formed over a capping dielectric layer 78 and a conductive via structure 98 formed in the top insulating layer 96. A conductive via structure is provided for each channel structure of the local word line transistor. In some embodiments, the conductive via structure 98 may be filled with a conductive material, such as tungsten or copper. Each conductive via structure 98 is electrically contacted with the channel layer 93 of the corresponding word line select transistor to act as the drain terminal of the word line select transistor. In this specification, the gate conductor layer of a partial word line structure is referred to as the source terminal of the word line select transistor, and the conductive via structure 98 is referred to as the drain terminal of the word line select transistor. It should be understood that the source and drain terminals of a field-effect transistor are interchangeable, and references to source and drain terminals as used herein are illustrative only. In this configuration, the gate conductor layer 75 completely or partially surrounds the channel structure, and the word line select transistor 36 is formed at the intersection of the gate conductor layer 75 and the channel structure.

[0068] For example, a conductive layer 99 of a metal layer is formed over the multilayer structure 55 and is in electrical contact with the conductive via structure 98. The conductive layer 99 traverses the X direction of the memory structure and acts as a global word line of the memory structure. In some embodiments, the conductive layer 99 is a copper layer with or without a conductive liner layer. In this configuration, each global word line 99 contacts a set of conductive via structures 98 aligned in the Y direction. In a row of local word lines in a given Y direction, a word line selection transistor 36 is selectively activated to connect the global word line 99 to the gate conductor layer 68 of the local word line structure.

[0069] In some embodiments, the gate dielectric layer 92 of the word line select transistor is formed of a non-memory type dielectric. In some instances, the gate dielectric layer 92 is hafnium oxide (HfO), aluminum oxide (Al2O3), or silicon dioxide (SiO2). In another instance, a low-temperature dielectric layer is used. In other instances, the gate dielectric layer 92 is a dielectric material having a dielectric constant of 3.9 or lower. In some embodiments, the channel layer 93 of the word line select transistor is formed of the same material as the channel layer of the ferroelectric memory transistor. In some instances, the channel layer 93 is formed using an amorphous oxide semiconductor material, such as indium gallium zinc oxide (InGaZnO or IGZO), indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO) or other such oxide semiconductor materials. A prominent feature of the memory device of the present invention is that both the memory transistor and the word line select transistor are thin-film junctionless transistors. The oxide semiconductor channel layer allows the source and drain conductive layers to be directly connected to the channel of the transistor. In this way, word line select transistors can be built into the memory array and formed as an additional multi-layer structure.

[0070] In embodiments of the present invention, the gate conductor layer 75 may be formed as a surrounding channel structure to form Figure 5 The word line select transistor. In other embodiments, the gate conductor layer 75 is separable and contacts only a portion of the channel structure, such as... Figure 3 As shown in the diagram. The exact configuration of the gate conductor layer 75 is not important for the practice of this invention, because the local word lines of the associated local word line structure act as the gate terminals of a pair of memory transistors in each layer formed by two adjacent active layers. Upon startup of each global word line, a set of word line selection transistors are selected to connect the global word line signal to the selected local word line, and the bit line (common drain layer) of the selected memory page is selected to perform memory operations.

[0071] In some embodiments, the word line select transistor is formed during a portion of the manufacturing process of the memory device in which a pre-charged transistor is formed. In other embodiments, the word line select transistor may be formed in other portions of the memory device manufacturing process. Exemplary manufacturing processes for forming the word line select transistor will be described below.

[0072] Figures 7(a) to 7(o) ,Include Figure 7(c1) , 7(c2) Figures 7(k1) and 7(k2) illustrate the manufacturing process of a memory structure in some embodiments that includes word line select transistors formed as integration with a three-dimensional memory array of memory transistors. Referring to Figure 7(a), in an embodiment of the invention, memory structure 50 includes word line select transistors formed on a memory array, wherein, as shown in Figure 7(k2), the word line select transistors are integrated with a three-dimensional memory array of memory transistors. Figure 6 The memory array will be manufactured in the manner described herein, and the details will not be repeated. Figure 6 The same components as those in Figure 7(a) and subsequent figures are given the same component symbols and will not be described further. Figure 7(a) contains two views: view (i) is a horizontal cross-sectional view along the conductive layer indicated by line A-A' in view (ii) (i.e., in the XY plane), and view (ii) is a vertical cross-sectional view along the plane indicated by line A-A' in view (i) (i.e., in the XZ plane). Figure 7(a) illustrates as follows Figure 6 The memory array 53 formed and described herein is a junctionless ferroelectric memory transistor. Specifically, FIG7(a) illustrates the manufacturing process for forming the memory array 53, and view (ii) of FIG7(a) illustrates a top view of the memory array including an active layer 51 formed in a memory stack between an auxiliary trench 79 and a local word line trench LWT, wherein the local word line structures are spaced apart in the Y direction and isolated from each other by dielectric-filled posts 98. Parts of the manufacturing process related to the word line select transistor formation process will be described with reference to FIG7(b) and subsequent figures.

[0073] Referring to FIG. 7(b), a multilayer structure 55 is formed above the memory array 53, particularly above the array isolation layers 71 and 72, by sequentially depositing dielectric and conductive layers. In this embodiment, the multilayer structure 55 includes a first dielectric layer 74 deposited on the isolation layer 72, a conductive layer 75 deposited on the first dielectric layer 74, and a second dielectric layer 76 deposited on the conductive layer 75. A capping dielectric layer 78 is formed on the multilayer structure. The conductive layer 75 will serve as the gate conductor layer, constituting the gate terminal of the word line select transistor to be formed. In some embodiments, the first and second dielectric layers are silicon dioxide (SiO2) layers, the conductive layer 75 is a tungsten layer with a titanium nitride liner, and the capping dielectric layer 78 is a silicon carbide (SiOC) layer. In some embodiments, the first and second dielectric layers and the conductive layer 75 may each have a thickness of 30 nm or less. The sublayers of the multilayer structure 55 may have the same or different thicknesses. In some embodiments, the capping dielectric layer 78 has a thickness of 40 nm or greater.

[0074] Referring to FIG. 7(c), an opening 80 is formed in the multilayer structure 55 to form a channel structure for a word line select transistor. In this embodiment, the opening 80 is arranged with the same periodicity as the local word line structure formed in the memory array 53. FIG. 7(c1) and FIG. 7(c2) are top views or horizontal cross-sectional views of the multilayer structure and illustrate two embodiments for forming the opening 80. The top view is taken at the capping dielectric layer 78. Referring first to FIG. 7(c1), a mask layer may be applied to define the opening 80 with the same periodicity as the local word line structure. For example, the opening 80 is formed by etching the multilayer structure 55 using an anisotropic dry etching process, the opening exposing the local word line structure formed in the underlying memory array. In another embodiment, referring to FIG. 7(c2), the opening 80 may be formed in a two-step process. A mask layer may be applied to define a trench in the multilayer structure covering the local word line structure. For example, the multilayer structure 55 is etched using an anisotropic dry etching process to form a trench in the multilayer structure. Next, the trench can be filled with dielectric layer 81. A second mask is applied to form an opening 80 in dielectric layer 81, which exposes the local word line structures formed in the underlying memory array. Specifically, in the two embodiments of FIG7(c1) and FIG7(c2), the gate conductor layer in each local word line structure is exposed to make electrical contact with the channel layer of the word line select transistor to be formed.

[0075] With the opening 80 thus formed, a gate dielectric layer 92 is deposited on the multilayer structure 55, as shown in FIG7(d). In this embodiment, the gate dielectric layer 92 is an aluminum oxide (Al2O3) layer. In this embodiment, the gate dielectric layer 92 is deposited conformally, for example, using an atomic layer deposition (ALD) process, and thus the gate dielectric layer 92 is formed on all exposed surfaces of the memory structure 50. After conformal deposition, the gate dielectric layer 92 is anisotropically etched back to remove the deposited material from the horizontal surfaces of the memory structure 50, as shown in FIG7(e). The gate dielectric layer 92 remains only on the sidewalls of the opening 80.

[0076] Following the gate dielectric layer, a channel layer 93 is deposited. In some embodiments, the channel layer is formed using a two-step deposition process. The first optional deposition process uses a room-temperature physical vapor deposition (PVD) process. For example, a PVDI IGZO layer can be deposited at room temperature. Room-temperature PVD deposition is preferred because it avoids oxidation of the exposed metal in the gate conductor layer of the underlying local word line structure. Typically, PVD deposition is non-conformal and will only be deposited on the horizontal surface of the memory structure, not on the vertical sidewalls of the opening. In this way, PVD IGZO will be deposited onto the exposed gate conductor layer 68 of the local word line structure, which facilitates contact with the metal layer of the gate conductor layer 68. The second deposition process uses atomic layer deposition (ALD) technology to deposit the channel material. For example, an ALD IGZO layer can be conformally deposited on the memory structure 50 to create the channel layer 93, as shown in FIG7(f).

[0077] Next, a filler dielectric layer 94 is deposited on the surface of the memory structure 50, simultaneously filling the remaining volume of the opening 80, as shown in FIG7(g). For example, the filler dielectric layer 94 may be a silicon dioxide (SiO2) layer. After the deposition step, excess material is removed from the top of the memory structure 50 using, for example, chemical mechanical polishing (CMP). The resulting memory structure 50 is shown in FIG7(h). Specifically, the polishing step stops at the channel layer 93, thereby connecting the channel layer on top of the memory structure to all the channel structures formed in the opening 80.

[0078] A channel layer separation process is performed to remove the channel layer material on the memory structure 50, as shown in FIG7(i). In one embodiment, the channel layer is an oxide semiconductor material, such as IGZO, and the channel layer separation process is performed by a wet etching process.

[0079] Next, a gate separation process is performed to isolate the gate conductive layer 75 of the word line select transistor from each memory stack. Referring to FIG7(j), trenches 84 are formed in the multilayer structure 55, extending in the Y direction to isolate the multilayer structure 55 from each memory stack. In this embodiment, trenches 84 are aligned with the positions of each auxiliary trench 79. Thus, the gate conductive layer 75 is formed as strips, each strip associated with a memory stack of the memory array. Subsequently, trenches 84 are filled with a dielectric layer 95, such as a silicon oxide layer (SiO2), as shown in FIG7(k). Word line select transistors 36 are formed at the intersections of each strip of the gate conductive layer 75 with a channel structure comprising a gate dielectric layer 92 and a channel layer 93.

[0080] Figure 7(k1) and 7(k2) This is a top view or horizontal cross-sectional view of a multi-layered structure, with explanations for the corresponding... Figure 7(c1) and 7(c2) The structures obtained after the selective gate separation process in the two embodiments shown are illustrated. Specifically, Figure 7(k1) and 7(k2) This illustrates a horizontal cross-sectional view of the word line select transistor at gate conductor layer 75. Referring first to Figure 7(k1), the channel structure of the word line select transistor is formed at the location where a local word line structure is formed in the memory array. Dielectric-filled trenches 95 isolate the multilayer structure into multiple segments. In the embodiment shown in Figure 7(k1), the gate conductor layer 75 is continuous over two memory stacks. That is, the gate conductor layer 75 surrounds the channel structure and is associated with two adjacent memory stacks between two adjacent auxiliary trenches. In the embodiment shown in Figure 7(k2), the gate conductor layer 75 has been isolated by previously formed trenches. A select gate separation process further isolates the gate conductor layer 75 into strips over each memory stack via dielectric-filled trenches 95. That is, the gate conductor layer 75 is formed adjacent to the channel structure spaced apart by dielectric-filled posts 81.

[0081] Fabrication of the word line select transistor continues to form the drain terminal. A top insulating layer 96 is deposited on the memory structure 50, as shown in FIG7(l). For example, the top insulating layer 96 is a silicon dioxide layer (SiO2). Next, as shown in FIG7(m), an opening 82 is formed to expose the channel structure formed in the multilayer structure 55. Then, the opening 82 is filled with a conductive material to form a conductive via structure 98, as shown in FIG7(n). In one example, the conductive material is copper. Finally, a conductive layer 99 is deposited on the memory structure 50 and patterned to form the global word line, as shown in FIG7(o). This forms the drain terminal of the word line select transistor 36.

[0082] Figures 8(a) to 8(f) An alternative process for performing selected gate separation in an alternative embodiment is described below. Referring to FIG8(a), the fabrication process has completed the formation of a multilayer structure 55 and a channel structure, as shown, for example, in FIG7(i). Subsequently, a top insulating layer 96 is deposited. Next, as shown in FIG8(b), an opening 82 is formed to expose the channel structure formed in the multilayer structure 55. Then, the opening 82 is filled with a conductive material to form a conductive via structure 98, as shown in FIG8(c). In one example, the conductive material is copper.

[0083] At this point, trenches 84 are formed in the multilayer structure 55, extending in the Y direction to isolate the multilayer structure 55 from each memory stack, as shown in FIG8(d). Subsequently, trenches 84 are filled with a dielectric layer 95, such as a silicon oxide layer (SiO2), as shown in FIG8(e). Finally, a conductive layer 99 is deposited on the memory structure 50 and patterned to form global word lines, as shown in FIG8(f). This forms the drain terminal of the word line select transistor 36.

[0084] In this detailed description, the process steps described for one embodiment may be applicable to different embodiments, even if no process steps are explicitly described in the different embodiments. When reference is made herein to a method comprising two or more defined steps, the defined steps may be performed in any order or simultaneously unless the context indicates or otherwise specifically provided herein. Furthermore, unless the context indicates or otherwise explicitly provided, the method may also include one or more other steps performed before any defined step, between two defined steps, or after all defined steps.

[0085] In this detailed description, various embodiments or examples of the invention may be implemented in multiple ways, including as processes, apparatus, systems, and material compositions. A detailed description of one or more embodiments of the invention, along with accompanying drawings illustrating the principles of the invention, has been provided above. The invention has been described in conjunction with these embodiments, but the invention is not limited to any particular embodiment. Many modifications and variations are possible within the scope of the invention. The scope of the invention is limited only by the claims, and the invention covers many alternatives, modifications, and equivalents. Numerous specific details are set forth in the description to provide a thorough understanding of the invention. These details are provided for purposes of illustration and the invention may be practiced according to the claims without some or all of these specific details. For clarity, technical materials known in the art associated with the invention have not been described in detail so as not to unnecessarily obscure the invention. The invention is defined by the appended claims.

Claims

1. A memory circuit comprising: An array of thin-film ferroelectric memory transistors is formed by multiple NOR memory strings intersecting with multiple local word line structures, the multiple NOR memory strings being arranged as multiple stacked, vertically aligned NOR memory strings, each of the multiple NOR memory strings including a common drain line and a common source line. The plurality of local word line structures include groups of local word line structures, each of the local word line structures in a respective group being arranged along at least one stack of the NOR memory strings. Each of the plurality of local word line structures extends vertically along the at least one stack of the vertically aligned NOR memory strings and includes a channel and a gate conductor separated by a ferroelectric gate dielectric layer. The thin-film ferroelectric memory transistors are formed at each intersection point of the common drain line and the common source line of the respective local word line structure and the respective NOR memory string. The gate conductor of each local word line structure serves as the common gate terminal of the thin-film ferroelectric memory transistors in the vertically aligned NOR memory strings of the plurality of stacks intersecting with the respective local word line structure. Multiple global word lines are arranged orthogonally to the multiple NOR memory strings, and each of the multiple global word lines is aligned with a set of local word line structures provided across the multiple stacks; as well as A plurality of word line select transistors, comprising groups of word line select transistors, each group arranged along the stacked NOR memory string, each of the plurality of word line select transistors being disposed between a respective local word line structure and an associated global word line, and including a source terminal for the gate conductor of the associated local word structure, a drain terminal coupled to the associated global word line, and a gate terminal coupled to receive a respective select gate signal, the group of each of the word line select transistors being controlled by the same select gate signal. In response to a global word line being asserted to select a set of associated local word line structures, a corresponding group of word line selection transistors is activated by a corresponding selection gate signal to electrically connect the asserted global word line to the common gate terminal of the associated local word line structure to activate one of the local word line structures in the set of local word line structures.

2. The memory device of claim 1, wherein the plurality of word line select transistors are thin-film transistors, each of the plurality of word line select transistors includes a channel layer and a gate dielectric layer, the gate dielectric layer being formed between the channel layer and the gate terminal, and the channel layer of the word line select transistor and the channel layer of the thin-film ferroelectric memory transistor being formed of the same material.

3. The memory device of claim 1, wherein the respective group of word line select transistors has a channel structure covering the associated local word line structure and having the same periodicity as the local word line structure, each of the channel structures including a gate dielectric layer surrounding the channel layer.

4. The memory device of claim 3, wherein the gate terminals of the plurality of word line select transistors include conductive layers formed over the plurality of stacked NOR memory strings, each conductive layer contacting the channel structure in each respective group of the word line select transistors.

5. The memory device of claim 3, wherein the gate terminals of the plurality of word line select transistors include a conductive layer formed to cover the plurality of stacked NOR memory strings and surround the channel structure in each respective group of the word line select transistors.

6. The memory device of claim 1, wherein a first global word line is asserted to select a first subset of thin-film ferroelectric memory transistors formed by the stack of the plurality of NOR memory strings and intersecting with a first set of local word line structures, and a first group of word line selection transistors is activated to select a second subset of the thin-film ferroelectric memory transistors in the first subset of the ferroelectric memory transistors that are associated with the activated local word line structures, the remaining thin-film ferroelectric memory transistors in the first subset remaining unselected.

7. The memory device of claim 6, wherein the second subset of the thin-film ferroelectric memory transistors includes the thin-film ferroelectric memory transistors in the stack of the NOR memory strings associated with the first set of the first local word line structure, the first set of the local word line structure having the gate conductor electrically connected to the asserted first global word line via the first group of the word line select transistors.

8. The memory device of claim 6, wherein the second subset of the thin-film ferroelectric memory transistors comprises thin-film ferroelectric memory transistors in the stack of two NOR memory strings associated with the first set of the local word line structure, the first set of the local word line structure having a gate conductor electrically connected to the asserted first global word line via the first group of the word line select transistors.

9. The memory device of claim 1, wherein each NOR memory string in the respective stack is isolated from adjacent NOR memory strings in the same stack by an insulating layer.

10. The memory device of claim 1, wherein in each local word line structure, the channel layer is formed adjacent to each NOR memory string in the stack and is discontinuous between adjacent NOR memory strings.

11. The memory device of claim 1, wherein the array of thin-film ferroelectric memory transistors is organized into a plurality of pages of thin-film ferroelectric memory transistors, and a global word line is asserted to select a set of local word line structures aligned with the global word line, a first subset of word line selection transistors being activated by the corresponding selection gate signal to electrically connect the asserted global word line to the common gate terminal of the associated local word line structure to activate the local word line structure associated with a given page of thin-film ferroelectric memory transistors.

12. A three-dimensional memory structure formed above a flat surface of a semiconductor substrate, the three-dimensional memory structure comprising: An array of thin-film ferroelectric memory transistors is organized into a plurality of stacked NOR memory strings, each of the plurality of stacks being separated from each of adjacent stacks by a trench along a first direction, the plurality of stacks extending along a second direction substantially parallel to the flat surface of the semiconductor substrate, the NOR memory strings of each stack being stacked on top of each other along a third direction substantially perpendicular to the flat surface, each NOR memory string including a common drain layer spaced apart from a common source layer, local word line structures being configured to contact the stacks of the NOR memory strings and spaced apart in the second direction, each local word line structure extending upward in the third direction and including a channel layer contacting the NOR memory strings in the associated stack, a ferroelectric gate dielectric layer being formed adjacent to the channel layer, and a gate conductor layer being disposed adjacent to the ferroelectric gate dielectric layer in the local word line structure, the gate conductor layer of each local word line structure serving as a common gate terminal for the thin-film ferroelectric memory transistors in the corresponding stack of the NOR memory strings associated with the local word line structure; as well as A plurality of word line select transistors, each of which is associated with a given local word line structure, each word line select transistor including a source terminal for the gate conductor layer of the associated local word structure, a drain terminal coupled to one of the plurality of global word lines, and a gate terminal coupled to receive a corresponding select gate signal. In response to a first global word line among the plurality of global word lines, a first global word line is asserted to select an associated set of local word line structures. A first word line selection transistor is activated by a first selection gate signal to electrically connect the asserted first global word line to the common gate terminal of the associated local word line structures to activate one of the local word line structures in the set of local word line structures.

13. The three-dimensional memory structure of claim 12, wherein the thin-film ferroelectric memory transistor in each NOR memory string includes a drain terminal formed by the common drain layer as a bit line, a source terminal formed by the common source layer, and a gate terminal formed by the gate conductor layer of the local word line structure in contact with the NOR memory string, each thin-film ferroelectric memory transistor being formed at the intersection of the NOR memory string and the local word line structure.

14. The three-dimensional memory structure of claim 12, wherein the plurality of word line select transistors are thin-film transistors, each word line select transistor including a channel layer and a gate dielectric layer, the gate dielectric layer being formed between the channel layer and the gate conductor layer, and the channel layer of the word line select transistor and the channel layer of the thin-film ferroelectric memory transistor being formed of the same material.

15. The three-dimensional memory structure of claim 12, wherein the plurality of global word lines extend in the first direction and have the same periodicity as the local word line structure.

16. The three-dimensional memory structure of claim 12, wherein the first global word line is asserted to select a first subset of the thin-film ferroelectric memory transistors that span the plurality of stacked NOR memory strings and intersect with a first set of local word line structures, and a first group of word line selection transistors is activated to select a second subset of the thin-film ferroelectric memory transistors in the first subset that are associated with the activated local word line structures, the remaining thin-film ferroelectric memory transistors in the first subset remaining unselected.

17. The three-dimensional memory structure of claim 16, wherein the second subset of the thin-film ferroelectric memory transistors includes thin-film ferroelectric memory transistors in a stacked NOR memory string associated with the first set of the local word line structure, the first set of the local word line structure having the gate conductor layer electrically connected to the asserted first global word line via the word line select transistor in the first group.

18. The three-dimensional memory structure of claim 16, wherein the second subset of the thin-film ferroelectric memory transistors comprises thin-film ferroelectric memory transistors in two stacked NOR memory strings associated with the first set of the local word line structure, the first set of the local word line structure having the gate conductor layer electrically connected to the asserted first global word line via the word line select transistor in the first group.

19. The three-dimensional memory structure of claim 12, wherein the plurality of word line select transistors comprises groups of word line select transistors, each group being arranged along the plurality of stacked NOR memory strings, and wherein the plurality of word line select transistors have channel structures covering the local word line structures and having the same periodicity as the local word line structures, each of the channel structures comprising a gate dielectric layer surrounding the channel layer.

20. The three-dimensional memory structure of claim 19, wherein the gate terminals of the plurality of word line select transistors include conductive layers formed to cover the plurality of stacked NOR memory strings, each conductive layer contacting the channel structure in each respective group of the word line select transistors.

21. The three-dimensional memory structure of claim 19, wherein the gate terminals of the plurality of word line select transistors include a conductive layer formed to cover the plurality of stacked NOR memory strings and surround the channel structure in each respective group of the word line select transistors.

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