Isolation switch and sequencer

Abstract

A conduction circuit (501) includes a first primary coil (511) connected to a pulse supply circuit (503) and a first secondary coil (512) electromagnetically coupled to the first primary coil (511). The pulse supply circuit (503) is configured to supply a pulse signal (Sp1) to the first primary coil (511) in a state in which the control signal (DIN) is at a first level, and to supply a pulse signal (Sp2) to the second primary coil (521) in a specific period after a point in time when the control signal (DIN) is switched from the first level to a second level different from the first level.

Description

Technical Field

[0001] This disclosure relates to disconnecting switches and sequencers using disconnecting switches. Furthermore, this disclosure relates to signal transmission devices. Background Technology

[0002] To date, switches that isolate the primary and secondary circuits from each other by using optocouplers have been employed (e.g., see Patent Document 1).

[0003] Furthermore, signal transmission devices that transmit signals between primary and secondary circuit systems while electrically isolating them are used in various applications (e.g., power supply devices or motor drive devices).

[0004] Note that another patent document 2 published by the applicant may be cited as an example of the related technology in relation to the above description.

[0005] Reference List

[0006] Patent documents

[0007] Patent Document 1: JP-A-2020-096051

[0008] Patent document 2: WO-A-2022 / 070944. Summary of the Invention

[0009] The demand for disconnecting switches that can operate stably for extended periods is constantly growing.

[0010] Furthermore, in signal transmission devices of related technologies, signal transmission from the primary circuit system to the secondary circuit system may be interfered with when the power supply to the primary circuit system is unstable or insufficient.

[0011] For example, the disconnecting switch according to this disclosure includes:

[0012] A switching unit is configured to be controlled to cause the switching unit to enter an on / off state;

[0013] A conduction circuit is configured to control the switching unit, causing the switching unit to enter the conduction state;

[0014] The regulating circuit is configured to at least adjust the switching unit from the on state to the off state; and

[0015] The pulse supply circuit is configured to...

[0016] Receive control signals; and

[0017] A pulse signal is provided to at least one of the conducting circuit and the regulating circuit.

[0018] The conducting circuit includes a first isolation device, which comprises:

[0019] The first primary coil connected to the pulse supply circuit, and

[0020] The first primary coil is electromagnetically coupled to the first primary coil, and

[0021] The conducting circuit is configured to use an induced current to put the switching unit into the conducting state, the induced current flowing in response to a rising pulse signal supplied to the first primary coil.

[0022] The regulating circuit includes:

[0023] The second isolation device includes

[0024] The second primary coil, which is connected to the pulse supply circuit, and the second stage coil, which is electromagnetically coupled to the second primary coil, and

[0025] The regulating device is configured to regulate the switching unit to the non-conducting state by adjusting the voltage at the control terminal of the switching unit using the induced current flowing through the secondary coil in response to the rise of the pulse signal.

[0026] The pulse supply circuit is configured as follows:

[0027] When the control signal is at a first level, the pulse signal is supplied to the first primary coil, and

[0028] After the control signal switches from the first level to a second level different from the first level, the pulse signal is supplied to the second primary coil.

[0029] The switching unit is configured to be turned on when the control signal is at the first level.

[0030] Furthermore, for example, the signal transmission device according to this disclosure is configured to transmit a signal between a primary circuit system and a secondary circuit system while isolating the primary circuit system and the secondary circuit system, the signal transmission device comprising:

[0031] A first isolation device is configured to transmit a first signal from the secondary circuit system to the primary circuit system;

[0032] A second isolation device is configured to transmit a second signal from the primary circuit system to the secondary circuit system;

[0033] A driving circuit is provided in the secondary circuit system and configured to drive the first isolation device;

[0034] A switching circuit, disposed in the primary circuit system and configured to switch the connection state between the first isolation device and the second isolation device according to an input signal; and

[0035] The receiving circuit is configured to detect the second signal and generate an output signal based on the input signal. Attached Figure Description

[0036] Figure 1 It is a diagram showing the basic structure of a signal transmission device.

[0037] Figure 2 This is a diagram showing the basic structure of a transformer chip.

[0038] Figure 3 This is a three-dimensional view of a semiconductor device used as a dual-channel transformer chip.

[0039] Figure 4 yes Figure 3 A top view of the semiconductor device shown.

[0040] Figure 5 It means in Figure 3 A top view of a layer in a semiconductor device in which a low-potential coil is formed.

[0041] Figure 6 It means in Figure 3 A top view of a layer in a semiconductor device in which a high-potential coil is formed.

[0042] Figure 7 It is along Figure 6 The cross-sectional view of line VIII-VIII shown.

[0043] Figure 8 It means Figure 7 The diagram shows an enlarged view (separated structure) of region XIII.

[0044] Figure 9 This is a schematic diagram illustrating an example of the layout of a transformer chip.

[0045] Figure 10 This is a schematic diagram of the first embodiment of the signal transmission device.

[0046] Figure 11 This is a diagram illustrating a first operational example (intermittent) of the first implementation scheme.

[0047] Figure 12 This is a diagram illustrating a second operational example (continuous) of the first implementation scheme.

[0048] Figure 13 This is a schematic diagram of a second embodiment of the signal transmission device.

[0049] Figure 14 This is a schematic diagram of a third embodiment of the signal transmission device.

[0050] Figure 15 This is a diagram illustrating an operational example of the third implementation scheme.

[0051] Figure 16 This is a schematic diagram of the fourth embodiment of the signal transmission device.

[0052] Figure 17 This is a schematic diagram of the fifth embodiment of the signal transmission device.

[0053] Figure 18 This is a schematic diagram of the sixth embodiment of the signal transmission device.

[0054] Figure 19 This is a diagram illustrating an operational example of the sixth implementation scheme.

[0055] Figure 20 This is a schematic diagram of the seventh embodiment of the signal transmission device.

[0056] Figure 21 This is a schematic diagram of the eighth embodiment of the signal transmission device.

[0057] Figure 22 This is a diagram illustrating an operational example of the eighth implementation scheme.

[0058] Figure 23 This is a schematic circuit diagram illustrating various embodiments of the disconnecting switch according to the present disclosure.

[0059] Figure 24 This is a timing diagram showing the operation of the disconnecting switch.

[0060] Figure 25 This is a timing diagram showing the operation of the disconnecting switch in the first variant example.

[0061] Figure 26 This is a schematic circuit diagram of the disconnecting switch in the second variation.

[0062] Figure 27 This is a timing diagram showing the operation of the disconnecting switch in the second variant example.

[0063] Figure 28 This is a schematic circuit diagram of the disconnecting switch in the third variation.

[0064] Figure 29 This is a schematic circuit diagram of the disconnecting switch in the fourth variation.

[0065] Figure 30 This is a schematic circuit diagram of the disconnecting switch in the fifth variation.

[0066] Figure 31 This is a timing diagram showing the operation of the disconnecting switch in the fifth variant example.

[0067] Figure 32 This is a schematic circuit diagram of the disconnecting switch in the sixth variant example.

[0068] Figure 331 is a schematic circuit diagram showing another configuration example of the disconnecting switch of the sixth variant.

[0069] Figure 34 This is a schematic circuit diagram of the disconnecting switch in the seventh variation.

[0070] Figure 35 This is a timing diagram showing the operation of the disconnecting switch in the seventh variation.

[0071] Figure 36 This is a diagram illustrating an additional implementation of the disconnecting switch.

[0072] Figure 37 This is a diagram showing the first main part of the disconnecting switch according to an additional embodiment.

[0073] Figure 38 This is a diagram illustrating an example of operation in the first main part.

[0074] Figure 39 This is a diagram showing the second main part of the disconnecting switch according to an additional embodiment.

[0075] Figure 40 This is a diagram showing the third main part of the disconnecting switch according to an additional embodiment.

[0076] Figure 41 This is a diagram showing the third chip in the third main section.

[0077] Figure 42 This is a diagram showing a variant example of the third main part.

[0078] Figure 43 This is a diagram showing the third chip in a variant of the third main part.

[0079] Figure 44 This is a diagram showing a variant example of the second chip.

[0080] Figure 45 This is a diagram illustrating an operational example of the second chip in the variant.

[0081] Figure 46 This is a diagram illustrating an additional embodiment of the signal transmission device.

[0082] Figure 47 This is a diagram illustrating an example configuration of an isolated power supply circuit.

[0083] Figure 48 This is a diagram illustrating a variant example of a signal transmission device according to an additional embodiment.

[0084] Figure 49 This is a diagram showing a variation of an isolated power supply circuit.

[0085] Figure 50 This is a diagram illustrating a variation of a query isolation device. Detailed Implementation

[0086] In the following description, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout all the drawings to be referenced, the same components are designated by the same reference numerals, and redundant descriptions of the same components will generally not be given.

[0087] First, some terms used in embodiments of this disclosure will be described. The term "connection" between multiple parts forming a circuit (such as any device, wiring (wire), and node) covers not only mechanical connections but also electrical connections, i.e., states that allow current to flow. In other words, "connection" encompasses the case of "electrical connection."

[0088] This line refers to the wiring through which electrical signals are propagated or supplied. Ground potential refers to a reference conductive portion with a potential of 0V, or to the potential of 0V itself. The reference conductive portion is formed of a conductor such as a metal. A potential of 0V may sometimes be referred to as ground potential. In embodiments of this disclosure, voltages described without a specific reference represent potentials relative to ground potential.

[0089] "Level" refers to a potential level, and any signal or voltage at the Hi level has a potential higher than that at the Lo level. Any digital signal at the Hi or Lo level is a signal level. Strictly speaking, "a signal or voltage at the Hi level" means "the level of the signal or voltage is at the Hi level," and "a signal or voltage at the Lo level" means "the level of the signal or voltage is at the Lo level." A signal level can be expressed as a signal level, and a voltage level can be expressed as a voltage level. For any given signal, when the signal is at the Hi level, its inverted signal is at the Lo level, and when the signal is at the Lo level, its inverted signal is at the Hi level. Note that the Hi level can sometimes be referred to as the first level.

[0090] For any signal at a Hi or Lo level, the period during which the signal level is at the Hi level is called the Hi level period. Similarly, the period during which the signal level is at the Lo level is called the Lo level period. This also applies to any voltage at a Hi or Lo level.

[0091] A switching device is either turned on or off. When a switching device is turned on, conduction is established between its two terminals. Conversely, when a switching device is turned off, conduction is not established between its two terminals. Furthermore, the period during which a switching device is turned on is called the on-time, and the period during which a switching device is turned off is called the off-time. Similarly, turning on a previously off switching device can sometimes be referred to as turning on, and turning off a previously turned-on switching device can sometimes be referred to as turning off.

[0092] MOS (Metal-Oxide-Semiconductor) field-effect transistors can be used as examples of switching devices. A MOS field-effect transistor is a transistor with a gate structure consisting of at least three layers: a layer formed of conductor or semiconductor (such as polycrystalline silicon with low resistance), an insulating layer, and a P-channel, N-channel, or intrinsic semiconductor layer. That is, the gate structure of a MOS field-effect transistor is not limited to a three-layer structure composed of metal, oxide, and semiconductor.

[0093] For any transistor configured as a field-effect transistor (such as a MOS field-effect transistor), conduction is established between the drain and source when the transistor is turned on. Similarly, conduction is not established (disconnected) between the drain and source when the transistor is turned off. This also applies to transistors not classified as field-effect transistors. In any MOS field-effect transistor described below, the back gate is connected to the source unless otherwise stated. Note that in the following description, MOS field-effect transistors may sometimes be simply referred to as MOS transistors.

[0094] <Signal Transmission Device (Basic Structure)>

[0095] Figure 1 This diagram illustrates the basic structure of a signal transmission device. In this example, the signal transmission device 200 is a semiconductor integrated circuit device (so-called an insulated gate driver IC) that insulates the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system), and transmits pulse signals from the primary circuit system 200p to the secondary circuit system 200s to drive the gate of a switching element (not shown) disposed in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by sealing the controller chip 210, driver chip 220, and transformer chip 230 into a single package.

[0096] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (e.g., a maximum of 7V based on GND1). The controller chip 210 integrates, for example, a pulse transmitting circuit 211, buffers 212 and 213.

[0097] The pulse transmitting circuit 211 is a pulse generator that generates transmit pulse signals S11 and S21 based on the input pulse signal IN. More specifically, the pulse transmitting circuit 211 drives the transmit pulse signal S11 (single or multiple transmit pulse outputs) when the input pulse signal IN is high, and drives the transmit pulse signal S21 when the input pulse signal IN is low. That is, the pulse transmitting circuit 211 drives either the transmit pulse signal S11 or S21 according to the logic level of the input pulse signal IN.

[0098] The buffer 212 receives the input of the transmission pulse signal S11 from the pulse transmission circuit 211 and performs pulse drive on the transformer chip 230 (specifically the transformer 231).

[0099] The buffer 213 receives the input of the transmission pulse signal S21 from the pulse transmission circuit 211 and performs pulse drive on the transformer chip 230 (specifically the transformer 232).

[0100] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (e.g., a maximum of 30V based on GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0101] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically the transformer 231) and outputs it to the pulse receiving circuit 223.

[0102] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically the transformer 232) and outputs it to the pulse receiving circuit 223.

[0103] The pulse receiving circuit 223 drives the driver 224 based on the received pulse signals S12 and S22 input via buffers 221 and 222, thereby generating an output pulse signal OUT. More specifically, the pulse receiving circuit 223 drives the driver 224 in such a way that it receives the pulse of the received pulse signal S12 to raise the output pulse signal OUT to a high level, and on the other hand, it receives the pulse of the received pulse signal S22 to lower the output pulse signal OUT to a low level. That is, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. Furthermore, an RS flip-flop can be appropriately used as the pulse receiving circuit 223, for example.

[0104] The driver 224 generates an output pulse signal OUT according to the drive control of the pulse receiving circuit 223.

[0105] Transformer chip 230 uses transformers 231 and 232 to DC-ground insulate the controller chip 210 from the driver chip 220, and outputs the transmit pulse signals S11 and S21 input from the pulse transmit circuit 211 as receive pulse signals S12 and S22 to the pulse receive circuit 223. Furthermore, in this specification, "DC-ground insulation" means that the two objects to be insulated are not connected by a conductor.

[0106] More specifically, transformer 231 outputs a receiving pulse signal S12 from secondary coil 231s based on the transmitting pulse signal S11 input to primary coil 231p. On the other hand, transformer 232 outputs a receiving pulse signal S22 from secondary coil 232s based on the transmitting pulse signal S21 input to primary coil 232p.

[0107] Thus, due to the characteristics of the spiral coil used for communication between insulators, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (equivalent to rising and falling signals), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0108] Furthermore, the signal transmission device 200 of this embodiment differs from the controller chip 210 and the driver chip 220 in that it independently has a transformer chip 230 that only carries transformers 231 and 232, and these three chips are sealed into a single package.

[0109] By adopting this structure, both the controller chip 210 and the driver chip 220 can be formed using general low-to-medium voltage withstand processes (a few volts to tens of volts withstand voltage). Therefore, it is not necessary to use a dedicated high-voltage withstand process (a few thousand volts withstand voltage), which can reduce manufacturing costs.

[0110] Furthermore, the signal transmission device 200 can be appropriately utilized, for example, by a power supply device or an electric motor drive device of an on-board device mounted on the vehicle. In addition to engine-powered vehicles, the aforementioned vehicles also include electric vehicles (BEV [pure electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV [plug-in hybrid electric vehicle], or FCEV / FCV [fuel cell electric vehicle], etc. xEV).

[0111] <Transformer Chip (Basic Structure)>

[0112] Next, the basic structure of the transformer chip 230 will be explained. Figure 2 This diagram illustrates the basic structure of transformer chip 230. In the transformer chip 230 of this diagram, transformer 231 includes a primary side coil 231p and a secondary side coil 231s opposite each other in the vertical direction. Transformer 232 includes a primary side coil 232p and a secondary side coil 232s opposite each other in the vertical direction.

[0113] Primary side coils 231p and 232p are both formed on the first wiring layer (lower layer) 230a of the transformer chip 230. Secondary side coils 231s and 232s are both formed on the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. Furthermore, the secondary side coil 231s is positioned directly above the primary side coil 231p, opposite to it. Similarly, the secondary side coil 232s is positioned directly above the primary side coil 232p, opposite to it.

[0114] The primary side coil 231p is arranged in a spiral pattern, starting from the first end connected to the internal terminal X21 and spiraling clockwise around the internal terminal X21, with its second end connecting to the internal terminal X22. Conversely, the primary side coil 232p is arranged in a spiral pattern, starting from the first end connected to the internal terminal X23 and spiraling counterclockwise around the internal terminal X23, with its second end connecting to the internal terminal X22. The internal terminals X21, X22, and X23 are arranged in a straight line in the order shown in the diagram.

[0115] Internal terminal X21 is connected to external terminal T21 of the second layer 230b via conductive wiring Y21 and through-hole Z21. Internal terminal X22 is connected to external terminal T22 of the second layer 230b via conductive wiring Y22 and through-hole Z22. Internal terminal X23 is connected to external terminal T23 of the second layer 230b via conductive wiring Y23 and through-hole Z23. Furthermore, external terminals T21 to T23 are arranged in a straight line for wire connection with the controller chip 210.

[0116] The secondary-side coil 231s is spirally arranged around the external terminal T24 in a counter-clockwise direction, starting from the first end connected to the external terminal T24, and the second end, corresponding to its endpoint, is connected to the external terminal T25. On the other hand, the secondary-side coil 232s is spirally arranged around the external terminal T26 in a clockwise direction, starting from the first end connected to the external terminal T26, and the second end, corresponding to its endpoint, is connected to the external terminal T25. Furthermore, the external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure for wire connection to the driver chip 220.

[0117] Secondary coils 231s and 232s are AC connected to primary coils 231p and 232p via magnetic coupling, respectively, and are DC insulated from primary coils 231p and 232p. That is, driver chip 220 is AC connected to controller chip 210 via transformer chip 230, and is DC insulated from controller chip 210 via transformer chip 230.

[0118] <Transformer Chip (Dual-Channel Type)>

[0119] Figure 3 This is a perspective view of a semiconductor device 5 used as a dual-channel transformer chip. Figure 4 yes Figure 3 A top view of the semiconductor device 5 shown. Figure 5 It means in Figure 3 The diagram shows a top view of the semiconductor device 5 in which a low-potential coil 22 (equivalent to the primary coil of a transformer) is formed. Figure 6 It means in Figure 3 The diagram shows a top view of the layer in the semiconductor device 5 in which a high-potential coil 23 (equivalent to the secondary coil of a transformer) is formed. Figure 7 It is along Figure 6 The cross-sectional view of line VIII-VIII shown.

[0120] Reference Figures 3 to 7 The semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0121] Wide bandgap semiconductors are composed of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide bandgap semiconductor is preferably 2.0 eV or higher. Wide bandgap semiconductors can also be SiC (silicon carbide). Compound semiconductors can be III-V group compound semiconductors. Compound semiconductors may also contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0122] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a stacked structure comprising a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0123] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed into a quadrilateral shape (rectangular shape in this embodiment) when viewed from their normal direction Z in a top view (hereinafter referred to as "top view").

[0124] Chip sidewalls 44A to 44D include: a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and are opposite each other along a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend along the second direction Y and are opposite each other along the first direction X. Chip sidewalls 44A to 44D are formed by polished surfaces.

[0125] The semiconductor device 5 further includes an insulating layer 51 formed on a first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. In a top view, the insulating main surface 52 is formed as a quadrilateral shape (rectangular shape in this embodiment) matching the first main surface 42. The insulating main surface 52 extends parallel to the first main surface 42.

[0126] The insulating sidewalls 53A to 53D include: a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form grinding surfaces flush with the chip sidewalls 44A to 44D.

[0127] The insulating layer 51 is composed of a multilayer insulating stack structure including a lower insulating layer 55, an upper insulating layer 56, and multiple (11 layers in this embodiment) interlayer insulating layers 57. The lower insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The multiple interlayer insulating layers 57 are insulating layers located between the lower insulating layer 55 and the upper insulating layer 56. In this embodiment, the lower insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the lower insulating layer 55 and the thickness of the upper insulating layer 56 can be more than 1 μm and less than 3 μm (for example, about 2 μm).

[0128] The multiple interlayer insulating layers 57 each have a stacked structure comprising a first insulating layer 58 on the side of the lowest insulating layer 55 and a second insulating layer 59 on the side of the highest insulating layer 56. The first insulating layer 58 may also comprise silicon nitride. The first insulating layer 58 is formed as an etch stop layer relative to the second insulating layer 59. The thickness of the first insulating layer 58 may be greater than 0.1 μm and less than 1 μm (e.g., about 0.3 μm).

[0129] A second insulating layer 59 is formed on top of the first insulating layer 58. It comprises an insulating material different from the first insulating layer 58. The second insulating layer 59 may also comprise silicon oxide. The thickness of the second insulating layer 59 can be 1 μm or more and 3 μm or less (e.g., about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0130] The total thickness DT of the insulating layer 51 can be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the required insulation withstand voltage (insulation breakdown withstand voltage). In addition, the insulating materials of the bottom insulating layer 55, the top insulating layer 56 and the interlayer insulating layer 57 are arbitrary and not limited to specific insulating materials.

[0131] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (equivalent to the previous transformers). That is, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed spaced apart from the insulating sidewalls 53A to 53D inside the insulating layer 51. The multiple transformers 21 are formed spaced apart along a first direction X.

[0132] Specifically, in the top view, the plurality of transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed sequentially from the insulating sidewall 53C side toward the insulating sidewall 53D side. The plurality of transformers 21A to 21D each have the same construction. The construction of the first transformer 21A will be described below as an example. The description of the construction of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D, applicable to the construction of the first transformer 21A, is omitted.

[0133] Reference Figures 5 to 7 The first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within an insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 opposite to the low-potential coil 22 along the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in the region sandwiched between the lowermost insulating layer 55 and the uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0134] The low-potential coil 22 is formed within the insulating layer 51 on the side of the lowest insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 relative to the low-potential coil 22 on the side of the uppermost insulating layer 56 (insulating main surface 52). That is, the high-potential coil 23 is positioned opposite the semiconductor chip 41, separated from the low-potential coil 22. The placement of the low-potential coil 22 and the high-potential coil 23 is arbitrary. Furthermore, the high-potential coil 23 only needs to be positioned opposite the low-potential coil 22, separated from it by one or more interlayer insulating layers 57.

[0135] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulation 57) is appropriately adjusted according to the insulation withstand voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed in the third layer of interlayer insulation 57 starting from the side of the bottommost insulation layer 55. In this embodiment, the high-potential coil 23 is formed in the first layer of interlayer insulation 57 starting from the side of the topmost insulation layer 56.

[0136] The low-potential coil 22 is embedded in the interlayer insulation layer 57, passing through the first insulation layer 58 and the second insulation layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 wound in a spiral shape between the first inner end 24 and the first outer end 25. In the top view, the first helical portion 26 is wound in a spiral shape extending in an elliptical shape (oblong shape). The portion forming the innermost periphery of the first helical portion 26 divides an elliptical first inner region 66 in the top view.

[0137] The number of turns in the first helical portion 26 can be 5 or more and 30 or less. The width of the first helical portion 26 can also be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction orthogonal to the helical direction. The first winding pitch of the first helical portion 26 can be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction orthogonal to the helical direction.

[0138] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and not limited to any particular shape. Figure 5 As shown in the diagram. The first spiral portion 26 can also be wound into a polygonal shape such as a triangular shape or a quadrilateral shape or a circular shape in the top view. The first inner region 66 can also be divided into a polygonal shape such as a triangular shape or a quadrilateral shape or a circular shape in the top view according to the winding shape of the first spiral portion 26.

[0139] The low-potential coil 22 may also comprise at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may also have a laminated structure comprising a barrier layer and a main body layer. The barrier layer divides recessed spaces within the interlayer insulating layer 57. The barrier layer may comprise at least one of titanium and titanium nitride. The main body layer may comprise at least one of copper, aluminum, and tungsten.

[0140] A high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. In a top view, the second spiral portion 29 is spirally wound in an elliptical shape (oblong shape). In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines an elliptical second inner region 67 in a top view. The second inner region 67 of the second spiral portion 29 is opposite to the first inner region 66 of the first spiral portion 26 along the normal direction Z.

[0141] The number of turns in the second helical section 29 can be 5 or more and 30 or less. The number of turns in the second helical section 29 relative to the number of turns in the first helical section 26 is adjusted according to the voltage value to be boosted. Preferably, the number of turns in the second helical section 29 exceeds the number of turns in the first helical section 26. Of course, the number of turns in the second helical section 29 can be less than the number of turns in the first helical section 26, or it can be equal to the number of turns in the first helical section 26.

[0142] The width of the second helical portion 29 can be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction orthogonal to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0143] The second winding pitch of the second helical portion 29 can be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction orthogonal to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0144] The winding shape of the second spiral section 29 and the planar shape of the second inner region 67 are arbitrary and not limited to... Figure 6 As shown in the diagram. The second spiral portion 29 can also be wound into a polygonal shape such as a triangle or a quadrilateral shape, or a circle in the top view. The second inner region 67 can also be divided into a polygonal shape such as a triangle or a quadrilateral shape, or a circle in the top view, depending on the winding shape of the second spiral portion 29.

[0145] The high-potential coil 23 is preferably formed of the same conductive material as the low-potential coil 22. That is, the high-potential coil 23 preferably includes a barrier layer and a main body layer in the same way as the low-potential coil 22.

[0146] Reference Figure 4 The semiconductor device 5 includes a plurality of (12 in this figure) low-potential terminals 11 and a plurality of (12 in this figure) high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D.

[0147] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed at intervals along the second direction Y and at intervals along the first direction X in the region on the insulating sidewall 53B.

[0148] The plurality of low-potential terminals 11 includes: a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this embodiment, each of the plurality of low-potential terminals 11A to 11F is formed in twos. The number of the plurality of low-potential terminals 11A to 11F is arbitrary.

[0149] In the top view, the first low-potential terminal 11A is opposite to the first transformer 21A along the second direction Y. In the top view, the second low-potential terminal 11B is opposite to the second transformer 21B along the second direction Y. In the top view, the third low-potential terminal 11C is opposite to the third transformer 21C along the second direction Y. In the top view, the fourth low-potential terminal 11D is opposite to the fourth transformer 21D along the second direction Y. In the top view, the fifth low-potential terminal 11E is formed in the area between the first low-potential terminal 11A and the second low-potential terminal 11B. In the top view, the sixth low-potential terminal 11F is formed in the area between the third low-potential terminal 11C and the fourth low-potential terminal 11D.

[0150] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0151] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0152] Multiple high-potential terminals 12 and multiple low-potential terminals 11 are formed spaced apart on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple high-potential terminals 12 are formed spaced apart from the multiple low-potential terminals 11 in the region of the insulating sidewall 53A, and are arranged spaced apart along the first direction X.

[0153] In the top view, multiple high-potential terminals 12 are respectively formed in areas close to the corresponding transformers 21A to 21D. The high-potential terminals 12 are close to the transformers 21A to 21D in that the distance between the high-potential terminals 12 and the transformers 21 in the top view is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0154] Specifically, in the top view, a plurality of high-potential terminals 12 are spaced apart along the first direction X, opposite to a plurality of transformers 21A to 21D. More specifically, in the top view, the plurality of high-potential terminals 12 are spaced apart along the first direction X, located in the second inner region 67 of the high-potential coil 23 and the region between adjacent high-potential coils 23. Thus, in the top view, the plurality of high-potential terminals 12 are arranged side by side in a row with the plurality of transformers 21A to 21D along the first direction X.

[0155] The plurality of high-potential terminals 12 includes: a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this embodiment, each of the plurality of high-potential terminals 12A to 12F is formed in two. The number of the plurality of high-potential terminals 12A to 12F is arbitrary.

[0156] In the top view, a first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23). A second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23). A third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23). A fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23). A fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in the top view. A sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in the top view.

[0157] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0158] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0159] Reference Figures 5 to 7 The semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, respectively formed within an insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0160] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0161] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0162] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. The multiple first low-potential wirings 31 have the same construction. Hereinafter, the construction of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. The description of the construction of the other first low-potential wirings 31 is omitted for the first low-potential wiring 31 connected to the first transformer 21A.

[0163] The first low-potential wiring 31 includes: a through wiring 71, a low-potential connection wiring 72, a lead wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0164] The through-wire 71, low-potential connection wire 72, lead-out wire 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are preferably formed of the same conductive material as the low-potential coil 22. That is, the through-wire 71, low-potential connection wire 72, lead-out wire 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are preferably the same as the low-potential coil 22, each including a barrier layer and a main body layer.

[0165] The through-wire 71 extends through multiple interlayer insulation layers 57 in the insulation layer 51, forming a columnar shape extending along the normal direction Z. In this embodiment, the through-wire 71 is formed in the region between the lowermost insulation layer 55 and the uppermost insulation layer 56 in the insulation layer 51. The through-wire 71 has an upper end portion on the side of the uppermost insulation layer 56 and a lower end portion on the side of the lowermost insulation layer 55. The upper end portion of the through-wire 71 is formed in the same interlayer insulation layer 57 as the high-potential coil 23 and is covered by the uppermost insulation layer 56. The lower end portion of the through-wire 71 is formed in the same interlayer insulation layer 57 as the low-potential coil 22.

[0166] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed of the same conductive material as the low-potential coil 22. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80, like the low-potential coil 22, each include a barrier layer and a main body layer.

[0167] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and is opposite to the low-potential terminal 11 (first low-potential terminal 11A) along the normal direction Z. The second electrode layer 79 is formed in an island shape and is opposite to the first electrode layer 78 along the normal direction Z.

[0168] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulation layers 57 located between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the lowest insulation layer 55 to the highest insulation layer 56 in an electrically interconnected manner, and electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area smaller than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0169] Furthermore, the number of stacked layers of the plurality of wiring plug electrodes 80 is consistent with the number of stacked layers of the plurality of interlayer insulation layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulation layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulation layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 that penetrate multiple interlayer insulation layers 57 can also be formed.

[0170] A low-potential connection wiring 72 is formed within the same interlayer insulation layer 57 as the low-potential coil 22 in the first inner region 66 of the first transformer 21A (low-potential coil 22). The low-potential connection wiring 72 is formed in an island shape, facing the high-potential terminal 12 (first high-potential terminal 12A) along the normal direction Z. The low-potential connection wiring 72 preferably has a planar area exceeding the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0171] Lead-out wiring 73 is formed within interlayer insulating layer 57 in the region between semiconductor chip 41 and through wiring 71. In this embodiment, lead-out wiring 73 is formed within interlayer insulating layer 57, which is the first layer starting from the lowest insulating layer 55. Lead-out wiring 73 includes: a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of lead-out wiring 73 is located in the region between semiconductor chip 41 and the lower end of through wiring 71. The second end of lead-out wiring 73 is located in the region between semiconductor chip 41 and low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0172] The first connection plug electrode 74 is formed within the interlayer insulating layer 57 in the region between the through wiring 71 and the lead wiring 73, and is electrically connected to the first end of the through wiring 71 and the lead wiring 73. The second connection plug electrode 75 is formed within the interlayer insulating layer 57 in the region between the low-potential connection wiring 72 and the lead wiring 73, and is electrically connected to the second end of the low-potential connection wiring 72 and the lead wiring 73.

[0173] Multiple pad plug electrodes 76 are formed within the uppermost insulating layer 56 in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through wiring 71, respectively, and are electrically connected to the upper ends of the low-potential terminal 11 and the through wiring 71. Multiple substrate plug electrodes 77 are formed within the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the lead wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first ends of the lead wiring 73, respectively, and are electrically connected to the first ends of the semiconductor chip 41 and the lead wiring 73.

[0174] Reference Figure 6and Figure 7 Multiple first high-potential wirings 33 are electrically connected to the second inner ends 27 of the corresponding high-potential terminals 12A to 12D and the corresponding transformers 21A to 21D (high-potential coils 23), respectively. Each of the multiple first high-potential wirings 33 has the same construction. The following description uses the construction of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A as an example. The description of the construction of the other first high-potential wirings 33 is omitted for the first high-potential wiring 33 connected to the first transformer 21A.

[0175] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrodes 82 are preferably formed of the same conductive material as the low-potential coil 22, etc. That is, the high-potential connection wiring 81 and the pad plug electrodes 82 preferably include a barrier layer and a body layer, just like the low-potential coil 22, etc.

[0176] The high-potential connection wiring 81 is formed within the same interlayer insulation layer 57 as the high-potential coil 23 in the second inner region 67 of the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and is positioned opposite the high-potential terminal 12 (first high-potential terminal 12A) along the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. In the top view, the high-potential connection wiring 81 is formed with a gap from the low-potential connection wiring 72 and is not positioned opposite the low-potential connection wiring 72 along the normal direction Z. Therefore, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the insulation withstand voltage of the insulation layer 51 is improved.

[0177] Multiple pad plug electrodes 82 are formed within the uppermost insulating layer 56 in the region between the high-potential terminal 12 (first high-potential terminal 12A) and the high-potential connection wiring 81, respectively, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81. In a top view, each of the multiple pad plug electrodes 82 has a planar area smaller than the planar area of ​​the high-potential connection wiring 81.

[0178] Reference Figure 7Preferably, the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 (D2 < D1) between the low-potential coil 22 and the high-potential coil 23. Distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulation layers 57 (DT < D1). The ratio of distance D2 to distance D1, D2 / D1, can be 0.01 or more and 0.1 or less. Distance D1 is preferably 100 μm or more and 500 μm or less. Distance D2 can be 1 μm or more and 50 μm or less. Distance D2 is preferably 5 μm or more and 25 μm or less. The values ​​of distance D1 and distance D2 are arbitrary and appropriately adjusted according to the insulation withstand voltage to be achieved.

[0179] Reference Figure 6 as well as Figure 7 In the top view, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 in a manner that surrounds the transformers 21A to 21D.

[0180] The dummy pattern 85 is formed from a different pattern (a discontinuous pattern) than that of the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as a component of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D, suppressing electric field concentration targeting the high-potential coil 23. In this embodiment, the dummy pattern 85 is wound with a linear density equal to that of the high-potential coil 23 per unit area. The linear density of the dummy pattern 85 being equal to that of the high-potential coil 23 means that the linear density of the dummy pattern 85 converges within ±20% of the linear density of the high-potential coil 23.

[0181] The depth of the dummy pattern 85 inside the insulating layer 51 is arbitrary and adjusted according to the electric field strength to be mitigated. The dummy pattern 85 is preferably formed in a region in the normal direction Z that is close to the low-potential coil 22 and the high-potential coil 23. Furthermore, "close to the high-potential coil 23 in the normal direction Z" means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0182] In this case, electric field concentration against the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the better the electric field concentration against the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration against the high-potential coil 23 can be suppressed more appropriately. The dummy pattern 85 comprises multiple dummy patterns with different electrical states. The dummy pattern 85 may also include a high-potential dummy pattern.

[0183] The depth of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and adjusted according to the electric field strength to be mitigated. The high-potential dummy pattern 86 is preferably formed in a region in the normal direction Z that is close to the high-potential coil 23 relative to the low-potential coil 22. "Close to the high-potential coil 23 in the normal direction Z" means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0184] The dummy pattern 85 includes a suspended dummy pattern formed in an electrically suspended state within the insulation layer 51 in a manner located around the transformers 21A to 21D.

[0185] In this embodiment, the suspended dummy pattern, in the top view, appears as a densely wound line that partially covers and exposes the area surrounding the high-potential coil 23. The suspended dummy pattern can be formed with ends or without ends.

[0186] The depth position of the suspended dummy pattern inside the insulating layer 51 is arbitrary and can be adjusted according to the electric field strength to be mitigated.

[0187] The number of levitation lines is arbitrary and can be adjusted according to the electric field to be mitigated. A levitation dummy pattern can also be composed of multiple levitation dummy patterns.

[0188] Reference Figure 7 The semiconductor device 5 includes a second functional device 60 formed in the device region 62 on the first main surface 42 of the semiconductor chip 41. The second functional device 60 is formed utilizing the surface portion of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (lowest insulating layer 55). Figure 7 In the diagram, the second functional device 60 is simplified and shown through the dashed lines on the surface of the first main surface 42.

[0189] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring and to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is wound into the insulating layer 51 in order to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is wound into the insulating layer 51 in order to connect to the second functional device 60. Detailed descriptions of the low-potential and high-potential wirings of the second functional device 60 are omitted.

[0190] The second functional device 60 may also include at least one of a passive device, a semiconductor rectifier, and a semiconductor switch. Among the passive devices, the second functional device 60 may also include a circuit network formed by selectively combining any two or more of the passive devices, semiconductor rectifiers, and semiconductor switch devices. The circuit network may also form part or all of an integrated circuit.

[0191] Passive devices may include semiconductor passive devices. Passive devices may also include any one or both of resistors and capacitors. Semiconductor rectifier devices may also include at least one of pn junction diodes, PIN diodes, Zener diodes, Schottky barrier diodes, and fast recovery diodes. Semiconductor switching devices may also include at least one of BJTs (bipolar junction transistors), MISFETs (metal-insulator field-effect transistors), IGBTs (insulated gate bipolar junction transistors), and JFETs (junction field-effect transistors).

[0192] Reference Figures 5 to 7 The semiconductor device 5 further includes a sealing conductor 61 embedded within an insulating layer 51. In a top view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating sidewalls 53A to 53D, dividing the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 inhibits the ingress of moisture from the outer region 63 into the device region 62 and the formation of cracks.

[0193] Device area 62 is the area that includes the following: first functional device 45 (multiple transformers 21), second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, first low-potential wiring 31, second low-potential wiring 32, first high-potential wiring 33, second high-potential wiring 34, and dummy pattern 85. Outer area 63 is the area outside device area 62.

[0194] The sealed conductor 61 is electrically isolated from the device region 62. Specifically, the sealed conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealed conductor 61 is fixed in an electrically levitated state. The sealed conductor 61 does not form a current path connected to the device region 62.

[0195] In the top view, the sealing conductor 61 is formed as a strip along the insulating sidewalls 53A to 53D. In this embodiment, the sealing conductor 61 is formed as a four-sided ring (specifically, a rectangular ring) in the top view. Thus, the sealing conductor 61 divides the device region 62 into a four-sided (specifically, a rectangular) shape in the top view. In addition, the sealing conductor 61 divides the outer region 63 of the four-sided ring (specifically, a rectangular ring) surrounding the device region 62 in the top view.

[0196] Specifically, the sealing conductor 61 has an upper end portion on the insulating main surface 52 side, a lower end portion on the semiconductor chip 41 side, and a wall portion extending in a wall-like shape between the upper end portion and the lower end portion. In this embodiment, the upper end portion of the sealing conductor 61 is formed spaced apart from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end portion of the sealing conductor 61 is covered by the uppermost insulating layer 56. The upper end portion of the sealing conductor 61 may also be covered by one or more interlayer insulating layers 57. The upper end portion of the sealing conductor 61 may also be exposed from the uppermost insulating layer 56. The lower end portion of the sealing conductor 61 is formed spaced apart from the semiconductor chip 41 toward the upper end portion side.

[0197] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 such that it is located on the semiconductor chip 41 side relative to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Furthermore, the sealing conductor 61 is positioned within the insulating layer 51 opposite to the first functional device 45 (the plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Alternatively, the sealing conductor 61 may be positioned within the insulating layer 51 opposite to a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0198] The sealing conductor 61 comprises a plurality of sealing plug conductors 64 and one or more (in this embodiment, a plurality of) sealing through-hole conductors 65. The number of sealing through-hole conductors 65 is arbitrary. The uppermost sealing plug conductor 64 of the plurality of sealing plug conductors 64 forms the upper end of the sealing conductor 61. The plurality of sealing through-hole conductors 65 respectively form the lower end of the sealing conductor 61. The sealing plug conductors 64 and the sealing through-hole conductors 65 are preferably formed of the same conductive material as the low-potential coil 22. That is, the sealing plug conductors 64 and the sealing through-hole conductors 65 preferably include a barrier layer and a body layer, just like the low-potential coil 22.

[0199] Multiple hermetically sealed plug conductors 64 are embedded in multiple interlayer insulating layers 57, forming, in top view, four-sided rings (specifically rectangular rings) surrounding the device region 62. The multiple hermetically sealed plug conductors 64 are stacked from the bottom insulating layer 55 to the top insulating layer 56 in an interconnected manner. The number of stacks of the multiple hermetically sealed plug conductors 64 is the same as the number of stacks of the multiple interlayer insulating layers 57. Alternatively, one or more hermetically sealed plug conductors 64 may be formed that penetrate through multiple interlayer insulating layers 57.

[0200] If an assembly of multiple sealing plug conductors 64 forms a ring-shaped sealing conductor 61, it is not necessary for all of the multiple sealing plug conductors 64 to be formed in a ring shape. For example, at least one of the multiple sealing plug conductors 64 can also be formed in an end-to-end shape. Alternatively, at least one of the multiple sealing plug conductors 64 can also be divided into multiple end-to-end strip-shaped portions. However, given the risk of moisture ingress and crack formation within the device region 62, it is preferable that the multiple sealing plug conductors 64 be formed in an endless (ring-shaped) shape.

[0201] Multiple sealing via conductors 65 are formed in the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the sealing plug conductor 64. The multiple sealing via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the sealing plug conductor 64. The multiple sealing via conductors 65 have a planar area smaller than the planar area of ​​the sealing plug conductor 64. In the case where a single sealing via conductor 65 is formed, the single sealing via conductor 65 may also have a planar area greater than or equal to the planar area of ​​the sealing plug conductor 64.

[0202] The width of the sealing conductor 61 can be 0.1 μm or more and 10 μm or less. Preferably, the width of the sealing conductor 61 is 1 μm or more and 5 μm or less. The width of the sealing conductor 61 is defined by the width in a direction orthogonal to the direction in which the sealing conductor 61 extends.

[0203] Reference Figure 7 as well as Figure 8The semiconductor device 5 further includes a separation structure 130 located between the semiconductor chip 41 and the sealing conductor 61, electrically isolating the sealing conductor 61 from the semiconductor chip 41. The separation structure 130 preferably includes an insulator. In this embodiment, the separation structure 130 is formed of a field insulating film 131 formed on a first main surface 42 of the semiconductor chip 41.

[0204] The field insulating film 131 comprises at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 is composed of a LOCOS (Local Selective Oxidation of Silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary, as long as it is sufficient to insulate the semiconductor chip 41 from the sealing conductor 61. The thickness of the field insulating film 131 can be 0.1 μm or more and 5 μm or less.

[0205] The separation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the sealing conductor 61 in a top view. In this embodiment, the separation structure 130 is formed as a four-sided ring (specifically a rectangular ring) in a top view. The separation structure 130 has a connection portion 132 that connects to the lower end of the sealing conductor 61 (sealing via conductor 65). The connection portion 132 may also be an anchoring portion recessed into the lower end of the sealing conductor 61 (sealing via conductor 65) toward the semiconductor chip 41. Of course, the connection portion 132 may also be formed flush with the main surface of the separation structure 130.

[0206] The separation structure 130 includes: an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. In the top view, the inner end portion 130A divides the region where the second functional device 60 is formed (i.e., device region 62). The inner end portion 130A may also be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0207] The outer end portion 130B exposes from and is connected to the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may also be formed spaced apart from the chip sidewalls 44A to 44D within the first main surface 42.

[0208] The main body 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connecting portion 132 that connects to the lower end of the sealing conductor 61 (sealing through-hole conductor 65). The connecting portion 132 is formed in the main body 130C in a portion spaced apart from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can be implemented in various ways other than the field insulating film 131.

[0209] Reference Figure 7 The semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 in a manner that covers the sealing conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from the insulating main surface 52.

[0210] In this embodiment, the inorganic insulating layer 140 has a stacked structure comprising a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may also comprise silicon oxide. Preferably, the first inorganic insulating layer 141 comprises undoped silicon oxide, i.e., USG (undoped silicon glass). The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may also comprise silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the insulation withstand voltage on the high-potential coil 23 can be improved.

[0211] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the insulation breakdown voltage (V / cm) of USG exceeds that of silicon nitride. Therefore, when the inorganic insulating layer 140 is made thicker, it is preferable to form a first inorganic insulating layer 141 that is thicker than the second inorganic insulating layer 142.

[0212] The first inorganic insulating layer 141 may also comprise at least one of BPSG (borosilicate glass) and PSG (phosphosilicate glass), which are examples of silicon oxide. However, in this case, impurities (boron or phosphorus) are contained in the silicon oxide. Therefore, it is particularly preferable to form the first inorganic insulating layer 141 composed of USG in order to improve the insulation withstand voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may also have a single-layer structure composed of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0213] The inorganic insulating layer 140 covers the entire area of ​​the sealing conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed outside the sealing conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11 respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12 respectively. The inorganic insulating layer 140 may also have an overlapping portion that overlaps the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may also have an overlapping portion that overlaps the periphery of the high-potential terminals 12.

[0214] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may also contain a photosensitive resin. The organic insulating layer 145 may also contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0215] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Additionally, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. Based on these structures, the thickening of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, while the insulation withstand voltage on the high-potential coil 23 can be appropriately increased through the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0216] The organic insulating layer 145 includes a first portion 146 covering a region on the low-potential side and a second portion 147 covering a region on the high-potential side. The first portion 146 covers the sealing conductor 61 through the inorganic insulating layer 140. The first portion 146 has a plurality of low-potential terminal openings 148 in the region outside the sealing conductor 61, exposing a plurality of low-potential terminals 11 (low-potential pad openings 143). The first portion 146 may also have an overlap (overlap) that overlaps the periphery of the low-potential pad openings 143.

[0217] The second portion 147 is formed spaced apart from the first portion 146, such that the inorganic insulating layer 140 is exposed between the first portion 146 and the second portion 147. The second portion 147 has a plurality of high-potential terminal openings 149 that expose a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may also have an overlapping portion that overlaps the periphery of the high-potential pad openings 144.

[0218] Part 147 also covers transformers 21A to 21D and dummy pattern 85. Specifically, Part 147 also covers multiple high-potential coils 23, multiple high-potential terminals 12, a first high-potential dummy pattern 87, a second high-potential dummy pattern 88, and a floating dummy pattern 121.

[0219] The present invention can also be implemented in other ways. In the described embodiments, an example having a first functional device 45 and a second functional device 60 has been illustrated. However, it is also possible to employ a configuration that does not have a first functional device 45 and only has a second functional device 60. In this case, the dummy pattern 85 can also be removed. According to this configuration, the second functional device 60 can achieve the same effect as described in the first embodiment (except for the effect of the dummy pattern 85).

[0220] That is, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesirable conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed. Furthermore, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesirable conduction between the low-potential terminal 11 and the sealing conductor 61 can be suppressed.

[0221] Furthermore, in the described embodiment, an example with a second functional device 60 was given. However, the second functional device 60 is not necessary and may be omitted.

[0222] Furthermore, in the described embodiment, an example with a dummy pattern 85 was given. However, the dummy pattern 85 is not necessary and can be removed.

[0223] Furthermore, in the described embodiment, an example of a multi-channel type comprising multiple transformers 21 was given. However, a single-channel type comprising a single transformer 21 may also be used for the first functional device 45.

[0224] <Transformer Arrangement>

[0225] Figure 9 This is a top view (top view) schematically illustrating an example of the transformer arrangement in a dual-channel transformer chip 300 (equivalent to the previous semiconductor device 5). The transformer chip 300 in this figure includes: a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0226] In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary side coil L1s forming the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary side coil L1s. Pads a2 and b2 are connected to one end of the secondary side coil L2s forming the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary side coil L2s.

[0227] Additionally, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0228] Furthermore, the primary coils forming the first transformer 301, the second transformer 302, the third transformer 303, and the fourth transformer 304 are not explicitly shown in [the diagram / description]. Figure 9 However, the primary coils have essentially the same structure as the secondary coils L1s to L4s, and are arranged directly below each of the secondary coils L1s to L4s in a manner that is opposite to them respectively.

[0229] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. In addition, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0230] Additionally, pads a7 and b7 are connected to one end of the primary winding of the third transformer 303, and pads c4 and d4 are connected to the other end of the primary winding. Similarly, pads a8 and b8 are connected to one end of the primary winding of the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary winding.

[0231] However, the aforementioned pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the interior of the transformer chip 300 to the surface via through-holes (not shown).

[0232] Of the aforementioned pads, pads a1 to a8 correspond to the first current supply pads, and pads b1 to b8 correspond to the first voltage measurement pads. Additionally, pads c1 to c4 correspond to the second current supply pads, and pads d1 to d4 correspond to the second voltage measurement pads.

[0233] Therefore, in the case of the transformer chip 300 of this structural example, the series resistance of each coil can be accurately measured during defect inspection. Thus, not only can defective products with open circuits in each coil be rejected, but defective products with abnormal resistance values ​​in each coil (e.g., short circuits between coils) can also be appropriately rejected, thereby preventing defective products from entering the market.

[0234] Furthermore, for the transformer chip 300 that has passed the aforementioned defective product inspection, it is sufficient to use the aforementioned multiple pads as connection units with the primary-side chip and the secondary-side chip (such as the previously mentioned controller chip 210 and driver chip 220).

[0235] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 can be connected to the signal input or signal output terminals of the secondary-side chip, respectively. In addition, pads c1 and d1, and pads c2 and d2 can be connected to the common voltage application terminal (GND2) of the secondary-side chip, respectively.

[0236] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 can be connected to the signal input or signal output terminals of the primary-side chip, respectively. In addition, pads c3 and d3, and pads c4 and d4 can be connected to the common voltage application terminal (GND1) of the primary-side chip, respectively.

[0237] Here, as Figure 9 As shown, the first transformer 301 to the fourth transformer 304 are coupled together according to their respective signal transmission directions. If described in conjunction with this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary side chip to the secondary side chip, form a first pair via the first guard ring 305. Furthermore, for example, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary side chip to the primary side chip, form a second pair via the second guard ring 306.

[0238] The reason for this coupling is to ensure a withstand voltage between the primary and secondary coils when the primary and secondary coils that form the first transformer 301 to the fourth transformer 304 are stacked in a vertical configuration on the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0239] In addition, the first protection ring 305 and the second protection ring 306 can be connected to low-impedance wiring such as the grounding terminal via pads e1 and e2, respectively.

[0240] Furthermore, in the transformer chip 300, pads c1 and d1 are shared between secondary-side coils L1s and L2s. Pads c2 and d2 are shared between secondary-side coils L3s and L4s. Pads c3 and d3 are shared between primary-side coils L1p and L2p. Pads c4 and d4 are shared with their respective primary-side coils. By adopting this structure, the number of pads can be reduced, enabling miniaturization of the transformer chip 300.

[0241] In addition, such as Figure 9 As shown, the primary and secondary windings of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track-like shape with rounded corners) in the top view of the transformer chip 300. By arranging it in this way, the area of ​​the overlapping portions of the primary and secondary windings is increased, which can improve the transmission efficiency of the transformer.

[0242] Of course, the transformer arrangement in this diagram is just one example; the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices that integrate coils onto a semiconductor chip.

[0243] <Research on Power Supply>

[0244] In a signal transmission device that transmits signals between a primary circuit system and a secondary circuit system while electrically isolating them, power is supplied from the respective power sources of the primary and secondary circuit systems. However, the respective power sources for the primary and secondary circuit systems may not have sufficient current supply capability. Generally, the signal transmission side (e.g., the primary circuit system) requires a high current to drive the isolation devices. Therefore, in the event of an unstable or insufficient power supply to the primary circuit system, signal transmission from the primary circuit system to the secondary circuit system may be interfered with.

[0245] In signal transmission devices, such as those used as isolation comparators, isolation amplifiers, or isolation ADCs (analog-to-digital converters), the primary circuit system can function as a detection system (signal transmitting side), and the secondary circuit system can function as a monitoring and control system (signal receiving side). In this case, a power supply capable of reliably supplying high current to the primary circuit system may not exist.

[0246] In view of the above research, a signal transmission device is proposed in the following description, wherein signal transmission from the primary circuit system to the secondary circuit system is prevented from being interfered with even when the power supply of the primary circuit system is unstable or insufficient.

[0247] <Signal Transmission Device (First Implementation Scheme)>

[0248] Figure 10 This is a schematic diagram of a first embodiment of the signal transmission device. The signal transmission device 400 in this embodiment is a semiconductor integrated circuit device that transmits the input pulse signal IN of the primary circuit system 400p as the output pulse signal OUT of the secondary circuit system 400s while electrically isolating the primary circuit system 400p (VCC1-GND1 system) and the secondary circuit system 400s (VCC2-GND2 system).

[0249] The signal transmission device 400 is widely applicable to general applications that require signal transmission between a primary circuit system 400p and a secondary circuit system 400s while isolating them (such as isolation comparators, isolation amplifiers, isolation ADCs, or motor drivers or DC / DC converters that handle high voltages).

[0250] Signal transmission device 400 may include the signal transmission device 200 previously described ( Figure 1 Similar to the first chip 410, the second chip 420, and the third chip 430. The first chip 410, the second chip 420, and the third chip 430 can be sealed in a single package.

[0251] A switching circuit 411, which is located in the main circuit system 400p, is integrated into the first chip 410. The switching circuit 411 is operated by supplying a power supply voltage VCC1 from the power supply (not shown) of the main circuit system 400p.

[0252] The drive circuit 421, receiver circuit 422, and buffer 423, which are located in the secondary circuit system 400s, are integrated into the second chip 420. All of these drive circuits 421, receiver circuit 422, and buffer 423 operate by supplying a power supply voltage VCC2 from the power supply (not shown) of the secondary circuit system 400s. Note that the power supply for the secondary circuit system 400s has the ability to stably supply a current higher than the power supply current for the primary circuit system 400p.

[0253] Isolation devices 431 and 432, which serve as signal transmission paths between the primary circuit system 400p and the secondary circuit system 400s and provide electrical isolation between them, are integrated in the third chip 430. Isolation devices 431 and 432 correspond to the first isolation device and the second isolation device, respectively.

[0254] Isolating devices 431 and 432 can each be a transformer. That is, isolating device 431 includes a pair of primary coils 431p and secondary coils 431s that can be electromagnetically coupled to each other. Similarly, isolating device 432 includes a pair of primary coils 432p and secondary coils 432s that can be electromagnetically coupled to each other.

[0255] The switching circuit 411 switches the connection state between the isolation device 431 and the isolation device 432 according to the positive-phase input pulse signal INP and the negative-phase input pulse signal INN that are differentially input from the outside of the signal transmission device 400. As shown in the figure, the switching circuit 411 includes a comparator CMP and a switching device SW1 (for example, an analog switch).

[0256] The comparator CMP compares the positive-phase input pulse signal INP to be input to the non-inverting input terminal (+) and the negative-phase input pulse signal INN to be input to the inverting input terminal (-) with each other, and outputs an input pulse signal IN. In a state where INP > INN is established, the input pulse signal IN is at a high level. On the other hand, in a state where INP < INN is established, the input pulse signal is at a low level. The logic levels of the positive-phase input pulse signal INP and the negative-phase input pulse signal INN are inverted with respect to each other.

[0257] The first terminal of the switching device SW1 is connected to the first terminal of the primary coil 431p that forms the isolation device 431. The second terminal of the switching device SW2 is connected to the first terminal of the primary coil 432p that forms the isolation device 432. The corresponding second terminals of the primary coils 431p and 432p are connected to each other. In this way, the switching device SW1 is connected in series between the primary coil 431p of the isolation device 431 and the primary coil 432p of the isolation device 432. That is, the switching device SW1 is connected to cooperate with the corresponding primary coils 431p and 432p of the isolation devices 431 and 432 to form a closed loop.

[0258] The switching device SW1 is turned on, for example, in a state where the input pulse signal IN is at a high level. At this time, conduction is established between the primary coil 431p of the isolation device 431 and the primary coil 432p of the isolation device 432. On the other hand, the switching device SW1 is turned off, for example, in a state where the input pulse signal IN is at a low level. At this time, the conduction between the primary coil 431p of the isolation device 431 and the primary coil 432p of the isolation device 432 is cut off.

[0259] The drive circuit 421 pulse-drives a first signal Po (details will be given later) to be applied to the secondary coil 432s of the isolation device 431 cyclically or continuously.

[0260] The receiving circuit 422 detects a second signal Ri to be output from the isolation device 432, and generates an output pulse signal OUT according to the input pulse signal IN.

[0261] The buffer 423 performs waveform shaping on the output pulse signal OUT, and outputs the output pulse signal OUT to the outside of the signal transmission device 400.

[0262] Isolator 431 transmits the single-phase first signal Po from the secondary circuit system 400s to the primary circuit system 400p. Isolator 431 is used as a polling isolation device.

[0263] Isolator 432 transmits the single-phase second signal Ri from the primary circuit system 400p to the secondary circuit system 400s. Isolator 432 is used as a response isolation device.

[0264] <Operation Description (First Implementation Plan)>

[0265] When the input pulse signal IN is high, the switching device SW1 is turned on. Therefore, conduction is established between the primary coil 431p of isolation device 431 and the primary coil 432p of isolation device 432. Thus, in response to the application of a first signal Po to the secondary coil 431s of isolation device 431, a first signal Po (more precisely, an induced signal based on the first signal Po) is generated in the primary coil 431p of isolation device 431. Therefore, the primary coil 432p of isolation device 432 is driven based on the first signal Po generated in the primary coil 431p of isolation device 431. At this time, a second signal Ri (corresponding to the induced signal based on the first signal Po) is generated in the secondary coil 432s of isolation device 432.

[0266] In other words, when the input pulse signal IN is at a high level, the switching circuit 411 switches the connection between the isolation device 431 and the isolation device 432 to the first connection state. In the first connection state, the isolation device 432 is driven according to the first signal Po.

[0267] On the other hand, when the input pulse signal IN is at a low level, the switching device SW1 is turned off. Therefore, the conduction between the primary coil 431p of the isolation device 431 and the primary coil 432p of the isolation device 432 is cut off. Therefore, even if the first signal Po is applied to the secondary coil 431s of the isolation device 431 in response to the driving action, the first signal Po (more precisely, the induced signal based on the first signal Po) will not be generated in the primary coil 431p of the isolation device 431. Therefore, the primary coil 432p of the isolation device 432 is not driven, and thus the second signal Ri (corresponding to the induced signal based on the first signal Po) is not generated in the secondary coil 432s of the isolation device 432.

[0268] In other words, when the input pulse signal IN is at a low level, the switching circuit 411 switches the connection state between the isolation device 431 and the isolation device 432 to a second connection state. In the second connection state, the isolation device 432 is not driven according to the first signal Po.

[0269] The receiving circuit 422 can distinguish the logic level of the input pulse signal IN by detecting whether a second signal Ri has been generated in the secondary coil 432s of the isolation device 432. For example, the receiving circuit 422 sets the output pulse signal OUT to a high level by determining that the input pulse signal IN is at a high level in response to receiving the second signal Ri. On the other hand, the receiving circuit 422 sets the output pulse signal OUT to a low level by determining that the input pulse signal IN is at a low level in response to not receiving the second signal Ri.

[0270] In this manner, the signal transmission device 400 according to this embodiment employs a reflective isolation communication method, wherein the primary circuit system 400p responds to queries from the secondary circuit system 400s. Therefore, the primary circuit system 400p can drive the primary coil 432p of the isolation device 432 solely by performing switch control according to the input pulse signal IN. Thus, even when the power supply (not shown) of the primary circuit system 400p is unstable or insufficient, interference with signal transmission from the primary circuit system 400p to the secondary circuit system 400s can be prevented.

[0271] Note that in the signal transmission device 400 of this embodiment, both the driving circuit 421 that drives the first signal Po and the receiving circuit 422 that receives the second signal Ri operate powered from a common power supply (corresponding to the power supply of the secondary circuit system 400s). Furthermore, both the driving circuit 421 and the receiving circuit 422 are integrated into a common second chip 420. Therefore, the signal transmission device 400 of this embodiment can perform stable signal transmission without requiring margin design considering various combinations of different power supply voltages VCC1 and VCC2. Moreover, the receiving sensitivity of the second signal Ri can be adjusted according to the transmission strength of the first signal Po.

[0272] Figure 11 This is a diagram illustrating a first operational example (intermittent) of the first embodiment. The input pulse signal IN, the first signal Po, the second signal Ri, and the output pulse signal OUT are shown sequentially from the top of the diagram.

[0273] As shown in the diagram, the driving circuit 421 cyclically drives (e.g., pulse-driven) the first signal Po to be input to the secondary coil 431s of the isolation device 431. When the input pulse signal IN is high, the pulse drive of the first signal Po generates an induced pulse in the second signal Ri. Therefore, the receiving circuit 422 sets the output pulse signal OUT high in response to detecting the induced pulse in the second signal Ri. On the other hand, when the input pulse signal IN is low, even if the first signal Po is pulse-driven, no induced pulse is generated in the second signal Ri. Therefore, the receiving circuit 422 sets the output pulse signal OUT low in response to not detecting the induced pulse in the second signal Ri.

[0274] Figure 12 This is a diagram illustrating a second operational example (continuous) of the first implementation scheme. As previously stated... Figure 11 As mentioned, the input pulse signal IN, the first signal Po, the second signal Ri, and the output pulse signal OUT are displayed sequentially from the top of the chart.

[0275] As shown in the diagram, the driving circuit 421 can continuously drive (e.g., sinusoidal drive) the first signal Po to be input to the secondary coil 431s of the isolation device 431. When the input pulse signal IN is high, the sinusoidal drive of the first signal Po also induces a sine wave in the second signal Ri. Therefore, the receiving circuit 422 sets the output pulse signal OUT to high in response to detecting the sine wave in the second signal Ri. On the other hand, when the input pulse signal IN is low, even when the first signal Po is sinusoidally driven, no sine wave is induced in the second signal Ri. Therefore, the receiving circuit 422 sets the output pulse signal OUT to low in response to not detecting the sine wave in the second signal Ri.

[0276] <Signal Transmission Device (Second Implementation Scheme)>

[0277] Figure 13 This is a schematic diagram of a second embodiment of the signal transmission device. Except for a change in the configuration of the switching circuit 411, the signal transmission device 400 of this embodiment is essentially the same as the signal transmission device of the first embodiment. Figure 10 In the aspect shown in the figure, the switching circuit 411 includes an inverter INV and a switching device SW2 in place of the previously described switching device SW1.

[0278] The first terminal of switching device SW2 is connected to the first terminal of primary coil 431p. The second terminal of switching device SW2 is connected to the second terminal of primary coil 431p. In this way, switching device SW2 can be connected in parallel to primary coil 431p. Note that the corresponding first terminals of primary coils 431p and 432p are connected to each other. Similarly, the corresponding second terminals of primary coils 431p and 432p are connected to each other. That is, primary coils 431p and 432p are connected to form a closed loop.

[0279] The inverter INV generates an inverted input pulse signal INB by inverting the logic level of the input pulse signal IN. When the input pulse signal IN is high, the inverted input pulse signal INB is low. Conversely, when the input pulse signal IN is low, the inverted input pulse signal INB is high.

[0280] Switching device SW2 is turned on, for example, when the inverting input pulse signal INB is high. At this time, the terminals of the primary coil 431p are short-circuited to each other. Conversely, switching device SW2 is turned off, for example, when the inverting input pulse signal INB is low. At this time, the terminals of the primary coil 431p are all open.

[0281] <Operation Description (Second Implementation Plan)>

[0282] When the input pulse signal IN is high, the inverting input pulse signal INB is low, thus the switching device SW2 is open. Therefore, all terminals of the primary coil 431p forming the isolator 431 are open. Thus, in response to the application of the first signal Po to the secondary coil 431s of the isolator 431, the primary coil 432p of the isolator 432 is driven according to the first signal Po generated in the primary coil 431p of the isolator 431 (more precisely, the induced signal according to the first signal Po). At this time, a second signal Ri (corresponding to the induced signal according to the first signal Po) is generated in the secondary coil 432s of the isolator 432.

[0283] In other words, when the input pulse signal IN is at a high level, the switching circuit 411 switches the connection state between the isolation device 431 and the isolation device 432 to the first connection state driven by the isolation device 432 according to the first signal Po.

[0284] On the other hand, when the input pulse signal IN is low, the inverting input pulse signal INB is high, thus turning on the switching device SW2. Therefore, the terminals of the primary coil 431p forming the isolator 431 are short-circuited to each other. Therefore, even in response to the driving of the first signal Po applied to the secondary coil 431s of the isolator 431, the primary coil 432p of the isolator 432 is not driven according to the first signal Po generated in the primary coil 431p of the isolator 431 (more precisely, the induced signal according to the first signal Po). Therefore, the second signal Ri (corresponding to the induced signal according to the first signal Po) is not generated in the secondary coil 432s of the isolator 432.

[0285] In other words, when the input pulse signal IN is at a low level, the switching circuit 411 switches the connection state between the isolation device 431 and the isolation device 432 to a second connection state. In the second connection state, the isolation device 432 is not driven according to the first signal Po.

[0286] Compared with the previously described first embodiment ( Figure 10 Similarly, the receiving circuit 422 can distinguish the logic level of the input pulse signal IN by detecting whether a second signal Ri has been generated in the secondary coil 432s of the isolation device 432. For example, the receiving circuit 422 determines that the input pulse signal IN is at a high level in response to the reception of the second signal Ri, and sets the output pulse signal OUT to a high level. On the other hand, the receiving circuit 422 determines that the input pulse signal IN is at a low level in response to the absence of the second signal Ri, and sets the output pulse signal OUT to a low level.

[0287] Note that switching device SW2 does not necessarily need to be connected in parallel to the primary coil 431p of isolation device 431, as shown in the figure. For example, switching device SW2 can be connected in parallel to the primary coil 432p of isolation device 432. Alternatively, switching devices SW1 and SW2 can be provided in combination.

[0288] <Signal Transmission Device (Third Implementation Scheme)>

[0289] Figure 14 This is a schematic diagram of a third embodiment of the signal transmission device. Except for a change in the configuration of the switching circuit 411, the signal transmission device 400 of this embodiment is essentially the same as the signal transmission device of the second embodiment (previously described). Figure 13 ))same.

[0290] As shown in the figure, the previously described isolation device 432 includes a positive phase isolation device 432P and a negative phase isolation device 432N, and differentially outputs the corresponding output signals from the positive phase isolation device 432P and the negative phase isolation device 432N as second signals Rip and RiN.

[0291] Note that the positive phase isolator 432P and the negative phase isolator 432N can each be a transformer. That is, the positive phase isolator 432P includes a pair of primary coils 432Pp and secondary coils 432Ps that can be electromagnetically coupled to each other. Similarly, the negative phase isolator 432N includes a pair of primary coils 432Np and secondary coils 432Ns that can be electromagnetically coupled to each other.

[0292] In addition, the switching circuit 411 includes switching devices SW3 and SW4 in place of the previously described switching device SW2.

[0293] The first terminal of the switching device SW3 is connected to the first terminal of the primary coil 432Pp. The second terminal of the switching device SW3 is connected to the second terminal of the primary coil 432Pp. That is, the switching device SW3 is connected in parallel to the primary coil 432Pp.

[0294] The first terminal of the switching device SW4 is connected to the first terminal of the primary coil 432Np. The second terminal of the switching device SW4 is connected to the second terminal of the primary coil 432Np. That is, the switching device SW4 is connected in parallel to the primary coil 432Np.

[0295] Note that the corresponding first terminals of primary coils 431p and 432Pp are connected to each other. The corresponding second terminals of primary coils 432Pp and 432Np are both connected to the ground terminal. The second terminal of primary coil 431p and the first terminal of primary coil 432Np are connected to each other. That is, primary coils 431p, 432Pp, and 432Np are connected to form a closed loop.

[0296] Switching device SW3 is turned on, for example, when the inverting input pulse signal INB is high. At this time, the terminals of the primary coil 432Pp are short-circuited. Conversely, switching device SW3 is turned off, for example, when the inverting input pulse signal INB is low. At this time, the terminals of the primary coil 432Pp are all disconnected.

[0297] Switching device SW4 is turned on, for example, when the input pulse signal IN is high. In this case, the terminals of the primary coil 432Np are short-circuited. Conversely, switching device SW4 is turned off, for example, when the input pulse signal IN is low. In this case, all terminals of the primary coil 432Np are open.

[0298] <Operation Description (Third Implementation Plan)>

[0299] When the input pulse signal IN is high and the inverting input pulse signal INB is low, switching device SW3 is turned off and switching device SW4 is turned on. Therefore, the terminals of the primary coil 432Pp forming the positive phase isolation device 432P are all disconnected, and the terminals of the primary coil 432Np forming the negative phase isolation device 432N are short-circuited to each other.

[0300] Therefore, in response to the driving of the first signal Po to be applied to the secondary coil 431s of the isolator 431, the primary coil 432Pp of the positive isolator 432P is driven according to the first signal Po generated in the primary coil 431p of the isolator 431 (more precisely, according to the induced signal of the first signal Po). At this time, a positive second signal RiP (corresponding to the induced signal according to the first signal Po) is generated in the secondary coil 432Ps of the positive isolator 432P. On the other hand, the negative second signal RiN is not generated in the secondary coil 432Ns of the negative isolator 432N.

[0301] In other words, when the input pulse signal IN is at a high level and the inverted input pulse signal INB is at a low level, the switching circuit 411 switches the connection between the isolation device 431 and the isolation device 432 to the first connection state. In the first connection state, the positive isolation device 432P is driven according to the first signal Po.

[0302] On the other hand, when the input pulse signal IN is low and the inverting input pulse signal INB is high, switch SW3 is turned on and switch SW4 is turned off. Therefore, the terminals of the primary coil 432Pp forming the positive phase isolation device 432P are short-circuited to each other, and the terminals of the primary coil 432Np forming the negative phase isolation device 432N are all disconnected.

[0303] Therefore, in response to the driving of the first signal Po to be applied to the secondary coil 431s of the isolation device 431, the primary coil 432Np of the negative phase isolation device 432N is driven according to the first signal Po generated in the primary coil 431p of the isolation device 431 (more precisely, the induced signal according to the first signal Po). At this time, a negative phase second signal RiN (corresponding to the induced signal according to the first signal Po) is generated in the secondary coil 432Ns of the negative phase isolation device 432N. On the other hand, no positive phase second signal RiP is generated in the secondary coil 432Ps of the positive phase isolation device 432P.

[0304] In other words, when the input pulse signal IN is at a low level and the inverted input pulse signal INB is at a high level, the switching circuit 411 switches the connection state between the isolation device 431 and the isolation device 432 to the second connection state. In the second connection state, the negative phase isolation device 432N is driven according to the first signal Po.

[0305] The receiving circuit 422 can distinguish the logic level of the input pulse signal IN by detecting the difference between the positive phase second signal RiP and the negative phase second signal RiN.

[0306] For example, the receiving circuit 422 can set the output pulse signal OUT to a high level by determining that the input pulse signal IN is at a high level when the positive-phase second signal RiP is stronger than the negative-phase second signal RiN. Alternatively, for example, the receiving circuit 422 can set the output pulse signal OUT to a high level by determining that the input pulse signal IN is at a high level when the difference (RiP-RiN) obtained by subtracting the negative-phase second signal RiN from the positive-phase second signal RiP is greater than a predetermined threshold (e.g., a positive threshold + Vth).

[0307] On the other hand, for example, the receiving circuit 422 can set the output pulse signal OUT to a low level by determining that the input pulse signal IN is at a low level when the positive-phase second signal RiP is weaker than the negative-phase second signal RiN. Alternatively, for example, the receiving circuit 422 can set the output pulse signal OUT to a low level by determining that the input pulse signal IN is at a low level when the difference (RiP-RiN) obtained by subtracting the negative-phase second signal RiN from the positive-phase second signal RiP is less than a predetermined threshold (e.g., a negative threshold -Vth).

[0308] In this way, by detecting the amplitude relationship or amplitude of the difference between the second signals RiP and RiN to be differentially input, rather than the configuration of the presence or absence of the second signal Ri to be input in a single phase, the common-mode transient immunity (commonly referred to as CMTI) to transients in each of the ground voltages GND1 and GND2 is enhanced.

[0309] Figure 15 This is a diagram illustrating an example of the operation of the third embodiment. From top to bottom, the diagram sequentially shows the input pulse signal IN, the first signal Po, the positive-phase second signal RiP, the negative-phase second signal RiN, and the output pulse signal OUT. As shown in the diagram, the drive circuit 421 can cyclically drive (e.g., pulse drive) the first signal Po to be input to the secondary coil 431s of the isolation device 431.

[0310] When the input pulse signal IN is in the high - level state, when an induced pulse is generated in the positive - phase second signal RiP in response to the pulse drive of the first signal Po, no induced pulse is generated in the negative - phase second signal RiN. Therefore, the receiving circuit 422 detects that RiP > RiN (or RiP - RiN > +Vth), and sets the output pulse signal OUT to the high level.

[0311] Conversely, when the input pulse signal IN is in the low - level state, when an induced pulse is generated in the negative - phase second signal RiN in response to the pulse drive of the first signal Po, no induced pulse is generated in the positive - phase second signal RiP. Therefore, the receiving circuit 422 detects that RiP < RiN (or RiP - RiN < -Vth), and sets the output pulse signal OUT to the low level.

[0312] <Signal transmission device (Fourth embodiment)>

[0313] Figure 16 FIG. is a schematic diagram of the fourth embodiment of the signal transmission device. Except for changing the configuration of the switch circuit 411, the signal transmission device 400 of this embodiment is substantially the same as the signal transmission device of the previously described third embodiment ( Figure 14 ). As shown in the figure, the switch circuit 411 includes switch devices SW5 and SW6 instead of the previously described switch devices SW3 and SW4.

[0314] The respective first terminals of the switch devices SW5 and SW6 are connected to the first terminal of the primary coil 431p. The second terminal of the switch device SW5 is connected to the second terminal of the primary coil 432Pp. The second terminal of the switch device SW6 is connected to the first terminal of the primary coil 432Np. The second terminal of the primary coil 431p is connected to the respective second terminals of the primary coils 432Pp and 432Np. In this way, the switch device SW5 is connected to form a closed loop in cooperation with the primary coils 431p and 432Pp. Similarly, the switch device SW6 is connected to form a closed loop in cooperation with the primary coils 431p and 432Np.

[0315] The switch device SW5 is turned on, for example, when the input pulse signal IN is in the high - level state. At this time, conduction is established between the primary coil 431p of the isolation device 431 and the primary coil 432Pp of the positive - phase isolation device 432P. On the other hand, the switch device SW5 is turned off when the input pulse signal IN is in the low - level state. At this time, the conduction between the primary coil 431p of the isolation device 431 and the primary coil 432Pp of the positive - phase isolation device 432P is cut off.

[0316] Switching device SW6 is turned on, for example, when the inverting input pulse signal INB is high. At this time, conduction is established between the primary coil 431p of isolation device 431 and the primary coil 432Np of negative phase isolation device 432N. Conversely, switching device SW6 is turned off when the inverting input pulse signal INB is low. At this time, conduction between the primary coil 431p of isolation device 431 and the primary coil 432Np of negative phase isolation device 432N is interrupted.

[0317] <Operation Description (Fourth Implementation Plan)>

[0318] When the input pulse signal IN is high and the inverting input pulse signal INB is low, switching device SW5 is turned on and switching device SW6 is turned off. Therefore, conduction is established between primary coil 431p and primary coil 432Pp, and conduction is interrupted between primary coil 431p and primary coil 432Np. As a result, a positive-phase second signal RiP is generated in the secondary coil 432Ps of the positive-phase isolator 432P. On the other hand, a negative-phase second signal RiN is not generated in the secondary coil 432Ns of the negative-phase isolator 432N.

[0319] On the other hand, when the input pulse signal IN is low and the inverting input pulse signal INB is high, switching device SW5 is turned off and switching device SW6 is turned on. Therefore, the connection between primary coil 431p and primary coil 432Pp is broken, and the connection between primary coil 431p and primary coil 432Np is established. Therefore, a negative-phase second signal RiN is generated in the secondary coil 432Ns of the negative-phase isolator 432N. On the other hand, a positive-phase second signal RiP is not generated in the secondary coil 432Ps of the positive-phase isolator 432P.

[0320] The receiving circuit 422 is able to distinguish the logic level of the input pulse signal IN by detecting the difference between the positive-phase second signal RiP and the negative-phase second signal RiN, as described in the third embodiment (previously). Figure 14 ).

[0321] <Signal Transmission Device (Fifth Implementation Scheme)>

[0322] Figure 17 This is a schematic diagram of a fifth embodiment of the signal transmission device. Except for a change in the configuration of the switching circuit 411, the signal transmission device 400 of this embodiment is essentially the same as the signal transmission device of the fourth embodiment. Figure 15 As shown in the figure, in the switching circuit 411, the previously described switching device SW5 is always off.

[0323] Note that switch SW5 is provided to enhance the symmetry with switch SW6 (i.e., the similarity of device layout and wiring layout on the substrate). However, switch SW5 can be omitted. Furthermore, wiring does not necessarily need to be connected to switch SW5.

[0324] <Operation Description (Fifth Implementation Plan)>

[0325] When the inverting input pulse signal INB is low, the switching device SW6 is turned off. Therefore, the conduction between the primary coil 431p and the primary coil 432Np is broken. Thus, even in response to the first signal Po, the negative-phase second signal RiN is not generated.

[0326] On the other hand, when the inverting input pulse signal INB is high, the switching device SW6 is turned on. Therefore, conduction is established between the primary coil 431p and the primary coil 432Np. Consequently, in response to the first signal Po, a negative-phase second signal RiN is generated.

[0327] The receiving circuit 422 is able to distinguish the logic level of the input pulse signal IN by detecting the difference between the positive-phase second signal RiP and the negative-phase second signal RiN, as described in the third embodiment (previously). Figure 14 Furthermore, when the second signals RiP and RiN are differential, excellent common-mode transient immunity can be obtained.

[0328] Please note that in the signal transmission device 400 of this embodiment, a positive-phase second signal RiP is not generated even in response to the driving of the first signal Po. Therefore, the receiving circuit 422 essentially distinguishes the logic level of the input pulse signal IN by detecting the presence or absence of the negative-phase second signal RiN. This configuration is similar to the first embodiment described previously. Figure 10 Configuration of ).

[0329] <Signal Transmission Device (Sixth Implementation Scheme)>

[0330] Figure 18 This is a schematic diagram of a sixth embodiment of the signal transmission device. Except that isolation devices 433 and 434 (both capacitors) are included in place of isolation devices 431 and 432 (both transformers), the signal transmission device 400 of this embodiment is similar to the previously described first embodiment. Figure 10 They are basically the same.

[0331] Isolator 433 includes a positive-phase isolator 433P and a negative-phase isolator 433N. The positive-phase isolator 433P and the negative-phase isolator 433N transmit the differential first signals PoP and PoN from the secondary circuit system 400s to the primary circuit system 400p, respectively. Note that the first signals PoP and PoN are driven in opposite phases. Isolator 433 serves as a polling isolator.

[0332] Isolator 434 includes a positive-phase isolator 434P and a negative-phase isolator 434N. The positive-phase isolator 434P and the negative-phase isolator 434N transmit the differential second signals RiP and RiN from the primary circuit system 400p to the secondary circuit system 400s, respectively. Isolator 434 serves as a response isolation device.

[0333] All corresponding first terminals of the positive phase isolator 433P, negative phase isolator 433N, positive phase isolator 434P, and negative phase isolator 434N are disposed in the main circuit system 400p. All corresponding second terminals of the positive phase isolator 433P, negative phase isolator 433N, positive phase isolator 434P, and negative phase isolator 434N are disposed in the secondary circuit system 400s.

[0334] The corresponding first terminals of positive phase isolators 433P and 434P are connected to each other. The corresponding first terminals of negative phase isolators 433N and 434N are connected to each other. The second terminal of positive phase isolator 433P is connected to the first output terminal of drive circuit 421 (corresponding to the application terminal of the positive first signal PoP). The second terminal of negative phase isolator 433N is connected to the second output terminal of drive circuit 421 (corresponding to the application terminal of the negative first signal PoN). The second terminal of positive phase isolator 434P is connected to the first input terminal of receiver circuit 422 (corresponding to the application terminal of the positive second signal RiP). The second terminal of negative phase isolator 434N is connected to the second input terminal of receiver circuit 422 (corresponding to the application terminal of the negative second signal RiN).

[0335] Furthermore, the configuration of the switching circuit 411 is also different in the signal transmission device 400 of this embodiment. In the aspect shown in the figure, the switching circuit 411 includes an inverter INV and switching devices SW7 and SW8 instead of the previously described switching device SW1.

[0336] Switching device SW7 is connected between the respective first terminals of positive phase isolators 433P and 434P and a fixed potential terminal (e.g., ground terminal). Switching device SW8 is connected between the respective first terminals of negative phase isolators 433N and 434N and a fixed potential terminal (e.g., ground terminal).

[0337] When the inverting input pulse signal INB is high, both switching devices SW7 and SW8 are turned on. At this time, conduction is established between the corresponding first terminals of the positive-phase isolators 433P, 433N, 434P, and 434N and the fixed-potential terminals. Conversely, when the inverting input pulse signal INB is low, both switching devices SW7 and SW8 are turned off. At this time, the conduction between the corresponding first terminals of the positive-phase isolators 433P, 433N, 434P, and 434N and the fixed-potential terminals is broken.

[0338] <Operation Description (Sixth Implementation Plan)>

[0339] When the input pulse signal IN is high, the inverting input pulse signal INB is low, thus both switching devices SW7 and SW8 are disconnected. Therefore, the connection between the corresponding first terminals of the positive isolation devices 433P, 433N, 434P, and 434N and the fixed potential terminal is broken. Consequently, the first signals PoP and PoN to be output from the drive circuit 421 are transmitted to the positive isolation devices 434P and 434N via the positive isolation devices 433P and 433N. As a result, the second signals Rip and RiN (corresponding to the first signals PoP and PoN) are transmitted to the receiving circuit 422 via the positive isolation devices 434P and 434N.

[0340] In other words, when the input pulse signal IN is at a high level, the switching circuit 411 switches the connection between the isolation device 433 and the isolation device 434 to a first connection state. In the first connection state, the isolation device 434 is driven according to the first signals PoP and PoN.

[0341] On the other hand, when the input pulse signal IN is at a low level, the inverting input pulse signal INB is at a high level, so both switching devices SW7 and SW8 are turned on. Therefore, conduction is established between the corresponding first terminals of the positive isolation devices 433P, 433N, 434P, and 434N and the fixed potential terminals. Consequently, the first signals PoP and PoN output from the drive circuit 421 are attenuated and not transmitted to the positive isolation devices 434P and 434N. As a result, the second signals Rip and RiN (corresponding to the first signals PoP and PoN) via the positive isolation devices 434P and 434N are not transmitted to the receiving circuit 422.

[0342] That is, in a state where the input pulse signal IN is at a low level, the switch circuit 411 switches the connection state between the isolation device 433 and the isolation device 434 to the second connection state. In the second connection state, the isolation device 434 is not driven according to the first signals PoP and PoN.

[0343] The receiving circuit 422 can distinguish the logic level of the input pulse signal IN by detecting the difference between the positive-phase second signal RiP and the negative-phase second signal RiN, as described in the third embodiment ( Figure 14 ) and the fourth embodiment ( Figure 16 ).

[0344] Note that in the figure, a differential system with excellent common-mode transient immunity is adopted. However, the signal transmission system is not limited to this at all, and single-phase signals can be transmitted. In this case, for example, all the negative-phase isolation devices 433N and 434N and the switching device SW8 can be omitted.

[0345] Figure 19 is a diagram showing an operation example of the sixth embodiment. The input pulse signal IN, the positive-phase first signal PoP, the negative-phase first signal PoN, the positive-phase second signal RiP, the negative-phase second signal RiN, and the output pulse signal OUT are shown in order from the top of the diagram. As shown in the diagram, the drive circuit 421 can continuously drive (for example, sinusoidal drive) the first signals PoP and PoN in opposite phases to be applied to the second terminals of the positive-phase isolation device 433P and the negative-phase isolation device 433N, respectively.

[0346] In a state where the input pulse signal IN is at a high level, the first signals PoP and PoN are transmitted as the second signals Rip and RiN. Therefore, the receiving circuit 422 detects, for example, |RiP - RiN| > Vth and sets the output pulse signal OUT to a high level.

[0347] On the contrary, in a state where the input pulse signal IN is at a low level, even in response to the drive of the first signals PoP and PoN, the first signals PoP and PoN are rarely transmitted as the second signals Rip and RiN. Therefore, the receiving circuit 422 detects, for example, |RiP - RiN| < Vth and sets the output pulse signal OUT to a low level.

[0348] <Signal transmission device (seventh embodiment)>

[0349] Figure 20 is a schematic diagram of the signal transmission device of the seventh embodiment of the signal transmission device. Except for changing the configuration of the switch circuit 411, the signal transmission device 400 of this embodiment is basically the same as the signal transmission device of the sixth embodiment ( Figure 18As shown in the figure, the switching circuit 411 also includes switching devices SW9 and SW10.

[0350] Switching device SW9 is connected between the first terminal of positive phase isolator 433P and the first terminal of positive phase isolator 434P. Switching device SW10 is connected between the first terminal of negative phase isolator 433N and the first terminal of negative phase isolator 434N.

[0351] When the input pulse signal IN is high, both switching devices SW9 and SW10 are turned on. At this time, conduction is established between the first terminals of positive isolators 433P and 434P, and also between the first terminals of negative isolators 433N and 434N. Conversely, when the input pulse signal IN is low, both switching devices SW9 and SW10 are turned off. At this time, the conduction between the first terminals of positive isolators 433P and 434P, and between the first terminals of negative isolators 433N and 434N, is interrupted.

[0352] <Operation Description (Seventh Implementation Plan)>

[0353] When the input pulse signal IN is high and the inverted input pulse signal INB is low, switches SW7 and SW8 are both off, and switches SW9 and SW10 are both on. Therefore, the first signals PoP and PoN are transmitted to the positive isolation devices 434P and 434N via the positive isolation device 433P and the negative isolation device 433N. Consequently, the second signals Rip and RiN (corresponding to the first signals PoP and PoN) are sent to the receiving circuit 422 via the positive isolation device 434P and the negative isolation device 434N.

[0354] On the other hand, when the input pulse signal IN is low and the inverted input pulse signal INB is high, both switching devices SW7 and SW8 are turned on, and both switching devices SW9 and SW10 are turned off. Therefore, the first signals PoP and PoN are attenuated and not transmitted to the positive isolation device 434P and the negative isolation device 434N. Consequently, the second signals Rip and RiN (corresponding to the first signals PoP and PoN) via the positive isolation device 434P and the negative isolation device 434N are not transmitted to the receiving circuit 422.

[0355] The receiving circuit 422 can distinguish the logic level of the input pulse signal IN by detecting the difference between the positive-phase second signal RiP and the negative-phase second signal RiN, as described in the sixth embodiment (previously). Figure 18As in ( ).

[0356] <Signal Transmission Device (Eighth Implementation Scheme)>

[0357] Figure 21 This is a schematic diagram of an eighth embodiment of the signal transmission device. The signal transmission device 400 in this embodiment is basically the same as the signal transmission device in the sixth embodiment. Figure 18 Except that the isolation device 433 is changed to be of the type that transmits a single-phase first signal Po, the configuration of the switching circuit 411 is also changed. In the aspect shown in the figure, the switching circuit 411 includes switching devices SW11 to SW14 in place of the previously described switching devices SW7 and SW8.

[0358] Switching device SW11 is connected between the first terminal of positive phase isolator 434P and a fixed potential terminal (e.g., ground terminal). Similarly, switching device SW12 is connected between the first terminal of negative phase isolator 434N and a fixed potential terminal (e.g., ground terminal). Switching device SW13 is connected between the first terminal of isolator 433 and the first terminal of positive phase isolator 434P. Similarly, switching device SW14 is connected between the first terminal of isolator 433 and the first terminal of negative phase isolator 434N.

[0359] When the inverting input pulse signal INB is high, the switching device SW11 is turned on. Therefore, a connection is established between the first terminal of the non-inverting isolator 434P and the fixed potential terminal. Conversely, when the inverting input pulse signal INB is low, the switching device SW11 is turned off. Therefore, the connection between the first terminal of the non-inverting isolator 434P and the fixed potential terminal is broken.

[0360] When the input pulse signal IN is high, the switching device SW12 is turned on. Therefore, a connection is established between the first terminal of the negative phase isolation device 434N and the fixed potential terminal. Conversely, when the input pulse signal IN is low, the switching device SW12 is turned off. Therefore, the connection between the first terminal of the negative phase isolation device 434N and the fixed potential terminal is broken.

[0361] When the inverting input pulse signal INB is high, switching device SW13 is turned on. Therefore, conduction is established between the first terminal of isolator 433 and the first terminal of non-inverting isolator 434P. Conversely, when the inverting input pulse signal INB is low, switching device SW13 is turned off. Therefore, conduction between the first terminal of isolator 433 and the first terminal of non-inverting isolator 434P is interrupted.

[0362] When the input pulse signal IN is at a high level, the switching device SW14 conducts. As a result, conduction is established between the first terminal of the isolation device 433 and the first terminal of the negative-phase isolation device 434N. On the other hand, the switching device SW14 turns off when the input pulse signal IN is at a low level. Therefore, the conduction between the first terminal of the isolation device 433 and the first terminal of the negative-phase isolation device 434N is cut off.

[0363] Figure 22 It is a diagram showing an operation example of the eighth embodiment. The input pulse signal IN, the first signal Po, the positive-phase second signal RiP, the negative-phase second signal RiN, and the output pulse signal OUT are shown in order from the top of the diagram. As shown in the diagram, the drive circuit 421 can continuously drive (e.g., sinusoidal drive) the first signal Po to be applied to the second terminal of the isolation device 433.

[0364] When the input pulse signal IN is at a high level, the first signal Po is transmitted as the second signal Rip. Therefore, the receiving circuit 422 detects, for example, |RiP - RiN| > Vth and sets the output pulse signal OUT to a high level.

[0365] Conversely, when the input pulse signal IN is at a low level, the first signal Po is transmitted as the second signal RiN. Therefore, the receiving circuit 422 detects, for example, |RiP - RiN| < Vth and sets the output pulse signal OUT to a low level.

[0366] <Isolation switch 500>

[0367] Figure 23 It is a schematic circuit diagram showing an embodiment of the isolation switch 500 according to an embodiment of the present disclosure. Figure 23 The isolation switch 500 shown in is incorporated in a sequencer or the like and serves as a switch for turning on / off a circuit that supplies the power voltage Vp to the load ZL.

[0368] The isolation switch 500 includes a power supply terminal Ps, an input terminal Pin, a ground terminal Pgd, a first terminal N1, and a second terminal N2. The power supply terminal Ps is connected to a control voltage source that provides the control voltage Vin. The control voltage Vin is the voltage of the drive pulse supply circuit 503.

[0369] The control signal DIN, which is a signal for operating the load ZL, is input from an external control circuit CONT to the input terminal Pin. The control signal DIN is a signal that is at a Hi level in a state where the power voltage Vp has been supplied to the load ZL, that is, the switching unit 504 of the isolation switch 500 described below has been controlled to conduct. The ground terminal Pgd is connected to the ground potential GND.

[0370] The first terminal N1 is connected to a voltage source that supplies power voltage Vp to the load ZL. Note that the load ZL is positioned between the voltage source and the first terminal N1. The second terminal N2 is connected to ground potential GND. The disconnecting switch 500 controls the switching unit 504 to turn on / off according to the control signal DIN, and controls the first terminal N1 and the second terminal N2, causing these terminals to establish or disconnect conduction. In this way, the disconnecting switch 500 supplies power voltage Vp to the load ZL.

[0371] Figure 23 The disconnect switch 500 shown includes a conduction circuit 501, an adjustment circuit 502, a pulse supply circuit 503, and a switching unit 504.

[0372] <Switch Unit 504>

[0373] Switching unit 504 is controlled to be on or off. In disconnecting switch 500, switching unit 504 includes switching device 541 composed of an n-channel MOS field-effect transistor. In switching device 541, the drain is connected to a first terminal N1. The source is connected to a second terminal N2. The gate is connected to a conduction circuit 501, and switching device 541 is turned on by supplying a voltage from conduction circuit 501. Furthermore, the gate is connected to a regulating circuit 502, and switching device 541 is turned off by drawing current from regulating circuit 502. Additionally, the back gate of switching device 541 is connected to the source and to the second terminal N2, which is connected to ground potential GND.

[0374] In other words, the conducting circuit 501 is the circuit that turns on the switching device 541 that constitutes the switching unit 504, and the regulating circuit 502 is the circuit that turns off the switching unit 504. Note that the regulating circuit 502 can be understood as a discharge circuit that discharges the parasitic capacitance of the gate of the switching device 541.

[0375] <Pulse Supply Circuit 503>

[0376] The pulse supply circuit 503 is connected to the power supply terminal Ps, the input terminal Pin, and the ground terminal Pgd. The control voltage Vin is supplied to the pulse supply circuit 503 via the power supply terminal Ps. Note that the control voltage Vin is the value of the voltage that drives the electronically-based pulse supply circuit 503, and is lower than the power supply voltage Vp used to operate the load ZL. The pulse supply circuit 503 is connected to the ground potential GND via the ground terminal Pgd.

[0377] The control signal DIN is input to the pulse supply circuit 503 via the input terminal Pin. The control signal DIN is a signal at either Hi or Lo level, and is at Hi level during the period when the power supply voltage Vp is supplied to the load ZL. That is, when the control signal DIN is at Hi level, the switching device 541 of the switching unit 504 is turned on to supply the power supply voltage Vp to the load ZL. On the other hand, when the control signal DIN is at Lo level, the switching device 541 of the switching unit 504 is turned off to prevent the supply of power supply voltage Vp to the load ZL.

[0378] The pulse supply circuit 503 is connected to the first primary coil 511 of the conduction circuit 501 described below and the second primary coil 521 of the adjustment circuit 502 described below. The pulse supply circuit 503 supplies a first pulse signal Sp1 to the first primary coil 511 and a second pulse signal Sp2 to the second primary coil 521.

[0379] The pulse supply circuit 503 includes a pulse generation circuit 531 and an oscillator circuit 532. The oscillator circuit 532 provides a clock signal to the pulse generation circuit 531, which indicates the timing of generating pulse signals (a first pulse signal Sp1 or a second pulse signal Sp2). The clock signal to be output from the oscillator circuit 532 is, for example, a square wave with a predetermined frequency and a predetermined duty cycle. The oscillator circuit 532 is configured to modulate the frequency of the clock signal and to output and stop the clock signal.

[0380] The pulse generation circuit 531 generates and outputs a pulse signal based on the clock signal output by the oscillator circuit 532. The pulse generation circuit 531 can be configured to generate a pulse signal, for example, when the clock signal rises. Alternatively, the pulse generation circuit 531 can be configured to generate pulse signals at two timed intervals, for example, when the clock signal rises and falls.

[0381] Oscillator circuit 532 outputs a clock signal during the period when the control signal DIN is at the Hi level and during a specific period after the control signal DIN has switched from the Hi level to the Lo level. It should be noted that the period when the control signal DIN is at the Hi level and the specific period after the control signal DIN has switched from the Hi level to the Lo level can be distinguished from each other under the control of pulse generation circuit 531 or oscillator circuit 532. For example, when oscillator circuit 532 controls the distinction, it can generate a clock signal such that the interval of the clock signal during the period when the control signal DIN is at the Hi level is different from the interval of the clock signal during the specific period after the control signal DIN has switched from the Hi level to the Lo level.

[0382] <Conduction Circuit 501>

[0383] The conducting circuit 501 includes a first isolation device 510, a diode 513, a resistor 514, and a capacitor 515. The first isolation device 510 includes a first primary coil 511 and a first secondary coil 512. In the conducting circuit 501, the first primary coil 511 and the first secondary coil 512 are electrically isolated from each other and electromagnetically coupled to each other. Signals, etc., can be transmitted from the first primary coil 511 to the first secondary coil 512 via electromagnetic induction. Using this first isolation device 510 helps to cut off the current flow from the circuit on the first secondary coil 512 side to the first primary coil 511.

[0384] The first primary coil 511 is connected to the pulse supply circuit 503 and receives a first pulse signal Sp1 supplied from the pulse supply circuit 503. The first pulse signal Sp1 is provided when the control signal DIN is at the Hi level. The winding directions of the first primary coil 511 and the first primary coil 512 are configured such that, in response to the rise of the first pulse signal Sp1, an induced current Id1 is generated from the second terminal P12 to the first terminal P11 of the first primary coil 512 when the first pulse signal Sp1 has been supplied to the first primary coil 511.

[0385] Furthermore, the first terminal P11 of the first primary coil 512 is connected to the gate of the switching device 541 via a diode 513 and a resistor 514. The anode of the diode 513 is connected to the first terminal P11 of the first primary coil 512. The cathode of the diode 513 is connected to the gate of the switching device 541 via a resistor 514. That is, the diode 513 is configured such that its forward direction is the direction of flow of the induced current Id1 generated in the first primary coil 512 in response to the rise of the first pulse signal Sp1 provided to the first primary coil 511. The arrangement of the diode 513 in the conduction circuit 501 helps to prevent the induced current generated in response to the fall of the first pulse signal Sp1 from flowing through the conduction circuit 501. Note that a bipolar transistor with its base and collector connected to each other can be used instead of the diode 513.

[0386] Resistor 514 is disposed between diode 513 and switching device 541. Furthermore, the first terminal of capacitor 515 is connected to the gate of resistor 514 and switching device 541, and the second terminal of capacitor 515 is connected to the source of switching device 541, i.e., ground potential GND. Resistor 514 and capacitor 515 constitute a smoothing circuit, which smooths the induced current Id1 according to the first pulse signal Sp1, thereby generating voltage Vgs. Capacitor 515 is charged by the induced current Id1. Through the charging of capacitor 515, voltage Vgs increases and eventually maintains a certain voltage.

[0387] <Adjustment Circuit 502>

[0388] The regulating circuit 502 includes a second isolation device 520, a diode 523, a first regulating switch device 524, a resistor 525, and a capacitor 5251. The second isolation device 520 includes a second primary coil 521 and a second secondary coil 522. The second primary coil 521 is connected to the pulse supply circuit 503 and receives a second pulse signal Sp2 supplied from the pulse supply circuit 503. The second pulse signal Sp2 is a pulse signal supplied during a specific time period after the control signal DIN switches from Hi level to Lo level. The winding directions of the second primary coil 521 and the second secondary coil 522 are configured such that, in response to the rise of the second pulse signal Sp2 supplied to the second primary coil 521, an induced current Id2 is generated from the second terminal P22 to the first terminal P21 of the second secondary coil 522.

[0389] Furthermore, the first terminal P21 of the second primary coil 522 is connected to the gate of the first regulating switch device 524 via a diode 523. The anode of the diode 523 is connected to the first terminal P21 of the second primary coil 522. The cathode of the diode 523 is connected to the gate of the first regulating switch device 524. That is, the diode 523 is configured such that its forward direction is the direction of flow of the induced current Id2 generated in the second primary coil 522 in response to the rise of the second pulse signal Sp2 provided to the second primary coil 521. Note that a bipolar transistor with its base and collector connected to each other can be used instead of the diode 523. The arrangement of the diode 523 in the regulating circuit 502 helps to prevent the induced current generated in response to the fall of the second pulse signal Sp2 from flowing through the regulating circuit 502.

[0390] The first regulating switch device 524 is an n-channel MOS transistor. The drain of the first regulating switch device 524 is connected to the gate of the switch device 541 of the switching unit 504. The source of the first regulating switch device 524 is connected to the second terminal N2, and the source of the switch device 541 is also connected to the second terminal N2, thereby connecting to the ground potential GND. The cathode of the diode 523 is connected to the gate of the first regulating switch device 524. Furthermore, the gate and source of the first regulating switch device 524 are connected to each other via a resistor 525. The resistor 525 is positioned to allow the flow of the induced current Id2. The potential difference generated in response to the flow of the induced current Id2 is the gate-source voltage of the first regulating switch device 524, and the first regulating switch device 524 is controlled to turn on.

[0391] Furthermore, capacitor 5251 is parallel to resistor 525, and its first and second terminals are connected to the gate and source of the first regulating switch 524, respectively. Capacitor 5251 is also charged by the induced current Id2. That is, the induced current Id2 is smoothed by capacitor 5251. The voltage smoothed by capacitor 5251 is applied between the gate and source of the first regulating switch 524, and the first regulating switch 524 remains on. Furthermore, the gate and source of the first regulating switch 524 are connected to each other via resistor 525 to slow the current flow from the gate to the source. Therefore, in response to the gate-source voltage dropping to a threshold or less, the first regulating switch 524 is turned off.

[0392] The disconnect switch 500 has the above-described configuration. The disconnect switch 500 includes a primary circuit to which a first primary coil 511 and a second primary coil 521 are connected, and a secondary circuit to which a first primary coil 512 and a second secondary coil 522 are connected. That is, in the disconnect switch 500, the primary circuit and the secondary circuit are isolated from each other by a first isolation device 510 and a second isolation device 520. Therefore, current flowing through the secondary circuit and operating the load ZL can be prevented from flowing through the primary circuit.

[0393] The operation of the disconnector switch 500 will now be described with reference to the accompanying drawings. Figure 24 This is a timing diagram showing the operation of the disconnector switch 500.

[0394] like Figure 24 As shown, in order to supply the power supply voltage Vp to the load ZL, the control signal DIN input to the pulse supply circuit 503 is switched from Lo level to Hi level. In response to the control signal DIN switching from Lo level to Hi level, the pulse supply circuit 503 supplies the first pulse signal Sp1 to the first primary coil 511.

[0395] With the first pulse signal Sp1 already supplied to the first primary coil 511, an induced current Id1 is generated in the first primary coil 512 in response to the rise of the first pulse signal Sp1. Since the induced current Id1 is a current flowing in the forward direction along the diode 513, the induced current Id1 flows through the diode 513 and charges the capacitor 515. It is worth noting that even in response to the fall of the first pulse signal Sp1, the configuration of the diode 513 prevents current from flowing through the conduction circuit 501.

[0396] A first pulse signal Sp1 is supplied from the pulse supply circuit 503 to the first primary coil 511. Then, capacitor 515 is charged by the induced current Id1 generated in the first primary coil 512 in response to the rise of the first pulse signal Sp1. The voltage Vgs between the two terminals of capacitor 515 increases to a predetermined voltage value Vo. As described above, the voltage between the two terminals of capacitor 515 is the gate-source voltage Vgs of switching device 541. In response to voltage Vgs exceeding a threshold value Vth, switching device 541 is turned on.

[0397] In response to the switching device 541 being turned on, conduction is established between the drain and source of the switching device 541, and the first terminal N1 and the second terminal N2 are turned on. Thus, the power supply voltage Vp is supplied to the load ZL, and the load ZL operates.

[0398] When the control signal DIN at the Hi level is received, the pulse supply circuit 503 continues to output the first pulse signal Sp1. At this time, the voltage Vgs is smoothed by the gate capacitance of the switching device 541 and the capacitor 515. That is, the capacitor 515 is used to maintain the voltage Vgs at the voltage value Vo. Note that, preferably, the period of the first pulse signal Sp1 is the period of charging the capacitor 515 without interruption. In this way, the voltage Vgs is maintained by the capacitor 515 at a voltage value Vo equal to or greater than the threshold Vth. Therefore, the switching device 541 is stably maintained in the on state. That is, the power supply voltage Vp is stably supplied to the load ZL. Note that when the gate capacitance of the switching device 541 is sufficiently high, the capacitor 515 can be omitted.

[0399] To terminate the operation of load ZL, the control signal DIN from the control circuit CONT switches from the Hi level to the Lo level. In response to detecting the switch from Hi to Lo, the pulse supply circuit 503 stops supplying the first pulse signal Sp1. Since capacitor 515 has been charged, the switching device 541 remains on even though the supply of the first pulse signal Sp1 has stopped and the induced current Id1 has stopped. That is, despite the command to stop load ZL, the power supply voltage Vp continues to be supplied to load ZL.

[0400] As a countermeasure, in the isolating switch 500, in response to detecting a switch signal DIN switching from Hi level to Lo level, the supply of the first pulse signal Sp1 is stopped, and the second pulse signal Sp2 is supplied to the second primary coil 521. With the second pulse signal Sp2 supplied to the second primary coil 521, an induced current Id2 is generated in the second primary coil 522 in response to the rise of the second pulse signal Sp2. This induced current Id2 is a current flowing along the forward direction of the diode 523, and it flows through the resistor 525. In response to the current flowing through the resistor 525, the gate-source voltage of the first regulating switch device 524 increases, and the first regulating switch device 524 is turned on.

[0401] It should be noted that although the induced current Id2 is a current that flows only in a short period of time, the first regulating switch 524 remains on because the gate-source voltage of the first regulating switch 524 is smoothed by the capacitor 5251, thus supplying the second pulse signal Sp2 simultaneously. Note that when the gate capacitance of the first regulating switch 524 is high, the first regulating switch 524 can remain on even without the capacitor 5251.

[0402] The drain of the first regulating switch 524 is connected to the gate of the switch 541, and its source is connected to ground potential GND. Therefore, in response to the conduction of the first regulating switch 524, the charge at the gate of the switch 541 is extracted. At this time, the charge in the capacitor 515 is also extracted. Therefore, the gate-source voltage Vgs of the switch 541 decreases.

[0403] The induced current Id2 increases the gate-source voltage of the first regulating switch 524 to turn it on. Therefore, the gate charge of switch 541 and the charge in capacitor 515 are drawn out, causing the voltage Vgs to drop. This turns switch 541 off.

[0404] In other words, by supplying the second pulse signal Sp2 multiple times from the pulse supply circuit 503, the regulating circuit 502 turns off the switching device 541 and puts the switching unit 504 into a non-conducting state. In this way, by providing the regulating circuit 502, the switching unit 504 switches to a non-conducting state after the control signal DIN has switched from the Hi level to the Lo level.

[0405] As described above, the use of the disconnecting switch 500 helps to protect the primary circuit by cutting off the current flowing through the secondary circuit into the primary circuit, and also helps to switch the switching unit 504 to the on and off states according to the control signal DIN.

[0406] The disconnect switch 500, configured to use an isolation device utilizing magnetic coupling, experiences less signal degradation due to fouling, aging, etc., compared to the case of using an isolation device utilizing optical signals (such as an optocoupler). Therefore, the disconnect switch 500 with the configuration disclosed herein can stably open and close over extended periods. Furthermore, the disconnect switch 500 can operate stably even in areas exposed to external light.

[0407] <First Variation>

[0408] Figure 25 This is a timing diagram illustrating the operation of the disconnector 500 in the first variant example. The disconnector 500 in the first variant example has... Figure 23 The disconnector switch 500 shown has the same configuration. Therefore, elements indicated by the same reference numerals as those for the disconnector switch 500 will not be described.

[0409] When the control signal DIN is at the Lo level, the gate-source voltage Vgs of the switching device 541 in the switching unit 504 is 0V, and it takes time to reach the threshold Vth for the switching device 541 to turn on. Preferably, in the disconnecting switch 500, the switching unit 504 enters the on state as quickly as possible after the control signal DIN has switched from the Lo level to the Hi level.

[0410] Therefore, in the isolating switch 500 of the first variant, the pulse supply circuit 503 outputs a first pulse signal Sp1 at a first frequency for a specific period after the control signal DIN switches from the Lo level to the Hi level. Then, after the specific period has elapsed, the pulse supply circuit 503 outputs the first pulse signal Sp1 at a second frequency lower than the first frequency. In this way, the pulse supply circuit 503 supplies the first pulse signal Sp1 at a higher frequency for a specific period after the control signal DIN switches from the Lo level to the Hi level. This helps to rapidly increase the gate-source voltage Vgs.

[0411] Therefore, after the control signal DIN switches from the Lo level to the Hi level, the switching unit 504 can immediately switch to the ON state. Furthermore, after the switching unit 504 switches to the ON state, the frequency of the first pulse signal Sp1 decreases. In the pulse supply circuit 503, power consumption increases when the frequency of the pulse signal to be output (in the figure, the first pulse signal Sp1) is high. As disclosed herein, by configuring the first pulse signal Sp1 to be output at a higher frequency only for a finite period since the voltage Vgs rises, power consumption can be suppressed more than if the first pulse signal Sp1 continues to be output at a high frequency. That is, according to this variant, the isolating switch 500 can provide an isolating switch with suppressed power consumption and satisfactory response characteristics.

[0412] It is worth noting that the frequency of the second pulse signal Sp2 can be adjusted so that the period from the time when the control signal DIN switches from the Hi level to the Lo level until the switching unit 504 enters the non-conducting state is close to the period from the time when the control signal DIN switches from the Lo level to the Hi level until the switching unit 504 enters the conducting state.

[0413] <Second Variation>

[0414] Figure 26 This is a schematic circuit diagram of the disconnector switch 500a in the second variant example. Figure 27 This is a timing diagram showing the operation of the disconnector switch 500a in the second variant example. Figure 26 The disconnector switch 500a shown in the second variant example has a similar function to... Figure 23 The configuration of the disconnector 500 shown is similar, except that its regulating circuit 502a differs from the regulating circuit 502 of the disconnector 500. Therefore, in Figure 26 Among the components of the disconnector switch 500a shown, with Figure 23 The components of the disconnecting switch 500 shown are substantially the same as those indicated by the same reference numerals, and the same components will not be described.

[0415] like Figure 26 As shown, the regulating circuit 502a of the disconnecting switch 500a includes a capacitor 526, which is configured to connect the anode of the diode 523 of the regulating circuit 502a and the cathode of the diode 513 of the conduction circuit 501 to each other.

[0416] Furthermore, in the disconnector switch 500a, the pulse supply circuit 503 is configured to supply a second pulse signal Sp21 and a second pulse signal Sp22 to the second isolation device 520. The second pulse signal Sp21 is a pulse signal that generates an induced current Id21 from the second terminal P22 toward the first terminal P21 of the second stage coil 522. On the other hand, the second pulse signal Sp22 generates an induced current Id22 from the first terminal P21 toward the second terminal P22 in the second stage coil 522.

[0417] In the disconnect switch 500a, the pulse supply circuit 503 supplies a second pulse signal Sp22 to the second primary coil 521. At this time, a magnetic force is applied to the second primary coil 522 to generate an induced current Id22 from the first terminal P21 to the second terminal P22. The induced current Id22 flows in the opposite direction to the diode 523, therefore no current flows through the regulating circuit 502a. Consequently, the potential on the anode side of the diode 523 decreases. Therefore, the potential on the cathode side of the diode 513 in the conducting circuit 501 decreases via the capacitor 526. This facilitates the provision of a forward voltage to the diode 513, and the current flows in the forward direction of the diode 513. The regulating circuit 502a is configured to assist the current flow in the forward direction of the diode 513 in the conducting circuit 501 by providing the second pulse signal Sp22 to the regulating circuit 502a.

[0418] Furthermore, when the second pulse signal Sp22 is supplied to the second isolation device 520, the first pulse signal Sp1 is supplied to the first isolation device 510. That is, the induced current Id1 according to the first pulse signal Sp1 flows through the conduction circuit 501. The induced current Id1 is a current flowing in the forward direction of the diode 513, and the operation of the regulating circuit 502a assists the induced current Id1 to flow in the forward direction of the diode 513.

[0419] Next, the operation of the disconnector switch 500a will be described. For example... Figure 27 As shown, in response to the control signal DIN switching from Lo level to Hi level, the pulse supply circuit 503 supplies a first pulse signal Sp1 to the first primary coil 511. Furthermore, simultaneously supplying the first pulse signal Sp1, the pulse supply circuit 503 supplies a second pulse signal Sp22 to the second primary coil 521.

[0420] Therefore, in the first-stage coil 512 of the conduction circuit 501, an induced current Id1 is generated in the direction in which the induced current Id1 is supplied to the gate of the switching device 541 of the switching unit 504. Furthermore, the second-stage coil 522 of the regulating circuit 502a operates to generate an induced current Id22. Consequently, the potential on the anode side of the diode 523 decreases. As a result, the voltage in the forward direction of the diode 513 in the conduction circuit 501 increases, shortening the time until current begins to flow through the diode 513. Then, the rate of rise of the gate-source voltage Vgs increases, and the period until the switching device 541 turns on due to the control signal DIN switching from Lo level to Hi level can be shortened.

[0421] Note that in the conduction circuit 501, as the induced current Id1 continues to flow through diode 513 for a longer period, the forward voltage of diode 513 becomes higher. Diode 513 has the characteristic of allowing current to flow easily in its forward direction when the forward voltage is at a certain level or higher. Therefore, in the disconnect switch 500a, the regulating circuit 502a assists in turning on the conduction circuit 501 at least until the current in the forward direction of diode 513 begins to flow easily. In this way, because the regulating circuit 502a assists in the operation of the conduction circuit 501, the time it takes for the switching unit 504 to enter the conduction state due to the control signal DIN switching from Lo level to Hi level can be shortened. That is, the response characteristics of the disconnect switch 500a can be enhanced. Note that the period for which the second pulse signal Sp22 is supplied by the pulse supply circuit 503 is very short, thus suppressing the increase in power consumption of the disconnect switch 500a.

[0422] <Third Variation>

[0423] Figure 28 This is a schematic circuit diagram of the disconnector switch 500b of the third variant example. Figure 28 The switching unit 504b of the disconnecting switch 500b shown differs from the switching unit 504 of the disconnecting switch 500. Furthermore, the first regulating switching device 524 is replaced by the first regulating switching device 524b. Additionally, although the shape remains unchanged, the first disconnecting device 510 is configured such that the induced current Id1 generated in the first stage coil 512 of the first disconnecting device 510 flows in the opposite direction, and the placement of the diode 513 and resistor 514 also changes according to the direction of the induced current Id1. Similarly, although the shape remains unchanged, the second disconnecting device 520 is configured such that the induced current Id2 generated in the second stage coil 522 of the second disconnecting device 520 flows in the opposite direction, and the placement of the diode 523 also changes according to the direction of the induced current Id2. Other features of the disconnecting switch 500b are the same as those of the disconnecting switch 500. Therefore, a detailed description of the configuration of the disconnecting switch 500b, which is substantially the same as that of the disconnecting switch 500, will not be given; the same configuration is indicated by the same reference numerals.

[0424] like Figure 28 As shown, the isolating switch 500b includes a switching device 541b composed of a p-channel MOS transistor. The source of the switching device 541b is connected to the first terminal N1, and the drain of the switching device 541b is connected to the second terminal N2. Furthermore, the conduction circuit 501 is configured such that the induced current Id1 generated in the first stage coil 512 of the first isolating device 510 causes the current to be drawn out through the gate of the switching device 541b.

[0425] The induced current Id1 is drawn out through the gate, and capacitor 515 is charged. Therefore, the gate-to-source voltage Vsg is pulled down. Then, in response to the absolute value of voltage Vsg exceeding the threshold Vth, switching device 541b is turned on. Thus, the first terminal N1 and the second terminal N2 enter the on state, and the power supply voltage Vp is supplied to the load ZL, which then enters the operating state. Note that the threshold Vth is the voltage at which the p-channel MOS transistor turns on, and may differ from the voltage at which the n-channel MOS transistor turns on.

[0426] In addition, such as Figure 28 As shown, the isolating switch 500b includes a first regulating switch device 524b composed of a p-channel MOS transistor. The source of the first regulating switch device 524b is connected to the first terminal N1, and the drain of the first regulating switch device 524b is connected to the gate of the switching device 541b. Then, the induced current Id2 generated in the second stage coil 522 of the second isolating device 520 turns on the first regulating switch device 524b. In response to the turn-on of the first regulating switch device 524b, current flows into the gate of the switching device 541b of the switching unit 504b. Then, each time the first regulating switch device 524b is turned on, a certain amount of current flows to pull up the gate voltage Vsg relative to the source. In this way, the switching device 541b is turned off. Note that the second terminal P22 of the second stage coil 522 is not connected to the second terminal N2, but is connected to the first terminal N1.

[0427] As described above, even when the disconnecting switch 500b has a configuration in which the switching unit 504b uses a switching device 541b including a p-channel MOS transistor, the disconnecting switch 500b can operate as if it were using a switching device 541b including an n-channel MOS transistor.

[0428] <Fourth Variation>

[0429] Figure 29 This is a schematic circuit diagram of the disconnector switch 500c of the fourth variant. In the disconnector switch 500c of the fourth variant, the configuration of the switching unit 504c differs from the configuration of the switching unit 504 of the disconnector switch 500. Other parts of the disconnector switch 500c are the same as those of the disconnector switch 500. Therefore, detailed descriptions of the parts of the disconnector switch 500c that are substantially the same as those of the disconnector switch 500 will not be given; the same parts are indicated by the same reference numerals.

[0430] like Figure 29 As shown, the switching unit 504c of the disconnecting switch 500c has a configuration in which a first switching device 5411 and a second switching device 5412 are connected in series. Furthermore, both the first switching device 5411 and the second switching device 5412 are n-channel MOS transistors.

[0431] The drain of the first switching device 5411 is connected to the first terminal N1. The source of the first switching device 5411 and the source of the second switching device 5412 are connected to each other. The drain of the second switching device 5412 is connected to the second terminal N2. Furthermore, the gate of the first switching device 5411 and the gate of the second switching device 5412 are connected to each other.

[0432] Furthermore, in the conduction circuit 501, the first terminal P11 of the first primary coil 512 of the first isolation device 510 is connected to the connection node, and the gates of the first switching device 5411 and the second switching device 5412 are connected to the connection node. Additionally, the second terminal P12 is connected to the connection node, and the sources of both switching devices 541 and 542 are connected to the connection node.

[0433] This configuration facilitates the flow of the induced current Id1 generated in the first primary coil 511 into the gate of the first switching device 5411 and the gate of the second switching device 5412. Consequently, the gate-source voltage Vgs of the first switching device 5411 and the second switching device 5412 increases. As a result, the first switching device 5411 and the second switching device 5412 are turned on, causing the first terminal N1 and the second terminal N2 to enter the on state.

[0434] In the regulating circuit 502, the induced current Id2 causes the first regulating switch 524 to turn on. In response to the turning on of the first regulating switch 524, current is drawn out through the gates of the first switch 5411 and the second switch 5412. In this way, the first switch 5411 and the second switch 5412 are controlled to turn off.

[0435] In the configuration of switching unit 504c, the first terminal P11 of the first stage coil 512 is connected to the gates of both the first switching device 5411 and the second switching device 5412. Furthermore, the second terminal P12 of the first stage coil 512 is connected to the source of both the first switching device 5411 and the second switching device 5412. Therefore, in the disconnector switch 500c, the power supply voltage Vp can be supplied to the load ZL regardless of which of the voltages at the first terminal N1 and the second terminal N2 is higher. This configuration helps to enhance the versatility of the disconnector switch 500c.

[0436] Note that in this variant, the n-channel MOS transistor does not necessarily need to be used as one of the two switching devices in switching unit 504c, and the p-channel MOS transistor can be used as both. In this case, diodes 513 and 523 are mounted in opposite directions.

[0437] <Fifth Variation>

[0438] Figure 30This is a schematic circuit diagram of the disconnecting switch 500d of the fifth variant. In the disconnecting switch 500d of the fifth variant, the regulating circuit 502d differs from the regulating circuit 502 in that it includes a resistor 527, a first regulating switch device 524, and a second regulating switch device 528. Other features of this configuration are similar to... Figure 29 The fourth variant shown has the same configuration features as the disconnector 500c. Therefore, detailed descriptions of the parts of the disconnector 500d that are substantially the same as those of the disconnector 500c will not be given, as these identical parts are indicated by the same reference numerals. Furthermore, Figure 30 The first regulating switch device 524 of the disconnecting switch 500d shown has a relationship with Figure 29 The first regulating switch device 524 of the disconnector switch 500c shown has the same configuration. Therefore, a detailed description of the configuration of the first regulating switch device 524 will not be given. The first regulating switch device 524 is connected in parallel with the first primary coil 512.

[0439] like Figure 30 As shown, resistor 527 is positioned between diode 523 and the first regulating switch 524. Resistor 527 and capacitor 5251 form a smoothing circuit that smooths the induced current Id21 to be generated according to the second pulse signal Sp2, thereby generating a voltage that causes the first regulating switch 524 to turn on. The induced current Id21 causes the first regulating switch 524 to conduct.

[0440] The second regulating switch 528 is connected in series with resistor 525. Furthermore, the second regulating switch 528 is connected in parallel with the second stage coil 522. The second regulating switch 528 is an n-channel MOS transistor, and its source is connected to the second terminal P22 of the second stage coil 522. Note that the second terminal P22 of the second stage coil 522 is used as the negative electrode side when the induced current Id21 flows. Furthermore, the drain of the second regulating switch 528 is connected via resistor 525 between resistor 527 and the gate of the first regulating switch 524. Additionally, the gate of the second regulating switch 528 is connected between the first terminal P11 of the first stage coil 512 and the anode of diode 513.

[0441] This configuration allows the second regulating switch 528 to be turned on by the induced current Id1 induced by the first primary coil 512 when the first pulse signal Sp1 has been supplied to the first primary coil 511.

[0442] The fifth variant example of the disconnector switch 500d has the above configuration. Figure 31 This is a flowchart illustrating the operation of the disconnector switch 500d in the fifth variant example. (For example...) Figure 31As shown, in the disconnector switch 500d, in response to the control signal DIN switching from Lo level to Hi level, a first pulse signal Sp1 is provided to the first primary coil 511. Therefore, an induced current Id1 is generated in the first primary coil 512 to increase the voltage Vgs.

[0443] like Figure 31 As shown, the second regulating switch 528 is turned on by the induced current Id1 induced by the first primary coil 512. In response to the turning on of the second regulating switch 528, current is drawn out through the gate of the first regulating switch 524. In this way, the first regulating switch 524 is turned off. Figure 31 As shown, when the control signal DIN is at the Lo level, even when the gate voltage of the first regulating switch 524 has decreased slowly, current is drawn in response to the turn-on of the second regulating switch 528, and thus the gate voltage drops to the off state.

[0444] In other words, in the disconnector switch 500d, when the first pulse signal Sp1 has been supplied to the first primary coil 511, the second regulating switch device 528 is turned on by the induced current Id1 induced by the first primary coil 512. In response to the turn-on of the second regulating switch device 528, current is drawn out through the gate of the first regulating switch device 524, and the first regulating switch device 524 is turned off. Therefore, the voltage Vgs rises when the first regulating switch device 524 is turned off, and thus the rate of increase of the voltage Vgs increases.

[0445] As a result, the time until the first switching device 5411 and the second switching device 5412 are turned on can be shortened, and the isolating switch 500d is switched to the on state shortly after the control signal DIN has switched from Lo level to Hi level. In this way, the power supply voltage Vp is applied to the load ZL.

[0446] Note that the operation when the second pulse signal Sp2 is provided to the second primary coil 521 is the same as that in, for example, the disconnect switch 500.

[0447] <Sixth Variation>

[0448] Figure 32 This is a schematic circuit diagram of the disconnector switch 500e in the sixth variant example. In the disconnector switch 500e of the sixth variant example, the conducting circuit 501e and the regulating circuit 502e are different. Figure 23 The disconnecting switch 500 shown includes an on-circuit 501 and an adjustment circuit 502. Furthermore, the switching unit 504c has a connection with... Figure 29The disconnecting switch 500c shown has the same configuration as the switching unit 504c. The other parts of the disconnecting switch 500e have the same configuration as the disconnecting switch 500. Therefore, detailed descriptions of the parts of the disconnecting switch 500e that are substantially the same as those of the disconnecting switch 500 will not be given; the same parts are indicated by the same reference numerals.

[0449] like Figure 32 As shown, the conducting circuit 501e of the disconnecting switch 500e includes a first disconnecting device 5101 and a first disconnecting device 5102. The first disconnecting device 5101 includes a first primary coil 5111 and a first primary coil 5112. Similarly, the first disconnecting device 5102 includes a first primary coil 5121 and a first primary coil 5122. The first primary coils 5111 and 5121 are connected to the pulse supply circuit 503 and have... Figure 23 The first primary coil 511 of the disconnecting switch 500 shown has the same configuration.

[0450] In the conducting circuit 501e, the first primary coil 5112 and the first primary coil 5122 are connected in series. A first pulse signal Sp1 is provided to the first primary coil 5111 and the first primary coil 5121. The induced current Id1 generated in the first primary coil 5112 and the first primary coil 5122 is in the same direction. That is, the induced current Id1 generated in each of the first primary coils 5112 and 5122 flows to the gate of the first switching device 5411 and the second switching device 5412.

[0451] Diode 5131, resistor 5141, and capacitor 5151 are connected to the primary winding 5112. The primary winding 5112, diode 5131, resistor 5141, and capacitor 5151 have a connection with... Figure 26 The diode 513, resistor 514, and capacitor 515 of the disconnecting switch 500a shown are configured similarly. Therefore, a detailed description of those components will not be given. Similarly, diode 5132, resistor 5142, and capacitor 5152 are connected to the primary winding 5122. The primary winding 5122, diode 5132, resistor 5142, and capacitor 5152 have the same... Figure 26 The diode 513, resistor 514 and capacitor 515 of the disconnecting switch 500a shown are configured similarly.

[0452] Capacitor 5151 is a smoothing capacitor connected between the cathode of diode 5131 and the second terminal P22 of the secondary winding 522, and smooths the current to be output from diode 5131. Similarly, capacitor 5152 is a smoothing capacitor connected between the cathode of diode 5132 and the second terminal P22 of the secondary winding 522, and smooths the current to be output from diode 5132.

[0453] When the induced current Id1 flows, capacitor 5151 maintains a terminal-to-terminal voltage across the primary coil 5112. Similarly, when the induced current Id1 flows, capacitor 5152 maintains a terminal-to-terminal voltage across the primary coil 5122. Since the primary coils 5112 and 5122 are connected in series, the induced current Id1 generated in the two coils flows into the switching devices 5411 and 5412 of the switching unit 504c. Therefore, the period until the switching devices 5411 and 5412 are turned on is shorter than in the case of a single coil.

[0454] On the other hand, the regulating circuit 502e includes capacitors 5261 and 5262 connected to the first terminal P21 of the secondary coil 522. Similar to... Figure 26 The capacitors 526, 5261, and 5262 in the disconnecting switch 500a shown contribute to increasing the forward voltage of diodes 5131 and 5132. This also shortens the period before the switching devices 5411 and 5412 in the switching unit 504c turn on.

[0455] In this way, the conducting circuit 501e includes two first isolation devices 5101 and 5102, and their respective primary coils 5112 and 5122 are connected in series. Therefore, the response characteristics of the disconnecting switch 500e can be enhanced. Note that the two first isolation devices 5101 and 5102 need not be used as in the configuration example described in this variant, and three or more first isolation devices can be used.

[0456] like Figure 32 As shown, the second terminal of the first stage coil 5112 and the second terminal of the second stage coil 522 are both connected to a wiring connection that connects to the connection node between the sources of the first switching device 5411 and the second switching device 5412. In this case, as... Figure 33 As shown, the wiring connecting the second terminal of the first stage coil 5112 to the connection node between the source of the first switching device 5411 and the second switching device 5412, as well as the wiring connecting the second terminal of the second stage coil 522e to the connection node, can be integrated with each other. This helps to simplify the wiring. Note that... Figure 33 This is a schematic circuit diagram illustrating another configuration example of the disconnector switch 500e of this variant.

[0457] like Figure 33 As shown, when the wiring is integrated, the winding direction of the second primary coil 522e is opposite to that of the first primary coil 5112. Furthermore, when the adjustment circuit 502e assists in turning on the conduction circuit 501e, the pulse supply circuit 503 supplies a second pulse signal Sp21 to the second primary coil 521, causing the direction of the induced current Id22 to be the same as the direction of the induced current Id1. Moreover, when the second pulse signal Sp22 is provided to the second primary coil 521 causing the induced current Id21 to flow, the wiring connected to the first primary coils 5111 and 5121 is controlled to have high impedance.

[0458] In this variant, although the first primary coils 5111 and 5121 are arranged independently of each other, they can be integrated with each other.

[0459] <Seventh Variation>

[0460] Figure 34 This is a schematic circuit diagram of the disconnector switch 500f in the seventh variant example. Figure 35 This is a timing diagram illustrating the operation of the disconnector switch 500f in the seventh variant example. In the disconnector switch 500f of the seventh variant example, the first disconnector 510f is configured to also function as the second disconnector 520, and the conducting circuit 501f, the regulating circuit 507, and the pulse supply circuit 503f are different. Figure 23 The disconnecting switch 500 shown includes a conducting circuit 501, a regulating circuit 502, and a pulse supply circuit 503. Other parts of the disconnecting switch 500f have the same configuration as the disconnecting switch 500. Therefore, detailed descriptions of the parts of the disconnecting switch 500f that are substantially the same as those of the disconnecting switch 500 will not be given; the same parts are indicated by the same reference numerals.

[0461] like Figure 34 As shown, the first isolation device 510f includes a first primary coil 511f and a first secondary coil 512f. (As...) Figure 35 As shown, the pulse supply circuit 503f is configured to supply the pulse signal Sp4 only to the first primary coil 511f of the first isolation device 510f. That is, the pulse supply circuit 503f is only connected to the first terminal of the first primary coil 511f and is configured to supply the pulse signal Sp4 to that first terminal. Note that the first isolation device 510f is configured to allow current to flow from the second terminal p32 through the first primary coil 512f to the first terminal p31 in response to the supply of the pulse signal Sp4 to the first primary coil 511f.

[0462] like Figure 34As shown, the regulating circuit 507 of the disconnecting switch 500f has a resistor 571 disposed between the gate and source of the switching device 541 of the switching unit 504.

[0463] like Figure 35 As shown, in response to the control signal DIN switching from Lo level to Hi level, the pulse supply circuit 503f outputs a pulse signal Sp4. The pulse signal Sp4 is provided to the first primary coil 511f, generating an induced current Id1 in the first primary coil 512f. The induced current Id1 flows in the same direction as the forward direction of the diode 513. Therefore, the induced current Id1 flows to the gate of the switching device 541 of the switching unit 504, and the gate-source voltage Vgs increases. In response to the gate-source voltage Vgs exceeding the threshold Vth, the switching device 541 is turned on, causing the first terminal N1 and the second terminal N2 to enter the on state. Thus, the power supply voltage Vp is supplied to the load ZL.

[0464] Furthermore, in response to the control signal DIN switching from Hi level to Lo level, the pulse supply circuit 503f stops supplying the pulse signal Sp4. Therefore, the induced current Id1 is stopped from being supplied to the gate of the switching device 541. On the other hand, the gate of the switching device 541 is connected to the ground potential GND via resistor 571 of the adjustment circuit 507. Therefore, current is drawn to the ground potential through the gate of the switching device 541 via resistor 571. As a result, the gate voltage of the switching device 541 decreases. Then, in response to the gate voltage of the switching device 541 decreasing to a threshold Vth or less, the switching device 541 is turned off, and the first terminal N1 and the second terminal N2 enter a non-conducting state. As a result, the supply of power supply voltage Vp to the load ZL stops, and the load ZL stops.

[0465] As described above, in the disconnect switch 500f, the regulating circuit 507 consists only of resistor 571, thus simplifying the circuit configuration.

[0466] <Application>

[0467] The previously described disconnect switch can be used not only as one of the switches for PLCs (Programmable Logic Controllers), but also as a switch where the primary and secondary sides need to be isolated from each other.

[0468] <Disconnecting Switch (Additional Implementation Scheme)>

[0469] Figure 36 This diagram illustrates an additional embodiment of the disconnecting switch. The disconnecting switch 600 of this embodiment includes a first chip 610, a second chip 620, a third chip 630, and a switching circuit 640. The first chip 610, the second chip 620, and the third chip 630 can be hermetically packaged in a single package.

[0470] The first chip 610 integrates, for example, a pulse generation circuit 611, an oscillator circuit 612, and an UVLO (undervoltage lockout) circuit 613.

[0471] The pulse generation circuit 611 generates pulse signals I11 and I12 based on the logic level of the control signal DIN to be input from the outside. For example, when the control signal DIN is at a high level, the pulse generation circuit 611 generates pulse signal I11. On the other hand, when the control signal DIN is at a low level, the pulse generation circuit 611 generates pulse signal I12. Note that the pulse generation circuit 611 corresponds to the pulse generation circuit 531 described previously. Pulse signals I11 and I12 correspond to the aforementioned first pulse signal Sp1 (Sp21) and second pulse signal Sp2 (Sp22), respectively.

[0472] Oscillator circuit 612 provides a clock signal to pulse generation circuit 611. Pulse signals I11 and I12 are pulse-driven synchronously with the clock signal to be output from oscillator circuit 612. Note that oscillator circuit 612 corresponds to oscillator circuit 532 described previously.

[0473] UVLO 613 is a fault protection circuit. Specifically, in response to the power supply voltage VCC1 to be supplied to the first chip 610 dropping below the UVLO detection threshold, UVLO 613 causes each unit in the first chip 610 (including the pulse generation circuit 611 and the oscillator circuit 612) to enter a non-operating state. On the other hand, in response to the power supply voltage VCC1 exceeding the UVLO elimination threshold, UVLO 613 causes each unit in the first chip 610 to enter an operating state.

[0474] The second chip 620 integrates, for example, transistors n11 to n15 (e.g., npn bipolar transistors), transistors N11 and N12 (e.g., N-channel MOS field-effect transistors), capacitors C11 to C17, resistors R11 to R18, and Zener diode D11.

[0475] The base and collector of transistor n11 are connected to the first output terminal of the third chip 630 (corresponding to the first terminal of the secondary coil 631s described below). The emitter of transistor n11, and the base and collector of transistor n12, are both connected to the first terminal of capacitor C11. The emitter of transistor n12, and the base and collector of transistor n13, are both connected to the first terminal of capacitor C12. The emitter of transistor n13 and the first terminal of resistor R11 are both connected to the first terminal of capacitor C13.

[0476] The second terminal of capacitor C12 is connected to the first output terminal of the third chip 630. The corresponding second terminals of capacitors C11 and C13 are connected to the second output terminal of the third chip 630 (corresponding to the first terminal of the secondary coil 632s).

[0477] The second terminal of resistor R11, the first terminal of resistor R12, and the cathode of Zener diode D11 are all connected to the application terminal of the output pulse signal GO (corresponding to the control terminal of switching circuit 640). The second terminal of Zener diode D11 is connected to the application terminal of reference voltage SI. The second terminal of resistor R12 is connected to the drain of transistor N11. The source and back gate of transistor N11 are both connected to the application terminal of reference voltage SI.

[0478] The collector of transistor n14 and the first terminal of capacitor C14 are both connected to the second output terminal of the third chip 630. The base of transistor n14 is connected to the second terminal of capacitor C14 and the first terminal of resistor R14. The emitter of transistor n14 and the second terminal of resistor R14 are both connected to the first terminal of resistor R16. The second terminal of resistor R16 is connected to the gate of transistor N11.

[0479] The collector of transistor n15 and the first terminal of capacitor C15 are both connected to the first output terminal of the third chip 630. The base of transistor n15 is connected to the second terminal of capacitor C15 and the first terminal of resistor R15. The emitter of transistor n15 and the second terminal of resistor R15 are both connected to the first terminal of resistor R17.

[0480] The corresponding first terminals of resistors R13 and R18, the corresponding first terminals of capacitors C16 and C17, and the source and back gate of transistor N12 are all connected to the applied terminal of the reference voltage SI. The corresponding second terminals of resistors R13 and R17 and capacitor C16 are all connected to the gate of transistor N12. The corresponding second terminals of resistor R18 and capacitor C17, and the drain of transistor N12 are all connected to the gate of transistor N11.

[0481] The third chip 630 corresponds to an isolation circuit, used to transmit the pulse signals I11 and I12 of the first chip 610 as pulse signals (induced currents I21 and I22) of the second chip 620, while providing electrical isolation between the first chip 610 and the second chip 620.

[0482] As shown in the figure, isolation devices 631 and 632 are integrated in the third chip 630. Isolation device 631 can be a transformer including a primary coil 631p and a secondary coil 631s. A pulse signal I11 is applied to the primary coil 631p, and the secondary coil 631s is electromagnetically coupled to the primary coil 631p, inducing an induced current I21 through the primary coil 631p. Isolation device 632 can be a transformer including a primary coil 632p and a secondary coil 632s. A pulse signal I12 is applied to the primary coil 632p, and the secondary coil 632s is electromagnetically coupled to the primary coil 632p, inducing an induced current I22 through the primary coil 632p. The corresponding second terminals of the secondary coils 631s and 632s are both connected to the application terminal of the reference voltage SI.

[0483] Among the above components, transistors n11 to n13, capacitors C11 to C13, resistor R11, Zener diode D11, and isolation device 631 can be understood as components forming the aforementioned conduction circuit 501 (specifically, conduction circuit 501e).

[0484] Furthermore, among the components described above, transistors n14 and n15, transistors N11 and N12, capacitors C14 to C17, resistors R12 to R18, and isolation device 632 can be understood as components forming the previously described regulation circuit 502 (specifically, regulation circuits 502d and 502e).

[0485] Switching circuit 640 includes switching devices 641 and 642 (e.g., both N-channel MOS field-effect transistors). Note that switching circuit 640 corresponds to the previously described switching unit 504 (specifically, switching unit 504c).

[0486] The respective sources and back gates of switching devices 641 and 642 are connected to the application terminal of the reference voltage SI. The gates of switching devices 641 and 642 are connected to the application terminal of the output pulse signal GO.

[0487] In the first connection mode, the drain of switching device 641 can be connected to the application terminal of power supply voltage VCC2 via load ZL1, and the drain of switching device 642 can be connected to the application terminal of ground voltage GND2. In this case, switching circuit 640 functions as a low-side switch.

[0488] In the second connection mode, the drain of switching device 641 can be connected to the applied terminal of ground voltage GND2 via load ZL2, and the drain of switching device 642 can be connected to the applied terminal of power supply voltage VCC2. In this case, switching circuit 640 functions as a high-side switch.

[0489] Note that switching devices 641 and 642 correspond to the first switching device 5411 and the second switching device 5412 described previously, respectively.

[0490] First, the basic operation of the disconnector switch 600 will be described. During the high-level period of the control signal DIN, a pulse signal I11 is generated to drive the primary coil 631p. At this time, the secondary coil 631s generates an induced current I21 flowing in the corresponding forward direction of the diode-connected transistors n11 to n13.

[0491] Furthermore, during the high-level period of the control signal DIN, a pulse signal I12 in the first direction is generated to drive the primary coil 632p. At this time, the secondary coil 632s generates an induced current I22 flowing in the same direction as the induced current I21.

[0492] The induced current I21 is rectified and smoothed via transistors n11 to n13 and capacitors C11 to C13. Therefore, the output pulse signal GO rises to a high level. Consequently, switching devices 641 and 642 are turned on, thus providing drive current to load ZL1 (or load ZL2).

[0493] Note that when the induced current I21 flows, the gate-source voltage of transistor N12 rises via transistor N15, thus turning on transistor N12. Consequently, the gate-source voltage of transistor N11 is pulled down, thus turning off transistor N11. Therefore, the output pulse signal GO does not drop to a low level.

[0494] On the other hand, during the low-level period of the control signal DIN, a pulse signal I12 in the second direction (corresponding to the direction opposite to the first direction) is generated to drive the primary coil 632p. At this time, the secondary coil 632s generates an induced current I22, which flows in the direction opposite to the aforementioned direction, that is, in the positive direction of the diode-connected transistor n14.

[0495] When the induced current I22 flows in the aforementioned direction, the gate-source voltage of transistor N11 increases via transistor n14, thus turning on transistor N11. Therefore, the output pulse signal GO does not drop to a low level. Consequently, switching devices 641 and 642 are turned off, and therefore no drive current is supplied to load ZL1 (or load ZL2).

[0496] In this way, disconnector 600 is configured to work with the previously described disconnectors 500d and 500e. Figure 30 , Figure 32 and Figure 33 The basic principles are the same. Note that the disconnector 600 can be configured to work with other disconnectors 500, provided that the operation of the main parts described below is compatible with each other. Figure 23 ), 500a ( Figure 26 ), 500b Figure 28 ), 500c ( Figure 29 ) and 500f ( Figure 34 They are basically the same.

[0497] In the following description, each of the main parts of the disconnector switch 600 according to the additional embodiment will be described in detail.

[0498] Figure 37 This is a diagram showing the first main portion of a disconnecting switch 600 according to an additional embodiment. As previously described, the disconnecting switch 600 includes transistors n11 to n13 (e.g., npn bipolar transistors), capacitors C11 to C13, resistor R11, Zener diode D11, and isolation device 631 as elements forming the aforementioned conduction circuit 501 (specifically, conduction circuit 501e).

[0499] Specifically, in the above components, transistors n11 to n13 and capacitors C11 to C13 form boost circuits CP11 to CP1x as many times as the number x (note that x is an integer of 2 or greater) of stages connected in series between the secondary coil 631s and the control terminal (corresponding to the application terminal of the output pulse signal GO) of the switching circuit 640.

[0500] Note that although only two stages of the boost circuit CP11 and CP12 are illustrated on the right side of the figure for ease of description, the number of stages x of the boost circuit CP11 to CP1x is not limited to this example. For example, as previously referenced... Figure 36 As shown, three (or more) boost circuits CP11 to CP1x can be provided in the disconnector switch 600.

[0501] Furthermore, in the diagram, diode-connected transistors n11 and n12 are illustrated as rectifier devices forming boost circuits CP11 and CP12, respectively. Note, as previously mentioned... Figure 30 , Figure 32 , Figure 33 As shown, diodes (such as Schottky diodes) can be used as rectifiers. That is, in diode-connected transistors n11 and n12, their respective collectors correspond to the anode of the diode, and their respective emitters correspond to the cathode of the diode. In this way, it can be understood that the term "diode" conceptually also includes diode-connected transistors.

[0502] Note that boost circuits CP11 and CP12 each operate independently as rectifier-smoothing circuits (e.g., refer to the left side of the figure). However, boost circuits CP11 and CP12 each have cleverly designed circuit configurations (specifically, the connection destinations of capacitors C11 and C12) that pull up the high level of the output pulse signal GO.

[0503] In the boost circuits CP11 and CP12 shown on the right side of the figure, the boost circuit CP11 in the first stage (odd-numbered stage) includes transistor n11 and capacitor C11. Similarly, in the boost circuits CP11 and CP12, the boost circuit CP12 in the second stage (even-numbered stage) includes transistor n12 and capacitor C12.

[0504] Transistor n11 is connected as a diode between the first terminal of the secondary coil 631s (corresponding to the terminal where the node voltage Va is applied) and the control terminal of the switching circuit 640 (corresponding to the terminal where the output pulse signal GO is applied), such that its forward direction is the direction of flow of the induced current I21 generated in the secondary coil 631s. Specifically, the collector and base of transistor n11 are connected to the first terminal of the secondary coil 631s (corresponding to the terminal where the node voltage Va is applied). The emitter of transistor n11 is connected to the terminal where the node voltage V1 is applied.

[0505] Transistor n12 is connected as a diode between the first terminal of the secondary coil 631s (corresponding to the terminal where node voltage Va is applied) and the control terminal of the switching circuit 640 (corresponding to the terminal where output pulse signal GO is applied), such that its forward direction is the direction of flow of the induced current I21 generated in the secondary coil 631s. Specifically, the collector and base of transistor n12 are connected to the emitter of transistor n11 (corresponding to the terminal where node voltage V1 is applied). The emitter of transistor n12 is connected to the terminal where node voltage V2 is applied.

[0506] Capacitor C11 is connected between the emitter of transistor n11 (corresponding to the terminal at which node voltage V1 is applied) and the first terminal of the secondary coil 632s (corresponding to the terminal at which node voltage Vb is applied). Capacitor C12 is connected between the emitter of transistor n12 (corresponding to the terminal at which node voltage V2 is applied) and the first terminal of the secondary coil 631s (corresponding to the terminal at which node voltage Va is applied).

[0507] When this circuit configuration is used, in the boost circuit CP11 of the first stage, the signal level is increased by utilizing the voltage difference between node voltage V1 and node voltage Vb. Similarly, in the boost circuit CP12 of the second stage, the signal level is increased by utilizing the voltage difference between node voltage V2 and node voltage Va (corresponding to the slew rate voltage difference). Therefore, node voltage V2 is higher than node voltage V1, thus enabling effective boosting.

[0508] Figure 38 This is a diagram illustrating an example of the operation of the first main body. From the top of the diagram, pulse signals I11 and I12, node voltages Va and Vb (solid and dashed lines), and node voltages V1 and V2 (solid and dashed lines) are shown in sequence.

[0509] As shown in the figure, whenever pulse signals I11 and I12 are driven by pulses, node voltages V1 and V2 rise.

[0510] Then, the node voltage V1 gradually approaches max(Va-Vb)-Vf(n11). Note that max(Va-Vb) is the maximum value of the voltage difference obtained by subtracting the node voltage Vb from the node voltage Va. Furthermore, Vf(n11) is the forward voltage drop of the diode-connected transistor n11.

[0511] Similarly, the node voltage V2 gradually approaches V1 + max(Vb - Va) - Vf(n12). Note that max(Vb - Va) is the maximum value of the voltage difference obtained by subtracting the node voltage Va from the node voltage Vb. Furthermore, Vf(n12) is the forward voltage drop of the diode-connected transistor n12.

[0512] Note that, needless to say, the node voltage Vx (i.e., the high level of the output pulse signal GO) is further pulled up as the number of stages x of the boost circuit CP11 to CP1x becomes larger.

[0513] Figure 39 This is a diagram showing the second main part of the disconnecting switch 600 according to an additional embodiment. As previously described, the disconnecting switch 600 includes elements n14 and n15, transistors N11 and N12, capacitors C14 to C17, resistors R12 to R18, and isolation device 632 as elements forming the aforementioned regulating circuit 502 (specifically, regulating circuits 502d and 502e).

[0514] In particular, as can be seen from the comparison between the left and right sides of the figure, transistor n14 is not a diode-connected type that simply shorts its collector and base to each other, and is inherently designed to pull up the gate voltage of transistor N11.

[0515] As shown on the right side of the figure, capacitor C14 is connected between the collector and base of transistor n14. Additionally, resistor R14 is connected between the emitter and base of transistor n14.

[0516] This configuration helps maintain the voltage raised by capacitor C14 and, starting from the second pulse, raises the voltage based on the difference from the previous signal level. As a result, the emitter voltage of transistor n14 (i.e., the gate voltage of transistor N11) is pulled up.

[0517] Furthermore, it is appropriate for transistor n15 to employ a circuit configuration similar to that described above. (As previously mentioned...) Figure 36 As shown, it is appropriate to connect capacitor C15 between the collector and base of transistor n15. Furthermore, it is appropriate to connect resistor R15 between the emitter and base of transistor n15. This configuration helps to pull up the emitter voltage of transistor n15 (i.e., the gate voltage of transistor N12).

[0518] Figure 40 This diagram illustrates the third main portion of the disconnector switch 600 according to an additional embodiment. As previously described, disconnectors 631 and 632 are integrated in a third chip 630. Disconnector 631 may be a transformer comprising a primary coil 631p to which a pulse signal I11 is applied and a secondary coil 631s electromagnetically coupled to the primary coil 631p and induced to receive an induced current I21 therethrough. Disconnector 632 may be a transformer comprising a primary coil 632p to which a pulse signal I12 is applied and a secondary coil 632s electromagnetically coupled to the primary coil 632p and induced to receive an induced current I22 therethrough.

[0519] Note that primary coils 631p and 632p are connected in series. The corresponding second terminals of primary coils 631p and 632p (corresponding to the connection tap between the two coils) are connected to the applied terminal of ground voltage GND1. Similarly, secondary coils 631s and 632s are connected in series. The corresponding second terminals of secondary coils 631s and 632s (corresponding to the connection tap between the two coils) are connected to the applied terminal of reference voltage SI.

[0520] Specifically, the winding directions of the primary coils 631p and 632p are opposite to each other. Therefore, in isolation device 631, for example, in response to a pulse signal I11 flowing from the first terminal of the primary coil 631p to the second terminal (from top to bottom in the figure), an induced current I21 flows from the second terminal of the secondary coil 631s to the first terminal (from bottom to top in the figure). Conversely, in isolation device 632, for example, in response to a pulse signal I12 flowing from the first terminal of the primary coil 632p to the second terminal (from bottom to top in the figure), an induced current I22 flows from the first terminal of the secondary coil 632s to the second terminal (from bottom to top in the figure).

[0521] Figure 41 This is a diagram showing the third chip 630 in the third main part. Note that the basic structure of the third chip 630 is similar to the transformer chip 230 described earlier. Figure 2 The basic structure is as follows: Primary coils 631p and 632p are both formed in the first wiring layer (lower layer in the figure) of the third chip 630. Secondary coils 631s and 632s are both formed in the second wiring layer (upper layer in the figure) of the third chip 630. Secondary coil 631s is positioned directly above and facing the primary coil 631p. Similarly, secondary coil 632s is positioned directly above and facing the primary coil 632p.

[0522] Furthermore, as previously mentioned, the winding directions of the primary coils 631p and 632p are opposite to each other. Therefore, in response to the pulse signal I11 flowing from the first terminal to the second terminal (GND1) of the primary coil 631p, for example, an upward-facing magnetic field B1 is generated in the primary coil 631p. On the other hand, in response to the pulse signal I12 flowing from the first terminal to the second terminal (GND1) of the primary coil 632p, for example, a downward-facing magnetic field B2 is generated in the primary coil 632p. That is, magnetic fields B1 and B2 cancel each other out. Therefore, electromagnetic noise emitted from the third chip 630 can be reduced.

[0523] Figure 42 This is a diagram illustrating a variant of the third main part described above. As shown, in addition to the previously described isolation devices 631 and 632, the isolation switch 600 of this variant also includes isolation devices 633 and 634.

[0524] The isolation device 633 may be a transformer, which includes a primary coil 633p connected in series with the secondary coil 631s of the isolation device 631, and a secondary coil 633s electromagnetically coupled to the primary coil 633p.

[0525] The isolation device 634 may be a transformer, which includes a primary coil 634p connected in series with the secondary coil 632s of the isolation device 632, and a secondary coil 634s electromagnetically coupled to the primary coil 634p.

[0526] Primary coils 633p and 634p are connected in series. As shown in the diagram, the first terminal of primary coil 633p is connected to the first terminal of secondary coil 631s. The first terminal of primary coil 634p is connected to the first terminal of secondary coil 632s. The respective second terminals of primary coils 633p and 634p are connected to the respective second terminals of secondary coils 631s and 632s.

[0527] Similarly, secondary coils 633s and 634s are connected in series. The corresponding second terminals of secondary coils 633s and 634s (corresponding to the connection taps between the two coils) are connected to the application terminal of the reference voltage SI.

[0528] In isolation device 631, for example, in response to a pulse signal I11 flowing from the first terminal of the primary coil 631p to the second terminal (from top to bottom in the figure), an induced current I21 flows from the second terminal of the secondary coil 631s to the first terminal (from bottom to top in the figure). At this time, in isolation device 633, the induced current I21 flows from the first terminal of the primary coil 633p to the second terminal (from top to bottom in the figure). Therefore, the induced current I31 flows from the second terminal of the secondary coil 633s to the first terminal (from bottom to top in the figure).

[0529] In contrast, for example, in isolation device 632, in response to pulse signal I12 flowing from the first terminal of primary coil 632p to the second terminal (from bottom to top in the figure), induced current I22 flows from the first terminal of secondary coil 632s to the second terminal (from bottom to top in the figure). Meanwhile, in isolation device 634, induced current I22 flows from the second terminal of primary coil 634p to the first terminal (from top to bottom in the figure). Therefore, induced current I32 flows from the first terminal of secondary coil 634s to the second terminal (from bottom to top in the figure).

[0530] Note that in the isolating switch 600 of this variant, the switching circuit 640 is controlled by the aforementioned induced currents I31 and I32.

[0531] Figure 43 This is a diagram showing the third chip 630 in a variant of the third main part. As shown, the third chip 630a, in which isolation devices 631 and 632 are integrated, and the third chip 630b, in which isolation devices 633 and 634 are integrated, can be used as the previously described third chip 630.

[0532] Note that wire bonding can be performed between the third chip 630a and the third chip 630b. Specifically, wire bonding can be performed between the first terminal of the secondary coil 631s and the first terminal of the primary coil 633p, between the first terminal of the secondary coil 632s and the first terminal of the primary coil 634p, and between the respective second terminals of the secondary coils 631s and 632s and the respective second terminals of the primary coils 633p and 634p.

[0533] In this way, the overlapping configuration of multiple levels of isolation devices (isolation devices 631 and 633, and isolation devices 632 and 634 in the figure) can help increase the dielectric strength voltage between the first chip 610 and the second chip 620.

[0534] Figure 44 This diagram illustrates a variant of the second chip 620. Except for omitting transistor n13, capacitors C13, C14, and C16, and resistors R12 to R14, the second chip 620 of this variant is identical to the one previously referenced. Figure 36 The results are essentially the same. Because capacitor C14 is omitted, the base and collector of transistor n14 are directly short-circuited.

[0535] On the other hand, in the second chip 620 of this variant, transistors n16 (e.g., npn bipolar transistor), transistors N13 and N14 (e.g., n-channel MOS field-effect transistor), capacitor C18, and resistors R19 and R1A are added.

[0536] In the following description, redundant descriptions of the previously described components will not be given, as these components are composed of... Figure 36 The same reference numerals in the figures indicate that.

[0537] The collector of transistor n16 and the first terminal of capacitor C18 are both connected to the terminal for applying the induced current I22 (corresponding to the second output terminal of the third chip 630). The base of transistor n16 is connected to the second terminal of capacitor C18 and the first terminal of resistor R19. The emitter of transistor n16 and the second terminal of resistor R19 are both connected to the first terminal of resistor R1A. The second terminal of resistor R1A is connected to the drain of transistor N13.

[0538] The gates of transistors N13 and N14 are both connected to the drain of transistor N13. The drain of transistor N14 is connected to the gate of transistor N12. The sources of transistors N13 and N14 are both connected to the applied terminal of the reference voltage SI. Transistors N13 and N14 form a current mirror that replicates the drain current of transistor N13 as the drain current of transistor N14.

[0539] Figure 45This is a diagram illustrating the operation of the second chip 620 in the above-described modified example. From the top of the diagram, the control signal DIN, pulse signals I11 and I12, the gate-source voltage Vgs of transistor N11, and the on / off states of switching devices 641 and 642 are shown in sequence.

[0540] As shown in the figure, in response to switching the control signal DIN from Lo level to Hi level, pulse signals I11 and I12 are both pulse-driven. Therefore, induced currents I21 and I22 are generated in the second chip 620. This causes switching devices 641 and 642 to conduct.

[0541] Furthermore, in response to the control signal DIN switching from Hi level to Lo level, when pulse signal I11 stops pulse driving, pulse signal I12 continues pulse driving. Therefore, when induced current I21 stops flowing, induced current I22 continues flowing. This causes switching devices 641 and 642 to be turned off.

[0542] <Signal Transmission Device (Additional Implementation Scheme)>

[0543] Figure 46 This is a diagram illustrating an additional embodiment of the signal transmission device. In this embodiment, the signal transmission device 700 transmits the analog input pulse signal AIN of the primary circuit system 700p as the digital output pulse signal DOUT of the secondary circuit system 700s while electrically isolating the primary circuit system 700p (VREG-GND1 system) from the secondary circuit system 700s (VCC2-GND2 system).

[0544] The signal transmission device 700 may include a first chip 710, a second chip 720, and a third chip 730, similar to the previously described signal transmission device 200. Figure 1 ) and 400 Figure 10 (etc.). The first chip 710, the second chip 720, and the third chip 730 can be sealed in a single package.

[0545] The switching circuit 711, the reference voltage generation circuit 712, and the rectifier circuit 713, which are located in the primary circuit system 700p, are integrated into the first chip 710.

[0546] The drive circuit 721, receiver circuit 722, buffer 723, majority voting circuit 724, oscillator circuit 725, and power drive circuit 726, all located in the secondary circuit system 700s, are integrated into the second chip 420. All these circuit blocks operate by being supplied with a power supply voltage VCC2 (e.g., 4.5 to 5.5V) from an external power supply to the secondary circuit system 700s. Note that the external power supply for the secondary circuit system 700s may have, for example, the capability to supply 15mA of current.

[0547] Multiple isolation devices (731, 732P, 732N, 741 and 742) that serve as signal transmission paths between the primary circuit system 700p and the secondary circuit system 700s, while also electrically isolating them, are integrated in the third chip 730.

[0548] Switching circuit 711 switches the connection state between isolation device 731 and positive isolation device 732P and negative isolation device 732N according to analog input pulse signal AIN. In the aspect shown, switching circuit 711 includes switching devices SW5 and SW6, comparator CMP, and inverter INV, as in the fourth embodiment (previously described). Figure 16 As in ( ).

[0549] The comparator CMP outputs an input pulse signal IN by comparing the analog input pulse signal AIN, which is to be input to the non-inverting input terminal (+), with the reference voltage VREF, which is to be input to the inverting input terminal (-). When AIN > VREF, the input pulse signal IN is high. Conversely, when AIN < VREF, the input pulse signal IN is low. The current consumption of the comparator CMP can be, for example, 15 μA.

[0550] The inverter INV generates an inverted input pulse signal INB by inverting the logic level of the input pulse signal IN. When the input pulse signal IN is high, the inverted input pulse signal INB is low. Conversely, when the input pulse signal IN is low, the inverted input pulse signal INB is high.

[0551] When the input pulse signal IN is high and the inverting input pulse signal INB is low, switching device SW5 is turned on and switching device SW6 is turned off. Therefore, conduction is established between isolation device 731 and positive isolation device 732P, and conduction is interrupted between isolation device 731 and negative isolation device 732N. Thus, a positive second signal RiP is generated in positive isolation device 732P. On the other hand, the negative second signal RiN is not generated in negative isolation device 732N.

[0552] Conversely, when the input pulse signal IN is low and the inverted input pulse signal INB is high, switch SW5 is turned off and switch SW6 is turned on. Therefore, the conduction between isolation device 731 and positive isolation device 732P is interrupted, and the conduction between isolation device 731 and negative isolation device 732N is established. Thus, a negative-phase second signal RiN is generated in negative isolation device 732N. On the other hand, a positive-phase second signal RiP is not generated in positive isolation device 732P.

[0553] The reference voltage generation circuit 712 generates a predetermined reference voltage VREF (e.g., 1V). The current consumption of the reference voltage generation circuit 712 can be, for example, 5μA. The output accuracy of the reference voltage VREF can be, for example, ±2%. The reference voltage generation circuit 712 may have a trimming function to increase the output accuracy of the reference voltage VREF.

[0554] The rectifier circuit 713 generates the internal power supply voltage VREG (e.g., 2.4 to 3V) of the primary circuit system 700p by rectifying and smoothing the node voltages Va and Vb sensed by the isolation device 743. The switching circuit 711 and the reference voltage generation circuit 712 both operate by supplying the internal power supply voltage VREG from the rectifier circuit 713.

[0555] The driving circuit 721 periodically or continuously pulses the first signal Po to be applied to the isolation device 731. The current consumption of the driving circuit 721 can be, for example, 2mA. The driving frequency of the first signal Po can be, for example, 10MHz.

[0556] The receiver circuit 722 distinguishes the logic level of the input pulse signal IN by detecting the difference between the positive-phase second signal RiP and the negative-phase second signal RiN. The current consumption of the receiver circuit 722 can be, for example, 5mA.

[0557] The majority voting circuit 724 performs a majority decision process based on the differentiation results of the receiving circuit 722, generating a digital output pulse signal DOUT based on the analog input pulse signal AIN. This is similar to the signal transmission device 400 described previously. Figure 10 In (etc.), the majority voting circuit 724 can be omitted.

[0558] The buffer 723 performs waveform shaping on the digital output pulse signal DOUT and outputs the digital output pulse signal DOUT to the outside of the signal transmission device 700.

[0559] Oscillator circuit 725 generates a drive clock signal CLK for power supply drive circuit 726. The current consumption of oscillator circuit 725 can be, for example, 2mA. The oscillation frequency of drive clock signal CLK can be, for example, 40MHz.

[0560] The power supply drive circuit 726 generates pulse signals I11 and I12 synchronously with the drive clock signal CLK.

[0561] Isolator 431 transmits the single-phase first signal Po from the secondary circuit system 700s to the primary circuit system 700p. Isolator 731 is used as a polling isolation device.

[0562] Positive-phase isolator 732P and negative-phase isolator 732N transmit the differential second signals Rip and RiN from the primary circuit system 700p to the secondary circuit system 700s, respectively. Both positive-phase isolator 732P and negative-phase isolator 732N are used as response isolation devices.

[0563] Isolation devices 741 and 742 correspond to isolation circuits used to transmit the pulse signals I11 and I12 of the second chip 720 as pulse signals (induced currents I21 and I22) of the first chip 710, respectively.

[0564] Among the aforementioned components, the power drive circuit 726, the rectifier circuit 713, and the isolation devices 741 and 742 can be understood as components forming the isolated power supply circuit PW. In other words, the signal transmission device 700 differs from the previously described signal transmission device 400 in that it also includes the isolated power supply circuit PW.

[0565] <Isolation Power Supply Circuit>

[0566] Figure 47 This diagram illustrates an example configuration of an isolated power supply circuit PW. In this example configuration, the isolation device 741 can be a transformer including a secondary coil 741s and a primary coil 741p. A pulse signal I11 is applied to the secondary coil 741s, and the primary coil 741p is electromagnetically coupled to the secondary coil 741s, where an induced current I21 is induced. The isolation device 742 can also be a transformer including a secondary coil 742s and a primary coil 742p. A pulse signal I12 is applied to the secondary coil 742s, and the primary coil 742p is electromagnetically coupled to the secondary coil 742s, where an induced current I22 is induced. The respective second terminals of the primary coils 741p and 742p are both connected to the applied terminal of the ground voltage GND1.

[0567] Note that secondary coils 741s and 742s are connected in series. Similarly, primary coils 741p and 742p are connected in series. The corresponding second terminals of primary coils 741p and 742p (corresponding to the connection tap between the two coils) are connected to the applied terminal of ground voltage GND1.

[0568] Specifically, the winding directions of the secondary coils 741s and 742s are opposite to each other. Therefore, in isolation device 741, for example, in response to a pulse signal I11 flowing from the first terminal to the second terminal of the secondary coil 741s (from top to bottom in the figure), an induced current I21 flows from the second terminal to the first terminal of the primary coil 741p (from bottom to top in the figure). In contrast, in isolation device 742, for example, in response to a pulse signal I12 flowing from the first terminal to the second terminal of the secondary coil 742s (from bottom to top in the figure), an induced current I22 flows from the first terminal to the second terminal of the primary coil 742p (from bottom to top in the figure).

[0569] Therefore, the third main part of the disconnector switch 600 ( Figure 40 and Figure 41 The operating principle is similar to that of the third chip 730, which causes the magnetic fields generated in the isolation devices 741 and 742 to cancel each other out. Therefore, electromagnetic noise emitted from the third chip 730 can be reduced.

[0570] In addition, the rectifier circuit 713 includes transistors n21 to n23 (npn bipolar transistors), capacitors C21 to C23 and C25, and resistors R21 and R22.

[0571] Specifically, in the above components, transistors n21 to n23 and capacitors C21 to C23 form boost circuits CP21 to CP2x as many times as the number x (note that x is an integer of 2 or greater) of stages connected in series between the primary coil 741p and the applied terminal of the internal power supply voltage VREG. Note that although boost circuits CP21 to CP23 in three stages are illustrated in the figure, the number x of boost circuits CP21 to CP2x is by no means limited to this example.

[0572] All transistors n21 to n23 are diode connected between the first terminal of the primary coil 741p (corresponding to the terminal at which the node voltage Va is applied) and the terminal at which the internal power supply voltage VREG is applied, such that their forward direction is the direction in which the induced current I21 to be generated in the primary coil 741p flows.

[0573] Specifically, the base and collector of transistor n21 are connected to the first terminal of the primary coil 741p (corresponding to the terminal for applying node voltage Va). The emitter of transistor n21 and the collector and base of transistor n22 are connected to the terminal for applying node voltage V1. The emitter of transistor n22 and the collector and base of transistor n23 are connected to the terminal for applying node voltage V2. The emitter of transistor n23 is connected to the terminal for applying node voltage V3.

[0574] Note that transistors n21 to n23 can be replaced by diodes (Schottky diodes, etc.).

[0575] Capacitor C21 is connected between the terminals for applying node voltage V1 and node voltage Vb. Capacitor C22 is connected between the terminals for applying node voltage V2 and node voltage Va. Capacitor C23 is connected between the terminals for applying node voltage V3 and node voltage Vb. The capacitance value of each of capacitors C21 to C23 can be, for example, 10pF.

[0576] Resistor R21 is connected between the terminal where node voltage V3 is applied and the terminal where internal power supply voltage VREG is applied. The resistance value of resistor R21 can be, for example, 400Ω.

[0577] Both resistor R22 and capacitor C25 can be connected in parallel between each other between the terminal for applying the internal power supply voltage VREG and the terminal for applying the ground voltage GND1. The resistance value of resistor R22 can be, for example, 100kΩ (assuming a load of 25μA). The capacitance value of capacitor C25 can be, for example, 50pF.

[0578] The isolated power supply circuit PW in this configuration example is connected to the first main part of the isolating switch 600 ( Figure 37 and Figure 38 The operating principle is similar to that of the secondary circuit system 700s. Therefore, effective voltage boosting can be performed by utilizing the slew rate difference. Thus, even in systems without a stable external power supply for the primary circuit system 700p, power can be supplied from the secondary circuit system 700s to the primary circuit system 700p.

[0579] Furthermore, the isolated power supply circuit PW can house a small transformer (isolation devices 741 and 742) that can be incorporated into the signal transmission device 700. Therefore, the cost of the isolated power supply circuit PW is lower than that of a configuration using a common isolated DC / DC converter.

[0580] Note that the current supply capability of the isolation power supply circuit PW (e.g., 25 μA or less) is lower than the current supply capability of the external power supply for the secondary circuit system 700s. Therefore, preferably, the current consumption of the primary circuit system 700p is as low as possible.

[0581] In this regard, similar to the previously described signal transmission device 400 ( Figure 10 The signal transmission device 700 employs a reflective isolation communication method, wherein the primary circuit system 700p responds to a query from the secondary circuit system 700s. Therefore, the primary circuit system 700p only needs to perform switching control according to the input pulse signal IN at the appropriate time to drive the positive phase isolator 732P and the negative phase isolator 732N. Thus, even when the current supply capability of the isolation power supply circuit PW is low, interference is prevented in the signal transmission from the primary circuit system 700p to the secondary circuit system 700s.

[0582] Note that the signal transmission device 700 is configured to work with the fourth embodiment ( Figure 16 The signal transmission device is essentially the same as that of another embodiment (Note that even when the signal transmission device is configured to be similar to that of another embodiment). Figure 10 , Figure 13 , Figure 14 , Figure 17 , Figure 18 , Figure 20 or Figure 21 When the components are basically the same, an isolation power supply circuit PW can also be appropriately introduced.

[0583] Figure 48 This is a diagram illustrating a variant of the signal transmission device 700 according to an additional embodiment. In this variant of the signal transmission device 700, as previously mentioned... Figure 42 and Figure 43 In this context, multiple isolation devices at multiple levels are provided while overlapping.

[0584] As shown in the figure, the first signal Po is transmitted while isolated via isolators 731 and 733. The positive-phase second signal RiP is transmitted while isolated via positive-phase isolators 732P and 734p. The negative-phase second signal RiN is transmitted while isolated via negative-phase isolators 732N and 734N. The pulse signal I11 is transmitted while isolated via isolators 741 and 743. The pulse signal I12 is transmitted while isolated via isolators 742 and 744.

[0585] This configuration can help increase the dielectric strength voltage between the first chip 710 and the second chip 720.

[0586] Figure 49This is a diagram illustrating a variant of the isolated power supply circuit PW. As shown, in addition to the previously described isolation devices 741 and 742, the isolated power supply circuit PW of this variant also includes isolation devices 743 and 744.

[0587] The isolation device 743 may be a transformer, which includes a secondary coil 743s connected in series with the primary coil 741p of the isolation device 741, and a primary coil 743p electromagnetically coupled to the secondary coil 743s.

[0588] The isolation device 744 may be a transformer, which includes a secondary coil 744s connected in series with the primary coil 742p of the isolation device 742, and a primary coil 744p electromagnetically coupled to the secondary coil 744s.

[0589] Secondary coils 743s and 744s are connected in series. As shown in the figure, the first terminal of secondary coil 743s is connected to the first terminal of primary coil 741p. The first terminal of secondary coil 744s is connected to the first terminal of primary coil 742p. The respective second terminals of secondary coils 743s and 744s are connected to the respective second terminals of primary coils 741p and 742p.

[0590] Similarly, primary coils 743p and 744p are connected in series. The corresponding second terminals of primary coils 743p and 744p (corresponding to the connection tap between the two coils) are connected to the applied terminal of ground voltage GND1.

[0591] In isolation device 741, for example, in response to a pulse signal I11 flowing from the first terminal of the secondary coil 741s to the second terminal (from top to bottom in the figure), an induced current I21 flows from the second terminal of the primary coil 741p to the first terminal (from bottom to top in the figure). At this time, in isolation device 743, the induced current I21 flows from the first terminal of the secondary coil 743s to the second terminal (from top to bottom in the figure). Therefore, the induced current I31 flows from the second terminal of the primary coil 743p to the first terminal (from bottom to top in the figure).

[0592] Conversely, in isolation device 742, for example, in response to pulse signal I12 flowing from the first terminal of secondary coil 742s to the second terminal (from bottom to top in the figure), induced current I22 flows from the first terminal of primary coil 742p to the second terminal (from bottom to top in the figure). At this time, in isolation device 744, induced current I22 flows from the second terminal of secondary coil 744s to the first terminal (from top to bottom in the figure). Therefore, induced current I32 flows from the first terminal of primary coil 744p to the second terminal (from bottom to top in the figure).

[0593] Note that in the isolated power supply circuit PW of this variant, the aforementioned induced currents I31 and I32 flow through the rectifier circuit 713.

[0594] In addition to the previously described transistors n21 to n23, capacitors C21 to C23 and C25, and resistors R21 and R22, rectifier circuit 713 also includes transistor n24 (e.g., an npn bipolar transistor) and capacitor C24. That is, in addition to the previously described boost circuits CP21 to CP24, rectifier circuit 713 also includes boost circuit CP24 in the fourth stage.

[0595] As shown in the diagram, the collector and base of transistor n24 are connected to the terminal where node voltage V3 is applied. The emitter of transistor n24 is connected to the terminal where node voltage V4 is applied. Capacitor C24 is connected between the terminal where node voltage V4 is applied and the terminal where node voltage Va is applied.

[0596] In this way, as the number of boost circuits CP21 to CP2x increases, the internal power supply voltage VREG is pulled up.

[0597] Figure 50 This is a diagram illustrating variations of isolation devices 731 and 733. As shown on the left and in the center of the figure, isolation device 731 can be a transformer, which includes a secondary coil 731s to be connected to drive circuit 721 and a primary coil 731p to be electromagnetically coupled to the secondary coil 731s. Similarly, isolation device 733 can be a transformer, which includes a secondary coil 733s connected in series with the primary coil 731p of isolation device 731, and a primary coil 733p electromagnetically coupled to the secondary coil 733s.

[0598] In isolation device 731, for example, in response to the application of pulse signal I41 and first signal Po, current I51 flows from the first terminal of secondary coil 731s to the second terminal (from top to bottom in the figure), and induced current I51 flows from the second terminal of primary coil 731p to the first terminal (from bottom to top in the figure). At this time, in isolation device 733, induced current I51 flows from the first terminal of secondary coil 733s to the second terminal (from top to bottom in the figure). Therefore, induced current I61 flows from the second terminal of primary coil 733p to the first terminal (from bottom to top in the figure).

[0599] In this way, the configuration in which isolation devices 631 and 633 are simultaneously overlapped can help increase the dielectric strength voltage between the first chip 710 and the second chip 720.

[0600] Furthermore, as shown on the right side of the figure, isolation devices 735 and 636 can be integrated into the third chip 730. Isolation device 735 can be a transformer, which includes a secondary coil 735s to be connected to the drive circuit 721 and a primary coil 735p to be electromagnetically coupled to the secondary coil 735s. Similarly, isolation device 736 can be a transformer, which includes a secondary coil 736s ​​connected in series with the primary coil 735p of isolation device 735, and a primary coil 736p electromagnetically coupled to the secondary coil 736s.

[0601] Note that secondary coils 731s and 735s are connected in series. The corresponding second terminals of secondary coils 731s and 735s (corresponding to the connection tap between the two coils) are connected to the terminal for applying the ground voltage GND2.

[0602] Specifically, the winding directions of the secondary coils 731s and 735s are opposite to each other. Therefore, in isolation device 731, for example, in response to a pulse signal I41 flowing from the first terminal to the second terminal of the secondary coil 731s (from top to bottom in the figure), an induced current I51 flows from the second terminal to the first terminal of the primary coil 731p (from bottom to top in the figure). In contrast, in isolation device 735, for example, in response to a pulse signal I42 flowing from the first terminal to the second terminal of the secondary coil 735s (from bottom to top in the figure), an induced current I52 flows from the first terminal to the second terminal of the primary coil 735p (from bottom to top in the figure).

[0603] Therefore, the third main part of the disconnector switch 600 ( Figure 40 and Figure 41 The operating principle is similar to that of the third chip 730, causing the magnetic fields generated in the isolation devices 731 and 735 to cancel each other out. Therefore, electromagnetic noise emitted from the third chip 730 can be reduced.

[0604] Note that in response to the induced current I52 flowing from the first terminal of the primary coil 735p to the second terminal (from bottom to top in the figure), in the isolation device 736, the induced current I52 flows from the second terminal of the secondary coil 736s ​​to the first terminal (from top to bottom in the figure). Therefore, the induced current I62 flows from the second terminal of the primary coil 736p to the first terminal (from bottom to top in the figure).

[0605] <Appendix>

[0606] The appendices to this disclosure are provided in the following description.

[0607] [Appendix 1]

[0608] A disconnecting switch (500, 500a, 500b, 500c, 500d, 500e, 500f) includes:

[0609] The switching units (504, 504b, 504c) are configured to be controlled, causing the switching units (504, 504b, 504c) to enter the on / off state.

[0610] The conducting circuits (501, 501e) are configured to control the switching units (504, 504b, 504c) so that the switching units (504, 504b, 504c) enter the conducting state.

[0611] The regulating circuits (502, 502a, 502d) are configured to at least adjust the switching units (504, 504b, 504c) from the on state to the off state; and

[0612] The pulse supply circuits (503, 503f) are configured as follows:

[0613] Receive control signals (DIN), and

[0614] Pulse signals (Sp1, Sp2, Sp21, Sp22, Sp4) are supplied to at least one of the conducting circuits (501, 501e) and the regulating circuits (502, 502a, 502d).

[0615] The conducting circuit (501, 501e) includes a first isolation device (510, 5101, 5102), and the first isolation device (510, 5101, 5102) includes:

[0616] The first primary coil (511, 5111, 5121) connected to the pulse supply circuit (503, 503f), and

[0617] The first primary coils (512, 5112, 5122) are electromagnetically coupled to the first primary coils (511, 5111, 5121).

[0618] The conducting circuits (501, 501e) are configured to activate the switching units (504, 504b, 504c) using an induced current (Id1). The induced current (Id1) flows in response to the rising pulse signals (Sp1, Sp2, Sp21, Sp22, Sp4) supplied to the first primary coils (511, 5111, 5121).

[0619] The regulating circuits (502, 502a, 502d, 507) include:

[0620] The second isolation device (520) includes:

[0621] A second primary coil (521) connected to the pulse supply circuit (503, 503f), a second secondary coil (522) electromagnetically coupled to the second primary coil (521), and regulating devices (524, 524b) are configured to regulate the voltage at the control terminals of the switching units (504, 504b, 504c) to a non-conducting state by adjusting the voltage at the control terminals of the switching units (504, 504b, 504c) using the induced current (Id2, Id21) flowing through the second secondary coil (522) in response to the rise of pulse signals (Sp1, Sp2, Sp21, Sp22, Sp4).

[0622] The pulse supply circuits (503, 503f) are configured as follows:

[0623] With the control signal (DIN) at the first level, a pulse signal (Sp1) is provided to the first primary coil (511, 5111, 5121), and

[0624] After the control signal (DIN) switches from the first level to a second level different from the first level, the pulse signal (Sp22) is supplied to the second primary coil (521).

[0625] The switching units (504, 504b, 504c) are configured to be in the ON state when the control signal (DIN) is at the first level.

[0626] [Appendix 2]

[0627] According to the disconnecting switches (500, 500a, 500b, 500c, 500d, 500e, 500f) in Appendix 1, among which

[0628] The conducting circuit (501, 501e) has a diode (513) disposed between the primary coil (512) and the control terminal of the switching unit (504, 504b, 504c) such that the forward direction of the diode (513) is the direction of flow of the induced current to be generated in the primary coil (512).

[0629] [Appendix 3]

[0630] According to Appendix 1 or 2, the disconnecting switches (500, 500a, 500f) are as follows:

[0631] The switching units (504, 504c) include n-channel MOS transistors.

[0632] The conduction circuits (501, 501e) are configured to allow induced current to flow into the gate, and

[0633] The regulating circuits (502, 502a, 502d, 507) are configured to draw current through the gate.

[0634] [Appendix 4]

[0635] According to the disconnector switch (500b) described in Appendix 1, wherein

[0636] The switching unit (504b) includes a p-channel MOS transistor (541b).

[0637] The conduction circuit (501) is configured to draw current through the gate via the induced current, and the regulation circuit (502) is configured to supply current to the gate.

[0638] [Appendix 5]

[0639] According to any one of Appendices 1 to 4, the disconnecting switch (500c, 500d, 500e) wherein

[0640] The switching unit (504c) has a configuration in which a first switching device (5411) and a second switching device (5412) are connected in series.

[0641] Both the first switching device (5411) and the second switching device (5412) are either n-channel MOS transistors or p-channel MOS transistors, and

[0642] The first terminal (P11) of the first primary coil (512, 5121, 5122) in the conducting circuit (501) is connected to the connection node where the gates of the first switching device (5411) and the second switching device (5412) are connected, and

[0643] The second terminal (P12) of the first primary coil (512, 5121, 5122) in the conducting circuit (501) is connected to the connection node where the sources of the first switching device (5411) and the second switching device (5412) are connected.

[0644] [Appendix 6]

[0645] The disconnecting switches (500, 500a, 500b, 500c, 500d, 500e) according to any one of Appendices 1 to 5, wherein

[0646] The regulating circuits (502, 502a, 502d) include regulating switching devices (524, 524b) connected between the gate and source of the switching devices (541, 541b, 5411, 5412) forming the switching units (504, 504b, 504c), and...

[0647] The regulating circuits (502, 502a, 502d) are configured to turn on the regulating switching devices (524, 524b) using the induced current of the secondary coil (522).

[0648] [Appendix 7]

[0649] The disconnecting switches (500, 500a, 500c, 500d, 500e) according to any one of Appendices 1 to 6, wherein

[0650] The regulating circuits (502a, 502d, 502e) are configured to assist in the operation of putting the switching units (504, 504c) into the conducting state via the conduction circuits (501, 501a, 501e) when the control signal (DIN) is at the first level.

[0651] The pulse supply circuit (503) is configured to supply a pulse signal to the second primary coil (521) of the second isolation device (520) when the control signal (DIN) is at the first level.

[0652] [Appendix 8]

[0653] According to any one of Appendices 1 to 7, the disconnector (500d) wherein

[0654] The conduction circuit (501) is configured to suppress the operation of the adjustment circuit (502d) to put the switching unit (504c) into a non-conducting state when the control signal (DIN) is at the first level, and

[0655] The conducting circuit (501) is configured to turn off the first regulating switching device (524) using the induced current (Id1) of the primary coil (512).

[0656] [Appendix 9]

[0657] According to any one of Annexes 1 to 8, the disconnector (500e) wherein

[0658] The disconnector switch (500e) has the following configuration:

[0659] The primary winding includes multiple primary windings (5112, 5122) connected in series, and

[0660] The first primary coil includes multiple first primary coils (5111, 5121) that are electromagnetically coupled to multiple first primary coils (5112, 5122).

[0661] [Appendix 10]

[0662] According to any one of Annexes 1 to 9, the disconnector (500e) wherein

[0663] The primary coil (5112) and the secondary coil (522e) are connected in series, and

[0664] The winding direction of the second-stage coil (522e) is opposite to that of the first-stage coil (5112).

[0665] [Appendix 11]

[0666] According to any one of Appendices 1 to 7, the disconnector (500f) wherein

[0667] The first isolation device (510f) is configured to also function as the second isolation device.

[0668] [Appendix 12]

[0669] The disconnecting switches (500, 500a, 500b, 500c, 500d, 500e, 500f) according to any one of Appendices 1 to 10, wherein

[0670] The pulse supply circuits (503, 503f) are configured to generate pulse signals (Sp1, Sp4) in a first cycle within a predetermined time period after the control signal (DIN) switches from the second level to the first level, and then generate pulse signals in a second cycle that is longer than the first cycle.

[0671] [Appendix 13]

[0672] According to the disconnector switch (500f) described in Appendix 11, wherein

[0673] The pulse supply circuit (503F) is

[0674] Configured to supply a pulse signal (Sp4) to the first terminal of the first primary coil (511f) when the control signal (DIN) is at the first level, and

[0675] It is configured not to supply pulse signals to the first primary coil (511f) when the control signal (DIN) is at the second level.

[0676] [Appendix 14]

[0677] According to Appendix 11 or 12, the disconnecting switch (500f) wherein

[0678] The regulating circuit (507) consists of a control terminal connected to the switching unit (504) and a resistor (571) connected to the ground potential (GND).

[0679] [Appendix 15]

[0680] According to any one of Appendices 1 to 8, the disconnector (500d)

[0681] The regulating circuit (502d) includes:

[0682] The first regulating switch device (524) connected in parallel with the primary coil (512), and

[0683] The second regulating switch (528) is connected in parallel with the second stage coil (522).

[0684] The regulating circuit (502d) has the following configuration:

[0685] With the pulse signal (Sp2) supplied to the second primary coil (521), the first regulating switch (524) is activated by the induced current (Id21) induced by the second primary coil (522), and

[0686] With the pulse signal (Sp1) already provided to the first primary coil (511), the first regulating switch (524) is turned off in response to the second regulating switch (528) being switched on by the induced current (Id1) induced by the first primary coil (512).

[0687] [Appendix 16]

[0688] According to any one of Appendices 1 to 15, the disconnector (600) wherein

[0689] The conduction circuit includes a multi-stage boost circuit (CP11, CP12) connected in series between the primary coil (631s) and the control terminal (GO) of the switching unit.

[0690] The odd-numbered boost circuit (CP11) in the multi-stage boost circuit (CP11, CP12) includes:

[0691] The first diode (n11) is connected between the primary coil (631s) and the control terminal (GO) of the switching unit, such that the forward direction of the first diode (n11) is the direction in which the induced current (I21) will flow in the primary coil (631s).

[0692] The first capacitor (CP11) is connected between the cathode of the first diode (n11) and the second stage coil (632s), and

[0693] The even-numbered boost circuit (CP12) in the multi-stage boost circuit (CP11, CP12) includes:

[0694] The second diode (n12) is connected between the primary coil (631s) and the control terminal (GO) of the switching unit, such that the forward direction of the second diode (n12) is the direction in which the induced current (I21) generated in the primary coil (631s) flows.

[0695] A second capacitor (CP12) is connected between the cathode of the second diode (n12) and the first stage coil (631s).

[0696] [Appendix 17]

[0697] The disconnector switch (600) according to any one of Appendices 1 to 16, wherein

[0698] The regulating circuit includes:

[0699] The first regulating switch (N11) is connected in parallel with the primary coil (631s).

[0700] The first transistor (n14) is connected between the second stage coil (632s) and the control terminal of the first regulating switch (N11).

[0701] A first capacitor (C14) is connected between the first main electrode of the first transistor (n14) and the control terminal.

[0702] The first resistor (R14) is connected between the second main electrode of the first transistor (n14) and the control terminal.

[0703] [Appendix 18]

[0704] According to the disconnector switch (600) described in Appendix 17, wherein

[0705] The regulating circuit includes:

[0706] The second regulating switch (N12) is connected in parallel with the second stage coil (632s).

[0707] The second transistor (n15) is connected between the control terminal of the first stage coil (631s) and the second regulating switch device (N12).

[0708] The second capacitor (C15) is connected between the first main electrode of the second transistor (n15) and the control terminal, and

[0709] The second resistor (R15) is connected between the second main electrode and the control terminal of the second transistor (n15).

[0710] [Appendix 19]

[0711] The disconnector switch (600) according to any one of Appendices 1 to 18, wherein

[0712] The first primary coil (631p) and the second primary coil (632p) are connected in series, and

[0713] The winding direction of the first primary coil (631p) is opposite to that of the second primary coil (632p).

[0714] [Appendix 20]

[0715] The disconnector switch (600) according to any one of Appendices 1 to 19 further includes:

[0716] The third isolation device (633) includes

[0717] The third primary coil (633p) is connected in series with the first primary coil (631s), and

[0718] The third-stage coil (633s) is electromagnetically coupled to the third primary coil (633p); and

[0719] The fourth isolation device (634) includes

[0720] The fourth primary coil (634p) is connected in series with the second-stage coil (632s), and

[0721] The fourth secondary coil (634s) is electromagnetically coupled to the fourth primary coil (634p), in which...

[0722] The switching unit (640) is controlled by induced currents (I31, I32) flowing through the third secondary coil (633s) and the fourth secondary coil (634s), respectively.

[0723] [Appendix 21]

[0724] A sequencer comprising disconnecting switches (500, 500a, 500b, 500c, 500d, 500e, 500f) according to any one of Appendices 1 to 20.

[0725] According to Appendices 1 to 21, disconnecting switches and sequencers that can operate stably for extended periods can be provided.

[0726] [Appendix 22]

[0727] A signal transmission device (400) is configured to transmit a signal between a primary circuit system (400p) and a secondary circuit system (400s), while isolating the primary circuit system (400p) and the secondary circuit system (400s). The signal transmission device (400) includes:

[0728] First isolation devices (431, 433) are configured to transmit a first signal (Po) from the secondary circuit system (400s) to the primary circuit system (400p);

[0729] The second isolation devices (432, 434) are configured to transmit the second signal (Ri) from the primary circuit system (400p) to the secondary circuit system (400s);

[0730] A drive circuit (421) is disposed in the secondary circuit system (400) and configured to drive the first isolation devices (431, 433);

[0731] A switching circuit (411) is provided in the main circuit system (400p) and configured to switch the connection state between the first isolation device (431) and the second isolation device (432, 434) according to the input signals (INP, INN); and

[0732] The receiving circuit (422) is provided in the secondary circuit system (400s) and is configured to detect the second signal (Ri) and generate an output signal (OUT) based on the input signal (INP, INN).

[0733] [Appendix 23]

[0734] According to the signal transmission device (400) described in Appendix 22, wherein

[0735] The second isolation device (432) is configured to output a second signal (Ri) in a single phase, and the switching circuit (411) switches the connection state between the first isolation device (431, 433) and the second isolation device (432, 434) to either a first connection state or a second connection state. In the first connection state, the second isolation device (432) is driven according to the first signal (Po), and in the second connection state, the driving of the second isolation device (432) is suppressed according to the first signal (Po).

[0736] [Appendix 24]

[0737] According to the signal transmission device (400) described in Appendix 22, wherein

[0738] The second isolation device (432) includes a positive phase isolation device (432P) and a negative phase isolation device (432N), and is configured to differentially output the corresponding output signals from the positive phase isolation device (432P) and the negative phase isolation device (432N) as a second signal (Rip, RiN).

[0739] The switching circuit (411) switches the connection state between the first isolation device (431) and the second isolation device (432) to either the first connection state or the second connection state. In the first connection state, the positive phase isolation device (432P) is driven according to the first signal (Po), and in the second connection state, the negative phase isolation device (432N) is driven according to the first signal (Po).

[0740] [Appendix 25]

[0741] The signal transmission device (400) according to any one of Appendices 22 to 24, wherein

[0742] The first isolation device (431) and the second isolation device (432) are each transformers, and

[0743] The switching circuit (411) includes switching devices (SW1, SW5, SW6) connected between the first isolation device (431) and the second isolation device (432).

[0744] [Appendix 26]

[0745] The signal transmission device (400) according to any one of Appendices 22 to 25, wherein

[0746] The first isolation device (431) and the second isolation device (432) are each transformers, and

[0747] The switching circuit (411) includes switching devices (SW2, SW3, SW4) connected in parallel to at least one of the first isolation device (431) and the second isolation device (432).

[0748] [Appendix 27]

[0749] The signal transmission device (400) according to any one of Appendices 22 to 24, wherein

[0750] The first isolation device (433) and the second isolation device (434) are each capacitors, and the switching circuit (411) includes a first switching device (SW7, SW8) connected between the second isolation device (434) and the fixed potential terminal (GND).

[0751] [Appendix 28]

[0752] According to the signal transmission device (400) described in Appendix 27, wherein

[0753] The switching circuit (411) also includes a second switching device (SW9, SW10) connected between the first isolation device (433) and the second isolation device (434).

[0754] [Appendix 29]

[0755] The signal transmission device (400) according to any one of Appendices 22 to 28, wherein

[0756] The drive circuit (421) drives the first isolation device (431, 433) in one of two modes: cyclic and continuous.

[0757] [Appendix 30]

[0758] The signal transmission device (400) according to any one of Appendices 22 to 30, wherein

[0759] The current capability of the power supply used for the secondary circuit system (400s) is higher than that of the power supply used for the primary circuit system (400p).

[0760] [Appendix 31]

[0761] The signal transmission device (400) according to any one of Appendices 22 to 30 further includes:

[0762] The first chip (410) integrates a switching circuit (411);

[0763] The second chip (420) integrates a driving circuit (421) and a receiving circuit (422); and

[0764] The third chip (430) integrates a first isolation device (431, 433) and a second isolation device (432, 434), wherein...

[0765] The first chip (410), the second chip (420), and the third chip (430) are sealed in a single package.

[0766] [Appendix 32]

[0767] The signal transmission device (700) according to any one of Appendices 22 to 26 further includes an isolation power supply circuit (PW) configured to supply power from the secondary circuit system (700s) to the primary circuit system (700p) while isolating the primary circuit system (700p) and the secondary circuit system (700s).

[0768] [Appendix 33]

[0769] According to the signal transmission device (700) described in Appendix 32, wherein

[0770] The isolated power supply circuit (PW) includes:

[0771] The power supply drive circuit (726) is configured to generate both the third signal (I11) and the fourth signal (I12).

[0772] A third isolation device (741) is configured to be driven according to a third signal (I11) and simultaneously isolates the primary circuit system (700p) from the secondary circuit system (700s).

[0773] A fourth isolation device (742), configured to be driven according to a fourth signal (I12) and to isolate between the primary circuit system (700p) and the secondary circuit system (700s), and a rectifier circuit (713), configured to generate a power supply voltage (VREG) for the main circuit system (700p) by using a first voltage (Va) induced in the main circuit system (700p) via a third isolation device (741) and a second voltage (Vb) induced in the main circuit system (700p) via the fourth isolation device (742).

[0774] [Appendix 34]

[0775] According to the signal transmission device (700) described in Appendix 33, wherein

[0776] The rectifier circuit (713) includes a multi-stage boost circuit (CP21 to CP24) connected in series between the first voltage (Va) application terminal and the power supply voltage (VREG) application terminal.

[0777] The odd-numbered boost stages (CP21, CP23) in the multi-stage boost circuit (CP21 to CP24) include:

[0778] The first diodes (n21, n23) are connected between the terminal for applying the first voltage (Va) and the terminal for applying the power supply voltage (VREG), such that the forward directions of the first diodes (n21, n23) are respectively the flow directions of the first current (I31) to be induced through the third isolation device (741), and

[0779] The first capacitor (C21, C23) is connected between the cathode of the first diode (n21, n23) and the terminal where the second voltage (Vb) is applied, and

[0780] The even-numbered boost stages (CP22, CP24) in the multi-stage boost circuit (CP21 to CP24) include:

[0781] The second diodes (n22, n24) are connected between the terminal where the first voltage (Va) is applied and the terminal where the power supply voltage (VREG) is applied, such that the forward direction of the second diodes (n22, n24) is respectively the direction of flow of the first current (I31), and

[0782] The second capacitor (C22, C24) is connected between the cathode of the second diode (n22, n24) and the terminal where the first voltage (Va) is applied.

[0783] [Appendix 35]

[0784] According to the signal transmission device (700) described in Appendix 33 or 34, wherein

[0785] The secondary coil (741s) of the third isolation device (741) to which the third signal (I11) is applied, and the secondary coil (742s) of the second isolation device (742) to which the second signal (I12) is applied, are connected in series.

[0786] The winding direction of the secondary coil (741s) of the third isolation device (741) and the winding direction of the secondary coil (742s) of the fourth isolation device (742) are opposite to each other.

[0787] [Appendix 36]

[0788] The signal transmission device (700) according to any one of Appendices 33 to 35 further includes:

[0789] A fifth isolation device (743) configured to isolate the third isolation device (741) from the terminal where the first voltage (Va) is applied; and

[0790] A sixth isolation device (744) is configured to isolate the fourth isolation device (742) from the terminal where the second voltage (Vb) is applied.

[0791] [Appendix 37]

[0792] The signal transmission device (700) according to any one of Appendices 22 to 26 further includes a third isolation device (735), wherein

[0793] The driving circuit generates a third signal (I41) and a fourth signal (I42) as the first signal (Po).

[0794] The secondary coil (731s) of the first isolation device (731) to which the third signal (I41) is applied and the secondary coil (735s) of the third isolation device (735) to which the fourth signal (I42) is applied are connected in series, and

[0795] The winding direction of the secondary coil (731s) of the first isolation device (731) and the winding direction of the secondary coil (735s) of the third isolation device (7735) are opposite to each other.

[0796] [Appendix 38]

[0797] The signal transmission device (700) according to any one of Appendices 22 to 26 further includes:

[0798] A third isolation device (733) is configured to isolate the first isolation device (731) from the switching circuit (711); and

[0799] A fourth isolation device (734) is configured to isolate the second isolation device (732) from the receiving circuit 722.

[0800] The signal transmission device according to any one of Appendices 22 to 38 can help transmit signals that are independent of the power supply of the main circuit system.

[0801] [Appendix 39]

[0802] An isolated power supply circuit (PW) includes:

[0803] The power supply drive circuit (726) is configured to generate both a first signal (I11) and a second signal (I12);

[0804] A first isolation device (741) is configured to be driven according to a first signal (I11) while isolating the primary circuit system (700p) and the secondary circuit system (700s);

[0805] A second isolation device (742) configured to be driven according to a second signal (I12) while isolating the primary circuit system (700p) from the secondary circuit system (700s); and

[0806] The rectifier circuit (713) is configured to generate a power supply voltage (VREG) for the main circuit system (700p) by using a first voltage (Va) induced in the main circuit system (700p) via a first isolation device (741) and a second voltage (Vb) induced in the main circuit system (700p) via a second isolation device (742).

[0807] [Appendix 40]

[0808] According to the isolated power supply circuit (PW) described in Appendix 39, wherein

[0809] The rectifier circuit (713) includes a multi-stage boost circuit (CP21 to CP24) connected in series between the first voltage (Va) application terminal and the power supply voltage (VREG) application terminal.

[0810] The odd-numbered boost stages (CP21, CP23) in the multi-stage boost circuit (CP21 to CP24) include:

[0811] The first diodes (n21, n23) are connected between the terminal for applying the first voltage (Va) and the terminal for applying the power supply voltage (VREG), such that the forward directions of the first diodes (n21, n23) are respectively the flow directions of the first current (I31) to be induced through the first isolation device (741), and

[0812] The first capacitor (C21, C23) is connected between the cathode of the first diode (n21, n23) and the terminal where the second voltage (Vb) is applied, and

[0813] The even-numbered boost stages (CP22, CP24) in the multi-stage boost circuit (CP21 to CP24) include:

[0814] The second diodes (n22, n24) are connected between the terminal where the first voltage (Va) is applied and the terminal where the power supply voltage (VREG) is applied, such that the forward direction of the second diodes (n22, n24) is respectively the direction of flow of the first current (I31), and

[0815] The second capacitor (C22, C24) is connected between the cathode of the second diode (n22, n24) and the terminal where the first voltage (Va) is applied.

[0816] The isolated power supply circuits according to Appendices 39 and 40 can help supply power from the secondary circuit system to the primary circuit system in the absence of a power source.

[0817] [Appendix 41]

[0818] An isolation circuit (630, 730) includes:

[0819] The first isolation device (631, 731, 741); and

[0820] Second isolation devices (632, 735, 742),

[0821] The first isolation device (631, 731, 741) includes:

[0822] The first coil (631p, 731s, 741s) is supplied with a first signal (I11, I41), and

[0823] The second coil (631s, 731p, 741p) is electromagnetically coupled to the first coil (631p, 731s, 741s).

[0824] The second isolation device (632, 735, 742) includes:

[0825] The third coil (632p, 735s, 742s) is supplied with the second signal (I12, I42), and

[0826] The fourth coil (632s, 735p, 742p) is electromagnetically coupled to the third coil (632p, 735s, 742s).

[0827] The first coil (631p, 731s, 741s) and the third coil (632p, 735s, 742s) are connected in series.

[0828] The winding directions of the first coil (631p, 731s, 741s) and the winding directions of the third coil (632p, 735s, 742s) are opposite to each other.

[0829] [Appendix 42]

[0830] The isolation circuits (630, 730) described in Appendix 41 also include:

[0831] Third isolation devices (633, 733, 743); and

[0832] The fourth isolation device (634, 736, 744), among which

[0833] The third isolation device (633, 733, 743) includes:

[0834] The fifth coil (633p, 733s, 743s) is connected in series with the second coil (631s, 731p, 741p), and

[0835] The sixth coil (633s, 733p, 743p) is electromagnetically coupled to the fifth coil (633p, 733s, 743s).

[0836] The fourth isolation device (634, 736, 744) includes:

[0837] The seventh coil (634p, 736s, 744s) is connected in series with the fourth coil (632s, 735p, 742p), and

[0838] The eighth coil (634s, 736p, 744p) is electromagnetically coupled to the seventh coil (634p, 736s, 744s).

[0839] <Other variations>

[0840] It should be noted that the various technical features disclosed herein can be implemented in any manner other than those in the above-described embodiments, and various modifications are permitted without departing from the essence of its technical originality. That is, the above-described embodiments should be understood as illustrative rather than restrictive in every respect. Furthermore, it should be understood that the technical scope of this disclosure is defined by the appended claims and covers any modifications within the equivalent scope and meaning of those claims.

[0841] Explanation of reference numerals in the attached figures

[0842] 5 Semiconductor Devices

[0843] 11, 11A~11F low potential terminals

[0844] 12, 12A~12F high potential terminals

[0845] 21. Transformers 21A to 21D (Transformers)

[0846] 22 Low-potential coil (primary side coil)

[0847] 23 High-potential coil (secondary side coil)

[0848] 24 First inner end

[0849] 25 First lateral end

[0850] 26 First spiral section

[0851] 27 Second inner end

[0852] 28 Second lateral end

[0853] 29 Second Spiral Section

[0854] 31 First Low-Potential Wiring

[0855] 32 Second Low Potential Wiring

[0856] 33 First High-Potential Wiring

[0857] 34 Second High Potential Wiring

[0858] 41 Semiconductor Chips

[0859] 42 First Main Page

[0860] 43 Second Main Face

[0861] 44A~44D chip sidewall

[0862] 45 First functional device

[0863] 51 Insulation layer

[0864] 52 Insulation Main Surface

[0865] 53A~53D Insulating Sidewalls

[0866] 55 Bottom insulation layer

[0867] 56. Topmost insulating layer

[0868] 57 interlayer insulation

[0869] 58 First Insulation Layer

[0870] 59 Second Insulation Layer

[0871] 60 Secondary functional devices

[0872] 61 Sealed conductor

[0873] 62 Device Area

[0874] 63 Outer region

[0875] 64 Sealed plug conductor

[0876] 65 Sealed Path Conductor

[0877] 66 First inner region

[0878] 67 Second inner region

[0879] 71 Through-wiring

[0880] 72 Low-potential connection wiring

[0881] 73 Lead-out wiring

[0882] 74 First connecting plug electrode

[0883] 75 Second connecting plug electrode

[0884] 76 Pad Plug Electrode

[0885] 77 Substrate plug electrode

[0886] 78 First Electrode Layer

[0887] 79 Second electrode layer

[0888] 80 Wiring plug electrode

[0889] 81 High-potential connection wiring

[0890] 82 Pad Plug Electrode

[0891] 85. Dummy Pattern

[0892] 86 High-potential virtual patterns

[0893] 87 First High Potential Dummy Pattern

[0894] 88 Second High Potential Dummy Pattern

[0895] 89 First District

[0896] 90 Second Zone

[0897] 91 Third Region

[0898] 92 First connecting part

[0899] 93 First Pattern

[0900] 94 Second Pattern

[0901] 95 Third Pattern

[0902] 96 First outer weekly line

[0903] 97 Second outer weekly line

[0904] 98 First median line

[0905] 99 First connecting line

[0906] 100 slits

[0907] 130 Separated Structure

[0908] 140 Inorganic Insulation Layer

[0909] 141 First Inorganic Insulation Layer

[0910] 142 Second Inorganic Insulation Layer

[0911] 143 Low-potential pad opening

[0912] 144 High-potential pad opening

[0913] 145 Organic Insulation Layer

[0914] 146 Part One

[0915] 147 Part Two

[0916] 148 Low-potential terminal opening

[0917] 149 High-potential terminal opening

[0918] 200 Signal Transmission Device

[0919] 200p primary circuit system

[0920] 200s secondary circuit system

[0921] 210 Controller Chip (First Chip)

[0922] 211 Pulse Transmission Circuit (Pulse Generator)

[0923] Buffers 212 and 213

[0924] 220 driver chip (second chip)

[0925] 221, 222 buffers

[0926] 223 Pulse Receiving Circuit (RS Flip-Flop)

[0927] 224 drives

[0928] 230 Transformer Chip (Third Chip)

[0929] 230a First wiring layer (lower layer)

[0930] 230b Second wiring layer (upper layer)

[0931] Transformers 231 and 232

[0932] 231p, 232p primary side coils

[0933] 231s and 232s secondary coils

[0934] 300 Transformer Chip

[0935] 301 First Transformer

[0936] 302 Second Transformer

[0937] 303 Third Transformer

[0938] 304 Fourth Transformer

[0939] 305 First Protection Ring

[0940] 306 Second Protective Ring

[0941] 400 Signal Transmission Device

[0942] 400p primary circuit system

[0943] 400s secondary circuit system

[0944] 410 First Chip

[0945] 411 Switching Circuit

[0946] 420 Second Chip

[0947] 421 Drive Circuit

[0948] 422 Receiver Circuit

[0949] 423 Buffer

[0950] 430 Third Chip

[0951] 431, 432 Isolation Devices (Transformers)

[0952] 432P Non-phase Isolator (Transformer)

[0953] 432N Negative Phase Isolation Device (Transformer)

[0954] 431p, 432p, 432Pp, 432Np primary coils

[0955] 431s, 432s, 432Ps, 432Ns secondary coils; 433, 434 isolation devices (capacitors).

[0956] 433P and 434P positive phase isolation devices (capacitors)

[0957] 433N and 434N negative phase isolation devices (capacitors)

[0958] 500, 500a, 500b, 500c, 500d, 500e, 500f disconnect switches; 501, 501e, 501f conduction circuit.

[0959] 510, 510f First Isolation Device

[0960] 5101, 5102 First Isolation Devices

[0961] 511, 511f First Primary Coil

[0962] 5111, 5121 First Primary Coil

[0963] 512, 512f primary coil

[0964] 5112, 5122 primary coils

[0965] 513 diode

[0966] 5131 and 5132 diodes

[0967] 514 resistor

[0968] 5141 and 5142 resistors

[0969] 515 capacitor

[0970] 5151 and 5152 capacitors

[0971] 502, 502a, 502d, 502e adjustment circuits

[0972] 520 Second Isolation Device

[0973] 521 Second Primary Coil

[0974] 522, 522e Secondary Coil

[0975] 523 diode

[0976] 524, 524b First regulating switch device

[0977] 525 resistor

[0978] 5251 capacitor

[0979] 526 capacitor

[0980] 5261 and 5262 capacitors

[0981] 527 resistor

[0982] 528 Second regulating switch device

[0983] 503, 503F pulse supply circuit

[0984] 531 Pulse Generation Circuit

[0985] 532 Oscillator Circuit

[0986] 504, 504b, 504c switch units

[0987] 541, 541b switching devices

[0988] 5411 First Switching Device

[0989] 5412 Second Switching Device

[0990] 507 Adjustment Circuit

[0991] 571 Resistor

[0992] 600 disconnector switch

[0993] 610 First Chip

[0994] 611 Pulse Generation Circuit

[0995] 612 Oscillator Circuit

[0996] 613UVLO circuit

[0997] 620 Second Chip

[0998] 630, 630a, 630b Third chip (isolation circuit)

[0999] 631, 632, 633, 634 isolation devices

[1000] 631p, 632p, 633p, 634p primary coils

[1001] Secondary coils of 631s, 632s, 633s, and 634s

[1002] 640 Switching Circuit

[1003] 641 and 642 switching devices

[1004] 700 signal transmission device

[1005] 700p primary circuit system

[1006] 700s secondary circuit system

[1007] 710 First Chip

[1008] 711 Switching Circuit

[1009] 712 Reference Voltage Generation Circuit

[1010] 713 Rectifier Circuit

[1011] 720 Second Chip

[1012] 721 drive circuit

[1013] 722 Receiver Circuit

[1014] 723 Buffer

[1015] 724 Majority Voting Circuit

[1016] 725 Oscillator Circuit

[1017] 726 Power supply drive circuit

[1018] 730 Third Chip (Isolation Circuit)

[1019] Isolation devices (transformers) 731 to 736, 741 to 744

[1020] 732P and 734P positive phase isolation devices (transformers)

[1021] 732N, 734N negative phase isolation devices (transformers)

[1022] Primary coils 731p, 733p, 735p, 736p, 741p, 742p, 743p, 744p; secondary coils A1-A8 pads (corresponding to the first current feed pads)

[1023] pads b1-b8 (corresponding to the first voltage measurement pads)

[1024] C1-C4 pads (corresponding to the second current feed pads)

[1025] Pads d1-d4 (corresponding to the second voltage measurement pads)

[1026] e1, e2 pads

[1027] C11 to C18, C21 to C25 capacitors

[1028] CMP comparator

[1029] CONT control circuit

[1030] CP11, CP12, CP21 to CP24 boost circuits

[1031] D11 Zener diode

[1032] INV Inverter

[1033] L1p, L2p primary coils

[1034] L1, L2, L3, L4 secondary coils

[1035] Transistors n11 to n16 and n21 to n24 (npn bipolar transistors)

[1036] N11 to N14 transistors (N-channel MOS field-effect transistors)

[1037] PW isolated power supply circuit

[1038] Resistors R11 to R19, R1A, R21, and R22

[1039] Switching devices SW1 to SW14

[1040] T21, T22, T23, T24, T25, T26 external terminals

[1041] X First Direction

[1042] X21, X22, X23 internal terminals

[1043] Y second direction

[1044] Y21, Y22, Y23 wiring

[1045] Z-normal direction

[1046] Z21, Z22, Z23 through holes

[1047] Loads ZL, ZL1, and ZL2.

Claims

1. A disconnecting switch, comprising: A switching unit is configured to be controlled to cause the switching unit to enter an on / off state; A conduction circuit is configured to control the switching unit, causing the switching unit to enter the conduction state; The regulating circuit is configured to at least adjust the switching unit from the on state to the off state; as well as The pulse supply circuit is configured to... Receive control signals; as well as A pulse signal is provided to at least one of the conducting circuit and the regulating circuit. The conducting circuit includes a first isolation device, the first isolation device comprising: The first primary coil connected to the pulse supply circuit, and The first primary coil is electromagnetically coupled to the first primary coil. The conducting circuit is configured to use an induced current to put the switching unit into the conducting state, the induced current flowing in response to a rising pulse signal supplied to the first primary coil, and the regulating circuit includes: The second isolation device includes: The second primary coil is connected to the pulse supply circuit, and The second-stage coil, which is electromagnetically coupled to the second primary coil, and The regulating device is configured to regulate the switching unit to the non-conducting state by adjusting the voltage at the control terminal of the switching unit by regulating the induced current flowing through the secondary coil in response to the rise of the pulse signal. The pulse supply circuit is configured as follows: When the control signal is at a first level, the pulse signal is supplied to the first primary coil, and After the control signal switches from the first level to a second level different from the first level, the pulse signal is supplied to the second primary coil. The switching unit is configured to be turned on when the control signal is at the first level.

2. The disconnecting switch according to claim 1, wherein, The conducting circuit is configured such that a diode is disposed between the primary coil and the control terminal of the switching unit, such that the forward direction of the diode is the direction of flow of the induced current to be generated in the primary coil.

3. The disconnecting switch according to claim 1, wherein... The switching unit includes an n-channel MOS transistor. The conduction circuit is configured to allow the induced current to flow into the gate, and The regulating circuit is configured to allow current to be drawn out through the gate.

4. The disconnecting switch according to claim 1, wherein The switching unit includes a p-channel MOS transistor. The conduction circuit is configured to draw current through the gate via the induced current, and The regulating circuit is configured to supply the current to the gate.

5. The disconnecting switch according to claim 1, wherein... The switching unit has a configuration in which a first switching device and a second switching device are connected in series. Both the first switching device and the second switching device are one type of transistor, namely an n-channel MOS transistor and a p-channel MOS transistor. The first terminal of the primary coil in the conducting circuit is connected to the connection node where the gates of the first switching device and the second switching device are connected, and The second terminal of the primary coil in the conducting circuit is connected to the connection node where the sources of both the first and second switching devices are connected.

6. The disconnecting switch according to claim 1, wherein The regulating circuit includes a regulating switching device connected between the gate and source of the switching device forming the switching unit, and The regulating circuit is configured to activate the regulating switch using the induced current of the secondary coil.

7. The disconnecting switch according to claim 1, wherein... The regulating circuit is configured to assist in the operation of putting the switching unit into the conducting state through the conducting circuit when the control signal is at the first level. The pulse supply circuit is configured to supply the pulse signal to the second primary coil of the second isolation device when the control signal is at the first level.

8. The disconnecting switch according to claim 6, wherein The conduction circuit is configured to suppress the operation of the adjustment circuit to bring the switching unit into the non-conducting state when the control signal is at the first level, and The conducting circuit is configured to use the induced current of the primary coil to turn off the regulating switching device.

9. The disconnecting switch according to claim 1, wherein The disconnecting switch has the following configuration: The primary winding comprises multiple primary windings connected in series, and The first primary coil includes a plurality of first primary coils that are electromagnetically coupled to the plurality of first primary coils respectively.

10. The disconnecting switch according to claim 1, wherein The first-stage coil and the second-stage coil are connected in series, and The winding direction of the second-stage coil is opposite to that of the first-stage coil.

11. The disconnecting switch according to claim 1, wherein The first isolation device is configured to also function as the second isolation device.

12. The disconnecting switch according to claim 1, wherein The pulse supply circuit is configured to generate the pulse signal in a first cycle during a predetermined period after the time point when the control signal switches from the second level to the first level, and then generate the pulse signal in a second cycle that is longer than the first cycle.

13. The disconnecting switch according to claim 11, wherein The pulse supply circuit is Configured to supply the pulse signal to the first terminal of the first primary coil when the control signal is at the first level, and It is configured to not supply the pulse signal to the first primary coil when the control signal is at the second level.

14. The disconnecting switch according to claim 11, wherein The regulating circuit consists of a control terminal connected to the switching unit and a resistor connected to the ground potential.

15. The disconnecting switch according to claim 1, wherein The regulating circuit includes: The first regulating switch device connected in parallel with the primary coil, and The second regulating switch device is connected in parallel with the second stage coil. The regulating circuit has the following configuration: With the pulse signal already provided to the second primary coil, the first regulating switch is activated by the induced current induced by the second primary coil. When a pulse signal has been provided to the first primary coil, the second regulating switch is turned on and the first regulating switch is turned off in response to the induced current induced by the first primary coil.

16. The disconnecting switch according to claim 1, wherein The conduction circuit includes a multi-stage boost circuit connected in series between the primary coil and the control terminal of the switching unit. The odd-numbered stages of the multi-stage boost circuit include: A first diode is connected between the primary winding and the control terminal of the switching unit, such that the forward direction of the first diode is the direction of flow of the induced current to be generated in the primary winding. A first capacitor is connected between the cathode of the first diode and the second stage coil. The even-numbered stages of the multi-stage boost circuit include: A second diode is connected between the primary winding and the control terminal of the switching unit, such that the forward direction of the second diode is the direction of flow of the induced current to be generated in the primary winding. A second capacitor is connected between the cathode of the second diode and the primary winding.

17. The disconnecting switch according to claim 1, wherein The regulating circuit includes: The first regulating switch device is connected in parallel with the primary coil. The first transistor is connected between the second stage coil and the control terminal of the first regulating switch device. A first capacitor is connected between the first main electrode of the first transistor and the control terminal, and A first resistor is connected between the second main electrode of the first transistor and the control terminal.

18. The disconnecting switch according to claim 17, wherein The regulating circuit includes: The second regulating switch is connected in parallel with the second stage coil. The second transistor is connected between the primary coil and the control terminal of the second regulating switch. A second capacitor is connected between the first main electrode of the second transistor and the control terminal, and A second resistor is connected between the second main electrode of the second transistor and the control terminal.

19. The disconnecting switch according to claim 1, wherein The first primary coil and the second primary coil are connected in series, and The winding direction of the first primary coil and the winding direction of the second primary coil are opposite to each other.

20. The disconnecting switch according to claim 1, further comprising: The third isolation device includes: The third primary coil is connected in series with the first primary coil, and The third-stage coil, which is electromagnetically coupled to the third primary coil; and The fourth isolation device includes: The fourth primary coil, which is connected in series with the second-stage coil, and The fourth secondary coil is electromagnetically coupled to the fourth primary coil, wherein, The switching unit is controlled by the induced current flowing through the third secondary coil and the fourth secondary coil, respectively.

21. A sequencer comprising an isolating switch according to any one of claims 1 to 20.

Images