Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device having good electrical characteristics. The semiconductor device includes: a first conductive layer; a first insulating layer on the first conductive layer; a second conductive layer on the first insulating layer; a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer; a third insulating layer and a semiconductor layer on the first conductive layer; a fourth insulating layer on the semiconductor layer; and a fourth conductive layer on the fourth insulating layer. The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are provided with a first opening portion reaching the first conductive layer. The third insulating layer has a second opening in a region overlapping the first opening, and is in contact with a side surface of the second conductive layer and a side surface of the third conductive layer. The semiconductor layer is in contact with a top surface of the first conductive layer and a top surface of the third conductive layer through the second opening. The fourth conductive layer has a region facing the second conductive layer with the fourth insulating layer, the semiconductor layer, and the third insulating layer interposed therebetween.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a storage device, a display device, and an electronic device. Furthermore, another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving or manufacturing methods for the aforementioned devices.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as semiconductor elements (transistors, diodes, photodiodes, etc.), circuits including semiconductor elements, and devices having circuits including semiconductor elements. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips incorporating integrated circuits, and electronic components containing chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes include semiconductor devices. Background Technology

[0004] In recent years, semiconductor devices have been developed, with LSI (Large Scale Integration), CPU (Central Processing Unit), and memory being the main components used in semiconductor devices. A CPU is an assembly of semiconductor elements that include integrated circuits (at least transistors and capacitors) fabricated from semiconductor wafers and having electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards, and are used as components of various electronic devices.

[0006] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as suitable semiconductor thin films for transistors. Among other materials, oxide semiconductors have garnered attention.

[0007] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely small in the off state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Additionally, for example, Patent Document 2 discloses a storage device that utilizes the characteristic of low leakage current of transistors using oxide semiconductors to achieve long-term retention of stored content.

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which multiple memory cells are stacked in an overlapping manner by layering a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of integrated circuits. Furthermore, Patent Document 4 discloses a technique for achieving high-density integrated circuits by arranging the channels of transistors using oxide semiconductor films longitudinally. [Preliminary Technology Documents] [Patent Literature]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Publication No. 2013-211537 [Non-patent literature]

[0010] [Non-Patent Literature 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech.Dig., 2019, pp.50-53 Summary of the Invention The technical problem that the invention aims to solve

[0011] One objective of this invention is to provide a transistor with excellent electrical characteristics. Furthermore, one objective of this invention is to provide a transistor with a large on-state current. Furthermore, one objective of this invention is to provide a transistor with low parasitic capacitance. Furthermore, one objective of this invention is to provide a transistor, semiconductor device, or memory device capable of miniaturization or high integration. Furthermore, one objective of this invention is to provide a display device with high definition or high aperture ratio. Furthermore, one objective of this invention is to provide a transistor, semiconductor device, display device, or memory device with high reliability. Furthermore, one objective of this invention is to provide a semiconductor device, display device, or memory device with low power consumption. Furthermore, one objective of this invention is to provide a memory device with high operating speed. Furthermore, one objective of this invention is to provide a method for manufacturing the aforementioned transistor, semiconductor device, display device, or memory device.

[0012] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims. means of solving technical problems

[0013] One aspect of the present invention is a semiconductor device comprising: a first conductive layer; a first insulating layer on the first conductive layer; a second conductive layer on the first insulating layer; a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer; a third insulating layer on the first conductive layer and a semiconductor layer; a fourth insulating layer on the semiconductor layer; and a fourth conductive layer on the fourth insulating layer. A first opening is provided in each of the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer, extending to the first conductive layer. The third insulating layer has a second opening in a region overlapping with the first opening. The third insulating layer has a region contacting a side surface of the second conductive layer and a region contacting a side surface of the third conductive layer. The semiconductor layer has a region contacting the top surface of the first conductive layer through the second opening and a region contacting the top surface of the third conductive layer. The fourth conductive layer has a region opposite to the second conductive layer, separated by the fourth insulating layer, the semiconductor layer, and the third insulating layer. In cross-section, the width of the second opening is less than the value obtained by subtracting twice the thickness of the third insulating layer from the width of the first opening.

[0014] In the aforementioned semiconductor device, the depth of the second opening is preferably the same as the thickness of the third insulating layer.

[0015] In the above-described semiconductor device, the side end of the semiconductor layer preferably coincides with the side end of the third conductive layer.

[0016] In the above-described semiconductor device, the angle between the extension direction of the second conductive layer and the extension direction of the fourth conductive layer is preferably 45 degrees.

[0017] One aspect of the present invention is a semiconductor device comprising: a first conductive layer; a second conductive layer on the first conductive layer; a first insulating layer on the first conductive layer and the second conductive layer; a third conductive layer on the first insulating layer; a second insulating layer on the third conductive layer; a fourth conductive layer on the second insulating layer; a third insulating layer on the second conductive layer and a semiconductor layer; a fourth insulating layer on the semiconductor layer; and a fifth conductive layer on the fourth insulating layer. A first opening extending to the first conductive layer is provided in the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer. The third insulating layer has a second opening in a region overlapping with the first opening. The third insulating layer has a region contacting a side surface of the third conductive layer and a region contacting a side surface of the fourth conductive layer. The semiconductor layer has a region contacting the top surface of the second conductive layer through the second opening and a region contacting the top surface of the fourth conductive layer. The fifth conductive layer has a region opposite to the third conductive layer, separated by the fourth insulating layer, the semiconductor layer, and the third insulating layer. In cross-section, the width of the fifth conductive layer is greater than the width of the second opening and less than the width of the first opening.

[0018] In the above-described semiconductor device, the side end of the semiconductor layer preferably coincides with the side end of the fourth conductive layer.

[0019] In the above-mentioned semiconductor device, the angle between the extension direction of the third conductive layer and the extension direction of the fifth conductive layer is preferably 45 degrees.

[0020] In the aforementioned semiconductor device, the semiconductor layer preferably comprises one or both of indium and zinc.

[0021] In the above-described semiconductor device, preferably, both the first insulating layer and the second insulating layer include a first layer, a second layer and a third layer located between the first layer and the second layer, both the first layer and the third layer contain silicon and nitrogen, and the relative permittivity of the second layer is lower than that of the first layer.

[0022] In the above-described semiconductor device, it is preferable that the second layer has a region that is thicker than the first layer, and that the second layer has a region that is thicker than the third layer.

[0023] One aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a second insulating layer on the second conductive layer; forming a third conductive layer on the second insulating layer; forming an opening reaching the first conductive layer by processing the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer; forming a third insulating layer that contacts the sidewalls and bottom of the opening; forming a layer on the third insulating layer; exposing the top surface of the first conductive layer in the region overlapping with the opening by processing the third insulating layer and the layer; removing the layer; forming a semiconductor layer on the first conductive layer, the third insulating layer, and the third conductive layer; forming a fourth insulating layer on the semiconductor layer; and forming a fourth conductive layer on the fourth insulating layer.

[0024] In the above-mentioned semiconductor device manufacturing method, it is preferable to use anisotropic etching to process the third insulating layer and the layer.

[0025] In the above-described method for manufacturing semiconductor devices, isotropic etching is preferably used to remove the layer. Invention Effects

[0026] According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a transistor with a large on-state current can be provided. Furthermore, according to one aspect of the present invention, a transistor with low parasitic capacitance can be provided. Furthermore, according to one aspect of the present invention, a transistor, semiconductor device, or memory device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a display device with high definition or high aperture ratio can be provided. Furthermore, according to one aspect of the present invention, a transistor, semiconductor device, display device, or memory device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device, display device, or memory device with low power consumption can be provided. Furthermore, according to one aspect of the present invention, a memory device with high operating speed can be provided. Furthermore, according to one aspect of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, display device, or memory device can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims. Brief description of the attached figures

[0028] Figure 1A This is a plan view showing an example of a semiconductor device. Figure 1B and Figure 1C This is a cross-sectional view showing an example of a semiconductor device. Figure 2A and Figure 2B This is a cross-sectional view showing an example of a semiconductor device. Figure 3A This is a plan view showing an example of a semiconductor device. Figure 3B and Figure 3C This is a cross-sectional view showing an example of a semiconductor device. Figures 4A to 4F This is a cross-sectional view showing an example of a semiconductor device. Figures 5A to 5D This is a cross-sectional view showing an example of a semiconductor device. Figure 6A This is a plan view showing an example of a semiconductor device. Figure 6B and Figure 6C This is a cross-sectional view showing an example of a semiconductor device. Figure 7A and Figure 7B This is a cross-sectional view showing an example of a semiconductor device. Figure 8A and Figure 8B This is a cross-sectional view showing an example of a semiconductor device. Figure 9A and Figure 9B This is a cross-sectional view showing an example of a semiconductor device. Figure 10A and Figure 10B This is a cross-sectional view showing an example of a semiconductor device. Figure 11A This is a plan view showing an example of a semiconductor device. Figure 11B and Figure 11C This is a cross-sectional view showing an example of a semiconductor device. Figures 12A to 12F This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 13A to 13F This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 14A to 14F This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 15A This is a floor plan showing an example of a storage device. Figure 15B and Figure 15C This is a cross-sectional view showing an example of a storage device. Figure 16A This is a floor plan showing an example of a storage device. Figure 16B This is a cross-sectional view showing an example of a storage device. Figure 17A and Figure 17B It is a layout diagram illustrating the storage device. Figure 18 It is a layout diagram illustrating the storage device. Figure 19 This is a cross-sectional view showing an example of a storage device. Figure 20 This is a cross-sectional view showing an example of a storage device. Figure 21 This is a block diagram illustrating an example of the structure of a semiconductor device. Figures 22A to 22H This is a diagram illustrating an example of the circuit structure of a memory cell. Figure 23A and Figure 23B This is a three-dimensional diagram illustrating an example of the structure of a semiconductor device. Figure 24 This is a block diagram illustrating the CPU. Figure 25A and Figure 25B It is a 3D diagram of a semiconductor device. Figure 26A and Figure 26B It is a 3D diagram of a semiconductor device. Figure 27A and Figure 27B It is a diagram showing the hierarchy of various storage devices. Figure 28A and Figure 28B This is a perspective view showing an example of a display device. Figure 29 This is a cross-sectional view showing an example of a display device. Figure 30 This is a cross-sectional view showing an example of a display device. Figures 31A to 31C This is a diagram showing an example of the structure of a display device. Figure 32A and Figure 32B This is a diagram showing an example of an electronic component. Figures 33A to 33C This is a diagram illustrating an example of a large computer. Figure 33D This is a diagram illustrating an example of a space device. Figure 33E This is a diagram illustrating an example of a secondary storage system that can be used in a data center. Figures 34A to 34F This is a diagram illustrating an example of an electronic device. Figures 35A to 35G This is a diagram illustrating an example of an electronic device. Figures 36A to 36F This is a diagram illustrating an example of an electronic device. Methods of implementing the invention

[0029] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0030] Note that in the invention structure described below, the same symbols are used in different figures to show the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when parts with the same function are indicated, the same shading lines are sometimes used without additional symbols.

[0031] For ease of understanding, the positions, sizes, and extents of the constituent elements shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0032] Note that, for convenience, ordinal numbers such as "first" and "second" are used in this specification, etc., but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, the ordinal numbers used for constituent elements in one part of this specification may sometimes differ from those used for the same constituent element in other parts of this specification or in the claims.

[0033] A transistor is a type of semiconductor device that can amplify current or voltage and control switching operations, such as turning on or off. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0034] In this specification and other materials, transistors that use oxide semiconductors or metal oxides as semiconductor layers and transistors that include oxide semiconductors or metal oxides in the channel formation region are sometimes referred to as OS transistors. Furthermore, transistors that include silicon in the channel formation region are sometimes referred to as Si transistors.

[0035] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (also called a channel-forming region) between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode) that forms a channel, through which current can flow between the source and drain. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0036] Furthermore, in cases where transistors of different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0037] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration below 0.1 atomic% can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity in the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water sometimes also acts as an impurity. Furthermore, the incorporation of impurities can sometimes lead to oxygen vacancies (also referred to as V) in the oxide semiconductor. O The formation of ).

[0038] Note that in this specification, oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content.

[0039] For example, the content of elements such as hydrogen, oxygen, carbon, and nitrogen in the membrane can be analyzed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less or 1 atomic% or less). When comparing elemental contents, it is more preferable to use a combined analysis of SIMS and XPS.

[0040] Furthermore, depending on the situation or state, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be changed into a "conductive film." Similarly, an "insulating film" can be changed into an "insulating layer."

[0041] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10 degrees and less than 10 degrees. Therefore, it also includes states where the angle is greater than or equal to -5 degrees and less than 5 degrees. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -30 degrees and less than 30 degrees. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 80 degrees and less than 100 degrees. Therefore, it also includes states where the angle is greater than or equal to 85 degrees and less than 95 degrees. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 60 degrees and less than 120 degrees.

[0042] In this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, and other elements with various functions.

[0043] Furthermore, in this specification and other materials, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and source. gs Below the threshold voltage V th (V in p-channel transistor) gs Higher than V th ) state.

[0044] In this specification, normally-on characteristic refers to the state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate. Normally-off characteristic refers to the state in which no current flows through the transistor when no voltage is applied to the gate or when the gate is supplied with a ground potential.

[0045] In this specification and the like, the top surface shape of a constituent element refers to the edge shape of the constituent element when viewed from above. Furthermore, "viewing from above" refers to the view taken from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0046] In this specification, "generally consistent top surface shape" means that at least a portion of the edges of each layer in a stack overlaps. This includes, for example, cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, strictly speaking, sometimes the edges do not overlap and the upper layer is located inside or outside the lower layer; these cases can also be described as having "generally consistent top surface shape." When the top surface shape is consistent or generally consistent, it can also be said that the positions are consistent or generally consistent when viewed from above, the ends are aligned or generally aligned, or the side ends are consistent or generally consistent.

[0047] In this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region where the angle (also referred to as the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Here, the side surface of the constituent element, the substrate surface, and the surface to be formed do not necessarily have to be completely flat; they may also be approximately planar with slight curvature or approximately planar with slight irregularities.

[0048] In this specification and the like, when it is stated that "A is in contact with B", at least a portion of A is in contact with B. Therefore, for example, it can be said that A includes the area in contact with B.

[0049] In this specification, etc., when it is stated that "A is located on B", at least a portion of A is located on B. Therefore, for example, it can be said that A includes the area located on B.

[0050] In this specification and the like, when it is stated that "A covers B", at least a portion of A covers B. Therefore, for example, it can be said that A includes the area that covers B.

[0051] In this specification and the like, when it is stated that "A overlaps with B", at least a portion of A overlaps with B. Therefore, for example, it can be said that A includes the region that overlaps with B.

[0052] In this specification, devices manufactured using a metal mask or FMM (Fine Metal Mask) are sometimes referred to as devices with an MM (Metal Mask) structure. Furthermore, devices manufactured without a metal mask or FMM are sometimes referred to as devices with an MML (Metal Mask Less) structure.

[0053] In this specification and other materials, the structure in which light-emitting elements (also called light-emitting devices) with different emission wavelengths are separately fabricated is sometimes referred to as an SBS (Side By Side) structure. Because the SBS structure allows for optimization of materials and structure for each light-emitting element, the freedom of material and structure selection is increased, making it easier to achieve improvements in brightness and reliability.

[0054] In this specification and other materials, holes or electrons are sometimes referred to as "carriers." Specifically, a hole injection layer or electron injection layer is sometimes referred to as a "carrier injection layer," a hole transport layer or electron transport layer as a "carrier transport layer," and a hole blocking layer or electron blocking layer as a "carrier blocking layer." Note that the above distinctions between carrier injection layer, carrier transport layer, and carrier blocking layer are sometimes unclear. Furthermore, sometimes a single layer functions as two or three of the following: a carrier injection layer, a carrier transport layer, and a carrier blocking layer.

[0055] In this specification, the light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Examples of layers included in the EL layer (also referred to as functional layers) include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification, the light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes. In this specification, sometimes one of the pairs of electrodes is referred to as a pixel electrode, and the other as a common electrode.

[0056] In this specification, the sacrificial layer (also known as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape in the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0057] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is disconnected due to the shape of the surface to which it is formed (e.g., a step).

[0058] Note that arrows indicating the X, Y, and Z directions are sometimes included in the accompanying drawings and other materials of this specification. Note that in this specification, "X direction" refers to the direction along the X-axis, and unless explicitly stated otherwise, its direction (clockwise or counterclockwise) is not always distinguished. The same applies to "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are intersecting directions. For example, the X, Y, and Z directions are orthogonal to each other.

[0059] (Implementation Method 1) In this embodiment, refer to Figures 1A to 14F A semiconductor device according to one aspect of the present invention is described.

[0060] One aspect of the semiconductor device of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer.

[0061] A first insulating layer is located on a first conductive layer, a second conductive layer is located on a first insulating layer, a second insulating layer is located on a second conductive layer, and a third conductive layer is located on a second insulating layer. The first insulating layer, the second conductive layer, the third insulating layer, and the third conductive layer each have an opening reaching the first conductive layer. The third insulating layer has a protrusion in the opening that contacts the top surface of the first conductive layer, a region that contacts the side surface of the second conductive layer, and a region that contacts the side surface of the third conductive layer. The semiconductor layer has a region in the opening that contacts the top surface of the first conductive layer and a region that contacts the top surface and side surface of the protrusion in the third insulating layer. A fourth insulating layer is located on the semiconductor layer in the opening. The fourth conductive layer has a region in the opening that is opposite to the second conductive layer, separated by the fourth insulating layer, the semiconductor layer, and the third insulating layer.

[0062] The first conductive layer is used as one of the source and drain electrodes of the transistor. The third conductive layer is used as the other of the source and drain electrodes of the transistor. The fourth conductive layer is used as the first gate electrode of the transistor, and the fourth insulating layer is used as the first gate insulating layer of the transistor. The second conductive layer is used as the second gate electrode of the transistor, and the third insulating layer is used as the second gate insulating layer of the transistor.

[0063] One aspect of the semiconductor device of the present invention includes a fourth conductive layer serving as a first gate electrode and a second conductive layer serving as a second gate electrode. The threshold voltage V of the transistor can be controlled by independently changing the potential applied to the second conductive layer without linking it to the potential applied to the fourth conductive layer. th In particular, by applying a negative potential to the second conductive layer, the Vt of the transistor can be further increased. th This reduces the off-state current. Therefore, compared to not applying a negative potential to the second conductive layer, applying a negative potential to the second conductive layer can reduce the drain current when the potential applied to the fourth conductive layer is 0V. Furthermore, the fourth conductive layer can be used as the second gate electrode, and the second conductive layer can be used as the first gate electrode.

[0064] Alternatively, the second conductive layer can be connected to the fourth conductive layer. By connecting the second and fourth conductive layers and applying the same potential to them, the on-state current can be increased, the initial characteristic deviation can be reduced, the electrical characteristic degradation under negative GBT (Gate Bias-Temperature) stress testing can be suppressed, and the rise voltage variation of the on-state current under different drain voltages can be suppressed.

[0065] As described above, one aspect of the semiconductor device of the present invention includes a first gate electrode and a second gate electrode, thereby improving the electrical characteristics of the transistors included in the semiconductor device.

[0066] In one embodiment of the present invention, the source and drain electrodes of the transistor are located at different heights, so the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction has a height (vertical) component; therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical-channel transistor, etc.

[0067] Because the source electrode, semiconductor layer, and drain electrode can be stacked, the area occupied by a transistor of one aspect of the present invention can be much smaller than that of a so-called planar transistor in which the semiconductor layer is configured as a planar shape.

[0068] <Example 1 of semiconductor device structure> Reference Figures 1A to 8B The structure of a semiconductor device according to one aspect of the present invention is described. Figure 1A This is a plan view of a semiconductor device including transistor 200A. Figure 1B It is along Figure 1A The cross-sectional view of the dotted line A1-A2 shown. Figure 1C It is along Figure 1A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 1A In the plan view, some constituent elements are omitted for clarity. Sometimes, some constituent elements are also omitted in the plan view shown below.

[0069] Figures 1A to 8B The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200A on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 281 on the insulating layer 280, and an insulating layer 283 on the transistor 200A. The insulating layers 210, 280, 281, and 283 are used as interlayer films.

[0070] Transistor 200A includes a conductive layer 220, a conductive layer 215 on an insulating layer 280, a conductive layer 240 on an insulating layer 281, an insulating layer 225 on a conductive layer 220, a semiconductor layer 230, an insulating layer 250 on a semiconductor layer 230, and a conductive layer 260 on an insulating layer 250.

[0071] like Figure 1B and Figure 1CAs shown, the insulating layer 280, conductive layer 215, insulating layer 281, and conductive layer 240 are provided with openings 290 that reach the conductive layer 220. Here, the bottom of the opening 290 is the top surface of the conductive layer 220, and the sidewalls of the opening 290 are the sidewalls of the insulating layer 280, the conductive layer 215, the insulating layer 281, and the conductive layer 240. The opening 290 includes the openings of the insulating layer 280, the conductive layer 215, the insulating layer 281, and the conductive layer 240. In other words, the opening in the region where the insulating layer 280 overlaps with the conductive layer 220 is part of the opening 290, the opening in the region where the conductive layer 215 overlaps with the conductive layer 220 is another part of the opening 290, the opening in the region where the insulating layer 281 overlaps with the conductive layer 220 is another part of the opening 290, and the opening in the region where the conductive layer 240 overlaps with the conductive layer 220 is another part of the opening 290.

[0072] At least a portion of the constituent elements of transistor 200A are disposed within opening 290. Specifically, at least a portion of each of insulating layer 225, semiconductor layer 230, insulating layer 250, and conductive layer 260 is disposed within opening 290. Furthermore, the portions of insulating layer 225, semiconductor layer 230, and insulating layer 250 disposed within opening 290 reflect the shape of opening 290. Specifically, insulating layer 225 is disposed to cover a portion of the bottom and sidewalls of opening 290, semiconductor layer 230 is disposed to cover another portion of the bottom of opening 290 and insulating layer 225, and insulating layer 250 is disposed to cover semiconductor layer 230. Furthermore, conductive layer 260 is disposed to be embedded in a recess of insulating layer 250 that reflects the shape of opening 290.

[0073] The insulating layer 225 contacts a portion of the top surface of the conductive layer 220, the side surface of the insulating layer 280, the side surface of the conductive layer 215, the side surface of the insulating layer 281, and the side surface of the conductive layer 240 in the opening 290.

[0074] Figure 2A yes Figure 1B An enlarged view of the area P enclosed by the dotted line. The insulating layer 225 has an opening 192 in the area overlapping with the opening 290. Figure 2A In the diagram, double-headed arrows with double dots represent the width D of opening 290, the width D192 of opening 192, and the width W225 of insulating layer 225, which corresponds to the shortest distance between the surface of insulating layer 225 in contact with conductive layer 215 and the surface in contact with semiconductor layer 230. Note that in this specification, the width W225 is sometimes referred to as the thickness of insulating layer 225. In this case, as... Figure 2AAs shown, the width D192 of the opening 192 is less than the value obtained by subtracting twice the width W225 from the width D of the opening 290 (“D-2×W225”). In other words, the insulating layer 225 has a protrusion 225p in the opening 290. The protrusion 225p contacts the top surface of the conductive layer 220. Figure 2A In the diagram, the double-headed arrow with double dots and dashes represents the width W225p corresponding to the width of the protrusion 225p in the cross-section. At this time, the width D192 of the opening 192 can be calculated as "D-2×W225-2×W225p".

[0075] In addition, Figure 2A In the diagram, a double-headed arrow with double dots indicates the height H225p, which corresponds to the height of the protrusion 225p in the cross-section. Note that the height H225p is also the depth of the opening 192. For example, when forming the insulating layer 225 using atomic layer deposition (ALD), the ALD method has excellent thickness uniformity, so the height H225p is the same as or approximately the same as the width W225.

[0076] The width W225p is preferably small. For example, the width W225p is preferably the same as or smaller than the width W225. By reducing the width W225p, the contact area between the semiconductor layer 230 and the conductive layer 220 can be increased. This improves the on-state current of the transistor 200A and achieves good electrical characteristics. Therefore, a high-speed semiconductor device can be realized. Alternatively, the semiconductor device can also adopt a structure where the width W225p is larger than the width W225.

[0077] Semiconductor layer 230 contacts the top surface of conductive layer 220 through opening 192. Semiconductor layer 230 contacts the top and side surfaces of protrusions 225p of insulating layer 225 and the side surfaces of insulating layer 225 in opening 290. Semiconductor layer 230 contacts the top surface of conductive layer 240.

[0078] In transistor 200A, semiconductor layer 230 is used as semiconductor layer, conductive layer 260 is used as first gate electrode, insulating layer 250 is used as first gate insulating layer, conductive layer 215 is used as second gate electrode, insulating layer 225 is used as second gate insulating layer, conductive layer 220 is used as one of source electrode and drain electrode, and conductive layer 240 is used as the other of source electrode and drain electrode.

[0079] As described above, at least a portion of the semiconductor layer 230 is disposed within the opening 290. Furthermore, in the transistor 200A, one of the source and drain electrodes (in this conductive layer 220) is below and the other of the source and drain electrodes (in this conductive layer 240) is above, thus the transistor 200A has a structure in which current flows in the vertical direction. That is, a channel is formed along the sidewall of the opening 290.

[0080] The sidewalls of the opening 290 are preferably perpendicular to the top surface of the insulating layer 210. This structure enables miniaturization or high integration of the semiconductor device. In this case, the films disposed inside the opening 290 are preferably formed using the ALD method. The ALD method deposits atoms layer by layer, resulting in advantages such as the ability to deposit very thin films, deposit structures with high aspect ratios, deposit with fewer defects such as pinholes, achieve high coverage, and deposit at low temperatures. Therefore, the film can be deposited with high coverage on the sidewalls of the opening 290. For example, the insulating layer 225, semiconductor layer 230, insulating layer 250, and conductive layer 260 are all preferably formed using the ALD method.

[0081] like Figure 1B and Figure 1C As shown, the insulating layer 250 is disposed in contact with the top surface of the semiconductor layer 230. Furthermore, a portion of the insulating layer 250 is located outside the opening 290, i.e., on the conductive layer 240 and the insulating layer 281. Outside the opening 290, the insulating layer 250 has a region that contacts the side surface of the semiconductor layer 230, a region that contacts the side surface of the conductive layer 240, and a region that contacts the top surface of the insulating layer 281. In this case, the insulating layer 250 preferably covers the end of the semiconductor layer 230. This prevents a short circuit between the conductive layer 260 and the semiconductor layer 230. Furthermore, the insulating layer 250 preferably covers the end of the conductive layer 240. This prevents a short circuit between the conductive layer 260 and the conductive layer 240. Additionally, it reduces the parasitic capacitance generated between the conductive layers 260 and 240.

[0082] The conductive layer 240 is preferably not disposed in the opening of the insulating layer 281. That is, the conductive layer 240 preferably does not have a region that contacts the side surface of the insulating layer 281 in the opening 290. By adopting this structure, both the opening of the conductive layer 240 and the opening of the insulating layer 281 can be formed simultaneously. Furthermore, by aligning the side surface of the conductive layer 240 in the opening 290 with the side surface of the insulating layer 280 in the opening 290, the thickness distribution of the insulating layer 225, semiconductor layer 230, etc., disposed in the opening 290 can be made uniform. Moreover, it can prevent the insulating layer 225, semiconductor layer 230, etc., from separating due to the step between the conductive layer 240 and the insulating layer 281.

[0083] Although Figure 1B and Figure 1C The diagram shows a structure where the side surface of the conductive layer 240 in the opening 290 is aligned with the side surface of the insulating layer 281 in the opening 290, but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 281 in the opening 290 may be discontinuous. Furthermore, the inclination angles of the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 281 in the opening 290 may differ from each other. In this case, for example, the angle formed by the side surface of the conductive layer 240 in the opening 290 and the top surface of the insulating layer 210 is preferably smaller than the angle formed by the side surface of the insulating layer 281 in the opening 290 and the top surface of the insulating layer 210. By adopting this structure, the coverage of the side surface of the conductive layer 240 within the opening 290 by the insulating layer 225, semiconductor layer 230, etc., is improved, thereby reducing defects such as voids.

[0084] Transistor 200A preferably contains a metal oxide (also called an oxide semiconductor) serving as a semiconductor in the semiconductor layer 230 having a channel formation region. In this case, transistor 200A can be considered an OS transistor. Furthermore, the semiconductor layer containing the oxide semiconductor is sometimes referred to as an oxide semiconductor layer.

[0085] In an OS transistor, when oxygen vacancies (V0) exist in the channel formation region of the oxide semiconductor... O When impurities such as Oxygen Vacancy are present, the electrical properties are easily altered, potentially reducing reliability. Furthermore, hydrogen entering defects in oxygen vacancies (sometimes referred to below as Vacancy defects) can also affect reliability. O H) may generate electrons that become charge carriers. Therefore, when the channel formation region in an oxide semiconductor contains oxygen vacancies, the OS transistor tends to have always-on characteristics. Thus, it is preferable to minimize oxygen vacancies and impurities in the channel formation region of an oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region of the oxide semiconductor is reduced and is i-typed (intrinsicized) or substantially i-typed.

[0086] On the other hand, the source and drain regions of the OS transistor are preferably the following regions: due to the higher oxygen vacancy rate compared to the channel formation region, V... O High concentrations of impurities such as hydrogen, nitrogen, and metal elements increase carrier concentration, thus reducing resistance. In other words, compared to the channel formation region, the source and drain regions of an OS transistor are preferably n-type regions with high carrier concentration and low resistance.

[0087] The conductive layer 260 has a region sandwiching the insulating layer 250, the semiconductor layer 230, and the insulating layer 225 opposite to the conductive layer 215. The region of the semiconductor layer 230 sandwiched between the conductive layers 260 and 215, and its vicinity, is used as the channel formation region of the transistor 200A. One of the regions of the semiconductor layer 230 that contact the conductive layer 220 and the region of the semiconductor layer 230 that contact the conductive layer 240 is used as the source region, and the other is used as the drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0088] When the semiconductor layer 230 contacts the conductive layer 220, metal compounds or oxygen vacancies are formed, reducing the resistance of the region of the semiconductor layer 230 in contact with the conductive layer 220. This reduces the contact resistance between the semiconductor layer 230 and the conductive layer 220. Similarly, when the semiconductor layer 230 contacts the conductive layer 240, the region of the semiconductor layer 230 in contact with the conductive layer 240 also reduces the resistance. This reduces the contact resistance between the semiconductor layer 230 and the conductive layer 240.

[0089] Here, Figure 2B It is along Figure 2A The cross-sectional view shown is the dotted-dash line A5-A6. Figure 2B It can also be described as a cross-sectional view of the XY plane including conductive layer 260 and conductive layer 215. For example... Figure 2B As shown, insulating layer 250 contacts the entire inner periphery of semiconductor layer 230. Additionally, insulating layer 225 contacts the entire outer periphery of semiconductor layer 230. Therefore, the channel formation region of transistor 200A may be formed either on the entire inner periphery of the portion of semiconductor layer 230 formed in the same layer as insulating layer 250, or on the entire outer periphery of the portion formed in the same layer as insulating layer 225. Furthermore, Figure 2B It can also be described as a cross-sectional view of the XY plane including the channel formation region of semiconductor layer 230.

[0090] When the conductive layer 260 is used as the first gate electrode, in cross-section, the channel length of the transistor 200A is the length of the region of the semiconductor layer 230 that overlaps with the conductive layer 260 across the insulating layer 250. That is, the channel length of the transistor 200A can be determined based on the thickness of the insulating layer 280 on the conductive layer 220, the thickness of the conductive layer 215, the thickness of the insulating layer 281, the depth of the opening 290, the thickness of the semiconductor layer 230, and the thickness of the insulating layer 250, etc. Figure 2A In the diagram, the channel length L of transistor 200A is represented by a dashed double arrow.

[0091] When the conductive layer 215 is used as the first gate electrode, the channel length of the transistor 200A in cross-section is the length of the region of the semiconductor layer 230 that overlaps with the conductive layer 215 across the insulating layer 225. In other words, the channel length of the transistor 200A is determined by the thickness of the conductive layer 215. Furthermore, when the conductive layer 260 and the conductive layer 215 are connected, the channel length of the transistor 200A in cross-section is the length of the region of the semiconductor layer 230 sandwiched between the conductive layer 260 and the conductive layer 215. In other words, the channel length of the transistor 200A is determined by the thickness of the conductive layer 215.

[0092] In planar transistors, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. However, in this invention, the channel length can be set according to the thickness of the insulating layers 280 and 281 or the thickness of the conductive layer 215. Therefore, the channel length of transistor 200A can be set to a very fine structure below the exposure limit of photolithography (e.g., below 60nm, 50nm, 40nm, 30nm, 20nm, or below 10nm and above 0.1nm, 1nm, or 5nm). Consequently, the on-state current of transistor 200A increases, thereby improving frequency characteristics.

[0093] Furthermore, as described above, a channel forming region, a source region, and a drain region can be formed within the opening 290. Therefore, compared to a lateral transistor where the channel forming region, source region, and drain region are respectively provided on the XY plane, the occupied area of ​​the transistor 200A can be reduced. This allows for high integration of the semiconductor device. Moreover, when the semiconductor device according to one aspect of the present invention is used in a memory device, the storage capacity per unit area can be increased.

[0094] In addition, such as Figure 2B As shown, the insulating layer 225, semiconductor layer 230, insulating layer 250, and conductive layer 260 are arranged in a concentric circle. Therefore, the side of the conductive layer 260 located at the center faces the side of the semiconductor layer 230 across the insulating layer 250. Furthermore, the side of the conductive layer 215 in the opening 290 faces the side of the semiconductor layer 230 across the insulating layer 225. In other words, when viewed from above, the entire edge of the semiconductor layer 230 forms the channel formation region. At this time, for example, the channel width of the transistor 200A is determined by the length of the inner circumference of the semiconductor layer 230 or the length of the edge of the semiconductor layer 230. That is to say, the channel width of the transistor 200A is determined by the width of the opening 290 (the diameter if the opening 290 is circular when viewed from above) and the thickness of the insulating layer 225. Figure 2A and Figure 2B In the diagram, a double-headed arrow with a double-dotted line indicates the width D of the opening 290. Figure 2B In the diagram, the channel width W of transistor 200A is indicated by a double-headed dotted arrow. By increasing the width D of the opening 290, the channel width per unit area can be increased, thereby increasing the on-state current. Furthermore, by decreasing the thickness (width W225) of the insulating layer 225, the channel width per unit area can be increased, thereby increasing the on-state current.

[0095] When forming the opening 290 using photolithography, the width D of the opening 290 is limited by the exposure limit of the photolithography. Furthermore, the width D of the opening 290 is set according to the thickness of each of the insulating layer 225, semiconductor layer 230, insulating layer 250, and conductive layer 260 disposed in the opening 290. For example, the width D of the opening 290 can be 5 nm or more, 10 nm or more, or 20 nm or more and 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in top view, the width D of the opening 290 is equivalent to the diameter of the opening 290, and the channel width W can be calculated as "(D-2×W225)×π".

[0096] Furthermore, the channel length L of transistor 200A is preferably at least smaller than the channel width W of transistor 200A. The channel length L of transistor 200A is preferably 0.1 times or more and 0.99 times or less than the channel width W of transistor 200A, more preferably 0.5 times or more and 0.8 times or less. By adopting this structure, a transistor with good electrical characteristics and high reliability can be realized.

[0097] Furthermore, by forming the opening 290 in a circular shape when viewed from above, the insulating layer 225, semiconductor layer 230, insulating layer 250, and conductive layer 260 are arranged in a concentric circle. As a result, the distance between the conductive layer 260 and the semiconductor layer 230 is approximately uniform, and the distance between the conductive layer 215 and the semiconductor layer 230 is also approximately uniform, so a gate electric field can be applied to the semiconductor layer 230 approximately uniformly.

[0098] Note that this embodiment shows an example where the opening 290 is circular when viewed from above, but the present invention is not limited thereto. For example, the opening 290 may also be a roughly circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a shape in which the corners of the quadrilateral or other polygons are rounded.

[0099] Note that in Figure 1B and Figure 1C The opening 290 is provided such that the sidewall of the opening 290 is perpendicular to the top surface of the insulating layer 210, but the present invention is not limited thereto. For example, the sidewall of the opening 290 may also have a tapered shape.

[0100] Reference Figures 3A to 3C This describes the structure of a semiconductor device with a tapered sidewall of opening 290. Figure 3A This is a plan view of a semiconductor device including transistor 200A. Figure 3B It is along Figure 3A The cross-sectional view of the dotted line A1-A2 shown. Figure 3C It is along Figure 3A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 3A In the plan view, some constituent elements are omitted for clarity. Sometimes, some constituent elements are also omitted in the plan view shown below.

[0101] like Figure 3B and Figure 3C As shown, by making the sidewalls of the opening 290 tapered, the coverage of the insulating layer 225, semiconductor layer 230, insulating layer 250, etc., can be improved, thereby reducing defects such as voids. When the sidewalls of the opening 290 have a tapered shape, for example, the angle formed by the side surface of the insulating layer 280 and the top surface of the insulating layer 210 in the opening 290 is preferably 45 degrees or more and less than 90 degrees. Specifically, when this angle is 80 degrees or more and less than 90 degrees, as described above, miniaturization or high integration of the semiconductor device can be achieved, so it is preferred. Furthermore, when this angle is 45 degrees or more or 50 degrees or more and less than 80 degrees, or 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, the coverage of the film formed in the opening 290 is improved, so it is preferred. Furthermore, the angles formed by the side surface of the conductive layer 215 in the opening 290 and the top surface of the insulating layer 210, as well as the angles formed by the side surface of the insulating layer 281 in the opening 290 and the top surface of the insulating layer 210, are preferably within the aforementioned ranges.

[0102] Note that, as Figure 3B and Figure 3C As shown, the width of the opening 290 sometimes varies in the depth direction. In this specification, in particular, the width D of the opening 290 is the shortest distance between the two sides of the insulating layer 280 located on the conductive layer 220 in cross-section. In other words, the width D of the opening 290 is the minimum value of the width of the opening 290 in the insulating layer 280.

[0103] Alternatively, for example, the sidewall of the opening 290 may also have an inverted conical shape. In other words, the angle formed by the side surface of the insulating layer 280 and the top surface of the insulating layer 210 in the opening 290 may also be greater than 90 degrees. In this case, the angle formed by the side surface of the conductive layer 215 and the top surface of the insulating layer 210 in the opening 290, as well as the angle formed by the side surface of the insulating layer 281 and the top surface of the insulating layer 210 in the opening 290, may both be within the aforementioned range.

[0104] in addition, Figure 1B and Figure 1C The diagram shows a structure with a flat top surface of the conductive layer 220, but the invention is not limited thereto. For example, as... Figure 4A and Figure 4B As shown, a first recess overlapping the opening 290 can also be formed on the top surface of the conductive layer 220. By forming at least a portion of the insulating layer 225, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 in a manner that embeds into the first recess, the gate electric field of the conductive layer 260 can be easily applied to the vicinity of the conductive layer 220 of the semiconductor layer 230.

[0105] For example, such as Figure 4C and Figure 4D As shown, a second recess can also be formed on the top surface of the conductive layer 220, overlapping the opening of the insulating layer 225. By forming at least a portion of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 in a manner that embeds the second recess, the contact area between the semiconductor layer 230 and the conductive layer 220 can be increased. This improves the on-state current of the transistor 200A and achieves good electrical characteristics. Therefore, a high-speed semiconductor device can be realized.

[0106] For example, such as Figure 4E and Figure 4F As shown, a first recess and a second recess can also be formed on the top surface of the conductive layer 220.

[0107] in addition, Figure 1B and Figure 1C The diagram shows the structure where the side of the insulating layer 225 in the opening 290 that contacts the semiconductor layer 230 is perpendicular to the top surface of the insulating layer 210; however, the invention is not limited thereto. For example, as... Figure 5A and Figure 5B As shown, the side of the insulating layer 225 that contacts the semiconductor layer 230 in the opening 290 can also have a tapered shape. By making this side of the insulating layer 225 tapered, the coverage of the semiconductor layer 230, the insulating layer 250, etc., can be improved, thereby reducing defects such as voids.

[0108] in addition, Figure 5A and Figure 5B The diagram shows a structure where the top surface of the insulating layer 225 coincides with the top surface of the conductive layer 240. Note that the invention is not limited to the condition where the top surface of the insulating layer 225 is above the top surface of the conductive layer 215 (on the side of the conductive layer 240). For example, the top surface of the insulating layer 225 may also be below the top surface of the conductive layer 240 (on the side of the conductive layer 220). That is, the top surface of the insulating layer 225 may also be above the top surface of the conductive layer 215 and below the top surface of the conductive layer 240.

[0109] Figure 5C and Figure 5D This diagram shows a structure in which the insulating layer 225 contacts a portion of the side surface of the conductive layer 240 at the opening 290. In other words, it shows a structure where the top surface of the insulating layer 225 is located between the bottom and top surfaces of the conductive layer 240. By employing this structure, the semiconductor layer 230 can contact a portion of the side surface of the conductive layer 240 at the opening 290, in addition to the top surface of the conductive layer 240. Therefore, the contact area between the semiconductor layer 230 and the conductive layer 240 can be increased. This, in turn, can improve the on-state current of the transistor 200A and achieve good electrical characteristics. Furthermore, the height of the top surface of the insulating layer 225 can be the same as the height of the bottom surface of the conductive layer 240. In this case, the insulating layer 225 does not contact the conductive layer 240. By employing this structure, the semiconductor layer 230 can make overall contact with the side surface of the conductive layer 240 at the opening 290, in addition to the top surface of the conductive layer 240.

[0110] Alternatively, the top surface of the insulating layer 225 can also be located above the top surface of the conductive layer 240. In this structure, the semiconductor layer 230 can also be in contact with the top surface of the conductive layer 240.

[0111] Figure 1B The diagram shows a structure where the side ends of the semiconductor layer 230 and the conductive layer 240 coincide outside the opening 290. By employing this structure, the semiconductor film forming the semiconductor layer 230 and the conductive film forming the conductive layer 240 can be processed continuously using the same etching mask, thereby improving the productivity of semiconductor devices. Note that the invention is not limited thereto.

[0112] Figures 6A to 6C Show as Figures 1A to 1C The semiconductor device shown is a modified example of a semiconductor device. Figure 6A This is a plan view of the semiconductor device. Figure 6B It is along Figure 6A The cross-sectional view shown is the dotted-dash line A1-A2. Figure 6C It is along Figure 6A The cross-sectional view of the dotted-dash line A3-A4 is shown. For example, as shown... Figures 6A to 6C As shown, a structure can also be adopted in which the end of the semiconductor layer 230 on the outer side of the opening 290 is located inside the end of the conductive layer 240. By adopting this structure, the conductive layer 240 and the semiconductor layer 230 can be processed in different steps, making each processing of the conductive layer 240 and the semiconductor layer 230 easier. In addition, the step of the surface on which the insulating layer 250 is formed is reduced, thereby improving the coverage of the insulating layer 250.

[0113] Alternatively, for example, a structure can be adopted in which the end of the semiconductor layer 230 in the X direction is located outside the end of the conductive layer 240 located outside the opening 290. In other words, a structure can be adopted in which the semiconductor layer 230 covers the side of the conductive layer 240 located outside the opening 290 in the X direction. By adopting this structure, the contact area between the semiconductor layer 230 and the conductive layer 240 can be increased. As a result, the on-state current of the transistor 200A can be improved and good electrical characteristics can be achieved.

[0114] Materials Constituting Semiconductor Devices The following describes the materials that can be used in the semiconductor device of this embodiment. Each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked structure. Figure 1B and Figure 1C An example is shown where conductive layer 220, insulating layer 225, semiconductor layer 230, conductive layer 240, insulating layer 250, and conductive layer 260 all have a single-layer structure. Furthermore, Figures 7A to 8B An example is shown in which conductive layer 220, insulating layer 225, semiconductor layer 230, conductive layer 240, insulating layer 250 and conductive layer 260 all have a stacked structure.

[0115] [Semiconductor layer 230] As described above, semiconductor layer 230 has a channel formation region. This channel formation region is i-type (intrinsic) or substantially i-type. Semiconductor layer 230 also has a source region and a drain region. This source region and the drain region are n-type regions (low-resistance regions) with higher carrier concentrations compared to the channel formation region.

[0116] There are no particular restrictions on the crystallinity of the semiconductor material used for semiconductor layer 230; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with a portion of crystalline regions) can be used. When using single-crystal semiconductors or crystalline semiconductors, the degradation of transistor characteristics can be suppressed, so they are preferred.

[0117] The bandgap of the metal oxide used as the semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap, the off-state current of the transistor can be reduced. The off-state current of the OS transistor is small, thus significantly reducing the power consumption of the semiconductor device. Furthermore, the OS transistor has high frequency characteristics, enabling the semiconductor device to operate at high speeds.

[0118] Examples of metal oxides that can be used in semiconductor layer 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Note that element M is a metallic or semi-metallic element with a high bonding energy with oxygen, for example, a metallic or semi-metallic element with a higher bonding energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. Note that in this specification and other documents, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification and other documents sometimes include half-metallic elements.

[0119] Semiconductor layer 230 may use, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also known as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), aluminum zinc oxide (Al-Zn oxide, also known as A Zinc oxide (IZO), indium aluminum zinc oxide (In-Al-Zn oxide, also known as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also known as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also known as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also known as IGAZO, IGZAO, or IAGZO), etc. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0120] The field-effect mobility of a transistor can be improved by increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements in the metal oxide. Furthermore, transistors with high on-state currents can be realized.

[0121] Note that metal oxides can also replace indium or contain one or more metals with high period numbers in the periodic table besides indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers in the periodic table, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers in the periodic table include those belonging to period 5 and period 6. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0122] Metal oxides can also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved due to increased carrier concentration or narrower band gap. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0123] Furthermore, by increasing the ratio of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. As a result, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0124] Furthermore, by increasing the ratio of the number of atoms of element M to the total number of atoms of all metal elements in the metal oxide, a metal oxide with a wider band gap can be obtained. Additionally, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state currents. Furthermore, threshold voltage drift of the transistor can be suppressed. Moreover, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0125] The electrical characteristics and reliability of transistors vary depending on the composition of the metal oxide used in the semiconductor layer 230. Therefore, by varying the composition of the metal oxide to correspond to the required electrical characteristics and reliability of the transistor, it is possible to realize a semiconductor device that combines excellent electrical characteristics and high reliability.

[0126] When the metal oxide is an In-M-Zn oxide, the ratio of the number of In atoms in the In-M-Zn oxide is preferably greater than or equal to the ratio of the number of M atoms. Examples of the atomic ratios of the metal elements in this In-M-Zn oxide include In:M:Zn = 1:1:0.5, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:1:2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, and compositions in their vicinity. Furthermore, the surrounding composition includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of transistors can be improved.

[0127] In In-M-Zn oxides, the atomic ratio of In can also be less than that of M. Examples of such In-M-Zn oxide atomic ratios include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, and compositions close to these ratios. By increasing the proportion of M atoms in the metal oxide, the formation of oxygen vacancies can be suppressed.

[0128] Note that when element M contains multiple metallic elements, the total proportion of the number of atoms of each metallic element can be the proportion of the number of atoms of element M.

[0129] In this specification, the proportion of indium atoms relative to the total number of atoms of all metallic elements contained herein is sometimes stated as the indium content. The same applies to other metallic elements.

[0130] Furthermore, when the metal oxide is an In-Zn oxide, examples of the atomic ratio of the metal element in the In-Zn oxide include In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, and compositions close to these ratios. In addition, In-Zn oxides may also contain trace amounts of element M. For example, when Sn is included as element M, examples of the atomic ratio of the metal element in the metal oxide include In:Sn:Zn = 2:0.1:1, In:Sn:Zn = 4:0.1:1, and compositions close to these ratios.

[0131] For analysis of the composition of the metal oxide used in semiconductor layer 230, methods such as energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, multiple methods can be combined. Note that the actual content of elements with low concentrations may differ from the analytically obtained content due to the limitations of analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content.

[0132] Metal oxides can be formed appropriately using sputtering or ALD methods. Note that when metal oxides are formed using sputtering, the composition of the deposited metal oxide sometimes differs from that of the target material. In particular, the zinc content in the deposited metal oxide can sometimes be reduced to about 50% of the zinc content in the target material. Furthermore, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and pulsed laser deposition (PLD) methods can also be used when depositing metal oxides.

[0133] Semiconductor layer 230 may also have a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers comprising semiconductor layer 230 may also be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0134] The compositions of the two or more metal oxide layers included in the semiconductor layer 230 may also be different.

[0135] Figure 7A An example of a two-layer structure is shown, in which semiconductor layer 230 has semiconductor layer 230a and semiconductor layer 230b on semiconductor layer 230a.

[0136] For example, semiconductor layer 230a is preferably made of a material with higher conductivity than semiconductor layer 230b. By using a material with high conductivity in semiconductor layer 230a, which contacts the source electrode and the drain electrode (conductive layer 220 and conductive layer 240), the contact resistance between semiconductor layer 230 and conductive layer 220 and the contact resistance between semiconductor layer 230 and conductive layer 240 can be reduced, thereby enabling transistors with high on-state current.

[0137] Here, when a material with high conductivity is used in the semiconductor layer 230b disposed on the side of the conductive layer 260 serving as the first gate electrode, it sometimes causes a drift in the threshold voltage of the transistor 200A, thereby increasing the drain current (hereinafter also referred to as the cutoff current) flowing when the gate voltage is 0V. Specifically, when the transistor 200A is an n-channel transistor, the threshold voltage sometimes decreases. Therefore, it is preferable to use a material with lower conductivity than the semiconductor layer 230a for the semiconductor layer 230b. As a result, when the transistor 200A is an n-channel transistor, the threshold voltage can be increased, and a transistor with a small cutoff current can be realized. Note that the state with a small cutoff current is sometimes referred to as normally off.

[0138] By having the semiconductor layer 230 have a stacked structure as described above and using a material with higher conductivity than semiconductor layer 230b for semiconductor layer 230a, a transistor that is normally off and has a large on-state current can be realized. Thus, a semiconductor device that combines low power consumption and high performance can be realized.

[0139] Furthermore, the carrier concentration of semiconductor layer 230a is preferably higher than that of semiconductor layer 230b. By increasing the carrier concentration of semiconductor layer 230a, the conductivity increases, which reduces the contact resistance between semiconductor layer 230 and conductive layer 220, as well as the contact resistance between semiconductor layer 230 and conductive layer 240, thereby enabling a transistor with a large on-state current. Conversely, by decreasing the carrier concentration of semiconductor layer 230b, the conductivity decreases, thereby enabling a normally off transistor.

[0140] Note that the semiconductor layer 230 is not limited to the structure described above; the semiconductor layer 230a may also be made of a material with a lower conductivity than the semiconductor layer 230b. Furthermore, the carrier concentration of the semiconductor layer 230a may be lower than that of the semiconductor layer 230b.

[0141] Furthermore, the band gap of the first metal oxide used in semiconductor layer 230a is preferably different from the band gap of the second metal oxide used in semiconductor layer 230b. For example, the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.

[0142] The band gap of the first metal oxide used for semiconductor layer 230a is preferably smaller than that of the second metal oxide used for semiconductor layer 230b. This reduces the contact resistance between semiconductor layer 230 and conductive layer 220, as well as between semiconductor layer 230 and conductive layer 240, thus enabling a transistor with a large on-state current. Furthermore, when transistor 200A is an n-channel transistor, the threshold voltage can be increased, thereby enabling a normally-off transistor. Additionally, due to the large band gap of the second metal oxide, the generation and induction of charge carriers in semiconductor layer 230b and at the interface between semiconductor layer 230b and insulating layer 250 can be suppressed. This improves the reliability of the transistor.

[0143] For example, the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide. More specifically, it is preferable, for example, to use a metal oxide with an In:M:Zn ratio of 1:1:1 or similar as the semiconductor layer 230a, and to use a metal oxide with an In:M:Zn ratio of 1:3:2 or similar as the semiconductor layer 230b. In this case, one or more of gallium, aluminum, and tin are particularly preferred as element M.

[0144] Note that the semiconductor layer 230 is not limited to the structure described above, and the band gap of the first metal oxide can also be larger than that of the second metal oxide.

[0145] Furthermore, the content of element M in the first metal oxide is preferably lower than that in the second metal oxide. The first metal oxide may also contain trace amounts of element M or may not contain element M at all. For example, the first metal oxide used for semiconductor layer 230a is preferably an In-Zn oxide, and the second metal oxide used for semiconductor layer 230b is preferably an In-M-Zn oxide. Specifically, the first metal oxide may be an In-Zn oxide, and the second metal oxide may be an In-Ga-Zn oxide.

[0146] For example, as semiconductor layer 230a, metal oxides with an In:Zn ratio of 1:1 or similar, In:Zn ratio of 2:1 or similar, In:Sn:Zn ratio of 2:0.1:1 or similar, In:Zn ratio of 4:1 or similar, In:Sn:Zn ratio of 4:0.1:1 or similar, or indium oxide are preferred. Furthermore, as semiconductor layer 230b, metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, In:Ga:Zn ratio of 1:3:2 or similar, or In:Ga:Zn ratio of 1:3:4 or similar are preferred. This increases the on-state current of transistor 200A, thus enabling a transistor structure with less non-uniformity and higher reliability.

[0147] The semiconductor layer 230 is not limited to the above structure, and the content of element M in the first metal oxide can also be higher than the content of element M in the second metal oxide.

[0148] Semiconductor layer 230 preferably comprises a crystalline metal oxide layer. Examples of crystalline metal oxide structures include CAAC (c-axis aligned crystal) structures, polycrystalline structures, and nano-crystal (nc) structures. By using a crystalline metal oxide layer in semiconductor layer 230, the defect state density in semiconductor layer 230 can be reduced, thereby enabling a highly reliable semiconductor device.

[0149] The higher the crystallinity of the metal oxide layer used for semiconductor layer 230, the lower the defect state density in semiconductor layer 230 can be. On the other hand, by using a metal oxide layer with low crystallinity, transistors capable of carrying large currents can be realized.

[0150] When forming a metal oxide layer using sputtering, the higher the substrate temperature (stage temperature) during formation, the more crystalline the metal oxide layer can be formed. Furthermore, the higher the oxygen flow rate ratio relative to the overall deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the more crystalline the metal oxide layer can be formed.

[0151] The crystallinity of the semiconductor layer 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, multiple of the above methods can be combined for analysis.

[0152] The semiconductor layer 230 may also have a stacked structure of two or more metal oxide layers with different crystallinity. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer disposed on the first metal oxide layer, wherein the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. In this case, the compositions of the first metal oxide layer and the second metal oxide layer may be different, the same, or substantially the same.

[0153] For example, as semiconductor layer 230a, a metal oxide with an In:M:Zn ratio of 1:3:2 or similar, or an In:M:Zn ratio of 1:3:4 or similar, is preferably used. As semiconductor layer 230b, a metal oxide with an In:M:Zn ratio of 1:1:1 or similar, is preferably used. By using a metal oxide with a high Zn:In ratio as semiconductor layer 230a, the crystallinity of semiconductor layer 230a can be improved. Furthermore, by forming semiconductor layer 230b on the highly crystallinity semiconductor layer 230a, the crystallinity of semiconductor layer 230b is easily improved. Therefore, the overall crystallinity of semiconductor layer 230 can be improved, which is preferred. In this case, gallium, aluminum, or tin is particularly preferred as element M. For example, two IGZOs with different compositions can also be stacked. For example, a stacked structure selected from any one of indium oxide, indium gallium oxide and IGZO and any one of IAZO, IAGZO and ITZO (registered trademarks) can also be used.

[0154] also, Figure 7B An example of a three-layer structure is shown, comprising a semiconductor layer 230c, a semiconductor layer 230a on the semiconductor layer 230c, and a semiconductor layer 230b on the semiconductor layer 230a.

[0155] Semiconductor layers 230a and 230b can adopt the above-described structure. Semiconductor layer 230c can adopt the same structure as that used in semiconductor layer 230b.

[0156] For example, as semiconductor layer 230a, metal oxides with an In:Zn ratio of 1:1 or similar, In:Zn ratio of 2:1 or similar, In:Sn:Zn ratio of 2:0.1:1 or similar, In:Zn ratio of 4:1 or similar, In:Sn:Zn ratio of 4:0.1:1 or similar, or indium oxide are preferably used. Furthermore, as semiconductor layers 230b and 230c, metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, In:Ga:Zn ratio of 1:3:2 or similar, or In:Ga:Zn ratio of 1:3:4 or similar are preferably used.

[0157] Preferably, the band gaps of semiconductor layers 230b and 230c are both larger than the band gap of semiconductor layer 230a. Thus, semiconductor layer 230a is sandwiched between semiconductor layers 230b and 230c, which have larger band gaps, and semiconductor layer 230a is primarily used as a current path (channel). By sandwiching semiconductor layer 230a between semiconductor layers 230b and 230c, the trap levels at and near the interface of semiconductor layer 230a can be reduced. This allows for the realization of an embedded-channel transistor with the channel far from the insulating layer interface, thereby improving field-effect mobility. Furthermore, the influence of interface states that can form on the back channel side can be reduced to suppress transistor optical degradation (e.g., optical negative bias degradation), thereby improving transistor reliability.

[0158] The thickness of the semiconductor layer 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more and 30 nm or less, 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.

[0159] Sometimes, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to metal atoms to form water, thus creating oxygen vacancies (V0) in the oxide semiconductor. O Furthermore, sometimes V O Hydrogen (H) is used as a donor to generate electrons as charge carriers. Furthermore, sometimes a portion of the hydrogen bonds with oxygen atoms bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have always-on characteristics (i.e., a negative threshold voltage). Moreover, because hydrogen in oxide semiconductors is easily mobile due to heat, electric fields, etc., a large amount of hydrogen in the oxide semiconductor may lead to reduced transistor reliability.

[0160] Preferably, the V in semiconductor layer 230 should be minimized.O H is used to make the semiconductor layer 230 a high-purity intrinsic or substantially high-purity intrinsic. To obtain this V... O For oxide semiconductors with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen from the oxide semiconductor (sometimes described as dehydration or dehydrogenation treatment); and repair oxygen vacancies by supplying oxygen to the oxide semiconductor. This is achieved by... O When oxide semiconductors with sufficiently reduced impurities such as hydrogen are used in the channel formation region of transistors, they can impart stable electrical characteristics. Note that the process of supplying oxygen to oxide semiconductors to repair oxygen vacancies is sometimes referred to as oxidation treatment.

[0161] The carrier concentration of the oxide semiconductor used as the channel formation region is preferably 1 × 10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 Further optimization of less than 1×10 16 cm -3 Further optimization of less than 1×10 13 cm -3 Further optimization of less than 1×10 12 cm -3 Note that there is no specific limit to the lower limit of the carrier concentration of the oxide semiconductor in the region used as the channel formation region; for example, it can be set to 1 × 10⁻⁶. -9 cm -3 .

[0162] Here, we explain the effects of various impurities in metal oxides (oxide semiconductors).

[0163] When an oxide semiconductor contains silicon or carbon, one of Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 Below. Furthermore, the silicon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶.20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 the following.

[0164] Furthermore, when nitrogen is included in oxide semiconductors, electrons are generated as charge carriers, increasing the charge carrier concentration and making them more susceptible to n-type conversion. As a result, transistors using nitrogen-containing oxide semiconductors tend to exhibit always-on characteristics. Alternatively, when nitrogen is included in oxide semiconductors, trapped states can sometimes form. Consequently, the electrical characteristics of the transistor can sometimes be unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0165] Furthermore, hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using hydrogen-containing oxide semiconductors tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 5×10 19 atoms / cm3 More preferably less than 1×10 19 atoms / cm 3 More preferably less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 .

[0166] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect states are sometimes formed, generating charge carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0167] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0168] Furthermore, transistors using other semiconductor materials in the semiconductor layer 230 can also be used in the semiconductor device of this embodiment. Examples of such other semiconductor materials include semiconductors or compound semiconductors composed of a single element. Examples of semiconductors composed of a single element include silicon or germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. Furthermore, examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may also contain impurities as dopants.

[0169] Silicon, as a semiconductor material that can be used as a transistor, can be categorized into monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. For example, low-temperature polycrystalline silicon (LTPS) can be cited as a polycrystalline silicon.

[0170] Examples of compound semiconductors that can be used in semiconductor layer 230 include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride suitable for use in semiconductor layer 230 preferably has an amorphous structure. Boron arsenide suitable for use in semiconductor layer 230 preferably comprises crystals with a cubic crystal structure.

[0171] Semiconductor layer 230 may also contain layered materials used as semiconductors. Layered materials are a general term for a group of materials with layered crystal structures. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together by bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials have high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity in the channel formation region, transistors with large on-state currents can be provided.

[0172] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (belonging to Group 16 elements). Furthermore, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0173] [Insulating layer] Inorganic insulating films are preferably used as insulating layers (insulating layer 210, insulating layer 225, insulating layer 250, insulating layer 280, insulating layer 281, insulating layer 283, etc.) included in the semiconductor device. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. In addition, organic insulating films can also be used as insulating layers included in semiconductor devices.

[0174] For example, with the advancements in transistor miniaturization and high integration, problems such as leakage current sometimes arise due to the thinning of the gate insulating layer. By using a material with a high relative permittivity (high-k) in the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, by using a material with a low relative permittivity in the insulating layer used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, materials can be selected based on the function of the insulating layer. Moreover, materials with a low relative permittivity are also materials with high dielectric strength.

[0175] Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0176] Examples of materials with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride, as well as resins such as polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. Furthermore, examples of inorganic insulating materials with low relative permittivity other than those mentioned above include fluorinated silicon oxide, carbon-containing silicon oxide, and silicon oxide containing both carbon and nitrogen. Porous silicon oxide is also an example. Additionally, these silicon oxides may contain nitrogen.

[0177] Furthermore, ferroelectric materials can be used as insulating layers in semiconductor devices. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO. X (X is a real number greater than 0) and other metal oxides. Furthermore, materials that can exhibit ferroelectric properties include hafnium oxide with the addition of element J1 (here, element J1 is selected from one or more of zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to 1. Furthermore, materials that can exhibit ferroelectric properties include zirconium oxide with the addition of element J2 (here, element J2 is selected from one or more of hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Furthermore, the ratio of the number of zirconium atoms to the number of element J2 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to 1. Additionally, lead titanate (PbTiO2) can also be used as a material that can exhibit ferroelectric properties. XPiezoelectric ceramics with perovskite structure include barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate.

[0178] Furthermore, metal nitrides containing elements M1, M2, and nitrogen can be cited as materials that can exhibit ferroelectric properties. Here, element M1 is selected from one or more of aluminum, gallium, indium, etc. Furthermore, element M2 is selected from one or more of boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, the atomic ratio of element M1 to element M2 can be appropriately set. Moreover, metal oxides containing element M1 and nitrogen sometimes exhibit ferroelectric properties even without element M2. Furthermore, materials that can exhibit ferroelectric properties include those to which element M3 is added. Note that element M3 is selected from one or more of magnesium, calcium, strontium, zinc, cadmium, etc. Here, the atomic ratio of element M1, element M2, and element M3 can be appropriately set.

[0179] In addition, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and κ-type alumina such as GaFeO3 can be cited as materials that can exhibit ferroelectric properties.

[0180] Note that examples of metal oxides and metal nitrides are shown in the above description, but the invention is not limited to these examples. For instance, metal oxynitrides with nitrogen added to the aforementioned metal oxides or metal oxynitrides with oxygen added to the aforementioned metal nitrides may also be used.

[0181] Furthermore, as a material that can exhibit ferroelectricity, for example, a mixture or compound composed of multiple materials selected from the above-mentioned materials can be used. Additionally, the insulating layer can have a laminated structure composed of multiple materials selected from the above-mentioned materials. Note that the crystal structure (properties) of the materials listed above may vary not only depending on the deposition conditions but also depending on various processes, etc. Therefore, in this specification, materials exhibiting ferroelectricity are referred not only to ferroelectric materials but also to materials that can exhibit ferroelectricity.

[0182] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in areas of very small size. Therefore, by using metal oxides containing one or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0183] Note that in this specification, materials that are formed in a layered manner and can exhibit ferroelectric properties are sometimes referred to as ferroelectric layers, metal oxide films, or metal nitride films. Furthermore, in this specification, devices comprising ferroelectric layers, metal oxide films, or metal nitride films are sometimes referred to as ferroelectric devices.

[0184] Furthermore, ferroelectricity is thought to arise from the displacement of oxygen or nitrogen in the crystal contained within the ferroelectric layer under the influence of an applied electric field. Moreover, the presence of ferroelectricity is presumed to depend on the crystal structure of the crystal contained within the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, it needs to contain a crystal. In particular, the insulating layer preferably has a crystal with an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure of the crystal contained in the insulating layer can be any one or more selected from tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. Alternatively, the insulating layer can also have an amorphous structure. In this case, the insulating layer can also have a composite structure of amorphous and crystalline structures.

[0185] Furthermore, by surrounding a transistor using metal oxides with an insulating layer that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. For example, the insulating layer that suppresses the permeation of impurities and oxygen can be a single layer or a stack of insulating layers selected from one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the material used for the insulating layer that suppresses the permeation of impurities and oxygen can be metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0186] Specifically, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include oxides containing aluminum and hafnium (hafnium aluminate). Additionally, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxynitride, and silicon nitride.

[0187] Furthermore, insulating layers that are in contact with or near the oxide semiconductor layer, such as gate insulating layers, preferably have regions containing oxygen that has been removed by heating (hereinafter sometimes referred to as excess oxygen). For example, by contacting or placing an insulating layer with regions containing excess oxygen in contact with or near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or porous silicon oxide.

[0188] Insulating layer 210 is used as an interlayer film, so its relative permittivity is preferably low. By using a material with a low relative permittivity as the interlayer film, parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are suitable for use as insulating layer 210 because they have thermal stability.

[0189] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. This suppresses the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 230.

[0190] As the insulating layer 210, a hydrogen-blocking insulating layer is preferably used. By providing hydrogen-blocking properties for the insulating layer 210 disposed on the outside of the semiconductor layer 230, hydrogen diffusion into the semiconductor layer 230 can be suppressed.

[0191] Materials that can be used as hydrogen barrier insulating layers include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride.

[0192] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, barrier properties refer to the property that the corresponding substance does not easily diffuse (the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Additionally, hydrogen, referred to as the corresponding substance, includes, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel-forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc.

[0193] For example, silicon nitride film is preferably used as insulating layer 210.

[0194] Insulating layers 280 and 281 are preferably the hydrogen-barrier insulating layers described above. Insulating layers 280 and 281 are disposed around the semiconductor layer 230. By providing hydrogen-barrier properties, the hydrogen diffusion into the semiconductor layer 230 can be suppressed, provided that insulating layers 280 and 281 are disposed on the outer side of the semiconductor layer 230. For example, insulating layers 280 and 281 preferably comprise silicon nitride films.

[0195] Furthermore, silicon nitride also possesses oxygen-barrier properties. Therefore, by using silicon nitride in insulating layers 280 and 281, the formation of excessive oxygen vacancies in semiconductor layer 230 due to oxygen detachment can be suppressed. Additionally, oxidation of conductive layer 215 and the resulting increase in resistance of conductive layer 215 can be prevented.

[0196] Furthermore, by using silicon nitride for insulating layers 280 and 281, excess oxygen can be prevented from being supplied to semiconductor layer 230. Therefore, excess oxygen in the channel formation region of semiconductor layer 230 can be prevented, thus improving the reliability of transistor 200A.

[0197] Furthermore, insulating layers 280 and 281 preferably include the aforementioned oxide insulating film, oxynitride insulating film, or insulating layer having a region containing excess oxygen.

[0198] For example, an insulating layer having regions containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. By using a sputtering method that does not require the use of hydrogen-containing molecules as a deposition gas, the hydrogen concentration in insulating layer 280 and insulating layer 281 can be reduced. Thus, by depositing at least a portion of the layer constituting insulating layer 280, oxygen can be supplied from insulating layer 280 to the channel formation region of semiconductor layer 230, thereby reducing oxygen vacancies and VoH. Furthermore, by depositing at least a portion of the layer constituting insulating layer 281, oxygen can be supplied from insulating layer 281 to the channel formation region of semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0199] Furthermore, the concentration of impurities such as water and hydrogen in insulating layers 280 and 281 is preferably reduced. This suppresses the mixing of impurities such as water and hydrogen into the channel formation region of semiconductor layer 230.

[0200] Note that the thicknesses of insulating layer 280 and insulating layer 281 correspond to the channel length of transistor 200A, so the thicknesses of insulating layer 280 and insulating layer 281 are appropriately set according to the design value of the channel length of transistor 200A.

[0201] For example, a single-layer structure of silicon nitride film is preferably used as insulating layer 280 and insulating layer 281.

[0202] The insulating layer 250 preferably has the function of trapping or fixing hydrogen. This reduces the hydrogen concentration in the semiconductor layer 230 (especially in the channel formation region of the transistor). Therefore, the Vt in the channel formation region can be reduced. O H is used to make the channel forming region i-shaped or substantially i-shaped.

[0203] Materials used as insulating layers with the function of trapping or fixing hydrogen include metal oxides such as hafnium oxides, magnesium oxides, aluminum oxides, and oxides containing both aluminum and hafnium (hafnium aluminate). Furthermore, these metal oxides may also contain zirconium; for example, oxides containing both hafnium and zirconium can be cited. In metal oxides with amorphous structures, the ability to trap or fix hydrogen is high because some oxygen atoms have dangling bonds. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure can be achieved by including silicon in these oxides. For example, oxides containing both hafnium and silicon (hafnium silicate) are preferred. Furthermore, sometimes a portion of the metal oxide has one or both of a crystalline region and a grain boundary.

[0204] Furthermore, the function of capturing or fixing the corresponding substance can also be described as possessing the property that the corresponding substance is not easily diffused. Therefore, the function of capturing or fixing the corresponding substance can also be referred to as barrier property.

[0205] Furthermore, the insulating layer 250 is in contact with the semiconductor layer 230. When an oxide semiconductor layer is used as the semiconductor layer 230, the insulating layer 250 preferably has regions containing excess oxygen. By having the insulating layer 250 have regions containing excess oxygen, oxygen vacancies in the semiconductor layer 230 can be reduced. Examples of insulating layers that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or porous silicon oxide.

[0206] Figure 7A and Figure 7B An example is shown of an insulating layer 250 having a two-layer structure of insulating layer 250a and insulating layer 250b on insulating layer 250a.

[0207] When the insulating layer 250 has a stacked structure, the layer in contact with the semiconductor layer 230 preferably has the function of trapping or fixing hydrogen. That is, in Figure 7A and Figure 7B In this process, insulating layer 250a preferably has the function of capturing or fixing hydrogen. Furthermore, as insulating layer 250b, the aforementioned hydrogen-blocking insulating layer is preferably used.

[0208] By utilizing the hydrogen-trapping or fixing function of the insulating layer 250a, hydrogen contained in the semiconductor layer 230 can be trapped or fixed more effectively. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. Hafnium silicate is preferably used as the insulating layer 250a, for example. Furthermore, the insulating layer 250a preferably has an amorphous structure.

[0209] By giving the insulating layer 250a an amorphous structure, the formation of grain boundaries can be suppressed. Suppressing grain boundary formation improves the flatness of the insulating layer 250a film. Consequently, the thickness distribution of the insulating layer 250a becomes more uniform, reducing extremely thin sections and thus improving the withstand voltage of the insulating layer 250a. Furthermore, it allows for a more uniform thickness distribution of the film disposed on the insulating layer 250a.

[0210] Furthermore, by suppressing the formation of grain boundaries in the insulating layer 250a, leakage current caused by defect states at grain boundaries can be reduced. Therefore, the insulating layer 250a can be used as an insulating film with low leakage current.

[0211] Furthermore, since hafnium oxide is a high-k material, hafnium silicate is also a high-k material depending on its silicon content. Therefore, when using insulating layer 250a as the gate insulating layer, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulating layer. Additionally, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced.

[0212] By using a hydrogen barrier insulating layer as insulating layer 250b, the diffusion of impurities contained in conductive layer 260 into semiconductor layer 230 can be suppressed. Silicon nitride has high hydrogen barrier properties, making it suitable for use as insulating layer 250b.

[0213] By adopting the above structure, a semiconductor device with good electrical characteristics can be provided. Furthermore, a semiconductor device with high reliability can be provided. Furthermore, a semiconductor device with small non-uniformity in the electrical characteristics of the transistor can be provided. Furthermore, a semiconductor device with large on-state current can be provided.

[0214] Furthermore, the insulating layer 250 is preferably made of a high-k material. Another example of a high-k material is an oxide comprising one or both of aluminum and hafnium. When a high-k material is used as the insulating layer 250, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulating layer. Additionally, the equivalent oxide thickness (EOT) of the insulating layer used as the gate insulating layer can be reduced.

[0215] Therefore, as the insulating layer 250a, it is preferable to use an oxide containing one or both of aluminum and hafnium, more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably aluminum oxide having an amorphous structure.

[0216] Furthermore, the insulating layer 250 may also include an insulating layer with a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0217] Furthermore, the insulating layer 250 preferably includes an oxygen-barrier insulating layer. This suppresses oxidation of the conductive layers 240 and 260, etc. When the insulating layer 250 has a laminated structure, the layers in contact with the conductive layer 240 and the layers in contact with the conductive layer 260 are preferably oxygen-barrier insulating layers.

[0218] For example, by using a hydrogen and oxygen barrier insulating layer as the aforementioned insulating layer 250b, the oxidation of the conductive layer 260 can be suppressed. Furthermore, the formation of oxygen vacancies in the semiconductor layer 230 due to the diffusion of oxygen contained in the semiconductor layer 230 into the conductive layer 260 can be suppressed.

[0219] Examples of oxides that contain one or both of aluminum and hafnium, such as magnesium oxide, gallium oxide, zinc gallium oxide, zinc indium gallium oxide, silicon nitride, and silicon oxynitride, can be used as oxygen barrier insulating layers. Other examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0220] The thickness of the insulating layer 250 is preferably 0.1 nm or more and 30 nm or less, preferably 0.1 nm or more and 20 nm or less, preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, even more preferably 0.5 nm or more and 5.0 nm or less, even more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less.

[0221] also, Figure 8A An example is shown of an insulating layer 250 having a three-layer structure, comprising an insulating layer 250c, an insulating layer 250a on the insulating layer 250c, and an insulating layer 250b on the insulating layer 250a.

[0222] The insulating layer 250a and insulating layer 250b can adopt the above structure.

[0223] As the insulating layer 250c, a material with a low relative permittivity is preferably used. Silicon oxide or silicon oxynitride is preferably used as the material with a low relative permittivity. The insulating layer 250c is the layer in contact with the semiconductor layer 230. By using an oxide insulating layer as the insulating layer 250c, oxygen can be supplied to the semiconductor layer 230. Furthermore, by providing the insulating layer 250b, the diffusion of oxygen contained in the insulating layer 250c to the conductive layer 260 can be suppressed, thereby suppressing the oxidation of the conductive layer 260. Furthermore, the reduction in the amount of oxygen supplied from the insulating layer 250c to the semiconductor layer 230 can be suppressed.

[0224] also, Figure 8BAn example is shown of an insulating layer 250 having a four-layer structure: an insulating layer 250d, an insulating layer 250c on the insulating layer 250d, an insulating layer 250a on the insulating layer 250c, and an insulating layer 250b on the insulating layer 250a.

[0225] The insulating layers 250a to 250c can adopt the above-described structure.

[0226] The insulating layer 250d preferably has oxygen-barrier properties. The insulating layer 250d is the layer in contact with the semiconductor layer 230. When the insulating layer 250d has oxygen-barrier properties, oxygen detachment from the semiconductor layer 230 can be suppressed. Alumina is preferably used, for example, as the insulating layer 250d. Because alumina has the function of trapping or fixing hydrogen, it is suitable as the insulating layer 250d in contact with the oxide semiconductor layer 230.

[0227] To achieve transistor miniaturization, the thickness of insulating layers 250a to 250d is preferably thin. The thickness of insulating layers 250a to 250d is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, further preferably 0.5 nm or more and 5 nm or less, even more preferably 1 nm or more and less than 5 nm, and still more preferably 1 nm or more and 3 nm or less. Note that at least a portion of insulating layers 250a to 250d may only require regions having the aforementioned thicknesses.

[0228] Typically, the thicknesses of insulating layers 250d, 250c, 250a, and 250b are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. This structure allows for good electrical characteristics even when transistors are miniaturized or highly integrated.

[0229] Insulating layer 225 is used as a second gate insulating layer. Therefore, insulating layer 225 can adopt the structure of insulating layer 250.

[0230] Figure 7A and Figure 7B An example is shown where the insulating layer 225 has a two-layer structure consisting of an insulating layer 225b and an insulating layer 225a on the insulating layer 225b. Figure 7A and Figure 7B In the middle, insulating layers 225a and 250a are provided in such a way that they sandwich semiconductor layer 230, and insulating layers 225b and 250b are provided on their outer sides.

[0231] Insulating layer 225a can have the structure of insulating layer 250a, and insulating layer 225b can have the structure of insulating layer 250b. For example, when insulating layer 225a and insulating layer 250a have the function of trapping or fixing hydrogen, the hydrogen concentration in semiconductor layer 230 can be reduced. Furthermore, for example, when insulating layer 225b and insulating layer 250b have hydrogen barrier properties, the diffusion of impurities contained in conductive layer 215 or conductive layer 260 into semiconductor layer 230 can be suppressed.

[0232] By adopting the above structure, a semiconductor device with good electrical characteristics can be provided. Furthermore, a semiconductor device with high reliability can be provided. Furthermore, a semiconductor device with small non-uniformity in the electrical characteristics of the transistor can be provided. Furthermore, a semiconductor device with large on-state current can be provided.

[0233] also, Figure 8A An example is shown of an insulating layer 225 having a three-layer structure, comprising an insulating layer 225b, an insulating layer 225a on the insulating layer 225b, and an insulating layer 225c on the insulating layer 225a.

[0234] The insulating layer 225c can have the structure of the insulating layer 250c. For example, by using an oxide insulating layer as the insulating layer 225c, oxygen can be supplied to the semiconductor layer 230. Furthermore, the diffusion of oxygen contained in the insulating layer 225c to the conductive layer 215 can be suppressed, thereby suppressing the oxidation of the conductive layer 215. In addition, the reduction of the amount of oxygen supplied from the insulating layer 225c to the semiconductor layer 230 can be suppressed.

[0235] Note that when a hydrogen-barrier insulating layer is used as insulating layer 225b, hydrogen diffusion into semiconductor layer 230 can be suppressed. Therefore, as long as a semiconductor layer 230 with a low hydrogen concentration can be formed, insulating layers 225a and 225c are not limited to the structures described above. For example, insulating layer 225a can use insulating layers with thermally stable structures such as silicon oxide or silicon oxynitride, and insulating layer 225c can use a hydrogen-barrier insulating layer. By adopting this structure, hydrogen diffusion through insulating layer 225a into semiconductor layer 230 can be suppressed. As an example, silicon oxide can be used for insulating layer 225a, and silicon nitride can be used for insulating layers 225b and 225c.

[0236] also, Figure 8B An example is shown of an insulating layer 225 having a four-layer structure, comprising an insulating layer 225b, an insulating layer 225a on the insulating layer 225b, an insulating layer 225c on the insulating layer 225a, and an insulating layer 225d on the insulating layer 225c.

[0237] The insulating layer 225d can adopt the structure of the insulating layer 250d. For example, when the insulating layer 225d has oxygen barrier properties, it can suppress the detachment of oxygen from the semiconductor layer 230.

[0238] To achieve transistor miniaturization, the thickness of insulating layers 225a to 225d is preferably thin. The thickness of insulating layers 225a to 225d is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, further preferably 0.5 nm or more and 5 nm or less, even more preferably 1 nm or more and less than 5 nm, and still more preferably 1 nm or more and 3 nm or less. Note that at least a portion of insulating layers 225a to 225d only needs to have the above-mentioned thickness.

[0239] Notice, Figure 7A , Figure 7B , Figure 8A and Figure 8B The diagram shows structures where the number of insulating layers in insulating layer 225 is the same as the number of insulating layers in insulating layer 250, but the invention is not limited thereto. The number of insulating layers in insulating layer 225 may also differ from the number of insulating layers in insulating layer 250. The structures of insulating layers 225 and 250 can be appropriately configured according to the characteristics required by transistor 200A.

[0240] As the insulating layer 283, a hydrogen barrier insulating layer is preferably used. This can suppress the diffusion of hydrogen from the top of the insulating layer 283 to the semiconductor layer 230. Since both silicon nitride film and silicon oxynitride film have the characteristics of releasing few impurities (e.g., water and hydrogen) and being difficult for oxygen and hydrogen to permeate, they are suitable for use in the insulating layer 283.

[0241] Silicon nitride deposited by sputtering is particularly preferred as the insulating layer 283. Because sputtering does not require hydrogen-containing molecules to be used in the deposition gas, the hydrogen concentration of the insulating layer 283 can be reduced. By depositing the insulating layer 283 by sputtering, a high-density silicon nitride can be formed.

[0242] Furthermore, an insulating layer with the function of trapping or fixing hydrogen can also be used as the insulating layer 283. By adopting this structure, the diffusion of hydrogen from above the insulating layer 283 to the semiconductor layer 230 can be suppressed, and the hydrogen contained in the semiconductor layer 230 can be trapped or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. Hafnium silicate, etc., can be used as the insulating layer 283.

[0243] Furthermore, the insulating layer 283 can also be a laminated structure of an insulating layer with the function of trapping or fixing hydrogen and a hydrogen-blocking insulating layer. For example, the insulating layer 283 can also be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.

[0244] [Conductive layer] The conductive layers (conductive layer 215, conductive layer 220, conductive layer 240, conductive layer 260, etc.) included in the semiconductor device are preferably made of a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. As alloys containing the above-mentioned metallic elements, nitrides or oxides of the alloys may also be used. For example, tantalum nitride, titanium nitride, nitrides containing tungsten, titanium, and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferred. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0245] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, as well as conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metallic elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also known as ITSO), indium zinc oxide (also known as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification, conductive films deposited using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0246] Conductive materials with tungsten, copper, or aluminum as the main components have high conductivity and are therefore preferred.

[0247] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0248] Furthermore, when using metal oxides in the channel formation region of a transistor, the conductive layer used as the gate electrode preferably employs a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0249] Conductive layers 220 and 240 are conductive layers in contact with semiconductor layer 230, so it is preferable to use conductive materials that are not easily oxidized, conductive materials that maintain low resistance even if oxidized, oxide conductive materials, or conductive materials that have the function of inhibiting oxygen diffusion. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. As a result, the decrease in conductivity of conductive layers 220 and 240 can be suppressed.

[0250] By using an oxygen-containing conductive material as conductive layer 220 or conductive layer 240, conductivity can be maintained even if conductive layer 220 or conductive layer 240 absorbs oxygen. Furthermore, when an oxygen-containing insulating layer such as hafnium oxide is used as insulating layer 210, conductive layer 220 can also maintain conductivity, which is therefore preferred. For example, ITO, ITSO, and IZO (registered trademark) are preferred as conductive layers 220 and 240.

[0251] Figures 7A to 8B An example is shown where the conductive layer 220 has a three-layer structure: a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, and a conductive layer 220c on the conductive layer 220b. In this case, it is preferable, for example, to use a conductive material that is not easily oxidized or a conductive material that inhibits oxygen diffusion as the conductive layer 220a, to use a highly conductive material as the conductive layer 220b, and to use an oxygen-containing conductive material as the conductive layer 220c. Specifically, it is preferable, for example, to use titanium nitride as the conductive layer 220a, tungsten as the conductive layer 220b, and ITO or ITSO as the conductive layer 220c. In this case, the titanium nitride is in contact with the insulating layer 210, and the ITO or ITSO is in contact with the semiconductor layer 230. By adopting this structure, conductivity can be maintained even when the conductive layer 220 is in contact with the semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 due to the insulating layer 210 can be suppressed. Furthermore, by using tungsten, which has high conductivity, as the conductive layer 220b, the conductivity of the conductive layer 220 can be improved.

[0252] Figures 7A to 8B The top surface of the conductive layer 220 is shown to have a recess that overlaps with the opening 290.

[0253] Figures 7A to 8B An example is shown of a two-layer structure having a conductive layer 240a and a conductive layer 240b on the conductive layer 240a. In this case, it is preferable, for example, to use a material with higher conductivity than the conductive layer 240b as the conductive layer 240a, and to use an oxygen-containing conductive material as the conductive layer 240b. Specifically, it is preferable, for example, to use ruthenium, tungsten, titanium nitride, or tantalum nitride as the conductive layer 240a, and to use ITO or ITSO as the conductive layer 240b. In this case, the ITO or ITSO is in contact with the semiconductor layer 230. By employing this structure, conductivity can be maintained even when the conductive layer 240 is in contact with the semiconductor layer 230. Furthermore, by using a material with higher conductivity than the conductive layer 240b as the conductive layer 240a, the conductivity of the conductive layer 240 can be improved.

[0254] The conductive layer 260 is preferably made of a material with high conductivity, such as tungsten. Furthermore, the conductive layer 260 is preferably made of a conductive material that is not easily oxidized or has the function of inhibiting oxygen diffusion. As mentioned above, examples of such conductive materials include nitrogen-containing conductive materials (e.g., titanium nitride or tantalum nitride) and oxygen-containing conductive materials (e.g., ruthenium oxide). This helps to suppress the decrease in conductivity of the conductive layer 260.

[0255] The conductive layer 260 preferably uses a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel. Alternatively, a conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Furthermore, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used. Additionally, indium gallium zinc oxide containing nitrogen may be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from an external insulating layer or the like can sometimes be trapped.

[0256] Figures 7A to 8B An example is shown where the conductive layer 260 has a two-layer structure comprising a conductive layer 260a and a conductive layer 260b on the conductive layer 260a. In this case, for example, titanium nitride is preferably used as the conductive layer 260a, and tungsten is preferably used as the conductive layer 260b. This improves the conductivity of the conductive layer 260.

[0257] The conductive layer 215 is preferably made of a material with high conductivity. Tungsten or aluminum is preferred for the conductive layer 215. Alternatively, ruthenium can be used as the conductive layer 215. Ruthenium is a material that maintains conductivity even when absorbing oxygen, so it is suitable for use when an oxide insulating layer is used as one or both of the insulating layers 280 and 281. Furthermore, nitrogen-containing conductive materials such as tantalum nitride or titanium nitride can be used as the conductive layer 215. Nitrogen-containing conductive materials are conductive materials that are not easily oxidized or have the function of inhibiting oxygen diffusion, so they are suitable for use when an oxide insulating layer is used as one or both of the insulating layers 280 and 281.

[0258] The thickness of the conductive layer 215 is preferably 2 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, even more preferably 4 nm or more and 20 nm or less, and even more preferably 5 nm or more and 15 nm or less.

[0259] [Substrate] Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0260] <Structure Example of a Semiconductor Device 2> Reference Figures 9A to 10B Other structures of a semiconductor device according to one aspect of the present invention will be described. Figure 9A This is a cross-sectional view of the semiconductor device including transistor 200B, viewed from the Y direction. Figure 9B This is a cross-sectional view of the semiconductor device viewed from the X direction. Figure 9A and Figure 9B The plan view of the semiconductor device shown can be referred to Figure 1A. Figure 10A This is a cross-sectional view of the semiconductor device including transistor 200B, viewed from the Y direction. Figure 10B This is a cross-sectional view of the semiconductor device viewed from the X direction. Figure 10A and Figure 10B The plan view of the semiconductor device shown can be referred to Figure 1A .

[0261] Figure 9A and Figure 9B The semiconductor device shown and Figure 10A and Figure 10B The semiconductor device shown is Figures 1A to 1C The semiconductor device shown differs in that it includes insulating layer 227; and both insulating layers 280 and 281 have a stacked structure. The following mainly describes the parts that differ from the above description; repeated parts are sometimes omitted from the description as described above.

[0262] exist Figure 9A and Figure 9B The semiconductor device shown and Figure 10A and Figure 10B In the semiconductor device shown, an insulating layer 227 is disposed on the insulating layer 210, and a conductive layer 220 and an insulating layer 280 are disposed on the insulating layer 227.

[0263] As the insulating layer 227, it is preferable to use an insulating layer that has the function of trapping or fixing hydrogen. Thus, hydrogen in the semiconductor layer 230 diffuses through the conductive layer 220 to the insulating layer 227, whereby the hydrogen can be trapped or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0264] For example, it is preferable to use a silicon nitride film as the insulating layer 210 and an oxide film (hafnium silicate film) containing hafnium and silicon as the insulating layer 227.

[0265] exist Figure 9A and Figure 9B In the semiconductor device shown, insulating layer 280 includes insulating layer 280a and insulating layer 280b on insulating layer 280a. Additionally, insulating layer 281 includes insulating layer 281b and insulating layer 281a on insulating layer 281b.

[0266] Insulating layer 280a has a region that contacts the top surface of insulating layer 227 and regions that contact the side and top surfaces of conductive layer 220. Insulating layer 281a has a region that contacts the bottom surface of conductive layer 240.

[0267] Materials with low relative permittivity are preferably used for insulating layers 280b and 281b. The relative permittivity of insulating layer 280b is preferably at least lower than that of insulating layer 280a, and the relative permittivity of insulating layer 281b is preferably at least lower than that of insulating layer 281a. This reduces the parasitic capacitance generated between conductive layer 220 and conductive layer 215, and between conductive layer 215 and conductive layer 240. Silicon oxide or silicon oxynitride can be used, for example, for insulating layers 280b and 281b.

[0268] Oxygen-barrier insulating layers are preferably used as insulating layers 280a and 281a. By providing insulating layer 280a between insulating layer 280b and conductive layer 220, the increase in resistance of conductive layer 220 due to oxidation of conductive layer 220 can be suppressed. Furthermore, by providing insulating layer 281a between insulating layer 281b and conductive layer 240, the increase in resistance of conductive layer 240 due to oxidation of conductive layer 240 can be suppressed.

[0269] Furthermore, insulating layers 280a and 281a can also be used that have the function of trapping or fixing hydrogen. By adopting this structure, the diffusion of hydrogen from below insulating layer 280a and above insulating layer 281a into semiconductor layer 230 can be suppressed, and hydrogen contained in semiconductor layer 230 can be trapped or fixed. Therefore, the hydrogen concentration in semiconductor layer 230 can be reduced. Magnesium oxide, aluminum oxide, hafnium oxide, or oxides containing hafnium and silicon can be used as insulating layers 280a and 281a. In addition, for example, a laminate of aluminum oxide and silicon nitride on aluminum oxide or a laminate of silicon nitride and aluminum oxide on silicon nitride can also be used as insulating layers 280a and 281a.

[0270] For example, silicon nitride can be used for insulating layers 280a and 281a, and silicon oxide can be used for insulating layers 280b and 281b. In this case, insulating layer 280b preferably has a region thicker than insulating layer 280a, and insulating layer 281b preferably has a region thicker than insulating layer 281a. Furthermore, insulating layer 280b on conductive layer 220 preferably has a region thicker than insulating layer 280a, and insulating layer 281b on conductive layer 215 preferably has a region thicker than insulating layer 281a. As an example, the thicknesses of insulating layer 280a, insulating layer 280b on conductive layer 220, insulating layer 281b on conductive layer 215, and insulating layer 281a are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.

[0271] exist Figure 10A and Figure 10BIn the illustrated semiconductor device, insulating layer 280 includes insulating layer 280a, insulating layer 280c, and insulating layer 280b located between insulating layer 280a and insulating layer 280c. Specifically, insulating layer 280 includes insulating layer 280a, insulating layer 280b on insulating layer 280a, and insulating layer 280c on insulating layer 280b. Additionally, insulating layer 281 includes insulating layer 281a, insulating layer 281c, and insulating layer 281b located between insulating layer 281a and insulating layer 281c. Specifically, insulating layer 281 includes insulating layer 281c, insulating layer 281b on insulating layer 281c, and insulating layer 281a on insulating layer 281b.

[0272] Insulating layer 280c has a region that contacts the bottom surface of conductive layer 215. Insulating layer 281c has a region that contacts the top surface of insulating layer 280c and regions that contact the side and top surfaces of conductive layer 215. That is, conductive layer 215 is surrounded by insulating layer 280c, insulating layer 281c and insulating layer 225.

[0273] Insulating layers 280a, 280b, 281a, and 281b can adopt the above-described structure.

[0274] Oxygen-barrier insulating layers are preferably used as insulating layers 280c and 281c. By surrounding the conductive layer 215 with an oxygen-barrier insulating layer, oxidation of the conductive layer 215 and the resulting increase in resistance of the conductive layer 215 can be suppressed.

[0275] As an example, insulating layers 280c and 281c can be made of silicon nitride. In this case, insulating layer 280b preferably has a region thicker than insulating layer 280c, and insulating layer 281b preferably has a region thicker than insulating layer 281c. Furthermore, insulating layer 280b on conductive layer 220 preferably has a region thicker than insulating layer 280c, and insulating layer 281b on conductive layer 215 preferably has a region thicker than insulating layer 281c. As an example, the thicknesses of insulating layer 280a, insulating layer 280b on conductive layer 220, insulating layer 280c, insulating layer 281c, insulating layer 281b on conductive layer 215, and insulating layer 281a are 5 nm, 10 nm, 5 nm, 5 nm, 10 nm, and 5 nm, respectively.

[0276] <Structure Example of a Semiconductor Device 3> Reference Figures 11A to 11C Other structures of a semiconductor device according to one aspect of the present invention will be described. Figure 11A This is a plan view of a semiconductor device including transistor 200C. Figure 11B It is along Figure 11A The cross-sectional view of the dotted line A1-A2 shown. Figure 11C It is along Figure 11A The cross-sectional view shown is the dotted-dash line A3-A4.

[0277] Figures 11A to 11C The semiconductor device shown includes a conductive layer 221 and an insulating layer 282, which is consistent with... Figures 1A to 1C The semiconductor device shown is different. The following mainly describes the parts that differ from the above content, and for repeated parts, the description is sometimes omitted as they are mentioned above.

[0278] exist Figures 11A to 11C In the semiconductor device shown, a conductive layer 221 and an insulating layer 282 are disposed on the conductive layer 220. An insulating layer 280, an insulating layer 225, and a semiconductor layer 230 are disposed on the conductive layer 221 and the insulating layer 282. The insulating layer 280 is disposed on the conductive layer 220 and the conductive layer 221.

[0279] An opening 191 leading to the conductive layer 220 is provided in the insulating layer 282. Figure 11B and Figure 11C The width Da of the opening 191 is indicated by a double-headed arrow with double dots. A conductive layer 221 is provided embedded within the opening 191. The width of the conductive layer 221 is equal to the width Da of the opening 191. The conductive layer 221 is in contact with at least a portion of the top surface of the conductive layer 220 and the bottom surface of the semiconductor layer 230. The conductive layer 221 serves as one of the source and drain electrodes of the transistor 200C, and the conductive layer 220 serves as a wiring connection to one of the source and drain electrodes.

[0280] The width Da of the opening 191 is preferably the same as or smaller than the width D of the opening 290. Furthermore, the width Da of the opening 191 is preferably the same as or larger than the width D192 of the opening 192. Therefore, the width Da of the opening 191 is preferably greater than or equal to the width D192 of the opening 192 and less than the width D of the opening 290, more preferably greater than the width D192 of the opening 192 and less than the width D of the opening 290. By employing this structure, the physical distance between the conductive layer 220 and the conductive layer 215 can be increased, and the parasitic capacitance generated between the conductive layer 220 and the conductive layer 215 can be reduced. In other words, compared to the case where the conductive layer 221 is not provided, the parasitic capacitance can be reduced when the conductive layer 221 is provided.

[0281] The conductive layer 221 can be formed in a single layer or in a stack using the conductive material described in the above [Conductive Layer] section.

[0282] As the insulating layer 282, it is preferable to select an insulating material that is used as an etching stop film when the insulating layer 280 is etched to form an opening. For example, when silicon nitride is used as the insulating layer 280 for forming the opening, silicon oxide or silicon oxynitride is preferably used as the insulating layer 282.

[0283] Furthermore, since insulating layer 282 is used as an interlayer film, its relative permittivity is preferably low. By using a material with a low relative permittivity as the interlayer film, parasitic capacitance generated between wirings can be reduced. As insulating layer 282, a single layer or a stack of insulating layers containing a material with a low relative permittivity can be used. Silicon oxide and silicon oxynitride have thermal stability and are therefore preferred.

[0284] In other words, transistor 200C has a structure that reduces the parasitic capacitance generated between the wiring connected to one of the source and drain electrodes and the second gate electrode. Therefore, the frequency characteristics of the circuit can be improved.

[0285] <Examples of Semiconductor Device Manufacturing Methods> Next, refer to Figures 12A to 14F This invention describes a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 12A to 14F In the accompanying drawings, A, C, and E are cross-sectional views of the semiconductor device viewed from the Y direction, and B, D, and F are cross-sectional views of the semiconductor device viewed from the X direction. Note that regarding the materials and manufacturing methods of each component, parts that are the same as those already described are sometimes omitted.

[0286] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, CVD, vacuum evaporation, PLD, ALD, and other methods.

[0287] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing conductive metal films. Furthermore, pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0288] Furthermore, CVD methods can be categorized into plasma CVD (PECVD), thermal CVD (TCVD), and photo CVD. Additionally, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0289] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a deposition method that reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) included in semiconductor devices sometimes accumulate charge due to receiving charge from plasma. This accumulated charge can sometimes damage the wiring, electrodes, and components in the semiconductor device. On the other hand, since thermal CVD does not produce this plasma damage, the yield of semiconductor devices can be improved. Moreover, since plasma damage during deposition is not generated in thermal CVD, films with fewer defects can be obtained.

[0290] In addition, as an ALD method, there are thermal ALD methods that use only thermal energy to react the precursors and reactants, and PEALD methods that use reactants excited by plasma.

[0291] CVD and ALD methods differ from sputtering methods that deposit particles released from a target or similar material. Therefore, CVD and ALD are deposition methods that are less affected by the shape of the workpiece and offer high step coverage. In particular, ALD exhibits excellent step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratios and openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0292] Furthermore, when using CVD, films of arbitrary composition can be deposited based on the source gas flow rate ratio. For example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. When deposition is performed while changing the source gas flow rate ratio, the deposition time can be shortened compared to using multiple deposition chambers because the time required for transfer or pressure adjustment is eliminated. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0293] When using the ALD method, membranes of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, by controlling the number of cycles for each precursor while introducing multiple different precursors, membranes of arbitrary composition can be deposited.

[0294] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0295] Furthermore, when processing thin films constituting semiconductor devices, photolithography or similar methods can be used. Alternatively, nanoimprinting, sandblasting, or lift-off methods can be employed to process the thin films. Additionally, island-shaped thin films can be directly formed using deposition methods that utilize metal masks or similar masking techniques.

[0296] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, then processing the film through etching or similar means, and finally removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to shape the film into the desired form.

[0297] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these rays. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can also be used. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams allow for extremely fine processing and are therefore preferred. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0298] As a method for etching thin films, dry etching, wet etching, and sandblasting can be used.

[0299] First, such as Figure 12A and Figure 12B As shown, an insulating layer 210 is formed on a substrate (not shown), a conductive layer 220 is formed on the insulating layer 210, and an insulating layer 280 is formed on the conductive layer 220. Note that it is preferable to perform a planarization process using chemical mechanical polishing (CMP) after depositing the insulating layer 280 to planarize the top surface of the insulating layer 280. By performing the planarization process on the insulating layer 280, the surface on which the conductive layer 215 is formed for wiring can be flattened, thereby suppressing the breakage of the conductive layer 215. Alternatively, the planarization process can be omitted, which reduces manufacturing costs.

[0300] Next, as Figure 12A and Figure 12BAs shown, a conductive layer 215 is formed on the insulating layer 280, an insulating layer 281 is formed on the conductive layer 215, a conductive layer 240 is formed on the insulating layer 281, and a layer 275F is formed on the conductive layer 240. Layer 275F serves as the hard mask 275 described below. For example, the conductive layer 215 is preferably deposited using a sputtering method. By utilizing a sputtering method that does not require the use of hydrogen-containing molecules as a deposition gas, the hydrogen concentration in the conductive layer 215 can be reduced, thereby suppressing hydrogen incorporation into the semiconductor layer 230.

[0301] Note that it is preferable to perform CMP treatment after depositing the insulating layer 281 to planarize the top surface of the insulating layer 281. By performing planarization treatment on the insulating layer 281, the surface on which the conductive layer 240 for wiring is formed can be flat, thereby suppressing the disconnection of the conductive layer 240. Alternatively, planarization treatment can be omitted, which can reduce manufacturing costs.

[0302] Next, as Figure 12C and Figure 12D As shown, layer 275F is processed to form a hard mask 275. Furthermore, the hard mask 275 can also be described as a layer with an opening. This opening is formed at a location overlapping with the conductive layer 220. Additionally, the width of this opening is equal to the width D of the subsequently formed opening 290.

[0303] Next, as Figure 12C and Figure 12D As shown, an opening 290 is formed in the conductive layer 240, the insulating layer 281, the conductive layer 215, and the position where the insulating layer 280 overlaps with the conductive layer 220 using a hard mask 275. In other words, the opening 290 reaching the conductive layer 220 is formed by processing the insulating layer 280, the conductive layer 215, the insulating layer 281, and the conductive layer 240.

[0304] The hard mask 275 preferably uses a material with a smaller etch rate than the workpiece (here, conductive layer 240, insulating layer 281, conductive layer 215, and insulating layer 280). For example, when the etch rate of the workpiece is 1, the etch rate of the material used for the hard mask is preferably 0.5 or less, more preferably 0.1 or less. Specifically, the hard mask 275 can be made of a metallic material or an inorganic insulating material. More specifically, tungsten deposited by sputtering can be used. By adopting this structure, the shape of the hard mask can be maintained during etching, thus suppressing the generation of shape defects in the workpiece. The material of the hard mask can be appropriately set according to the workpiece. Furthermore, the etch rate varies depending on conditions such as power supply, bias power, flow rate of etching gas, type of etching gas, and pressure (also called etching conditions), so the etching conditions can be appropriately set according to the hard mask and the workpiece.

[0305] Because of the high aspect ratio of the opening 290, it is preferable to use anisotropic etching to process a portion of the conductive layer 240, a portion of the insulating layer 281, a portion of the conductive layer 215, and a portion of the insulating layer 280. In particular, dry etching is suitable for micro-machining and is therefore preferred. Furthermore, this processing can be performed under different conditions. Additionally, depending on the processing conditions of the conductive layer 240, insulating layer 281, conductive layer 215, and insulating layer 280, the slope of the side surface of the conductive layer 240 in the opening 290 may differ from the slope of the side surface of the insulating layer 281. Furthermore, the slope of the side surface of the insulating layer 281 in the opening 290 may differ from the slope of the side surface of the conductive layer 215. Furthermore, the slope of the side surface of the conductive layer 215 in the opening 290 may differ from the slope of the side surface of the insulating layer 280.

[0306] Next, a heat treatment may be performed. For example, the heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.

[0307] Furthermore, the heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen and oxygen gas, the ratio of oxygen gas is preferably set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, in order to replenish the detached oxygen, the heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above-described heat treatment, impurities such as water contained in the insulating layer 280, etc., can be reduced before the deposition of the semiconductor layer 230, which will be described later.

[0308] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content of the gas used in the above-described heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulating layer 280 can be prevented as much as possible.

[0309] Next, as Figure 12E and Figure 12FAs shown, an insulating layer 225 is formed to cover the opening 290, and a layer 276 is formed on the insulating layer 225. The insulating layer 225 is formed to contact the sidewalls and bottom of the opening 290. In a subsequent process, layer 276 is removed, leaving the insulating layer 225. Therefore, it is preferable to select a material with a higher etch rate than the insulating layer 225 for layer 276. Furthermore, when the insulating layer 225 has a stacked structure, it is preferable to select the layer 276 as the uppermost layer of the insulating layer 225. Figure 7A The etching rate of layer 276 of the insulating layer 225a) is selected to be greater than that of the material. For example, when the etching rate of the insulating layer 225 (the uppermost layer of the insulating layer 225) is 1, the etching rate of the material used for layer 276 is preferably 2 or more, and more preferably 10 or more. As an example, aluminum oxide can be used for layer 276.

[0310] Layer 276 is preferably formed with a thickness thinner than that of insulating layer 225. By making layer 276 thinner than insulating layer 225, the width D192 of the subsequently formed opening 192 can be increased. In other words, the width W225p of the subsequently formed portion can be reduced. Therefore, the contact area between the subsequently formed semiconductor layer 230 and conductive layer 220 can be increased. As a result, the on-state current of transistor 200A can be improved and good electrical characteristics can be achieved. Therefore, a high-speed semiconductor device can be realized.

[0311] Next, as Figure 13A and Figure 13B As shown, by processing the insulating layer 225 and layer 276, the top surface of the conductive layer 220 in the region overlapping with the opening 290 is exposed. Anisotropic etching is preferably used to process the insulating layer 225 and layer 276. By removing a portion of the insulating layer 225 and a portion of the layer 276 using anisotropic etching, an insulating layer 225 and a layer 276 in contact with the sidewall of the opening 290 are formed. Thus, the insulating layer 225 is formed in contact with the sidewalls of the insulating layer 280, the conductive layer 215, the insulating layer 281, and the conductive layer 240. The conductive layer 220 is exposed at the center of the opening 290.

[0312] In addition, such as Figure 13A and Figure 13B As shown, a protrusion 225p is formed on the portion of the insulating layer 225 that overlaps with layer 276. In other words, the protrusion 225p is formed on the portion of the insulating layer 225 that contacts the top surface of the conductive layer 220. The protrusion 225p has a shape that protrudes further toward the center of the opening 290 than other portions of the insulating layer 225. That is, in cross-section, the insulating layer 225 has a so-called L-shaped shape.

[0313] Next, as Figure 13C and Figure 13D As shown, the hard mask 275 is removed. The hard mask 275 can be removed using wet etching or dry etching. By removing the hard mask 275 while layer 276 is present, damage to the insulating layer 225 during the removal of the hard mask 275 can be reduced.

[0314] Next, as Figure 13E and Figure 13F As shown, layer 276 is removed. Layer 276 can be removed using either wet etching or dry etching. Isotropic etching is preferred for removing layer 276. Using wet etching reduces damage to the insulating layer 225 during layer 276 removal compared to dry etching. When using wet etching, for example, a developer, an aqueous solution of tetramethylammonium hydroxide (TMAH), dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixture containing two or more of these is preferably used. Alternatively, a mixed acid solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid can also be used. Note that the solution used for wet etching can be alkaline or acidic.

[0315] Note that there are no restrictions on the order of the processes for removing the hard mask 275 and removing layer 276. For example... Figures 13C to 13F As shown, layer 276 can be removed after removing hard mask 275, hard mask 275 can be removed after removing layer 276, or both hard mask 275 and layer 276 can be removed simultaneously.

[0316] Next, as Figure 14A and Figure 14B As shown, the semiconductor layer 230 is formed such that it covers the opening 290 with the insulating layer 225 in between. In other words, the semiconductor layer 230 is formed on the conductive layer 220, the insulating layer 225, and the conductive layer 240. The semiconductor layer 230 is disposed in contact with a portion of the top surface of the conductive layer 220, the side and top surfaces of the insulating layer 225, and the top surface of the conductive layer 240.

[0317] The semiconductor layer 230 can be deposited, for example, by sputtering, CVD, MBE, PLD or ALD.

[0318] The semiconductor layer 230 is preferably formed in the opening 290 along the top surface of the conductive layer 220 and the side surface of the insulating layer 225, and has a film with the most uniform thickness possible. By using the ALD method for deposition, a thinner film can be deposited with high controllability. Therefore, the semiconductor layer 230 is preferably deposited using the ALD method.

[0319] Furthermore, when the crystallinity of the semiconductor layer 230 is high, the diffusion of impurities in the semiconductor layer 230 is suppressed, thus the electrical characteristics of the transistor are less likely to change, thereby improving reliability. Depositing the semiconductor layer 230 using sputtering is preferable because it is easier to form a highly crystalline layer compared to using the ALD method.

[0320] When depositing the semiconductor layer 230 using sputtering, oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the oxygen content in the sputtering gas, excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the aforementioned oxide film using sputtering, In-M-Zn oxide targets or the like can be used.

[0321] When forming the semiconductor layer 230 using sputtering, an oxygen-excess oxide semiconductor is formed when deposition is performed under conditions where the oxygen content in the sputtering gas exceeds 30% and is less than 100%, preferably more than 70% and less than 100%. Transistors using oxygen-excess oxide semiconductors in the channel formation region can achieve relatively high reliability. Note that the invention is not limited to this. When deposition is performed with the oxygen content in the sputtering gas set to 1% or more and less than 30%, preferably more than 5% and less than 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can have higher field-effect mobility. Furthermore, by performing deposition while heating the substrate, the crystallinity of the oxide semiconductor layer can be improved.

[0322] Next, heat treatment may be performed. The heat treatment is preferably performed within a temperature range where the semiconductor layer 230 is not polycrystalline. The preferred heat treatment temperature is 100°C or higher, 250°C or higher, or 350°C or higher but 650°C or lower, 600°C or lower, or 550°C or lower. For details regarding the heat treatment, please refer to the above description.

[0323] Furthermore, the gas used in the above-mentioned heat treatment is preferably of high purity. By using a high-purity gas for heat treatment, the absorption of moisture and other substances by the semiconductor layer 230 can be prevented as much as possible.

[0324] Furthermore, the aforementioned heat treatment is preferably performed in an atmosphere containing oxygen gas. This oxygen-containing heat treatment reduces impurities such as carbon, water, and hydrogen in the semiconductor layer 230. By reducing impurities in the film, the crystallinity of the semiconductor layer 230 is improved, resulting in a denser structure. Therefore, the crystalline region in the semiconductor layer 230 can be increased, and the in-plane non-uniformity of the crystalline region in the semiconductor layer 230 can be reduced. Consequently, the in-plane non-uniformity of the electrical characteristics of the transistor can be reduced.

[0325] Next, as Figure 14C and Figure 14D As shown, the semiconductor layer 230 and the conductive layer 240 are processed into a strip shape. Thus, the semiconductor layer 230 and the conductive layer 240 are disposed extending in the A3-A4 direction. Note that in this specification, etc., island-shaped or strip-shaped refers to a state in which two or more layers formed in the same process and using the same material are physically separated. Furthermore, strip-shaped refers to a shape having a region extending in a certain direction (e.g., the X direction, Y direction, or Z direction).

[0326] Furthermore, by processing the conductive layer 240 into a strip shape before forming the semiconductor layer 230, it is possible to manufacture... Figures 6A to 6C The semiconductor device shown.

[0327] Furthermore, the processes of fabricating the conductive layer 240 into a strip shape and forming openings at the overlap of the conductive layer 240 with the conductive layer 220 can be performed independently, and the order of these processes is not limited. Alternatively, etching can be performed after exposure using a mask to fabricate square island shapes and after exposure using a mask to form circular openings, thereby performing island fabrication and opening formation in one step. Furthermore, exposure using multi-level grayscale masks (typically halftone or grayscale masks) can also be used. Moreover, the same mask can be used to form openings in both the conductive layer 240 and the insulating layer 280, or different masks can be used to form openings.

[0328] Next, as Figure 14E and Figure 14F As shown, an insulating layer 250 is formed on the semiconductor layer 230, and a conductive layer 260 is formed on the insulating layer 250.

[0329] The insulating layer 250 is formed in contact with the semiconductor layer 230 disposed in the opening 290 with a high aspect ratio. Therefore, when depositing the insulating layer 250, it is preferable to use a deposition method with good coverage, and more preferably to use CVD or ALD methods.

[0330] By depositing an insulating layer 250 after processing the semiconductor layer 230 into an island or strip shape, the side ends of the semiconductor layer 230 are covered by the insulating layer 250. Therefore, short circuits between the semiconductor layer 230 and the conductive layer 260 can be prevented. Furthermore, by employing the above structure, the side ends of the conductive layer 240 are covered by the insulating layer 250. Therefore, short circuits between the conductive layer 240 and the conductive layer 260 can be prevented.

[0331] The conductive layer 260 is formed in contact with the insulating layer 250 disposed in the opening 290 with a high aspect ratio. Therefore, when depositing the conductive layer 260, it is preferable to use a deposition method with good coverage, and more preferably to use CVD or ALD methods.

[0332] Next, as Figures 1A to 1C As shown, an insulating layer 283 is formed on the insulating layer 250 and the conductive layer 260.

[0333] The semiconductor device of one aspect of the present invention can be manufactured through the above-described process.

[0334] As described above, one aspect of the semiconductor device of the present invention includes a first gate electrode and a second gate electrode, thereby improving the electrical characteristics of the transistors included in the semiconductor device.

[0335] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0336] (Implementation Method 2) In this embodiment, refer to Figures 15A to 20 This invention describes a storage device according to one aspect of the present invention. The storage device according to one aspect of the present invention includes a storage cell. The storage cell includes a transistor and a capacitor.

[0337] <Example 1 of storage device structure> Reference Figures 15A to 15C Describe the structure of a storage device that includes transistors and capacitors. Figure 15A It is a plan view of a storage device including transistor 200A and capacitor 100. Figure 15B It is along Figure 15A The cross-sectional view of the dotted line A1-A2 shown. Figure 15C It is along Figure 15A The cross-sectional view shown is the dotted-dash line A3-A4.

[0338] Figures 15A to 15C The illustrated storage device includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a storage cell 150 on the conductive layer 110, insulating layers 180 and 181 on the conductive layer 110, insulating layers 280 and 281 on the insulating layer 181, and an insulating layer 283 on the storage cell 150. Insulating layers 140, 180, 181, 280, 281, and 283 are used as interlayer films. The conductive layer 110 is used for wiring.

[0339] The storage cell 150 includes a capacitor 100 on the conductive layer 110 and a transistor 200A on the capacitor 100.

[0340] The capacitor 100 includes a conductive layer 115 on a conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130. The conductive layer 120 serves as one of a pair of electrodes (sometimes referred to as the upper electrode), the conductive layer 115 serves as the other of the pair of electrodes (sometimes referred to as the lower electrode), and the insulating layer 130 serves as the dielectric. In other words, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0341] like Figure 15B and Figure 15C As shown, an opening 190 is provided in the insulating layer 180, leading to the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in the opening 190 that contacts the top surface of the conductive layer 110, a region in the opening 190 that contacts the side surface of the insulating layer 180, and a region that contacts at least a portion of the top surface of the insulating layer 180. At least a portion of the insulating layer 130 is disposed in the opening 190. At least a portion of the conductive layer 120 is disposed in the opening 190. Furthermore, as... Figure 15B and Figure 15C As shown, the conductive layer 120 is preferably provided in a manner that embeds it into the opening 190. Furthermore, the films provided in the opening 190 are preferably formed using CVD or ALD methods. Thus, the film has good coverage. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are all preferably formed using CVD or ALD methods.

[0342] The capacitor 100 has a structure in which the upper and lower electrodes are opposed to each other with a dielectric material not only at the bottom but also on the sidewalls within the opening 190, thus increasing the electrostatic capacitance per unit area. Therefore, the deeper the opening 190, the larger the electrostatic capacitance of the capacitor 100 can be. In this way, by increasing the electrostatic capacitance per unit area of ​​the capacitor 100, the read operation of the storage device can be stabilized. Furthermore, it can promote the miniaturization or high integration of storage devices.

[0343] Figure 15B and Figure 15C An example is shown where the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. By adopting this structure, miniaturization or high integration of the storage device can be achieved.

[0344] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. Furthermore, a conductive layer 120 is provided on the insulating layer 130 in a manner that it is embedded in the opening 190. A capacitor 100 having this structure can be referred to as a trench capacitor or trench capacitor.

[0345] An insulating layer 181 is disposed on the insulating layer 130. The top surfaces of the conductive layer 120 and the insulating layer 181 are preferably flat. By making the top surfaces of the conductive layer 120 and the insulating layer 181 flat, subsequent processes are easier to perform, thereby improving the yield of the storage device.

[0346] An insulating layer 280 is disposed on the capacitor 100. That is, the insulating layer 280 is disposed on the insulating layer 181 and the conductive layer 120.

[0347] Transistor 200A includes conductive layer 120 (corresponding to Figure 1B The conductive layer 220, conductive layer 215 on insulating layer 280, conductive layer 240 on insulating layer 281, insulating layer 225, semiconductor layer 230, insulating layer 250 on semiconductor layer 230, and conductive layer 260 on insulating layer 250 are used as semiconductor layers. Semiconductor layer 230 is used as a semiconductor layer, conductive layer 260 is used as a first gate electrode, insulating layer 250 is used as a first gate insulating layer, conductive layer 215 is used as a second gate electrode, insulating layer 225 is used as a second gate insulating layer, conductive layer 120 is used as one of the source electrode and drain electrode, and conductive layer 240 is used as the other of the source electrode and drain electrode.

[0348] Regarding transistor 200A, please refer to implementation method 1 ( Figures 1A to 8B The description in () is omitted here. Furthermore, the transistors included in the memory cell 150 are not limited to transistor 200A; the transistors shown in Embodiment 1 can also be used.

[0349] like Figures 15A to 15C As shown, transistor 200A overlaps with capacitor 100. Furthermore, the opening 290 where the transistor 200A is disposed has a region overlapping with the opening 190 where the capacitor 100 is disposed. Specifically, the conductive layer 120 serves as one of the source and drain electrodes of transistor 200A and as the upper electrode of capacitor 100, so transistor 200A and capacitor 100 share a common structure. By employing this structure, transistor 200A and capacitor 100 can be disposed in a manner that does not significantly increase the occupied area when viewed from above. Therefore, the occupied area of ​​memory cell 150 can be reduced, and the storage capacity of the memory device can be increased by arranging memory cells 150 at a high density. In other words, high integration of the memory device can be achieved.

[0350] Furthermore, by placing transistor 200A above capacitor 100, transistor 200A is not affected by the heat treatment during the manufacturing of capacitor 100. Therefore, the degradation of the electrical characteristics of transistor 200A, such as threshold voltage fluctuations and increased parasitic resistance, as well as the increase in uneven electrical characteristics caused by such degradation, can be suppressed.

[0351] and Figures 11A to 11C Similarly, in the structure shown, a conductive layer 221 can be provided between the conductive layer 120 and the semiconductor layer 230. By providing the conductive layer 221, the physical distance between the conductive layer 120 and the conductive layer 215 can be increased, thereby increasing the area of ​​the conductive layer 120 when viewed from above. Therefore, the electrostatic capacitance per unit area of ​​the capacitor 100 can be increased without increasing the depth of the opening 190.

[0352] Figure 22A A circuit diagram of the storage device shown in this embodiment is illustrated. Figure 22A As shown, Figures 15A to 15C The structure shown is used as a storage cell. Storage cell 951 includes transistor M1 and capacitor CA. Here, transistor M1 corresponds to transistor 200A, and capacitor CA corresponds to capacitor 100.

[0353] One of the source and drain terminals of transistor M1 is connected to one of the electrodes of capacitor CA. The other of the source and drain terminals of transistor M1 is connected to wiring BIL. The first gate of transistor M1 is connected to wiring WOL. The second gate of transistor M1 is connected to wiring BGL. The other of the electrodes of capacitor CA is connected to wiring CAL.

[0354] Here, routing BIL corresponds to conductive layer 240, routing WOL corresponds to conductive layer 260, routing BGL corresponds to conductive layer 215, and routing CAL corresponds to conductive layer 110. Furthermore, routing WOL and routing BGL can be interchanged. Conductive layer 260 can also be used as routing BGL, and conductive layer 215 can also be used as routing WOL.

[0355] like Figures 15A to 15C As shown, preferably, conductive layer 260 extends in the X direction and conductive layer 240 extends in the Y direction. With this structure, the wiring BIL and wiring WOL intersect each other. Furthermore, in Figure 15A In this embodiment, the wiring CAL (conductive layer 110) is configured as a planar structure, but the present invention is not limited thereto. For example, the wiring CAL may also be parallel to the wiring WOL (conductive layer 260) or the wiring BIL (conductive layer 240). In this specification and the like, planar refers to the case where a continuous layer is configured for use by multiple elements (e.g., memory cells configured in a matrix).

[0356] Note that the storage unit will be described in detail in the following implementation.

[0357] [Capacitor 100] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 120. Furthermore, a conductive layer 110 is disposed below the conductive layer 115. The conductive layer 115 has a region that contacts the conductive layer 110.

[0358] A conductive layer 110 is disposed on the insulating layer 140. The conductive layer 110 is used as a wiring CAL, and may be disposed in a planar manner, for example. As the conductive layer 110, a single layer or a stack of conductive materials described in [Conductive Layer] of Embodiment 1 can be used. As the conductive layer 110, for example, a highly conductive material such as tungsten can be used. By using a highly conductive material in this way, the conductivity of the conductive layer 110 can be improved, thereby enabling the conductive layer 110 to fully perform its function as a wiring CAL.

[0359] Furthermore, as the conductive layer 115, it is preferable to use a conductive material that is not easily oxidized, either as a single layer or in a stack, or a conductive material that has the function of suppressing oxygen diffusion. For example, titanium nitride or indium tin oxide with added silicon may also be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may also be used. Alternatively, for example, a structure in which first titanium nitride, tungsten, and second titanium nitride are stacked sequentially may also be used. By adopting this structure, oxidation of the conductive layer 110 due to the insulating layer 130 can be suppressed when an oxide insulating layer 130 is used as the insulating layer 130. Furthermore, oxidation of the conductive layer 110 due to the insulating layer 180 can be suppressed when an oxide insulating layer 180 is used as the insulating layer 180.

[0360] An insulating layer 130 is disposed on the conductive layer 115. The insulating layer 130 is disposed in such a way that it contacts the top surface and side surface of the conductive layer 115. That is, the insulating layer 130 preferably covers the side end of the conductive layer 110. This prevents short circuits between the conductive layer 115 and the conductive layer 120.

[0361] Alternatively, the side end of the insulating layer 130 can be aligned with the side end of the conductive layer 115. By employing this structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, thereby simplifying the manufacturing process of the storage device.

[0362] The insulating layer 130 preferably uses a material with a high relative permittivity (high-k). By using a high-k material for the insulating layer 130, the thickness of the insulating layer 130 can be increased to a level that can suppress leakage current and sufficiently ensure the electrostatic capacitance of the capacitor 100.

[0363] Furthermore, as the insulating layer 130, it is preferable to use an insulator made of a high-k material, and more preferably a laminate structure using a material with a high relative permittivity (high-k) and a material with a dielectric strength greater than that high-k material. For example, as the insulating layer 130, an insulating film in which zirconium oxide, alumina, and zirconium oxide are stacked sequentially can be used. Alternatively, for example, an insulating film in which zirconium oxide, alumina, zirconium oxide, and alumina are stacked sequentially can be used. Furthermore, for example, an insulating film in which hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina are stacked sequentially can be used. By using an insulating layer with a high dielectric strength, such as alumina, the dielectric strength can be increased, thereby suppressing electrostatic breakdown of the capacitor 100.

[0364] Furthermore, a ferroelectric material can also be used as the insulating layer 130. For details regarding ferroelectric materials, please refer to the description in Embodiment 1.

[0365] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nm, and are therefore preferred for use in the insulating layer 130. The thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, further preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). Furthermore, for example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, the capacitor 100 can be combined with miniaturized semiconductor elements such as transistors to form a semiconductor device.

[0366] Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when their area is extremely small, and are therefore preferred for insulating layer 130. For example, the ferroelectric layer can have an area (occupied area) of 100 μm even when viewed from above. 2 Below, 10μm 2 Below, 1μm 2 Below or 0.1μm 2 The following can also exhibit ferroelectric properties. Furthermore, sometimes ferroelectric layers can exist even with a top-view area (occupied area) of 10000 nm. 2 Below or 1000nm 2 The following also exhibit ferroelectric properties. By reducing the area of ​​the ferroelectric layer, the occupied area of ​​the capacitor 100 can be reduced.

[0367] Ferroelectric materials are insulators that exhibit the property of becoming polarized internally under the influence of an applied electric field and maintaining this polarization even when the electric field is zero. Therefore, non-volatile storage elements can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) with this material as the dielectric. Non-volatile storage elements using ferroelectric capacitors are sometimes called FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, with one of the source and drain terminals of the transistor electrically connected to a terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as capacitor 100, the storage device shown in this embodiment is used as a ferroelectric memory.

[0368] The conductive layer 120 is disposed in contact with a portion of the top surface of the insulating layer 130. Furthermore, the side portion of the conductive layer 120 is preferably located inside the side portion of the conductive layer 115 in both the X and Y directions. Note that in a structure where the insulating layer 130 covers the side portion of the conductive layer 115, the side portion of the conductive layer 120 may also be located outside the side portion of the conductive layer 115.

[0369] The conductive layer 120 can be a single layer or a stack of conductive materials described in [Conductive Layer] of Embodiment 1. Preferably, the conductive layer 120 is made of a conductive material that is not easily oxidized or has the function of suppressing oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. Furthermore, for example, a structure in which tantalum nitride is stacked on titanium nitride may also be used. In this case, titanium nitride is in contact with the insulating layer 130, and tantalum nitride is in contact with the semiconductor layer 230. By adopting this structure, excessive oxidation of the conductive layer 120 due to the semiconductor layer 230 can be suppressed. Furthermore, when an oxide insulating layer is used as the insulating layer 130, excessive oxidation of the conductive layer 120 due to the insulating layer 130 can be suppressed. Alternatively, the conductive layer 120 may, for example, have a structure in which tungsten is stacked on titanium nitride.

[0370] Because the conductive layer 120 has a region in contact with the semiconductor layer 230, it is preferable to use an oxygen-containing conductive material. By using an oxygen-containing conductive material as the conductive layer 120, conductivity can be maintained even if the conductive layer 120 absorbs oxygen. Furthermore, when an oxygen-containing insulating layer such as zirconium oxide is used as the insulating layer 130, the conductive layer 120 can also maintain conductivity, which is also preferred. For example, a single layer or a stack of materials such as ITO, ITSO, and IZO (registered trademark) can be used as the conductive layer 120.

[0371] Insulating layers 180 and 181 are used as interlayer films, so their relative permittivity is preferably low. By using a material with a low relative permittivity in the interlayer film, parasitic capacitance generated between wirings can be reduced. As insulating layers 180 and 181, single layers or stacks of insulating layers containing materials with low relative permittivity can be used. Silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0372] Note that in Figure 15B and Figure 15C The diagram shows insulating layers 180 and 181 as single-layer structures, but the invention is not limited thereto. Insulating layer 180 may also have a two-layer stacked structure, or a three-layer or more stacked structure. Insulating layer 181 may also have a two-layer or more stacked structure.

[0373] <Example 2 of storage device structure> The memory cell 150, including transistor 200A and capacitor 100, shown in this embodiment, can be used as a memory cell of a memory device. An OS transistor is preferably used as transistor 200A. Because transistor 200A has a small off-state current, its use in a memory device allows for long-term retention of stored content. In other words, since refresh operations are not required or occur at extremely low frequencies, the power consumption of the memory device can be significantly reduced. Furthermore, due to the high frequency characteristics of transistor 200A, high-speed read and write operations of the memory device are possible.

[0374] A storage cell array can be constructed by arranging the storage cells 150 in a three-dimensional and matrix manner.

[0375] Figure 16A This is a floor plan of the storage device. Figure 16A An example is shown where two × two storage cells (storage cells 150a to 150d) are arranged in the X and Y directions.

[0376] Figure 16B It is along Figure 16A The cross-sectional view shown is along the dashed-dot line A3-A4. Figure 16A and Figure 16B In the middle, two storage units (in Figure 16B In this configuration, storage cells 150a and 150b are connected to a common wiring (conductive layer 246).

[0377] Here, Figure 16A and Figure 16B The memory cells 150a and 150b shown both have the same structure as memory cell 150. Memory cell 150a includes a capacitor 100a and a transistor 200a, and memory cell 150b includes a capacitor 100b and a transistor 200b. Furthermore, Figure 16AThe storage cells 150c and 150d shown also have the same structure as storage cell 150. Therefore, in Figure 16A and Figure 16B In the storage device shown, for those having the same Figures 15A to 15C Components with the same function as those in the shown storage device are marked with the same symbols. Furthermore, for details regarding storage cells 150a to 150d, please refer to the description of storage cell 150 in <Example 1 of Storage Device Structure>.

[0378] like Figure 16A and Figure 16B As shown, conductive layers 260, which serve as part of the wiring WOL, are respectively disposed in memory cells 150a and 150b. Furthermore, as... Figure 16A As shown, a conductive layer 260 is provided between storage cells 150a and 150c, and another conductive layer 260 is provided between storage cells 150b and 150d. Furthermore, conductive layers 215, serving as part of the wiring BGL, are respectively provided in storage cells 150a and 150b. Additionally, a conductive layer 215 is provided between storage cells 150a and 150c, and another conductive layer 215 is provided between storage cells 150b and 150d. Furthermore, a conductive layer 240, serving as part of the wiring BIL, is provided between storage cells 150a and 150b. Additionally, another conductive layer 240 is provided between storage cells 150c and 150d.

[0379] exist Figure 16A In this configuration, conductive layers 260 and 215 are arranged to extend in the X direction, and conductive layer 240 is arranged to extend in the Y direction. Parasitic capacitance is generated in each of the following regions: the region where conductive layer 240 overlaps with conductive layer 260 (also called the first region), the region where conductive layer 260 overlaps with conductive layer 215 (also called the second region), and the region where conductive layer 215 overlaps with conductive layer 240 (also called the third region). When parasitic capacitance is generated, the operating speed of the transistor may slow down and the frequency characteristics of the circuit may degrade.

[0380] Therefore, it is preferable to arrange the conductive layer 215 in a manner that differs from the extension directions of the conductive layer 260 and the conductive layer 240 when viewed from above. In other words, it is preferable to arrange the conductive layer 215 in a manner that the extension direction of the conductive layer 215 is inclined to each of the X and Y directions when viewed from above. For example, as Figure 17AAs shown, the conductive layer 215 is preferably provided with an angle of 45 degrees between the extension direction of the conductive layer 215 and the extension direction (X direction) of the conductive layer 260, and an angle of 45 degrees between the extension direction of the conductive layer 215 and the extension direction (Y direction) of the conductive layer 240. Figure 17A This is a layout diagram illustrating the storage device. Additionally, in Figure 17A In the diagram, angle θ260 represents the angle between the extension direction of conductive layer 215 and the extension direction of conductive layer 260, and angle θ240 represents the angle between the extension direction of conductive layer 215 and the extension direction of conductive layer 240.

[0381] Here, in Figure 17A In the diagram, a double-headed arrow with a double-dotted line represents the distance GP between adjacent memory cells 150 in the Y direction. For example, distance GP refers to the spacing between memory cells 150 arranged in the Y direction. Distance GP can be described as the center-to-center distance between adjacent openings 290 in the Y direction. Additionally, distance GP can be described as the spacing of the conductive layer 260 used as wiring WOL. Therefore, distance GP can be referred to as gate pitch.

[0382] In addition, Figure 17A In the diagram, a double-headed dotted arrow indicates the distance MP between adjacent memory cells 150 in the X direction. For example, distance MP refers to the spacing between memory cells 150 arranged in the X direction. Distance MP can be described as the center-to-center distance between adjacent openings 290 in the X direction. Additionally, distance MP can be described as the spacing of the conductive layers 240 used as wiring BILs. Therefore, distance MP can be referred to as metal pitch.

[0383] in addition, Figure 17A The structure is shown where the distance GP is the same as the distance MP.

[0384] In addition, Figure 17A In the diagram, area S150 represents the area occupied by storage unit 150.

[0385] Furthermore, regarding the structure in which the conductive layer 215 is positioned such that its extension direction is aligned with the extension direction (X direction) of the conductive layer 260, please refer to [reference needed]. Figure 16A .

[0386] Here, it is assumed that the parasitic capacitance generated in the first region, the second region, and the third region all have the same unit area. Under this assumption, by setting the conductive layer 215 in a manner that minimizes the sum of the areas of the first, second, and third regions, the sum of the parasitic capacitance generated in the first, second, and third regions can be minimized. Hereinafter, the sum of the areas of the first, second, and third regions is sometimes referred to as the total area.

[0387] In the structure where the conductive layer 215 extends in the same direction as the conductive layer 260 (X direction), the ratios of the areas of the first region, the second region, and the third region to the area S150 are 0.25, 0.50, and 0.25, respectively. Therefore, the ratio to the total area S150 is 1. On the other hand, in the structure where both angles θ260 and θ240 are 45 degrees, the ratios of the areas of the first region, the second region, and the third region to the area S150 are 0.25, 0.35, and 0.35, respectively. Therefore, the ratio to the total area S150 is 0.95. Thus, under the above assumptions, by setting the conductive layer 215 with both angles θ260 and θ240 being 45 degrees, parasitic capacitance can be reduced, thereby improving the operating speed of the storage device.

[0388] Figure 17B This is a layout diagram of a storage device in which the spacing of the conductive layer 215 is the same as the distance from GP and the distance from MP. Figure 17B Similarly, the structure in which the conductive layer 215 is arranged with both angles θ260 and θ240 being 45 degrees is also shown. Note that... Figure 17B The distance GP shown is Figure 17A The distance shown is 1.41 times that of GP. Figure 17B The distance MP shown is Figure 17A The distance shown is 1.41 times that of MP.

[0389] In the structure where the conductive layer 215 extends in the same direction as the X-direction, the ratios of the areas of the first region, the second region, and the third region to the area S150 are 0.13, 0.35, and 0.13, respectively. Therefore, the ratio to the total area of ​​S150 is 0.60. On the other hand, in the structure where the conductive layer 215 is arranged with both angles θ260 and θ240 being 45 degrees, the ratios of the areas of the first region, the second region, and the third region to the area S150 are 0.13, 0.18, and 0.18, respectively. Therefore, the ratio to the total area of ​​S150 is 0.48. Thus, under the above assumptions, by arranging the conductive layer 215 with both angles θ260 and θ240 being 45 degrees, parasitic capacitance can be reduced, thereby improving the operating speed of the storage device. Note that because the ratios of areas described in this specification are rounded to the third decimal place, the sum of the ratios of the individual areas may not always be the same as the ratio of the total area.

[0390] Figure 17A and Figure 17B The storage cells 150 are shown in a matrix configuration. Figure 18 Another example of a planar layout of a storage device is shown. Here, the storage cell adjacent to the first storage cell in the X direction is referred to as the second storage cell, and the storage cell connected to the conductive layer 260 adjacent to the conductive layer 260 connecting the first and second storage cells in the Y direction and having an equal distance from the first and second storage cells is referred to as the third storage cell. Figure 18 In this configuration, the third storage cell is located on a straight line passing between the first and second storage cells and parallel to the Y direction. Alternatively, it can be said that the third storage cell is located at a position offset by half in the X direction from the positions of the first and second storage cells.

[0391] Figure 18 The diagram shows a structure in which the conductive layer 240 is inclined at the Y-direction in its extension direction. Specifically, the conductive layer 240 is arranged such that the angle between its extension direction and the Y-direction is 30 degrees. Furthermore, Figure 18 The structure shown has a distance GP and a distance MP that are the same, and the spacing of the conductive layer 215 is the same as that of the distance GP and the distance MP.

[0392] exist Figure 18In the structure shown, it is preferable that the conductive layer 215 is arranged in a manner where, when viewed from above, the extending direction of the conductive layer 215 differs from the extending directions of the conductive layer 260 and the conductive layer 240. In the structure where the extending direction of the conductive layer 215 is aligned with the extending direction (X direction) of the conductive layer 260, the ratios of the areas of the first region, the second region, and the third region to the area S150 are 0.17, 0.50, and 0.17, respectively. Therefore, the ratio to the total area S150 is 0.83. On the other hand, in the structure where both angles θ260 and θ240 are 60 degrees, the ratios of the areas of the first region, the second region, and the third region to the area S150 are 0.17, 0.17, and 0.17, respectively. Therefore, the ratio to the total area S150 is 0.50. Therefore, under the above assumption, by setting the conductive layer 215 with both angles θ260 and θ240 being 60 degrees, parasitic capacitance can be reduced, thereby improving the operating speed of the storage device.

[0393] Thus, it is preferable to arrange the conductive layer 215 in a different manner from each of the extension directions of the conductive layer 260 and the conductive layer 240 when viewed from above.

[0394] Figure 16A and Figure 16B The illustrated storage device includes conductive layers 245 and 246 electrically connected to storage cells 150a and 150b, serving as plugs (or connection electrodes). Conductive layer 245 is disposed within openings formed in insulating layers 140, 180, 130, 181, 280, and 281 and contacts the bottom surface of conductive layer 240. Furthermore, conductive layer 246 is disposed within openings formed in insulating layers 287, 283, 250, and semiconductor layer 230 and contacts the top surface of conductive layer 240. Conductive materials suitable for conductive layer 240 can be used as conductive layers 245 and 246.

[0395] Insulating layer 287 is used as an interlayer film, so its relative permittivity is preferably low. By using a material with a low relative permittivity for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0396] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 287 is preferably reduced. This can suppress the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 230.

[0397] Conductive layers 245 and 246 are used as plugs or wiring for electrically connecting circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, as well as for wiring, electrodes, or terminals, to memory cells 150a and 150b. For example, a structure can be adopted where conductive layer 245 is connected to the plug or wiring of memory cells 150a and 150b. Figure 16B The read amplifier (not shown) under the storage device is electrically connected, and the conductive layer 246 is disposed with the read amplifier (not shown) under the storage device. Figure 16B The same storage device (not shown) is electrically connected to the storage device shown. In this case, conductive layers 245 and 246 are used as part of the wiring BIL. Thus, by... Figure 16B By placing storage devices on top of or below the storage device shown, the storage capacity per unit area can be increased.

[0398] Furthermore, memory cells 150a and 150b are linearly symmetrical about the perpendicular bisector of the dashed line A3-A4. Therefore, transistors 200a and 200b are also arranged linearly symmetrically, sandwiching conductive layers 245 and 246. Here, conductive layer 240 serves as one of the source and drain electrodes of transistor 200a and another of the source and drain electrodes of transistor 200b. Moreover, transistors 200a and 200b share conductive layers 245 and 246, which act as a connector. Thus, by employing the above structure as a connection between two transistors and a connector, a memory device capable of miniaturization or high integration can be provided.

[0399] Furthermore, the conductive layer 110 used for wiring CAL can be disposed separately in memory cells 150a and 150b, or it can be disposed together in memory cells 150a and 150b. Note that, as Figure 16B As shown, the conductive layer 110 is disposed separately from the conductive layer 245 to prevent short circuit between the conductive layer 110 and the conductive layer 245.

[0400] also, Figure 19 This shows n layers (n is an integer greater than or equal to 3) stacked along the Z direction. Figure 16A The example shown is of four storage units. Figure 19 It is along Figure 16A The cross-sectional view shown is the dotted-dash line A3-A4.

[0401] Figure 19The storage device shown includes an n-layer storage layer 160. Specifically, a storage layer 160[2] is disposed on storage layer 160[1], and (n-3) layers of storage layers are disposed on storage layer 160[2], with storage layer 160[n] being the topmost layer. There is no particular limitation on the number of storage cells included in a single storage layer 160, and it may include more than two storage cells. The storage cells included in the n-layer storage layer 160 are electrically connected to a readout amplifier (not shown) disposed under the n-layer storage layer 160 through conductive layers 245, 246, and 247.

[0402] like Figure 19 As shown, by stacking multiple storage cells, the cells can be configured in an integrated manner without increasing the footprint of the storage cell array. In other words, a 3D storage cell array can be constructed.

[0403] Figure 20 An example of a cross-sectional structure of a storage device having a layer containing memory cells stacked on top of a drive circuit including a sense amplifier is shown.

[0404] exist Figure 20 In the middle, the storage cell 150 (transistor 200A and capacitor 100) is disposed above the transistor 300.

[0405] Transistor 300 is one of the transistors included in the sense amplifier.

[0406] about Figure 20 The storage unit 150 shown can be referred to in the description of storage unit 150 in <Example 1 of the structure of storage device>.

[0407] like Figure 20 As shown, by employing a structure in which the read amplifier is arranged overlapping the memory cell 150, the bit line can be shortened. This reduces the bit line capacitance, thereby enabling high-speed driving of the memory device.

[0408] Figure 20 The storage device shown can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, transistor 300 corresponds to the transistor included in the sense amplifier 927 in semiconductor device 900. Furthermore, storage cell 150 corresponds to storage cell 950.

[0409] Transistor 300 is disposed on substrate 311 and includes a conductive layer 316 serving as a gate, an insulating layer 315 serving as a gate insulator, a semiconductor region 313 formed by a portion of substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. Transistor 300 may be p-channel or n-channel.

[0410] Here, in Figure 20 In the transistor 300 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductive layer 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulating layer 315 in between. The conductive layer 316 can also be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 300 is also called a FIN-type transistor. Furthermore, an insulating layer for forming the convex portion can be provided in contact with the upper surface of the convex portion. Although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0411] Notice, Figure 20 The structure of transistor 300 shown is only an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0412] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be provided depending on the design. Here, in conductive layers that function as plugs or wiring, the same symbol is sometimes used to represent multiple structures. Furthermore, in this specification, wiring and plugs electrically connected to wiring can also be considered as a single component. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a plug.

[0413] For example, on transistor 300, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductive layers 328 are embedded in insulating layers 320 and 322, and conductive layers 330 are embedded in insulating layers 324 and 326. Additionally, conductive layers 328 and 330 are used as connectors or wiring.

[0414] Furthermore, the insulating layer used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulating layer 322, its top surface can also be planarized by a planarization process using CMP or the like.

[0415] Alternatively, a wiring layer can be formed on the insulating layer 326 and the conductive layer 330. For example, in Figure 20 In the middle, insulating layers 350, 352, and 354 are stacked in sequence. Furthermore, a conductive layer 356 is formed in insulating layers 350, 352, and 354. The conductive layer 356 is used as a plug or wiring.

[0416] The insulating layers described above, which can be used in semiconductor devices or storage devices, can be used as insulating layers 352 and 354, which are used as interlayer films.

[0417] As conductive layers used as plugs or wiring, such as conductive layers 328, 330, and 356, conductive materials suitable for conductive layer 240 can be used. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred; tungsten is particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0418] The conductive layer 240 included in transistor 200A is electrically connected to the low-resistance region 314b, which serves as the source or drain region of transistor 300, through conductive layers 643, 642, 644, 645, 646, 356, 330, and 328.

[0419] Conductive layer 643 is embedded in insulating layers 280 and 281. Conductive layer 642 is disposed on insulating layer 130 and embedded in insulating layer 641. Conductive layer 642 can be manufactured using the same materials and processes as conductive layer 120. Conductive layer 644 is embedded in insulating layers 180 and 130. Conductive layer 645 is embedded in insulating layer 647. Conductive layer 645 can be manufactured using the same materials and processes as conductive layer 110. Conductive layer 646 is embedded in insulating layer 648. Transistor 300 and conductive layer 110 are electrically insulated by insulating layer 648.

[0420] As described above, the storage device of this embodiment includes transistors that reduce parasitic capacitance, thereby improving operating speed. Furthermore, because capacitors and transistors are stacked in the storage device of this embodiment, the area occupied by the storage cells when viewed from above can be reduced, thus enabling a highly integrated storage device.

[0421] This implementation method can be appropriately combined with other implementation methods.

[0422] (Implementation Method 3) In this embodiment, a semiconductor device 900 according to one aspect of the present invention is described. The semiconductor device 900 can be used as a storage device.

[0423] Figure 21 This is a block diagram illustrating a structural example of a semiconductor device 900. Figure 21 The semiconductor device 900 shown includes a driving circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Figure 21 An example of a memory array 920 including multiple memory cells 950 configured in a matrix is ​​shown.

[0424] As storage unit 950, the storage device (storage unit 150, etc.) described in Embodiment 2 can be used.

[0425] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and peripheral circuit 915. The peripheral circuit 915 includes peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0426] In the semiconductor device 900, the aforementioned circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0427] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Furthermore, signals PON1 and PON2 can also be generated in the control circuit 912.

[0428] The control circuit 912 is a logic circuit that controls the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 to execute the aforementioned operating mode.

[0429] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 928. For example, when the signal WAKE is given a signal of level H, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0430] The peripheral circuit 911 is used to write and read data from the storage unit 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0431] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row to be connected to by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0432] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data written to memory cell 950 (Din). The data read from memory cell 950 by column driver 924 (Dout) is output to output circuit 926. Output circuit 926 has the function of holding Dout. In addition, output circuit 926 has the function of outputting Dout to the outside of semiconductor device 900. The data signal output from output circuit 926 is signal RDA.

[0433] PSW931 controls the supply of V to the external circuit 915. DD The PSW932 has the function of controlling the supply of V to the line driver 923. HM The function of the semiconductor device 900. Here, the high power supply potential of the semiconductor device 900 is V. DD The low power supply potential is GND (ground potential). Additionally, V HM It is a high power supply potential used to make the word line high, which is higher than V. DD The PSW931 is controlled to turn on / off using signal PON1, and the PSW932 is controlled to turn on / off using signal PON2. Figure 21 In the middle, the peripheral circuit 915 is supplied with V DD The number of power domains can be 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0434] Reference Figures 22A to 22H This section describes an example of the structure of a storage cell that can be used in storage cell 950.

[0435] The following discussion of connecting two components includes cases where they are electrically connected via circuit elements (transistors, switches, diodes, resistors, etc.). An electrical connection refers to a state where current can flow between two components. Furthermore, when two components are connected via a switch or transistor, current can flow even when the switch or transistor is in the ON state; therefore, this is also included within the scope of an electrical connection.

[0436] [DOSRAM] Figure 22AAn example circuit structure of a DRAM-type memory cell is shown. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 951 includes transistor M1 and capacitor CA.

[0437] Transistor M1 includes a gate (sometimes called the top gate) and a back gate. In this case, the back gate can also be connected to a wiring supplied with a constant potential or signal, and the front gate can also be connected to the back gate.

[0438] The first terminal of transistor M1 is connected to the first terminal of capacitor CA. The second terminal of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor CA is connected to wiring CAL.

[0439] Wiring BIL is used as the bit line, and wiring WOL is used as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CA. During data writing and reading, it is preferable to apply a low-level potential (sometimes called the reference potential) to wiring CAL. Wiring BGL is used to apply a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0440] Data writing and reading are performed by applying a high-level potential to the wiring WOL to turn on the transistor M1, thereby making the wiring BIL and the first terminal of the capacitor CA conductive (allowing current to flow).

[0441] Furthermore, the memory cell that can be used as memory cell 950 is not limited to memory cell 951, and the circuit structure can be changed. For example, in memory cell 950, the back gate of transistor M1 can be connected to wiring WOL instead of wiring BGL. Additionally, for example, memory cell 950 can also be composed of a single-gate transistor, i.e., a transistor M1 without a back gate.

[0442] In addition, for example, it can also be used Figure 22B The storage cell 952 is shown. Storage cell 952 is an example excluding capacitor CA and wiring CAL. The first terminal of transistor M1 is in a floating state.

[0443] In memory cell 952, the potential written by transistor M1 is maintained in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0444] An OS transistor is preferably used as transistor M1. OS transistors have the characteristic of extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. That is, transistor M1 can hold written data for a long time, thereby reducing the refresh frequency of the memory cell. Alternatively, the refresh operation of the memory cell can be omitted. Furthermore, because the leakage current is very small, multi-valued data or analog data can be held in memory cells 951 and 952.

[0445] [NOSRAM] Figure 22C An example circuit structure of a gain-cell type memory cell including two transistors and one capacitor is shown. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and the like, a memory device including a gain-cell type memory cell that uses transistor OS for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0446] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; transistor M2's gate is connected to wiring WOL; and transistor M2's back gate is connected to wiring BGL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0447] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a predetermined potential to the second terminal of capacitor CB. During data writing, data holding, and data reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0448] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M2 and thus connects wiring WBL to the first terminal of capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL to write that potential to the first terminal of capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL, which turns off transistor M2, thereby maintaining the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3.

[0449] Data is read out by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate and the second terminal of transistor M3, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0450] For example, a structure that combines the wiring WBL and wiring RBL into a single wiring BIL can also be adopted. Figure 22D An example of the circuit structure of the memory cell in this case is shown. In memory cell 954, the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. That is, memory cell 954 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0451] Figure 22E The memory cell 955 shown is an example where the capacitor CB and wiring CAL of memory cell 953 are omitted. Furthermore, Figure 22F The memory cell 956 shown is an example of omitting the capacitor CB and wiring CAL found in memory cell 954. This structure improves the integration density of the memory cells.

[0452] Note that it is preferable to use the OS transistor as at least as transistor M2. In particular, it is preferable to use the OS transistor as both transistor M2 and transistor M3.

[0453] Because the OS transistor has extremely low off-state current, transistor M2 can be used to hold written data for a long time, thereby reducing the refresh frequency of the memory cell. Alternatively, the refresh operation of the memory cell can be omitted. In addition, due to the very low leakage current, multi-valued or analog data can be held in memory cells 953, 954, 955, and 956.

[0454] The memory cells 953, 954, 955, and 956, which use OS transistors as transistor M2, are a type of NOSRAM.

[0455] Si transistors can also be used as transistor M3. Si transistors can improve field-effect mobility and can be p-channel transistors, thus increasing the freedom of circuit design.

[0456] Furthermore, when the OS transistor is used as transistor M3, the memory cell can be constructed from a unipolar circuit.

[0457] also, Figure 22G A gain-cell type memory cell 957 with three transistors and one capacitor is shown. The memory cell 957 includes transistors M4 to M6 and capacitor CC.

[0458] Transistor M4's first terminal is connected to capacitor CC's first terminal. Transistor M4's second terminal is connected to wiring BIL. Transistor M4's gate is connected to wiring WOL. Transistor M4's back gate is connected to wiring BGL. Capacitor CC's second terminal is connected to transistor M5's first terminal and wiring GNDL. Transistor M5's second terminal is connected to transistor M6's first terminal, and transistor M5's gate is connected to capacitor CC's first terminal. Transistor M6's second terminal is connected to wiring BIL, and transistor M6's gate is connected to wiring RWL.

[0459] The BIL (Bite Line) is used as the bit line, the WOL (Write Word Line) is used as the write word line, and the RWL (Read Word Line) is used as the read word line. The GNDL (Ground Node Line) is used to supply a low-level potential.

[0460] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M4 and connects wiring BIL to the first terminal of capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to wiring BIL to write that potential to the first terminal of capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to wiring WOL, which turns off transistor M4, thereby maintaining the potential of the first terminal of capacitor CC and the potential of the gate of transistor M5.

[0461] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high-level potential to the wiring RWL. By making the wiring RWL high, transistor M6 is turned on, and the wiring BIL and the second terminal of transistor M5 are connected. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL will change correspondingly to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0462] Note that it is preferable to use the OS transistor as at least transistor M4.

[0463] Si transistors can also be used as transistors M5 and M6. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystal state of the silicon used in the semiconductor layer.

[0464] Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be constructed from unipolar circuits.

[0465] [OS-SRAM] Figure 22H An example of SRAM (Static Random Access Memory) using OS transistors is shown. In this specification, etc., SRAM using OS transistors will be referred to as OS-SRAM (Oxide Semiconductor-SRAM). Furthermore, Figure 22H The storage unit 958 shown is an SRAM-type storage unit capable of backup.

[0466] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, capacitor CD1, and capacitor CD2. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0467] Transistor M7's first terminal is connected to wiring BIL. Transistor M7's second terminal is connected to the first terminal of transistors MS1 and MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. Transistor M7's gate is connected to wiring WOL. Transistor M8's first terminal is connected to wiring BILB. Transistor M8's second terminal is connected to the first terminal of transistors MS2 and MS4, the gate of transistor MS1 and MS3, and the first terminal of transistor M9. Transistor M8's gate is connected to wiring WOL.

[0468] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0469] The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, and the gate of transistor M9 is connected to the wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, and the gate of transistor M10 is connected to the wiring BRL.

[0470] The second terminal of capacitor CD1 is connected to wiring GNDL, and the second terminal of capacitor CD2 is also connected to wiring GNDL.

[0471] The BIL and BILB wirings are used as bit lines, the WOL wiring is used as word lines, and the BRL wiring is used to control the on and off states of transistors M9 and M10.

[0472] Wiring VDL provides a high-level potential, and wiring GNDL provides a low-level potential.

[0473] Data is written by applying a high-level potential to the wiring WOL and the wiring BRL. Specifically, when transistor M10 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the second terminal side of transistor M10.

[0474] Storage cell 958 uses transistors MS1 to MS2 to form an inverter loop, so the inverted signal of the data signal corresponding to this potential is input to the second terminal of transistor M8. Since transistor M8 is in the on state, the potential applied to wiring BIL, that is, the inverted signal of the signal input to wiring BIL, is output to wiring BILB. In addition, since transistors M9 and M10 are in the on state, the potentials of the second terminals of transistor M7 and transistor M8 are maintained by the first terminals of capacitor CD2 and capacitor CD1, respectively. Then, by applying a low-level potential to wiring WOL and a low-level potential to wiring BRL to turn off transistors M7 to M10, the potentials of the first terminals of capacitor CD1 and capacitor CD2 are maintained.

[0475] Data readout is performed as follows: First, the wiring BIL and wiring BILB are pre-charged to a predetermined potential. Then, a high-level potential is applied to wiring WOL and wiring BRL. This causes the potential of the first terminal of capacitor CD1 to be refreshed by the inverter loop of storage cell 958 and output to wiring BILB. Similarly, the potential of the first terminal of capacitor CD2 is refreshed by the inverter loop of storage cell 958 and output to wiring BIL. Since wiring BIL and wiring BILB change from their pre-charged potentials to the potentials of the first terminals of capacitor CD2 and capacitor CD1, respectively, the potential held by the storage cell can be read from the potentials of wiring BIL or wiring BILB.

[0476] Transistors M7 to M10 are preferably OS transistors. This allows transistors M7 to M10 to hold written data for an extended period, thus reducing the refresh frequency of the memory cell. Alternatively, the refresh operation of the memory cell can be omitted. Note that in Figure 22H The description of the back gates of transistors M7 to M10 is omitted.

[0477] Furthermore, Si transistors are preferably used as transistors MS1 to MS4.

[0478] The driving circuitry 910 and the memory array 920 of the semiconductor device 900 are disposed on the same plane. Furthermore, as... Figure 23A As shown, the driving circuit 910 and the memory array 920 can also overlap. By overlapping the driving circuit 910 and the memory array 920, the signal transmission distance can be shortened. Figure 23B As shown, multiple memory arrays 920 can also be stacked on the drive circuit 910.

[0479] Next, an example of an arithmetic processing device that may include the aforementioned storage device or other semiconductor device will be described.

[0480] Figure 24 This is a block diagram of the arithmetic unit 960. Figure 24 The computing device 960 shown can be used, for example, as a CPU. Furthermore, the computing device 960 can also be used with processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units), which have more (tens to hundreds) processor cores than a CPU capable of parallel processing.

[0481] Figure 24 The arithmetic unit 960 shown has the following components on a substrate 990: an ALU 991 (ALU: Arithmetic Logic Unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also include a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be located on different chips.

[0482] Cache 999 is connected to the main memory located on different chips via cache interface 989. Cache interface 989 has the function of supplying a portion of the data stored in the main memory to cache 999. In addition, cache interface 989 has the function of outputting a portion of the data held in cache 999 to ALU 991 or register 996, etc., via bus interface 998.

[0483] As described later, the memory array 920 can be arranged in a manner that stacks on the computing device 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 can have the function of supplying data held in the memory array 920 to the cache 999. Furthermore, in this case, it is preferable that a portion of the cache interface 989 includes a drive circuit 910.

[0484] Note that you can also use memory array 920 as a cache instead of setting cache 999.

[0485] Figure 24 The arithmetic device 960 shown is merely an example with a simplified structure; therefore, the actual arithmetic device 960 has various structures depending on its application. For example, it is preferable to include... Figure 24 The computing device 960 shown has a multi-core structure, which consists of a single core and multiple cores that operate simultaneously. The more cores, the better the computing performance. More cores are preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, and sixteen cores or more are even more preferred. Furthermore, when used in servers or other applications requiring very high computing performance, a multi-core structure with 16 or more cores is preferred, more preferably 32 or more cores, and more preferably 64 or more cores. Additionally, the number of bits that can be processed in the internal computing circuitry, data bus, etc., of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0486] Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993 and, after being decoded, are input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0487] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing the program of the arithmetic unit 960, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask state. The register controller 997 generates the address of register 996 and reads and writes register 996 according to the state of the arithmetic unit 960.

[0488] Furthermore, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0489] exist Figure 24 In the arithmetic unit 960 shown, the register controller 997 selects the holding operation of register 996 according to instructions from ALU 991. In other words, the register controller 997 selects whether data is held in the memory cells of register 996 by flip-flops or by capacitors. When data is held by flip-flops, a power supply potential is supplied to the memory cells in register 996. When data is held by capacitors, the data is overwritten to the capacitors, and the power supply potential to the memory cells in register 996 can be stopped.

[0490] The memory array 920 and the arithmetic unit 960 can be arranged overlappingly. Figure 25A and Figure 25B This is a perspective view of semiconductor device 970A. Semiconductor device 970A includes a layer 930 on a computing device 960, on which memory arrays are disposed. Layer 930 houses memory arrays 920L1, 920L2, and 920L3. The computing device 960 and each memory array have overlapping areas. To facilitate understanding of the structure of semiconductor device 970A, in... Figure 25B The computing device 960 and the layer 930 are shown separately in the middle.

[0491] By overlapping the layer 930, which includes the memory array, and the computing device 960, the connection distance between them can be shortened. This improves the communication speed between them. Furthermore, the shorter connection distance reduces power consumption.

[0492] As a stacking method for the layer 930 including the memory array and the arithmetic device 960, the following methods can be used: directly stacking the layer 930 including the memory array on the arithmetic device 960 (also called monolithic stacking); or forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates together, and electrically connecting them using bonding techniques such as through-holes or conductive films (Cu-Cu bonding, etc.). The former method does not require consideration of misalignment during bonding, thus reducing both chip size and manufacturing costs.

[0493] Here, the memory arrays 920L1, 920L2, and 920L3, which do not include cache 999 in the arithmetic unit 960 and are disposed in layer 930, can all be used as caches. For example, memory arrays 920L1, 920L2, and 920L3 can be used as L1 cache (also called level 1 cache), L2 cache (also called level 2 cache), and L3 cache (also called level 3 cache), respectively. Among the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, memory array 920L1 has the smallest capacity and the highest access frequency.

[0494] Note that when the cache 999 in the arithmetic unit 960 is used as an L1 cache, the memory arrays in layer 930 can be used as lower-level caches or main memory. Main memory is memory with a larger capacity and lower access frequency than cache.

[0495] In addition, such as Figure 25B As shown, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

[0496] Note that although the case shown here is a three-array memory array used as a cache, it can also be one, two, or more than four.

[0497] When the memory array 920L1 is used as a cache, the driver circuit 910L1 can also be used as part of the cache interface 989, and the driver circuit 910L1 can also be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 can also be used as part of the cache interface 989 or connected to a part of the cache interface 989.

[0498] Whether the memory array 920 is used as cache or as main memory depends on the control circuit 912 included in each drive circuit 910. The control circuit 912 can use a portion of the multiple memory cells 950 contained in the semiconductor device 900 as RAM based on signals supplied from the arithmetic unit 960.

[0499] In the semiconductor device 900, a portion of the multiple storage cells 950 can be used as cache and the remainder as main memory. That is, the semiconductor device 900 can function as both cache and main memory. The semiconductor device 900 according to one embodiment of the invention can, for example, be used as a general-purpose memory.

[0500] Alternatively, a layer 930 including a memory array 920 may be provided in a manner that overlaps with the computing device 960. Figure 26A This is a 3D view of the semiconductor device 970B.

[0501] In the semiconductor device 970B, a memory array 920 can be divided into multiple regions and assigned different functions for use. Figure 26A This shows an example of using region L1, region L2, and region L3 as L1 cache, L2 cache, and L3 cache, respectively.

[0502] Furthermore, in the semiconductor device 970B, the capacity of each of regions L1 to L3 can be changed according to the situation. For example, the capacity of the L1 cache can be increased by increasing the area of ​​region L1. By adopting this structure, efficient computational processing can be achieved, thereby increasing processing speed.

[0503] In addition, multiple memory arrays can be stacked. Figure 26B This is a 3D view of the semiconductor device 970C.

[0504] Semiconductor device 970C includes a layer 930L1 comprising a memory array 920L1, a layer 930L2 comprising a memory array 920L2, and a layer 930L3 comprising a memory array 920L3. The memory array 920L1, physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, physically furthest from the arithmetic unit 960, can be used as a lower-level cache or main memory. By employing this structure, the capacity of each memory array can be increased, thus further improving processing power.

[0505] This implementation method can be appropriately combined with other implementation methods.

[0506] (Implementation Method 4) This embodiment illustrates an example of the application of a storage device according to one aspect of the present invention.

[0507] Generally speaking, various storage devices are used in semiconductor devices such as computers, depending on their purpose. Figure 27A The various memory devices used in semiconductor devices are shown in a hierarchical manner. Higher-level memory devices are required to operate at faster speeds, while lower-level memory devices are required to have larger storage capacities and higher recording densities. Figure 27A In this context, from the topmost level, the cache includes memory installed as registers in processing devices such as the CPU, L1 cache, L2 cache, L3 cache, main memory, and secondary storage. Note that although an example including up to L3 cache is shown here, it may also include caches at lower levels.

[0508] Because memory installed along with registers in arithmetic processing devices such as CPUs is used for temporary storage of calculation results, it is accessed frequently by the processing device. Therefore, faster operating speed is required compared to storage capacity. Furthermore, registers also have the function of holding settings information of the processing device.

[0509] A cache is a system that copies and maintains a portion of the information held in main memory. By copying frequently used data to the cache, the speed of data access can be improved. A cache requires less storage capacity than main memory, but its operating speed is higher. Furthermore, data that is modified in the cache is copied and provisioned to main memory.

[0510] Main memory has the function of storing programs, data, etc. read from secondary storage.

[0511] Secondary storage serves to hold data that needs to be preserved long-term and various programs used by computing devices. Therefore, compared to faster operating speeds, secondary storage requires larger storage capacity and higher recording density. For example, high-capacity non-volatile storage devices such as 3D NAND can be used.

[0512] According to one aspect of the present invention, a storage device (OS memory) using oxide semiconductors operates at high speed and can retain data for long periods. Therefore, as Figure 27A As shown, a storage device according to one aspect of the present invention can be used for both a cache hierarchy and a main memory hierarchy. Furthermore, a storage device according to one aspect of the present invention can also be used for a secondary storage hierarchy.

[0513] also, Figure 27B Examples are shown of cases where SRAM is used for one part of the cache and OS memory of one aspect of the present invention is used for another part.

[0514] The lowest level cache can be referred to as LLC (Last Level cache). LLCs do not require faster operating speeds than their parent caches, but are required to have larger storage capacity. One embodiment of the OS memory of this invention has a fast operating speed and can retain data for long periods, making it suitable for LLCs. Note that one embodiment of the OS memory of this invention can also be used for FLCs (Final Level cache).

[0515] For example, such as Figure 27B As shown, SRAM can be used for higher-level caches (L1 cache, L2 cache, etc.) and the OS memory of one embodiment of the present invention can be used for LLC. Furthermore, as... Figure 27B As shown, DRAM can be used in main memory in addition to OS memory.

[0516] This implementation method can be appropriately combined with other implementation methods.

[0517] (Implementation Method 5) This embodiment describes a display device according to one aspect of the present invention.

[0518] One aspect of the semiconductor device of the present invention can be used in a display device or a module including the display device. Examples of modules including the display device include modules in which the display device is mounted with connectors such as flexible printed circuit boards (FPC) or TCP (Tape Carrier Package), and modules in which integrated circuits (ICs) are mounted via COG (Chip On Glass) or COF (Chip On Film) methods.

[0519] Furthermore, the display device of this embodiment may also have the function of a touch panel. For example, various detection elements (also called sensor elements) capable of detecting the approach or contact of a detection object such as a finger can be used in the display device.

[0520] For example, sensor types include electrostatic capacitive, resistive film, surface acoustic wave, infrared, optical, and pressure-sensitive types.

[0521] Examples of electrostatic capacitive sensors include surface-type and projected-type electrostatic capacitive sensors. Furthermore, projected-type electrostatic capacitive sensors include self-capacitance and mutual-capacitance sensors. Mutual-capacitance sensors are preferred, as they allow for simultaneous multi-point detection.

[0522] Examples of touch panels include Out-Cell, On-Cell, and In-Cell types. Note that an In-Cell touch panel refers to a structure in which electrodes constituting the detection element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0523] [Display Module] Figure 28A A perspective view of display module 170 is shown. Display module 170 includes display device 600A and FPC 298. Note that the display device included in display module 170 is not limited to display device 600A, but may also be display device 600B, which will be described later.

[0524] The display module 170 includes a substrate 291 and a substrate 299. The display module 170 includes a display section 297. The display section 297 is an image display area in the display module 170, and can display light from each pixel disposed in the pixel section 294 described below.

[0525] Figure 28B This is a three-dimensional schematic diagram of one side of the substrate 291. A circuit section 292, a pixel circuit section 293 on the circuit section 292, and a pixel section 294 on the pixel circuit section 293 are stacked on the substrate 291. Furthermore, a terminal section 295 for connecting to the FPC 298 is provided on the portion of the substrate 291 that does not overlap with the pixel section 294. The terminal section 295 is electrically connected to the circuit section 292 via a wiring section 296 composed of multiple wirings.

[0526] In one aspect of the present invention, the semiconductor device can be applied to one or both of the circuit section 292 and the pixel circuit section 293.

[0527] The pixel unit 294 includes a plurality of pixels 294a arranged periodically. Figure 28B The right side shows a magnified view of pixel 294a. Figure 28B An example is shown where a pixel 294a includes a sub-pixel 130R that emits red light, a sub-pixel 130G that emits green light, and a sub-pixel 130B that emits blue light.

[0528] Subpixels include display elements. Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electromechanical Systems) elements using shutter-based or light-interference methods, as well as display elements employing microencapsulation, electrophoresis, electrowetting, or electronic powder fluid methods (registered trademark), can be used. Furthermore, QLED (Quantum-dot LED) technology utilizing a light source and employing quantum dot materials for color conversion can also be used.

[0529] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, MiniLEDs and MicroLEDs can be used as LEDs.

[0530] There are no particular limitations on the arrangement of pixels in the display device of this embodiment, and various methods can be used. Examples of pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement. Figure 28B This shows an example of a pixel arrangement using stripes.

[0531] The pixel circuit section 293 includes a plurality of pixel circuits 293a arranged periodically.

[0532] A pixel circuit 293a controls the driving of multiple elements included in a pixel 294a. A pixel circuit 293a may contain three circuits controlling the emission of light from a single light-emitting element. For example, the pixel circuit 293a may employ a structure with at least one selection transistor, one current control transistor (driving transistor), and a capacitor for each light-emitting element. In this case, the gate of the selection transistor receives a gate signal, and the source receives a source signal. This realizes an active matrix display device.

[0533] The circuit section 292 includes circuitry for each pixel circuit 293a of the driving pixel circuit section 293. For example, it preferably includes one or both of a gate line driving circuit and a source line driving circuit. Furthermore, it may include at least one of an arithmetic circuit, a storage circuit, and a power supply circuit.

[0534] The FPC298 is used for wiring to supply video signals or power potentials from the outside to the circuit section 292. Additionally, ICs can be mounted on the FPC298.

[0535] The display module 170 can adopt a structure in which one or both of the pixel circuit section 293 and circuit section 292 are stacked on the lower side of the pixel section 294, so that the display section 297 can have an extremely high aperture ratio (effective display area ratio). In addition, the pixels 294a can be arranged at an extremely high density, thereby enabling the display section 297 to have extremely high resolution.

[0536] This high-definition display module 170 is suitable for use in VR devices such as HMDs or AR devices such as glasses. For example, because the display module 170 has an extremely high-definition display section 297, even when the display section of the display module 170 is magnified by a lens, the user cannot see any pixels, thereby achieving a highly immersive display. Furthermore, the display module 170 can also be applied to electronic devices with relatively small display sections. For example, it is suitable for use in the display sections of wearable electronic devices such as watch-type devices.

[0537] [Example 1 of a display device structure] Figure 29 This is a cross-sectional view of display device 600A. Display device 600A is an example of a display device employing an MML structure. That is, display device 600A includes light-emitting elements manufactured without high-precision metal masks.

[0538] In display devices employing the MML structure, the island-shaped light-emitting layers in the light-emitting elements are formed by photolithography after depositing a light-emitting layer across the entire surface. Therefore, it is possible to achieve high-definition or high-aperture-ratio display devices that have been difficult to achieve until now. Furthermore, since light-emitting layers can be formed separately for each color, extremely vivid, high-contrast, and high-quality display devices can be realized. For example, when using three light-emitting elements—one emitting blue light, one emitting green light, and one emitting red light—to construct a display device, three island-shaped light-emitting layers can be formed by repeatedly forming the light-emitting layers three times and using photolithography.

[0539] Because devices with MML structures can be manufactured without metal masks, the resolution limitations imposed by the alignment accuracy of metal masks can be exceeded. Furthermore, manufacturing devices without metal masks eliminates the need for equipment related to metal mask fabrication and the metal mask cleaning process. Additionally, in photolithography, the same equipment used in transistor manufacturing can be used, eliminating the need for specialized equipment for manufacturing devices with MML structures. Thus, by utilizing MML structures, manufacturing costs can be reduced, making them suitable for mass production.

[0540] In display devices with MML structures, it is not necessary to use special pixel arrangements such as Pentile arrangement to improve sharpness in a pseudo-method. Thus, a display device can be realized in which a so-called stripe arrangement in which each sub-pixel of R, G, and B is arranged in one direction and has high sharpness (e.g., 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more).

[0541] Furthermore, by providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element. The sacrificial layer can remain in the finished display device or be removed during the manufacturing process. For example, Figure 29 and Figure 30 The sacrificial layer 618a shown is part of the sacrificial layer disposed on the light-emitting layer.

[0542] Furthermore, by employing a deposition process using a range mask and a processing process using a resist mask, light-emitting elements can be manufactured with a simpler process.

[0543] Figure 29 The display device 600A shown is a cross-sectional schematic diagram of a display device (semiconductor device) according to one embodiment of the present invention. In the display device 600A, pixel circuits, driving circuits, etc., are disposed on the substrate 410. Figure 29 In the display device 600A, in addition to component layers 620, 630 and 660, a wiring layer 670 is also shown. The wiring layer 670 is a layer on which wiring is provided.

[0544] In component layer 630, pixel circuitry for the display device is preferably provided. In component layer 620, driving circuitry for the display device (one or both of gate driver and source driver) is preferably provided. Furthermore, in component layer 620, one or more types of circuitry such as arithmetic circuitry and memory circuitry may also be provided.

[0545] As an example, the element layer 620 includes a substrate 410 on which a transistor 400d is formed. Furthermore, a wiring layer 670 is disposed above the transistor 400d, and the wiring layer 670 contains a connection layer that allows the transistor 400d to connect with a conductive layer or transistor disposed in the element layer 630. Figure 29 The conductive layer 514 in the middle is electrically connected to the wiring. Furthermore, a component layer 630 and a component layer 660 are disposed above the wiring layer 670. Component layer 630 includes, for example, a transistor MTCK. Component layer 660 includes a light-emitting element 650. Figure 29 The light-emitting elements include 650R, 650G, and 650B.

[0546] Transistor 400d is an example of a transistor included in element layer 620. Furthermore, transistor MTCK is an example of a transistor included in element layer 630. Additionally, light-emitting elements (light-emitting element 650R, light-emitting element 650G, and light-emitting element 650B) are an example of light-emitting elements included in element layer 660.

[0547] As substrate 410, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium) can be used. Furthermore, besides semiconductor substrates, substrate 410 can also be, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate containing stainless steel foil, a tungsten substrate, a substrate containing tungsten foil, a flexible substrate, a laminated film, or a paper or substrate film containing fibrous material. In this embodiment, the case where substrate 410 is a semiconductor substrate containing silicon as a material is described. Therefore, the transistors in element layer 620 can be Si transistors.

[0548] Transistor 400d includes a device separation layer 412, a conductive layer 416, an insulating layer 415, an insulating layer 417, a semiconductor region 413 formed by a portion of a substrate 410, a low-resistance region 414a serving as a source region or a drain region, and a low-resistance region 414b. Therefore, transistor 400d is a Si transistor. Although Figure 29 The diagram shows a structure in which the source or drain of transistor 400d is electrically connected to conductive layer 514 disposed in element layer 630 via conductive layer 428, conductive layer 430 and conductive layer 456. However, the electrical connection structure of a display device according to one embodiment of the present invention is not limited to this.

[0549] Transistor 400d can be implemented as a Fin-type structure, for example, by employing a structure in which the top surface of semiconductor region 413 and the side surfaces in the channel width direction are covered by a conductive layer 416 with an insulating layer 415 serving as a gate insulating layer. By forming a Fin-type transistor 400d, the effective channel width can be increased, thus improving the on-state characteristics of transistor 400d. Furthermore, since the effect of the electric field at the gate electrode can be enhanced, the off-state characteristics of transistor 400d can be improved. Alternatively, transistor 400d can also have a planar structure without a Fin-type structure.

[0550] Furthermore, transistor 400d can be either a p-channel transistor or an n-channel transistor. Additionally, multiple transistors 400d can be provided, and both p-channel and n-channel transistors can be used.

[0551] The channel formation region of semiconductor region 413, the region theren, and the low-resistance regions 414a and 414b used as source or drain regions preferably comprise silicon-based semiconductors, specifically monocrystalline silicon. Alternatively, the aforementioned regions may also be formed using germanium, silicon-germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride, for example. Silicon with effective quality controlled by applying stress to the crystal lattice to change the interplanar spacing can be used. Furthermore, transistor 400d may, for example, be a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.

[0552] As the conductive layer 416 used as the gate electrode, a semiconductor material such as silicon containing elements that impart n-type conductivity, such as arsenic or phosphorus, or elements that impart p-type conductivity, such as boron or aluminum, can be used. Alternatively, as the conductive layer 416, conductive materials such as metallic materials, alloy materials, or metal oxide materials can be used.

[0553] Furthermore, since the work function is determined by the material of the conductive layer, the threshold voltage of the transistor can be adjusted by selecting the material of the conductive layer. Specifically, titanium nitride and tantalum nitride, or both, are preferably used as the conductive layer. In order to achieve both conductivity and embeddability, a stack of metal materials, tungsten and aluminum, or both, is preferably used as the conductive layer, especially tungsten in terms of heat resistance.

[0554] To separate the multiple transistors formed on the substrate 410 from each other, a device separation layer 412 is provided. The device separation layer can be formed, for example, using LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or mesa isolation.

[0555] Figure 29 An insulating layer 420 and an insulating layer 422 are sequentially stacked on the transistor 400d from the substrate 410 side.

[0556] As insulating layers 420 and 422, for example, one or more selected from silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, and aluminum nitride can be used.

[0557] The insulating layer 422 can also be used as a planarization film to flatten the steps generated by the transistor 400d, etc., which are covered by the insulating layer 420 and the insulating layer 422. For example, in order to improve flatness, the top surface of the insulating layer 422 can also be planarized by a planarization process using CMP or the like.

[0558] A conductive layer 428 is embedded in insulating layers 420 and 422, and is connected to transistors such as MTCK disposed above insulating layer 422. Furthermore, the conductive layer 428 functions as a connector or wiring.

[0559] In the display device 600A, a wiring layer 670 is provided on the transistor 400d. The wiring layer 670 includes, for example, an insulating layer 424, an insulating layer 426, a conductive layer 430, an insulating layer 450, an insulating layer 452, an insulating layer 454, and a conductive layer 456.

[0560] Insulating layers 424 and 426 are sequentially stacked on insulating layer 422 and conductive layer 428. Furthermore, openings are formed in insulating layers 424 and 426 in the regions overlapping with conductive layer 428. A conductive layer 430 is embedded within these openings.

[0561] Furthermore, insulating layers 450, 452, and 454 are sequentially stacked on insulating layer 426 and conductive layer 430. Additionally, openings are formed in insulating layers 450, 452, and 454 in the regions overlapping with conductive layer 430. Conductive layer 456 is embedded within these openings.

[0562] The conductive layers 430 and 456, for example, have the function of a plug or wiring for connecting to the transistor 400d.

[0563] For example, similar to insulating layer 592 described later, insulating layers 424 and 450 preferably use insulating layers having barrier properties selected from one or more of hydrogen, oxygen, and water. Furthermore, similar to insulating layer 594 described later, insulating layers 426, 452, and 454 preferably use insulating layers with relatively low permittivity to reduce parasitic capacitance generated between wirings. In addition, insulating layers 426, 452, and 454 are used as interlayer insulating films and planarization films.

[0564] Furthermore, the conductive layer 456 preferably includes a conductive layer having a barrier effect selected from one or more of hydrogen, oxygen, and water.

[0565] Note that tantalum nitride is preferably used as an insulating layer with hydrogen barrier properties. Furthermore, by layering tantalum nitride and highly conductive tungsten, not only can the conductivity of the wiring be maintained, but hydrogen diffusion from the transistor 400d can also be suppressed. In this case, the hydrogen-barrier tantalum nitride layer is preferably in contact with the hydrogen-barrier insulating layer 450.

[0566] Furthermore, an insulating layer 513 is disposed above the insulating layer 454 and the conductive layer 456. An insulating layer IS1 is disposed on the insulating layer 513. Furthermore, a conductive layer 514, serving as a connector or wiring, is embedded in the insulating layers IS1 and 513. Thus, the transistor 400d can be electrically connected to the conductive layer 514 disposed in the element layer 630. Alternatively, one of the source and drain of the transistor MTCK can be electrically connected to one of the source and drain of the transistor 400d.

[0567] A transistor MTCK is disposed on an insulating layer IS1. Furthermore, insulating layers IS3, 574, and 581 are sequentially stacked on the transistor MTCK. Additionally, a conductive layer MPG, serving as a connector or wiring, is embedded within insulating layers IS3, 574, and 581.

[0568] The insulating layer 574 preferably has the function of inhibiting the diffusion of impurities such as water and hydrogen (e.g., one or both of hydrogen atoms and hydrogen molecules). In other words, the insulating layer 574 is preferably used as a barrier insulating film to inhibit the incorporation of such impurities into the transistor MTCK. Furthermore, the insulating layer 574 preferably has the function of inhibiting the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules). For example, the oxygen permeability of the insulating layer 574 is preferably lower than that of the insulating layers IS2 and IS3.

[0569] Therefore, insulating layer 574 is preferably used as a barrier insulating film to inhibit the diffusion of impurities such as water and hydrogen. Therefore, insulating layer 574 is preferably made of an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms (making it difficult for the aforementioned impurities to permeate). Alternatively, it is preferable to use an insulating material that has the function of inhibiting the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) (making it difficult for the aforementioned oxygen to permeate).

[0570] As an insulating layer that has the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, the material shown in Embodiment 1 that can be used as an insulating layer with the function of suppressing the permeation of impurities and oxygen can be used.

[0571] Particularly preferred is the use of aluminum oxide or silicon nitride as the insulating layer 574. This suppresses the diffusion of impurities such as water and hydrogen from above the insulating layer 574 to the transistor MTCK. Alternatively, it suppresses the diffusion of oxygen contained in insulating layers such as IS3 from above the insulating layer 574.

[0572] Insulating layer 581 is preferably used as an interlayer film and its relative permittivity is lower than that of insulating layer 574. By using a material with a low relative permittivity as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the relative permittivity of insulating layer 581 is preferably less than 4, more preferably less than 3. For example, the relative permittivity of insulating layer 581 is preferably less than 0.7 times the relative permittivity of insulating layer 574, more preferably less than 0.6 times. By using an interlayer film with a low relative permittivity as insulating layer 581, parasitic capacitance generated between wirings can be reduced.

[0573] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 581 is preferably reduced. In this case, silicon oxide, silicon oxynitride, silicon oxynitride, or silicon nitride can be used as the insulating layer 581, for example. Furthermore, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide can be used as the insulating layer 581, for example. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferred because they readily form regions containing oxygen released by heating. Furthermore, resin can be used as the insulating layer 581. In addition, combinations of the above-mentioned materials can be appropriately used as materials that can be used in the insulating layer 581.

[0574] Insulating layer 592 and insulating layer 594 are stacked sequentially on insulating layer 574 and insulating layer 581.

[0575] Furthermore, the insulating layer 592 preferably uses a barrier insulating film (referred to as a barrier insulating film) that prevents impurities such as water and hydrogen from diffusing from the substrate 410 and the transistor MTCK to the area above the insulating layer 592 (e.g., the area where light-emitting elements 650R, 650G, and 650B are disposed). Therefore, the insulating layer 592 preferably uses an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (making it difficult for the aforementioned oxygen to permeate). Furthermore, depending on the situation, the insulating layer 592 preferably uses an insulating material that has the function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms (making it difficult for the aforementioned impurities to permeate). Alternatively, it is preferable to have the function of suppressing the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules).

[0576] As a hydrogen-barrier membrane, silicon nitride formed by CVD can be used, for example.

[0577] The amount of hydrogen removed can be analyzed, for example, using thermal desorption spectrometry (TDS). For instance, within the TDS range of film surface temperature from 50°C to 500°C, when converting the amount of hydrogen removed (converted to hydrogen atoms) to the amount per unit area of ​​insulating layer 424, the preferred amount of hydrogen removed from insulating layer 424 is 10 × 10⁻⁶. 15 atoms / cm 2 The following is more preferably 5×10 15 atoms / cm 2 the following.

[0578] Similar to insulating layer 581, insulating layer 594 is preferably an interlayer film with a low relative permittivity. Therefore, insulating layer 594 can use materials that are also suitable for insulating layer 581.

[0579] Furthermore, the relative permittivity of insulating layer 594 is preferably lower than that of insulating layer 592. For example, the relative permittivity of insulating layer 594 is preferably less than 4, more preferably less than 3. Additionally, for example, the relative permittivity of insulating layer 594 is preferably 0.7 times or less than that of insulating layer 592, more preferably 0.6 times or less. By using an interlayer film with a low relative permittivity as insulating layer 594, parasitic capacitance generated between wirings can be reduced.

[0580] Furthermore, conductive layers MPG, serving as plugs or wiring, are embedded in insulating layers GI1 and IS3, and conductive layers 596, serving as plugs or wiring, are embedded in insulating layers 592 and 594. In particular, conductive layers MPG and 596 are electrically connected to light-emitting elements disposed above insulating layer 594. Note that the same symbol is sometimes used to represent multiple conductive layers serving as plugs or wiring. Furthermore, in this specification, wiring and plugs connected to wiring can also be a single component. That is, a portion of a conductive layer is sometimes used as wiring, and a portion of a conductive layer is sometimes used as a plug.

[0581] The materials used for the plugs and wiring (conductive layer MPG, conductive layer 428, conductive layer 430, conductive layer 456, conductive layer 514, and conductive layer 596) can be single layers or stacks of conductive materials selected from one or more of metallic materials, alloy materials, metal nitride materials, and metal oxide materials. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred; tungsten is particularly preferred. Furthermore, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0582] Insulating layer 598 and insulating layer 599 are sequentially formed on insulating layer 594 and conductive layer 596.

[0583] Similar to insulating layer 592, as an example, insulating layer 598 preferably uses an insulating layer having barrier properties for one or more of hydrogen, oxygen, and water. Furthermore, similar to insulating layer 594, insulating layer 599 preferably uses an insulating layer with a relatively low permittivity to reduce parasitic capacitance generated between wirings. In addition, insulating layer 599 serves as an interlayer insulating film and a planarization film.

[0584] A light-emitting element 650 and a connecting portion 640 are formed on the insulating layer 599.

[0585] The connecting portion 640, sometimes referred to as the cathode contact portion, is electrically connected to the cathode electrode of each of the light-emitting elements 650R, 650G, and 650B. Figure 29 In the connecting portion 640 shown, a conductive layer formed using the same process and materials as conductive layers 611a to 611c is electrically connected to the common electrode 615 described later. Although Figure 29 An example is shown in which the conductive layer is electrically connected to the common electrode 615 through the common layer 614 described later, but the conductive layer may also be in direct contact with the common electrode 615.

[0586] The connecting portion 640 can be arranged around the four sides of the display unit when viewed from above, or it can be arranged inside the display unit (for example, between adjacent light-emitting elements 650) (not shown).

[0587] The light-emitting element 650R includes a conductive layer 611a as a pixel electrode. Similarly, the light-emitting element 650G includes a conductive layer 611b as a pixel electrode, and the light-emitting element 650B includes a conductive layer 611c as a pixel electrode.

[0588] Conductive layers 611a, 611b, and 611c are respectively connected to conductive layer 596 embedded in insulating layer 594 via conductive layers (plugs) embedded in insulating layer 599.

[0589] Light-emitting element 650R includes layer 613a, a common layer 614 on layer 613a, and a common electrode 615 on the common layer 614. Furthermore, light-emitting element 650G includes layer 613b, a common layer 614 on layer 613b, and a common electrode 615 on the common layer 614. Furthermore, light-emitting element 650B includes layer 613c, a common layer 614 on layer 613c, and a common electrode 615 on the common layer 614.

[0590] As materials for the pair of electrodes (pixel electrode and common electrode) forming the light-emitting element, metals, alloys, conductive compounds, and mixtures thereof can be appropriately used. Specifically, examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys appropriately combining them. Furthermore, examples of such materials include indium tin oxide (In-Sn oxide, also known as ITO), In-Si-Sn oxide (also known as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Additionally, examples of such materials include aluminum alloys (alloys containing aluminum, nickel, and lanthanum, such as Al-Ni-La), and silver alloys (alloys containing silver and magnesium, and alloys containing silver, palladium, and copper, such as Ag-Pd-Cu, also denoted as APC). In addition, as materials, examples include elements belonging to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys of these elements in appropriate combinations, and graphene.

[0591] The 600A display device adopts an SBS structure. The SBS structure allows for optimization of materials and structure for each light-emitting element, increasing the freedom of material and structural selection and making it easier to improve brightness and reliability.

[0592] Furthermore, the display device 600A adopts a top-emitting type. In the top-emitting type, transistors and the like can be arranged in a manner that overlaps with the light-emitting area of ​​the light-emitting element, so the pixel aperture ratio can be further improved compared to the bottom-emitting type.

[0593] Layer 613a is formed to cover the top and side surfaces of conductive layer 611a. Similarly, layer 613b is formed to cover the top and side surfaces of conductive layer 611b. Furthermore, layer 613c is formed to cover the top and side surfaces of conductive layer 611c. Therefore, the entire area where conductive layers 611a, 611b, and 611c are disposed can be used as the light-emitting area of ​​light-emitting elements 650R, 650G, and 650B, thereby improving the pixel aperture ratio.

[0594] In light-emitting element 650R, layer 613a and common layer 614 can be collectively referred to as EL layers. Similarly, in light-emitting element 650G, layer 613b and common layer 614 can be collectively referred to as EL layers. Similarly, in light-emitting element 650B, layer 613c and common layer 614 can be collectively referred to as EL layers.

[0595] The EL layer includes at least a light-emitting layer. The light-emitting layer contains one or more light-emitting materials. Suitable light-emitting materials are those that emit light in colors such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red. Alternatively, materials that emit near-infrared light may also be used as light-emitting materials.

[0596] Light-emitting materials contained in light-emitting elements include, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0597] In addition to the luminescent material (guest material), the luminescent layer may also contain one or more organic compounds (host material, auxiliary material, etc.). As one or more organic compounds, one or both of the following can be used: a material with high hole transport (hole transport material) and a material with high electron transport (electron transport material). Furthermore, as one or more organic compounds, bipolar materials (materials with both high electron and hole transport properties) or TADF materials can also be used.

[0598] In addition to the light-emitting layer, the EL layer may also include one or more of the following: a layer containing a material with high hole injection capability (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking capability (electron blocking layer), a layer containing a material with high electron injection capability (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking capability (hole blocking layer). Furthermore, the EL layer may also include one or both of a bipolar material and a TADF material.

[0599] Light-emitting elements can use low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet printing, and coating.

[0600] Light-emitting elements can be either a single structure (a structure with only one light-emitting unit) or a series structure (a structure including multiple light-emitting units). Each light-emitting unit includes at least one light-emitting layer. A series structure has multiple light-emitting units connected in series via a charge-generating layer. The charge-generating layer functions to inject electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By employing a series structure, light-emitting elements capable of emitting light with high brightness can be realized. Furthermore, the series structure improves reliability because it reduces the current required to achieve the same brightness compared to a single structure. Additionally, the series structure can be referred to as a stacked structure.

[0601] Furthermore, when the light-emitting element has a microcavity structure, the color purity can be further improved.

[0602] Layers 613a, 613b, and 613c are processed into island shapes using photolithography. Therefore, the angle between the top and side surfaces of layers 613a, 613b, and 613c at each end is approximately 90 degrees. On the other hand, for example, organic films formed using FMM (Fine Metal Mask) tend to thin closer to the ends; for instance, their top surface may be sloped within a range of 1 μm to 10 μm from the end, making it difficult to distinguish between the top and side surfaces.

[0603] In layers 613a, 613b, and 613c, the top surface and the side surface are clearly distinguishable. Therefore, in adjacent layers 613a and 613b, one side surface of layer 613a and one side surface of layer 613b are opposite each other. The same applies to any combination of layers 613a, 613b, and 613c.

[0604] Layers 613a, 613b, and 613c each include at least a light-emitting layer. For example, it is preferable that layers 613a, 613b, and 613c each include a light-emitting layer emitting red light, a light-emitting layer emitting green light, and a light-emitting layer emitting blue light, respectively. Furthermore, the light-emitting layers may be cyan, magenta, yellow, or white, in addition to the colors mentioned above.

[0605] Layers 613a, 613b, and 613c preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Because the surfaces of layers 613a, 613b, and 613c are sometimes exposed during the manufacturing process of the display device, providing a carrier transport layer on the light-emitting layer can suppress the light-emitting layer from being exposed to the outermost surface, thereby reducing damage to the light-emitting layer. This improves the reliability of the light-emitting element.

[0606] The common layer 614 may include, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 614 may be a stack of both an electron transport layer and an electron injection layer, or a stack of both a hole transport layer and a hole injection layer. Light-emitting elements 650R, 650G, and 650B collectively include the common layer 614. Alternatively, the common layer 614 may be omitted, and the entire EL layer of the light-emitting element may be arranged in an island shape, similar to layers 613a, 613b, and 613c.

[0607] Furthermore, light-emitting elements 650R, 650G, and 650B collectively include a common electrode 615. Additionally, as... Figure 29As shown, the common electrode 615, which is shared by multiple light-emitting elements, is electrically connected to the conductive layer in the connecting portion 640.

[0608] The insulating layer 625 is preferably used as a barrier insulating layer against one or both of water and oxygen. Furthermore, the insulating layer 625 preferably has the function of inhibiting the diffusion...

Claims

1. A semiconductor device, comprising: First conductive layer; The first insulating layer on the first conductive layer; The second conductive layer on the first insulating layer; The second insulating layer on the second conductive layer; The third conductive layer on the second insulating layer; The third insulating layer and semiconductor layer on the first conductive layer; The fourth insulating layer on the semiconductor layer; as well as The fourth conductive layer on the fourth insulating layer, The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are provided with a first opening that reaches the first conductive layer. The third insulating layer has a second opening in the region overlapping with the first opening. The third insulating layer has a region that contacts the side surface of the second conductive layer and a region that contacts the side surface of the third conductive layer. The semiconductor layer has a region that contacts the top surface of the first conductive layer through the second opening and a region that contacts the top surface of the third conductive layer. The fourth conductive layer has a region that is opposite to the second conductive layer, separated by the fourth insulating layer, the semiconductor layer, and the third insulating layer. Furthermore, in cross-section, the width of the second opening is less than the value obtained by subtracting twice the thickness of the third insulating layer from the width of the first opening.

2. The semiconductor device according to claim 1, The depth of the second opening is the same as the thickness of the third insulating layer.

3. The semiconductor device according to claim 1, The side end of the semiconductor layer coincides with the side end of the third conductive layer.

4. The semiconductor device according to claim 1, The angle between the extension direction of the second conductive layer and the extension direction of the fourth conductive layer is 45 degrees.

5. A semiconductor device, comprising: First conductive layer; A second conductive layer on the first conductive layer; The first insulating layer on the first conductive layer and the second conductive layer; The third conductive layer on the first insulating layer; The second insulating layer on the third conductive layer; The fourth conductive layer on the second insulating layer; The third insulating layer and semiconductor layer on the second conductive layer; The fourth insulating layer on the semiconductor layer; as well as The fifth conductive layer on the fourth insulating layer, The first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer are provided with a first opening that reaches the first conductive layer. The third insulating layer has a second opening in the region overlapping with the first opening. The third insulating layer has a region that contacts the side surface of the third conductive layer and a region that contacts the side surface of the fourth conductive layer. The semiconductor layer has a region that contacts the top surface of the second conductive layer through the second opening and a region that contacts the top surface of the fourth conductive layer. The fifth conductive layer has a region that is separated from the fourth insulating layer, the semiconductor layer, and the third insulating layer, and is opposite to the third conductive layer. Furthermore, in cross-section, the width of the second conductive layer is greater than the width of the second opening and less than the width of the first opening.

6. The semiconductor device according to claim 5, The side end of the semiconductor layer coincides with the side end of the fourth conductive layer.

7. The semiconductor device according to claim 5, The angle between the extension direction of the third conductive layer and the extension direction of the fifth conductive layer is 45 degrees.

8. The semiconductor device according to any one of claims 1 to 7, The semiconductor layer comprises one or both of indium and zinc.

9. The semiconductor device according to any one of claims 1 to 7, Both the first insulating layer and the second insulating layer include a first layer, a second layer, and a third layer located between the first layer and the second layer. Both the first layer and the third layer contain silicon and nitrogen. Furthermore, the relative permittivity of the second layer is lower than that of the first layer.

10. The semiconductor device according to claim 9, The second layer has a region that is thicker than the first layer. Furthermore, the second layer has a region where its thickness is greater than that of the third layer.

11. A method for manufacturing a semiconductor device, comprising the following steps: Form the first conductive layer; A first insulating layer is formed on the first conductive layer; A second conductive layer is formed on the first insulating layer; A second insulating layer is formed on the second conductive layer; A third conductive layer is formed on the second insulating layer; An opening reaching the first conductive layer is formed by processing the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer. A third insulating layer is formed that contacts the sidewalls and bottom of the opening; A layer is formed on the third insulating layer; By processing the third insulating layer and the layer, the top surface of the first conductive layer in the area overlapping with the opening is exposed; Remove the layer; A semiconductor layer is formed on the first conductive layer, the third insulating layer, and the third conductive layer; A fourth insulating layer is formed on the semiconductor layer; as well as A fourth conductive layer is formed on the fourth insulating layer.

12. The method of manufacturing a semiconductor device according to claim 11, wherein the third insulating layer and the layer are processed using anisotropic etching.

13. The method for manufacturing a semiconductor device according to claim 12, The layer is removed using isotropic etching.

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