A wafer measurement method and system

Abstract

This invention provides a wafer metrology method and system, belonging to the field of semiconductor manufacturing technology. The method includes: setting a reference wafer; obtaining the theoretical overlay error of the semiconductor current layer and setting calibration parameters, wherein the calibration parameters are the ratio of the actual overlay error to the theoretical overlay error of the semiconductor current layer; obtaining a reference error value for the wafer under test based on the average overlay error of multiple batches of wafers under test; before processing the semiconductor current layer of the wafer under test, marking the semiconductor current layer as a structural layer or an unstructured layer according to the degree of structural change of the semiconductor current layer; if the semiconductor current layer is a structural layer, obtaining the overlay compensation value of the semiconductor current layer based on the differences between multiple wafers under test in the same batch and the differences between the wafer under test and the reference wafer, and obtaining the current layer error compensation value of the semiconductor current layer based on the overlay compensation value, calibration parameters, and reference error value. This invention provides a wafer metrology method and system that can improve the accuracy of overlay error measurement of wafers in the same batch.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer measurement method and system. Background Technology

[0002] In semiconductor manufacturing, wafers undergo various processes such as photolithography, etching, and polishing. The different tools used in these processes, as well as fluctuations in process parameters, can lead to differences between wafers of the same product and even within the same batch. Furthermore, if differences occur in the first layer of the wafer, overlay errors may occur in the photolithography process of that layer. Overlay error refers to the error that occurs when the photolithography machine, after exposing each field on the silicon wafer and then changing the wafer and mask, fails to accurately overlap the second layer pattern with the first layer due to various systematic and random errors.

[0003] There are many reasons for overlay errors. Once these errors exceed the allowable range, the wafer will need to be reworked, which reduces process efficiency. For multiple wafers undergoing simultaneous processing, failure to detect overlay errors exceeding the allowable range in time can potentially lead to significant wafer defects. Therefore, for semiconductor layers with tight specifications, it is difficult to reduce the sampling rate of wafers in the same batch to prevent rework. The difficulty in controlling the sampling rate during sampling testing not only increases production costs but also extends the product manufacturing cycle. Summary of the Invention

[0004] The purpose of this invention is to provide a wafer measurement method and system that can improve the accuracy of overlay error measurement for wafers in the same batch.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0006] This invention provides a wafer measurement method, comprising the following steps:

[0007] A reference plate is set up, wherein the reference plate has the same substrate material and substrate size as the wafer to be tested;

[0008] The theoretical overlay error of the semiconductor current layer is obtained, and a calibration parameter is set, wherein the calibration parameter is the ratio of the actual overlay error of the semiconductor current layer to the theoretical overlay error;

[0009] The reference error value of the wafer under test is obtained based on the average overlay error of multiple batches of the wafer under test.

[0010] Before processing the semiconductor layer of the wafer under test, the semiconductor layer is marked as a structured layer or an unstructured layer according to the degree of structural change of the semiconductor layer.

[0011] If the semiconductor current layer is a structural layer, based on the differences between multiple wafers under test in the same batch, and the differences between the wafer under test and the reference wafer, the overlay compensation value of the semiconductor current layer is obtained, and based on the overlay compensation value, the calibration parameters, and the reference error value, the current layer error compensation value of the semiconductor current layer is obtained; and

[0012] If the semiconductor current layer is a non-structural layer, the current layer error compensation value of the semiconductor front layer is used as the current layer error compensation value of the semiconductor current layer.

[0013] In one embodiment of the present invention, in the step of obtaining the overlay compensation value, the overlay error difference of multiple wafers in the same batch is used as the first overlay compensation value A. n The overlay error difference generated by the same batch of wafers being tested on the same machine is taken as the second overlay compensation value B. n The overlay error difference generated by the same batch of wafers under the same photomask is taken as the third overlay compensation value C. n .

[0014] In one embodiment of the present invention, when the semiconductor current layer is a structural layer, the error compensation value of the current layer is obtained according to the following formula:

[0015]

[0016] Among them, OVL n A is the current layer error compensation value for the semiconductor current layer. n For the first set of engraving values, B n For the second set of engraving values, C n For the third set of etch compensation values, OVL baseline Let K be the reference error value, and K be the calibration parameter.

[0017] In one embodiment of the present invention, the wafer measurement method includes:

[0018] Set multiple compensation types and input the system overlay error of the wafer under test under the specified compensation type; and

[0019] The sum of the system overlay error and the current layer error compensation value is obtained and used as the current layer overlay error of the semiconductor current layer.

[0020] In one embodiment of the present invention, the compensation types include planar graphic displacement error, graphic rotation error, and graphic magnification error.

[0021] In one embodiment of the present invention, the wafer measurement method further includes:

[0022] Set the overlay threshold;

[0023] The overlay error of the same layer for multiple wafers under test in the same batch was obtained respectively; and

[0024] If the overlay error of the current layer of the wafer under test is greater than the overlay threshold, then the overlay error of the current layer of the wafer under test is replaced by the overlay error of the adjacent wafer under test.

[0025] In one embodiment of the present invention, the wafer measurement method further includes:

[0026] Set the overlay threshold;

[0027] The overlay error of the same layer for multiple wafers under test in the same batch was obtained respectively; and

[0028] When the overlay error of multiple adjacent wafers under test is greater than the overlay threshold, the average overlay error of the wafers under test in the same batch is obtained, and the overlay error of the wafers under test that exceed the threshold is replaced by the average overlay error.

[0029] In one embodiment of the present invention, the step of distinguishing the semiconductor current layer includes:

[0030] Obtain the physical pattern structure of the semiconductor front layer as the first pattern structure;

[0031] Obtain the physical pattern structure of the semiconductor current layer design as the second pattern structure; and

[0032] When the first pattern structure and the second pattern structure are the same, the semiconductor layer is marked as a non-structure layer; when the first pattern structure and the second pattern structure are different, the semiconductor layer is marked as a structure layer.

[0033] In one embodiment of the present invention, the semiconductor current layer is a semiconductor layer that is about to undergo process processing, and the semiconductor front layer is a semiconductor layer that has just undergone process processing.

[0034] This invention provides a wafer measurement system, comprising:

[0035] A reference wafer monitoring module is used to monitor a reference wafer, wherein the reference wafer has the same substrate material and substrate size as the wafer under test;

[0036] The calibration parameter acquisition module is used to acquire the theoretical overlay error of the semiconductor current layer and set calibration parameters, wherein the calibration parameters are the ratio of the actual overlay error of the semiconductor current layer to the theoretical overlay error.

[0037] The reference error acquisition module is used to obtain the reference error value of the wafer under test based on the average overlay error of multiple batches of the wafer under test;

[0038] The layer differentiation module is used to mark the semiconductor layer as a structured layer or an unstructured layer according to the degree of structural change of the semiconductor layer before processing the semiconductor layer of the wafer under test.

[0039] The first compensation value acquisition module is configured to, when the semiconductor current layer is a structural layer, acquire the overlay compensation value of the semiconductor current layer based on the differences between multiple wafers under test in the same batch, and the differences between the wafer under test and the reference wafer, and acquire the current layer error compensation value of the semiconductor current layer based on the overlay compensation value, the calibration parameters, and the reference error value; and

[0040] The second compensation value acquisition module is used to use the current layer error compensation value of the semiconductor front layer as the current layer error compensation value of the semiconductor current layer when the current layer is a non-structural layer.

[0041] As described above, the present invention provides a wafer measurement method and system, the unexpected technical effect of which is that it allows for batch processing of wafers, thereby improving wafer manufacturing efficiency, and can measure the overlay error differences between wafers in the same batch, thus accurately knowing the actual processing status of the wafer under test. Furthermore, the wafer measurement method and system provided by the present invention can comprehensively consider factors such as changes in equipment, photomask, and wafer type, accurately depicting the actual overlay error of the wafer under test from multiple perspectives.

[0042] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the structure of the wafer and semiconductor layer in one embodiment of the present invention.

[0045] Figure 2 This is a schematic diagram of the measurement of wafers No. 1, No. 14 and No. 24 on the overlay machine in one embodiment of the present invention.

[0046] Figure 3 This is a schematic diagram of the measurement of displacement error of a planar graphic in one embodiment of the present invention.

[0047] Figure 4 This is a flowchart of a wafer measurement method in one embodiment of the present invention.

[0048] Figure 5 This is a schematic diagram of the measurement of graphic rotation error in one embodiment of the present invention.

[0049] Figure 6 This is a schematic diagram of the measurement of image magnification error in one embodiment of the present invention.

[0050] Figure 7 This is a flowchart of step S500 in one embodiment of the present invention.

[0051] Figure 8 This is a schematic diagram of the measurement system in one embodiment of the present invention.

[0052] In the figure: 10, wafer under test; 11, semiconductor front layer; 12, semiconductor current layer; 20, measurement system; 21, reference wafer monitoring module; 22, calibration parameter acquisition module; 23, reference error acquisition module; 24, layer differentiation module; 25, first compensation value acquisition module; 26, second compensation value acquisition module. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] Please see Figure 1 As shown, in this invention, during the semiconductor manufacturing process, multiple wafers 10 to be tested are placed in the same batch and processed synchronously to improve the batch production efficiency of wafers. The number of wafers placed in the same batch is, for example, 16 to 25. Within the same batch, multiple wafers 10 to be tested participate in various process items simultaneously. It should be noted that a wafer includes multiple semiconductor layers, which can be substrates, structural layers, metal interconnect layers, and pad layers, etc. This invention does not limit the structure and process of each semiconductor layer of the wafer. In this embodiment, the same semiconductor layer of multiple wafers 10 to be tested is processed simultaneously using the same process, thereby improving process efficiency. The same semiconductor layer can be manifested as a semiconductor layer with the same number of layers. The same number of layers can be manifested as the same layer name, the same layer number, etc.

[0055] Please see Figure 1As shown, in this invention, before and after the wafer fabrication process, a portion of wafers 10 from the same batch are selected for measurement to ensure that overlay errors do not exceed the allowable range during wafer manufacturing due to process changes. In this embodiment, a semiconductor front layer 11 and a semiconductor current layer 12 are provided. The semiconductor front layer 11 refers to the semiconductor layer on the wafer that has just completed its process processing. The semiconductor current layer 12 refers to the semiconductor layer on the wafer that is about to undergo process processing. Process processing can be understood as various semiconductor process types such as etching, photolithography, thin film deposition, ion implantation, and annealing. It should be noted that the number of processes performed on a single semiconductor layer is not singular; the same or different processes can be performed multiple times on the same semiconductor layer. This invention does not limit the number of processes performed on each semiconductor layer. In this embodiment, the semiconductor front layer 11 and the semiconductor current layer 12 can be semiconductor layers of different levels, and the semiconductor front layer 11 and the semiconductor current layer 12 are adjacent semiconductor layers. In this embodiment, the semiconductor front layer 11 and the semiconductor current layer 12 can also be semiconductor layers of the same level but with different processes.

[0056] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, due to fluctuations in process parameters, differences in overlay errors may occur among multiple wafers 10 to be tested within the same batch. In this invention, the overlay error of the semiconductor current layer 12 relative to the semiconductor front layer 11 can be measured on an overlay machine. Furthermore, the specific manifestation of the overlay error can be simulated using KLA software, and the numerical value of the overlay error can be obtained. In this embodiment, for example, there are 25 wafers in the same batch. These 25 wafers are numbered and sorted according to their numbers. Figure 2 As shown, in this embodiment, when selecting the object to be tested, two wafers at the edge positions are selected, such as wafer 1 and wafer 24, and one wafer located in the middle position is selected, such as wafer 14. Figure 2 As shown in the table below, the maximum error of wafer 1 in the horizontal X-axis direction is 12nm, and the maximum error in the vertical Y-axis direction is 10nm. The minimum error of wafer 1 in the horizontal X-axis direction is -6nm, and the minimum error in the vertical Y-axis direction is -11nm. The larger the value along the positive X-axis, the larger the error. The error magnitude here represents the numerical value, not the actual distance. It can be seen that the overlapping value (OVL) of wafers 1, 14, and 24 differs, and the difference is significant. In the Y-axis direction, the maximum overlapping error is 20nm for wafer 24. In the X-axis direction, the maximum overlapping error is 12nm for wafer 1. Figure 2As shown in Table 1 below, the sampling rate for this batch of wafers is 3 / 25. Due to the significant difference in values, the actual situation of other wafers in the same batch cannot be known. If the results of wafers 1, 14, and 24 are used as a reference, it is very likely that other wafers will exhibit overlay errors exceeding the acceptable range.

[0057] Table 1. Overlap error of multiple wafers selected from the same batch

[0058]

[0059] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, the measurement of overlay error is based on alignment marks. During the processing of the semiconductor current layer 12, alignment marks are formed on the wafer along with the mask pattern. In this embodiment, the alignment marks are, for example, crosshair-shaped, where Shift(X) represents the offset distance of the semiconductor current layer 12 relative to the semiconductor preceding layer 11 in the X-axis direction. Shift(Y) represents the offset distance of the semiconductor current layer 12 relative to the semiconductor preceding layer 11 in the Y-axis direction. The arrow indicates the offset vector of the center of the alignment mark. This can be determined according to... Figure 3 understand Figure 2 It should be noted that the shape of the alignment mark is not limited in this invention. In this invention, there are multiple alignment marks, and they can be of different shapes.

[0060] Please see Figure 1 and Figure 4 As shown, the present invention provides a wafer measurement method, which includes steps S100 to S600.

[0061] Step S100: Set a reference plate. The reference plate has the same substrate material and substrate size as the wafer 10 to be tested.

[0062] Step S200: Obtain the theoretical overlay error of the semiconductor current layer 12 and set the calibration parameters, wherein the calibration parameters are the ratio of the actual overlay error of the semiconductor current layer 12 to the theoretical overlay error.

[0063] Step S300: Obtain the reference error value of the wafer 10 to be tested based on the average overlay error of multiple batches of wafers 10 to be tested.

[0064] Step S400: Before processing the semiconductor layer 12 of the wafer 10 to be tested, the semiconductor layer 12 is marked as a structural layer or a non-structural layer according to the degree of structural change of the semiconductor layer 12.

[0065] Step S500: If the semiconductor current layer 12 is a structural layer, based on the differences between multiple test wafers 10 in the same batch, and the differences between the test wafer 10 and the reference wafer, the overlay compensation value of the semiconductor current layer 12 is obtained, and based on the overlay compensation value, calibration parameters and reference error value, the current layer error compensation value of the semiconductor current layer 12 is obtained.

[0066] Step S600: If the semiconductor current layer 12 is a non-structural layer, the current layer error compensation value of the semiconductor front layer 11 is used as the current layer error compensation value of the semiconductor current layer 12.

[0067] Please see Figure 1 and Figure 4 As shown, in one embodiment of the present invention, in step S100, the wafer used for manufacturing the product is set as the test wafer 10. In the present invention, multiple test wafers 10 are grouped into the same batch. The test wafers 10 in the same batch have the same process flow and can participate in the process processing and testing processes simultaneously. The test wafers 10 in the same batch have the same substrate. In this embodiment, the reference wafer is a test wafer and is not used for product manufacturing. The reference wafer and the substrate of the test wafer 10 have the same substrate material and the same substrate size. When manufacturing the same product, multiple batches of test wafers 10 can share the same reference wafer. In this embodiment, the substrate refers to the silicon substrate of the wafer before it undergoes any barrier layer treatment.

[0068] Please see Figure 1 , Figures 3 to 6 As shown, in one embodiment of the present invention, multiple compensation types are set, and the system overlay error of the wafer 10 under test is input under the compensation type. In this embodiment, the compensation types for overlay error include planar pattern displacement error, pattern rotation error, and pattern magnification error. The planar pattern displacement error is the displacement distance along the direction axis between the alignment mark of the current semiconductor layer 12 and the alignment mark of the previous semiconductor layer 11, such as... Figure 3 As shown, the planar pattern displacement error includes the displacement distance Shift(X) along the X-axis and the displacement distance Shift(Y) along the Y-axis. The pattern rotation error is the displacement error and rotation angle generated after the alignment mark of the semiconductor current layer 12 is rotated relative to the alignment mark of the semiconductor front layer 11, such as... Figure 5As shown, the pattern rotation error includes the horizontal axis rotation angle Wafer Rot (X), the vertical axis rotation angle Wafer Rot (Y), the horizontal center distance Span1 (X) after rotation, and the vertical center distance Span1 (Y) after rotation. The horizontal axis is the central axis of the alignment mark along the X direction, and the vertical axis is the central axis of the alignment mark along the Y direction. The horizontal axis rotation angle is the horizontal axis rotation angle of the semiconductor current layer 12 relative to the semiconductor front layer 11. The vertical axis rotation angle is the vertical axis rotation angle of the semiconductor current layer 12 relative to the semiconductor front layer 11. The horizontal center distance Span1 (X) after rotation is the maximum distance between the alignment marks after rotation and the alignment marks before rotation along the X-axis. The vertical center distance Span1 (Y) after rotation is the maximum distance between the alignment marks after rotation and the alignment marks before rotation along the Y-axis. The pattern magnification error is the displacement error of the alignment marks of the semiconductor current layer 12 after magnification compared to the alignment marks of the semiconductor front layer 11. Figure 6 As shown, the pattern magnification error includes a horizontal magnification error Span2(X) and a vertical magnification error Span2(Y). The horizontal magnification error Span2(X) is the spacing along the X-axis of the inner edge of the alignment mark in the semiconductor current layer 12. The vertical magnification error Span2(Y) is the spacing along the Y-axis of the inner edge of the alignment mark in the semiconductor current layer 12. It should be noted that there are various compensation types, and the positional difference of the alignment mark pattern between the semiconductor current layer 12 and the semiconductor front layer 11 can be described by various dimensional differences. For the same type of compensation, different dimensions can also be used to describe the positional difference of the alignment mark pattern. In this embodiment, based on the ability to reflect the differences, different mathematical methods can be used to represent the positional difference of the pattern.

[0069] Please see Figure 1 , Figures 3 to 6As shown, in one embodiment of the present invention, after determining the compensation type, the measurement value corresponding to the compensation type can be obtained through the data sampling system of the overlay machine as the system overlay error. It should be noted that the value obtained from the system overlay error is not completely accurate. Before executing step S200, the semiconductor layer 12 is processed. Then, the wafer to be tested 10 is transferred to the overlay machine, and the actual overlay error of the semiconductor layer 12 is measured by the overlay machine. In step S200, the theoretical overlay error of the semiconductor layer 12 is a value obtained based on experimental data and past processing experience of the same product. Before processing the semiconductor layer 12, the theoretical overlay error of the semiconductor layer 12 can be obtained during the design and experimental stages. In this embodiment, the theoretical overlay error of each layer of the wafer to be tested 10 is known, and the theoretical overlay error of multiple wafers to be tested 10 in the same batch is the same for the same semiconductor layer 12. However, during actual processing, the overlay errors of multiple wafers to be tested 10 in the same batch are different. In this embodiment, the actual overlay error of the semiconductor layer 12 is obtained by measuring with an overlay machine. In this embodiment, the calibration parameter K is the ratio of the actual overlay error K1 to the theoretical overlay error K2 of the semiconductor layer 12.

[0070] Please see Figure 1 and Figure 4 As shown, in one embodiment of the present invention, in step S300, multiple batches of the same product have been produced before the current batch of wafers to be tested 10 are manufactured. Therefore, the multiple batches of wafers produced before the current batch of wafers to be tested 10 are used as data references. Specifically, in this embodiment, the overlay error values ​​of multiple batches of produced wafers in the same semiconductor layer 12 are obtained, and the average overlay error of multiple batches of produced wafers in the semiconductor layer 12 is calculated. In this embodiment, the weighting weight between each batch of produced wafers can be adjusted to improve the reliability of the average overlay error. For example, if there are 5 batches of produced wafers, and the data of 3 batches are similar, the weighting value of the data of 3 batches of produced wafers can be increased. For example, the weighting weight of these 3 batches is 0.6, and the weighting weight of the other 2 batches is set to 0.4. In this embodiment, the average overlay error of multiple batches of produced wafers in the semiconductor layer 12 is recorded as the reference error value of the wafer 10 to be tested.

[0071] Please see Figure 1 and Figure 4As shown, in one embodiment of the present invention, in step S400, during the manufacturing process of the wafer 10 to be tested, when forming the semiconductor front layer 12, the process can change the structure of the semiconductor front layer 11, for example, by forming a deposition layer. Alternatively, the process can retain the structure of the semiconductor front layer 11, for example, through ion implantation. In this embodiment, if the structure of the semiconductor front layer 11 can be changed when forming the semiconductor front layer 12, then the semiconductor front layer 12 is marked as a structural layer. If the structure of the semiconductor front layer 11 is not changed when forming the semiconductor front layer 12, then the semiconductor front layer 12 is marked as a non-structural layer. Specifically, the physical pattern structure of the semiconductor front layer 11 is obtained as the first pattern structure. The physical pattern structure of the semiconductor front layer 12 is obtained as the second pattern structure. When the first pattern structure and the second pattern structure are the same, the semiconductor front layer 12 is marked as a non-structural layer; when the first pattern structure and the second pattern structure are different, the semiconductor front layer 12 is marked as a structural layer. The physical pattern structure refers to the structure retained on the wafer 10 to be tested after the process is completed.

[0072] Please see Figure 1 , Figure 4 and Figure 7 As shown, in one embodiment of the present invention, in step S500, if the semiconductor current layer 12 is a structural layer, the overlay compensation value of the semiconductor current layer 12 is obtained based on the differences between multiple test wafers 10 in the same batch, and the differences between the test wafer 10 and the reference wafer. Then, based on the overlay compensation value, calibration parameters, and reference error value, the current layer error compensation value of the semiconductor current layer 12 is obtained. Step S500 includes steps S510 to S540.

[0073] Step S510: Obtain the overlay error difference between multiple test wafers 10 in the same batch, and use it as the first overlay compensation value A. n .

[0074] Step S520: Obtain the overlay error difference between the wafer to be tested 10 and the reference wafer on the same machine, and use it as the second overlay compensation value B. n .

[0075] Step S530: Obtain the overlay error difference between the test wafer 10 and the reference wafer under the same process, and use it as the third overlay compensation value C. n .

[0076] Step S540: Based on the first set of etching compensation values, the second set of etching compensation values, the third set of etching compensation values, the reference error value, and the calibration parameters, obtain the current layer error compensation value of semiconductor current layer 12.

[0077] Please see Figure 1 , Figure 4 and Figure 7As shown, in one embodiment of the present invention, in step S510, according to the compensation type, the overlay error of each wafer 10 under test is sequentially obtained under the current compensation type. The overlay error of the wafer 10 under test can be obtained by acquiring the system overlay error of the wafer 10 under test. Then, according to the compensation type, the overlay error difference of all wafers 10 under test under the current compensation type is sequentially obtained. Next, all wafers 10 under test in the same batch are processed using statistical methods to obtain the overlay error difference of the wafers 10 under test in the same batch. For example, there are 25 wafers 10 under test in the same batch, and these 25 wafers 10 are numbered 1 to 25. Under the current compensation type, the variance data of the wafers 10 under test in the same batch can be obtained to reflect the differences between the wafers 10 under test in the same batch. Based on reflecting the differences between the wafers 10 under test, the present invention limits the mathematical method or algorithm type for obtaining the differences. Alternatively, the first overlay compensation value A can be calculated using the KLA software of the overlay machine. n It should be noted that each compensation type has its own first set of compensation values ​​A. n .

[0078] Please see Figure 1 , Figure 4 and Figure 7 As shown, in one embodiment of the present invention, in step S520, during the processing of multiple wafers, it is difficult for a single machine to simultaneously process wafers in the same batch, and even if processing is performed simultaneously on the same machine, it is difficult to guarantee that each wafer 10 under test will receive the exact same processing. Therefore, due to the processing limitations of the machine, differences may occur between wafers in the same batch. In this embodiment, in step S520, wafers 10 under test in the same batch that have undergone the same machine or the same processing are compared. In this embodiment, a reference wafer is used to help obtain a second set of etching compensation values ​​B. n The reference wafer is an unprocessed wafer. A reference mark can be set on the reference wafer as a reference reference mark. The reference wafer is placed on the overlay machine, and its overlay error value can be measured as the reference overlay error. The parameters of the overlay machine can be calibrated using the reference wafer to make the reference overlay error value zero. Then, according to the compensation type, the overlay error difference between the tested wafer 10 and the reference wafer under each compensation type is obtained sequentially and used as the second overlay compensation value B. n In this embodiment, the second set of engraving compensation values ​​B can be obtained using KLA software. n In this embodiment, each wafer 10 under test has multiple sets of second etch compensation values ​​B of various compensation types. n Obtain the second set of engraving compensation values ​​B. n This eliminates testing errors caused by measurement issues on the engraving machine.

[0079] Please see Figure 1 , Figure 4 and Figure 7 As shown, in one embodiment of the present invention, in step S530, the overlay error of the same batch of wafers 10 under the same photomask is obtained. It should be noted that in the photomask process, the photomask covers the area of ​​multiple chip particles. In the step of transferring the photomask pattern onto the wafer, after completing one pattern transfer, the photomask is moved, and the pattern is transferred to the wafer 10 under test again, and so on, performing multiple photomask movements and pattern transfers to achieve illumination processing of the entire wafer. Therefore, multiple illumination processing areas are formed on the wafer 10 under test, and the area of ​​each illumination processing area is equal to or smaller than the photomask area. In step S530, according to the compensation type, the same illumination processing areas of the same batch of wafers 10 under test are compared to obtain the overlay error. Then, the overlay error values ​​of the wafer 10 under test and the reference wafer are compared to obtain the third overlay compensation value C. n It should be noted that the wafer under test 10 can have multiple illumination treatment areas. The same illumination treatment areas can be compared separately, and the third set of etching compensation values ​​C for multiple illumination treatment areas can be obtained. n The average value is used as the third set of etch compensation values ​​C for wafer 10 under test. n .

[0080] Please see Figure 1 , Figure 4 and Figure 7 As shown, in one embodiment of the present invention, in step S540, after obtaining the first set of engraving compensation values ​​A... n The second set of engraving values ​​B n The third set of engraving values ​​C n By using calibration parameters and reference error values, the current layer error compensation value of semiconductor current layer 12 is obtained. The calculation of the current layer error compensation value is based on the following formula.

[0081]

[0082] In the above formula, OVL n A is the current layer error compensation value for the semiconductor current layer 12. n For the first set of engraving values, B n For the second set of engraving values, C n For the third set of etch compensation values, OVL baseline Let K be the reference error value, and K be the calibration parameter. The overlay error of a single wafer 10 under test is the sum of the system overlay error and the overlay error compensation value under the current compensation type. It should be noted that each wafer 10 under test has multiple overlay error compensation values ​​under multiple compensation types.

[0083] Please see Figure 1 and Figure 4As shown, in one embodiment of the present invention, in step S600, if the semiconductor current layer 12 is a non-structured layer, the current layer error compensation value of the semiconductor front layer 11 is used as the current layer error compensation value of the semiconductor current layer 12, and the current layer overlay error of the semiconductor current layer 12 is obtained based on the current layer error compensation value of the semiconductor current layer 12 and the system overlay error. When the semiconductor current layer 12 is a non-structured layer, the data sampling rate of the wafer 10 under test can be reduced, and the current layer overlay error can be obtained directly.

[0084] Please see Figure 1 and Figure 4 As shown, in one embodiment of the present invention, the measurement method provided by the present invention further includes setting an overlay threshold and acquiring the current layer overlay error of multiple wafers 10 under test in the same batch. When the current layer overlay error of wafer 10 under test is greater than the overlay threshold, the current layer overlay error of the current wafer 10 under test is replaced by the current layer overlay error of the adjacent wafer 10 under test. There can be multiple erroneous wafers 10 under test, and these multiple erroneous wafers 10 under test are not consecutively arranged in the same batch sequence; in this case, the data of the adjacent wafers 10 under test is used to replace the data of the wafer 10 under test that exceeds the threshold. When the current layer overlay errors of multiple adjacent wafers 10 under test are all greater than the overlay threshold, the average overlay error of the wafers 10 under test in the same batch can be obtained, and the average overlay error is used to replace the current layer overlay error of the wafer 10 under test that exceeds the threshold. It should be noted that multiple compensation types each set an overlay threshold, and when comparing and replacing the values ​​of the current layer overlay error, the replacement is also performed according to the corresponding compensation type.

[0085] Please see Figure 1 , Figure 4 and Figure 8As shown, this invention provides a wafer measurement system 20, which includes a reference wafer monitoring module 21, a calibration parameter acquisition module 22, a reference error acquisition module 23, a layer differentiation module 24, a first compensation value acquisition module 25, and a second compensation value acquisition module 26. The reference wafer monitoring module 21 monitors a reference wafer, which has the same substrate material and size as the wafer 10 under test. The calibration parameter acquisition module 22 acquires the theoretical overlay error of the semiconductor layer 12 and sets calibration parameters, where the calibration parameters are the ratio of the actual overlay error to the theoretical overlay error of the semiconductor layer 12. The reference error acquisition module 23 obtains the reference error value of the wafer 10 under test based on the average overlay error of multiple batches of wafers 10 under test. The layer differentiation module 24, before processing the semiconductor layer 12 of the wafer 10 under test, marks the semiconductor layer 12 as a structured layer or an unstructured layer based on the degree of structural change in the semiconductor layer 12. The first compensation value acquisition module 25 is used to acquire the overlay compensation value of the semiconductor current layer 12 when the semiconductor current layer 12 is a structural layer, based on the differences between multiple test wafers 10 in the same batch, and the differences between the test wafer 10 and the reference wafer, and to acquire the current layer error compensation value of the semiconductor current layer 12 based on the overlay compensation value, calibration parameters, and reference error value. The second compensation value acquisition module 26 is used to acquire the current layer error compensation value of the semiconductor front layer 11 when the semiconductor current layer 12 is a non-structural layer, using the current layer error compensation value of the semiconductor front layer 11 as the current layer error compensation value of the semiconductor current layer 12.

[0086] Please see Figure 1 and Figure 4 , Figure 8 As shown, in one embodiment of the present invention, the wafer measurement system 20 provided by the present invention can be used as part of an Advanced Process Control (APC) system. In this embodiment, data sampling data can be acquired through an overlay machine and an advanced process control system. The overlay error can be obtained by the advanced process control system. After the first compensation value acquisition module 25 obtains the first overlay compensation value, the second overlay compensation value, and the third overlay compensation value, the current layer error compensation value is calculated by calling a calculator in the computer, and then the current layer overlay error of semiconductor current layer 12 is calculated. In this embodiment, after obtaining the current layer overlay of semiconductor current layer 12, the subsequent process operations of the wafer 10 under test are realized through the control of the advanced process control system. For example, the wafer 10 under test can continue to undergo subsequent process operations, processing the next semiconductor current layer 12, while the current semiconductor current layer 12 is marked as the semiconductor front layer 11. Alternatively, the wafer 10 under test can be handed over to other stations for further various measurement operations, etc. The present invention does not limit the specific operation of the advanced process control system.

[0087] This invention provides a wafer measurement method, which includes the following steps: setting a reference wafer, wherein the reference wafer and the wafer to be measured have the same substrate material and substrate size. Obtaining the theoretical overlay error of the semiconductor current layer and setting calibration parameters, wherein the calibration parameters are the ratio of the actual overlay error to the theoretical overlay error of the semiconductor current layer. Obtaining the reference error value of the wafer to be measured based on the average overlay error of multiple batches of wafers to be measured. Before processing the semiconductor current layer of the wafer to be measured, the semiconductor current layer is marked as a structured layer or an unstructured layer according to the degree of structural change in the semiconductor current layer. If the semiconductor current layer is a structured layer, the overlay compensation value of the semiconductor current layer is obtained based on the differences between multiple wafers to be measured in the same batch, and the differences between the wafer to be measured and the reference wafer, and the current layer error compensation value of the semiconductor current layer is obtained based on the overlay compensation value, calibration parameters, and reference error value. If the semiconductor current layer is an unstructured layer, the current layer error compensation value of the preceding semiconductor layer is used as the current layer error compensation value of the semiconductor current layer. The unexpected technical effect of this invention lies in: batch processing of wafers, thereby improving wafer manufacturing efficiency, and the ability to measure the overlay error differences between wafers in the same batch, thus accurately knowing the actual processing status of the wafer under test. Furthermore, the wafer measurement method and system provided by this invention can comprehensively consider factors such as changes in equipment, photomask, and wafer type, accurately depicting the actual overlay error of the wafer under test from multiple perspectives.

[0088] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method of wafer metrology, the method comprising: The method comprises the following steps: setting a reference wafer, which has the same substrate material and the same substrate size as the wafer to be measured; obtaining a theoretical overlay error of a semiconductor layer of the wafer to be measured, and setting a calibration parameter, wherein the calibration parameter is a ratio of an actual overlay error of the semiconductor layer to the theoretical overlay error; obtaining a reference error value of the wafer to be measured according to average overlay errors of multiple batches of the wafer to be measured; before processing a semiconductor layer of the wafer to be measured, marking the semiconductor layer as a structure layer or a non-structure layer according to a structure change degree of the semiconductor layer; if the semiconductor layer is a structure layer, obtaining an overlay compensation value of the semiconductor layer according to differences between multiple wafers to be measured of the same batch and differences between the wafer to be measured and the reference wafer, and obtaining a layer error compensation value of the semiconductor layer according to the overlay compensation value, the calibration parameter and the reference error value; if the semiconductor layer is a non-structure layer, taking a layer error compensation value of a semiconductor pre-layer as a layer error compensation value of the semiconductor layer; and if the semiconductor layer is a structure layer, obtaining the layer error compensation value according to the following formula: Wherein, in the step of acquiring the overlay compensation value, the overlay error difference value of the multiple wafers in the same batch is the first overlay compensation value A n The overlay error difference value of the same batch of wafers generated in the same machine is the second overlay compensation value B n The overlay error difference value of the same batch of wafers generated under the same mask is the third overlay compensation value C n ; The wafer measurement method comprises: where OVL n is the target layer error compensation value for the semiconductor target layer, A n is the first overlay compensation value, B n is the second overlay compensation value, C n is the third overlay compensation value, OVL baseline is the reference error value, and K is a calibration parameter.

2. The wafer metrology method of claim 1, wherein setting multiple compensation types, and inputting system overlay errors of the wafer to be measured under the compensation types; and obtaining a sum of the system overlay errors and the layer error compensation value, and taking the sum as a layer overlay error of the semiconductor layer. The compensation types comprise planar pattern displacement error, pattern rotation error and pattern magnification error.

3. The wafer metrology method of claim 2, wherein, The wafer measurement method further comprises:

4. The wafer metrology method of claim 1, wherein, setting an overlay threshold value; obtaining layer overlay errors of multiple wafers to be measured of the same batch respectively; and when the layer overlay error of the wafer to be measured is greater than the overlay threshold value, replacing the layer overlay error of the wafer to be measured with a layer overlay error of an adjacent wafer to be measured. The wafer measurement method further comprises:

5. The wafer metrology method of claim 1, wherein, setting an overlay threshold value; obtaining layer overlay errors of multiple wafers to be measured of the same batch respectively; and when the layer overlay errors of multiple adjacent wafers to be measured are all greater than the overlay threshold value, obtaining an average overlay error of the wafers to be measured of the same batch, and replacing the layer overlay errors of the wafers to be measured exceeding the threshold value with the average overlay error. The step of distinguishing the semiconductor layer comprises:

6. The wafer metrology method of claim 1, wherein, obtaining a solid pattern structure of a semiconductor pre-layer as a first pattern structure; obtaining a solid pattern structure of a semiconductor design of the semiconductor layer as a second pattern structure; and when the first pattern structure and the second pattern structure are the same, marking the semiconductor layer as a non-structure layer, and when the first pattern structure and the second pattern structure are different, marking the semiconductor layer as a structure layer. The semiconductor layer is a semiconductor layer to be processed, and the semiconductor pre-layer is a semiconductor layer processed.

7. The wafer metrology method of claim 1, wherein, The method comprises:

8. A wafer metrology system for use in the wafer metrology method of any one of claims 1-7, wherein, a reference wafer monitoring module for monitoring a reference wafer, which has the same substrate material and the same substrate size as a wafer to be measured; ​ The calibration parameter acquisition module is configured to acquire a theoretical overlay error of a semiconductor layer of the wafer to be measured, and set a calibration parameter, wherein the calibration parameter is a ratio of an actual overlay error of the semiconductor layer to the theoretical overlay error; The reference error acquisition module is configured to acquire a reference error value of the wafer to be measured according to average overlay errors of multiple batches of the wafer to be measured; The hierarchical distinction module is configured to, before processing the semiconductor layer of the wafer to be measured, mark the semiconductor layer as a structure layer or a non-structure layer according to a structure change degree of the semiconductor layer; The first compensation value acquisition module is configured to, when the semiconductor layer is the structure layer, acquire an overlay compensation value of the semiconductor layer according to differences between multiple wafers to be measured of the same batch and a difference between the wafer to be measured and the reference wafer, and acquire a layer error compensation value of the semiconductor layer according to the overlay compensation value, the calibration parameter and the reference error value; and The second compensation value acquisition module is configured to, when the semiconductor layer is the non-structure layer, take the layer error compensation value of the semiconductor front layer as the layer error compensation value of the semiconductor layer.

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