LDO circuit with off-chip capacitor and chip

Abstract

The invention discloses an LDO circuit with an off-chip capacitor and a chip, and relates to the technical field of integrated circuits. The LDO circuit comprises a feedback control loop, a static branch and a dynamic branch. The feedback control loop comprises an LDO power tube, a feedback network, an error amplifier and a source follower. Wherein the static branch comprises a first resistor connected with the error amplifier in parallel, so that the output impedance of an output node of the error amplifier is reduced, the current flowing through the first resistor is controlled based on the bias voltage, and the static power consumption is reduced. When the current flowing through the LDO power tube is increased, the dynamic branch correspondingly increases the current flowing through the error amplifier so as to reduce the output impedance of the output node of the dynamic branch. Through decoupling of the static current of the static branch and the output impedance of the error amplifier, high-stability and high-performance output of the LDO circuit in a wide load range is achieved while low static power consumption of the LDO circuit is kept, and the LDO circuit is suitable for low static power consumption and large load current scenes.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to an LDO circuit with an off-chip capacitor and a chip. BACKGROUND

[0002] Low dropout regulator (LDO) is widely used in various chip systems due to its simple structure, low output noise, fast transient response and other advantages, especially in analog, radio frequency and high-performance digital circuit modules with high requirements for power supply noise and stability. Among them, LDO with off-chip large capacitor is particularly suitable for chip application scenarios that require high stability and fast dynamic response due to its excellent power supply rejection ratio (PSR) performance at low frequency band and good transient response capability.

[0003] However, in actual design and application, LDO with off-chip large capacitor still faces many challenges, especially in the trade-off between stability and power consumption. For LDO supporting large load current, the main pole is usually located at the output node, which is significantly affected by the off-chip large capacitor, and the phase margin of the LDO is difficult to meet the stability requirement. The traditional method to improve stability includes increasing the static bias current of the error amplifier (EA) or connecting a resistance in parallel with the EA output node to reduce the impedance of the node. However, the former directly increases the overall static power consumption of the LDO, which is not conducive to the application in low-power scenarios; the latter is difficult to simultaneously consider stability and low power consumption requirements due to the coupling relationship between output impedance and branch current.

[0004] The above content is only used to assist in understanding the technical solutions of the present application, and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0005] The main purpose of the present application is to provide an LDO circuit with an off-chip capacitor, which aims to solve the problem that the existing LDO circuit with an off-chip capacitor cannot simultaneously consider stability and low power consumption requirements.

[0006] To achieve the above purpose, the LDO circuit with an off-chip capacitor provided by the present application comprises:

[0007] LDO power output end, for connecting the load with off-chip capacitor;

[0008] Bias voltage input end for inputting bias voltage;

[0009] Reference voltage input end for inputting reference voltage;

[0010] LDO feedback control loop, the LDO feedback control loop comprises LDO power tube, feedback network, error amplifier and source follower; wherein,

[0011] The LDO power tube is connected with the LDO power output terminal and the source follower respectively;

[0012] The feedback network is connected with the error amplifier and the LDO power tube respectively, and is used for outputting a corresponding feedback voltage according to an output voltage of the LDO power tube;

[0013] The error amplifier is connected with the bias voltage input terminal and the reference voltage input terminal respectively, and is connected with the LDO power tube through the source follower; the error amplifier adjusts a current flowing through the LDO power tube based on the bias voltage, the reference voltage and the feedback voltage;

[0014] The static branch is connected with the bias voltage input terminal and the error amplifier respectively; the static branch comprises a first resistor which is arranged in parallel with the error amplifier, so as to reduce an equivalent output impedance of an output node of the error amplifier; the static branch also controls a static current flowing through the first resistor based on the bias voltage;

[0015] The dynamic branch is connected with the error amplifier and the LDO power tube through the source follower; the dynamic branch adjusts a current flowing through the error amplifier based on a current flowing through the LDO power tube.

[0016] In an embodiment, the bias voltage input terminal comprises a first bias voltage input terminal, a second bias voltage input terminal and a third bias voltage input terminal; and the error amplifier comprises a first amplifier tube, a second amplifier tube, a third amplifier tube, a fourth amplifier tube, a fifth amplifier tube, a sixth amplifier tube, a seventh amplifier tube, an eighth amplifier tube and a ninth amplifier tube;

[0017] The first end of the first amplification tube, the first end of the second amplification tube and the second end of the third amplification tube are connected, the controlled end of the third amplification tube is connected with the first bias voltage input end, the first end of the third amplification tube, the first end of the fourth amplification tube and the first end of the fifth amplification tube are connected with the power end of the LDO circuit with the off-chip capacitor, the second end of the first amplification tube, the first end of the sixth amplification tube and the second end of the eighth amplification tube are connected, the controlled end of the second amplification tube is connected with the reference voltage input end, the second end of the second amplification tube, the first end of the seventh amplification tube and the second end of the ninth amplification tube are connected, the controlled end of the first amplification tube is connected with the feedback network, the controlled end of the fourth amplification tube, the controlled end of the fifth amplification tube, the second end of the fourth amplification tube and the second end of the sixth amplification tube are connected, the second end of the fifth amplification tube is connected with the second end of the seventh amplification tube, the controlled end of the sixth amplification tube and the controlled end of the seventh amplification tube are connected with the second bias voltage input end, the controlled end of the eighth amplification tube and the controlled end of the ninth amplification tube are connected with the third bias voltage input end, and the first end of the eighth amplification tube and the first end of the ninth amplification tube are grounded.

[0018] In an embodiment, the static branch further comprises a tenth amplification tube and an eleventh amplification tube.

[0019] The one end of the first resistor is connected with the power end of the LDO circuit with the off-chip capacitor, the other end of the first resistor is connected with the first end of the tenth amplification tube, the controlled end of the tenth amplification tube, the second end of the tenth amplification tube, the second end of the eleventh amplification tube and the second end of the fifth amplification tube are connected, the first end of the eleventh amplification tube is grounded, and the controlled end of the eleventh amplification tube is connected with the third bias voltage input end.

[0020] In an embodiment, the dynamic branch comprises a twelfth amplification tube, a thirteenth amplification tube, a fourteenth amplification tube, a fifteenth amplification tube and a sixteenth amplification tube.

[0021] The controlled end of the twelfth amplification tube is connected with the controlled end of the LDO power tube, the first end of the twelfth amplification tube is connected with the power end of the LDO circuit with the off-chip capacitor, the second end of the twelfth amplification tube, the second end of the fifteenth amplification tube, the controlled end of the fifteenth amplification tube, the controlled end of the fourteenth amplification tube and the controlled end of the thirteenth amplification tube are connected, the second end of the thirteenth amplification tube is connected with the first end of the sixth amplification tube, the second end of the fourteenth amplification tube is connected with the first end of the seventh amplification tube, and the first end of the thirteenth amplification tube, the first end of the fourteenth amplification tube and the first end of the fifteenth amplification tube are grounded.

[0022] In an embodiment, the source follower comprises a sixteenth amplifier, a seventeenth amplifier and an eighteenth amplifier.

[0023] The first end of the sixteenth amplifier is connected to the power end of the LDO circuit with an off-chip capacitor, the controlled end of the sixteenth amplifier, the second end of the sixteenth amplifier, the first end of the seventeenth amplifier and the controlled end of the LDO power tube are connected, the controlled end of the seventeenth amplifier is connected to the second end of the fifth amplifier, the second end of the seventeenth amplifier is connected to the second end of the eighteenth amplifier, the controlled end of the eighteenth amplifier is connected to the third bias voltage input end, and the first end of the eighteenth amplifier is grounded.

[0024] In an embodiment, the feedback network comprises a second resistor and a third resistor.

[0025] The one end of the second resistor is connected to the output end of the LDO power tube, the other end of the second resistor and the one end of the third resistor are connected to the controlled end of the first amplifier, and the other end of the third resistor is grounded.

[0026] In an embodiment, any one or more of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier is a PMOS tube; any one or more of the sixth amplifier, the seventh amplifier, the eighth amplifier and the ninth amplifier is an NMOS tube.

[0027] In an embodiment, the tenth amplifier is a PMOS tube, and the eleventh amplifier is an NMOS tube.

[0028] In an embodiment, the twelfth amplifier is a PMOS tube, and any one or more of the thirteenth amplifier, the fourteenth amplifier, the fifteenth amplifier and the sixteenth amplifier is an NMOS tube.

[0029] The application also provides a chip comprising the LDO circuit with an off-chip capacitor.

[0030] The technical scheme of the application adopts an LDO circuit with an off-chip capacitor, comprising an LDO power output end, a bias voltage input end, a reference voltage input end, an LDO feedback control loop, a static branch and a dynamic branch. The LDO feedback control loop comprises an LDO power transistor, a feedback network, an error amplifier and a source follower. In the LDO feedback control loop, the error amplifier works under the action of the bias voltage, compares the reference voltage and the feedback voltage, and adjusts the LDO power transistor driven by the source follower according to the comparison result, thereby realizing stable control of the output voltage. The application also introduces a static branch and a dynamic branch. The static branch comprises a first resistor connected in parallel with the error amplifier, which can reduce the equivalent output impedance of the error amplifier output node. At the same time, the static branch can control the size of the static current flowing through the first resistor based on the input bias voltage, which can effectively reduce the static power consumption of the LDO circuit under no-load conditions. The dynamic branch is connected with the LDO power transistor through the source follower, and its current changes proportionally with the change of the output current of the LDO power transistor. In this way, when the load current increases, the dynamic branch can correspondingly increase the current flowing through the error amplifier, thereby further reducing the equivalent output impedance of the error amplifier output node and improving the stability and transient response performance of the LDO circuit under large load conditions. Compared with the prior art, the application decouples the static current of the static branch and the output impedance of the error amplifier, realizes high stability and high performance output of the LDO circuit in a wide load range while maintaining low static power consumption of the LDO circuit, effectively balances the design requirements of stability and low power consumption of the LDO circuit, and can be applied to low static power consumption and large load current scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from the structures shown in the drawings without creative labor.

[0032] Figure 1 An electronic circuit diagram of an embodiment of the LDO circuit with an off-chip capacitor provided by the application;

[0033] Figure 2 An electronic circuit diagram of an exemplary large load current LDO provided by the application;

[0034] Figure 3 An exemplary small signal model diagram of a large load current LDO provided by the application;

[0035] Figure 4An exemplary parallel resistor large load current LDO electronic circuit diagram provided in the present application;

[0036] Figure 5 An exemplary parallel resistor large load current LDO electronic circuit diagram provided in the present application;

[0037] Figure 6 An exemplary folded large load current LDO electronic circuit diagram provided in the present application;

[0038] Figure 7 An exemplary folded parallel resistor large load current LDO electronic circuit diagram provided in the present application;

[0039] Figure 8 An analysis diagram of the tenth amplifying tube drain output resistance of an LDO circuit embodiment provided in the present application with an off-chip capacitor.

[0040] Brief Description of the Drawings

[0041]

[0042]

[0043] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work under the premise that the present application falls within the scope of protection.

[0045] It should be noted that all the directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between the components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directionality indications will also change accordingly.

[0046] In addition, the descriptions involving "first", "second" and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the technical features indicated or implying the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the present application.

[0047] As the core module of electronic products, LDO (Low Dropout Regulator) usually provides low-ripple power supply for the entire electronic product. With the continuous emergence of various complex, multi-functional, mobile and portable application scenarios, the load capacity and low static power consumption of LDO are increasingly required by electronic products. Compared with LDO without off-chip capacitor, LDO with off-chip large capacitor usually has better PSR (Power Supply Rejection) capability and transient response.

[0048] However, LDO with off-chip large capacitor still faces many challenges in stability and power consumption. For LDO supporting large load current, the main pole is usually located at the output node, which is significantly affected by the off-chip large capacitor, and the phase margin of the LDO is difficult to meet the stability requirement. The traditional method to improve stability includes increasing the static bias current of the error amplifier (EA) or connecting a resistor in parallel at the output node of the EA to reduce the impedance of the node. However, the former directly increases the overall static power consumption of the LDO, which is not conducive to the application in low-power scenarios; the latter is difficult to simultaneously consider stability and low power consumption requirements due to the coupling relationship between output impedance and branch current.

[0049] Please refer to Figure 2 , Figure 2 The electronic circuit diagram of an exemplary large load current LDO provided by the present application is shown in FIG. 1. The LDO is composed of three stages of circuits, the first stage circuit is an error amplifier (EA) composed of five transistors, the second stage circuit is a source follower, and the third stage circuit is a power transistor and a feedback network. Among them, the current mirror structure composed of power transistor MP23 and power transistor MP24 can improve the PSR of the LDO. Generally, the output impedance of the first stage circuit is large, and the size of the power transistor of the third stage circuit is large to meet the requirement of large load current, so the gate capacitance of the power transistor is large. The second stage circuit as a buffer (BUF) has a small gate capacitance and a small output impedance. Therefore, by introducing the second stage BUF circuit, the high output impedance node and the large capacitance node can be separated, thereby increasing the secondary pole frequency, so that the LDO is more stable or has a wider bandwidth when the capacitance at the output of the LDO is certain.

[0050] For ease of analysis, we can obtain Figure 2 The LDO small-signal model shown is as follows: Figure 3 As shown, gm1 is the transconductance of the first-stage EA, ro1 and C21 are the output impedance and load capacitance of the EA output node, respectively; ro2 and C22 are the output impedance and load capacitance of the source follower output node, respectively (C22 mainly comes from the gate capacitance of the power transistor of the source follower). Therefore, ro2 is usually small, while C22 depends on the size of the power transistor, which can reach tens or even hundreds of picofarads; gmp and romp are the transconductance and output impedance of the third-stage power transistor, respectively. The gain (DC Gain), unity-gain bandwidth (GBW), and phase margin (PM) of the LDO can be easily expressed as:

[0051] Formula 1

[0052] DC Gain = gm1·ro1·gmp·[ro] mp ||R2 L ||(RF21+RF22)]

[0053] Where gm1 is the transconductance of the first-stage EA, ro1 is the output impedance of the EA output node, gmp is the transconductance of the third-stage power transistor, and ro mp R2 is the output impedance of the third-stage power transistor. L RF21 and RF22 are the load resistors, and ro is the two voltage divider resistors for the feedback network. mp ||R2 L ||(RF21+RF22) is the parallel equivalent resistance of the third-stage power transistor, load resistor, and feedback network.

[0054] Formula 2

[0055]

[0056] Where gm1 is the transconductance of the first stage EA, ro1 is the output impedance of the EA output node, gmp is the transconductance of the third stage power transistor, and C2 is the transconductance of the third stage power transistor. L These are external capacitors.

[0057] Formula 3

[0058]

[0059] Where gm1 is the transconductance of the first stage EA, ro1 is the output impedance of the EA output node, gmp is the transconductance of the third stage power transistor, C21 is the load capacitance of the EA output node, and C2 Lro2 is the output impedance of the source follower output node, C22 is the load capacitance of the source follower output node, and ESR2 is the equivalent series resistance of the off-chip capacitor.

[0060] Generally, the improvement of PM by smaller ESR is limited, and this term can be neglected for simplicity. From Equation 3, to achieve LDO stability and larger phase margin, ro1, ro2, C21, C22 can be reduced, or C2 L However, C21 and ro2 are usually small and difficult to reduce further, while C22 is usually mainly the gate capacitance of the power transistor, which depends on the size of the power transistor or the magnitude of the load current, and it is usually determined. The output load capacitance (including the off-chip capacitor C2 L ) is usually limited within a certain range based on cost and area considerations.

[0061] where ro1 is the parallel impedance of the output impedances of MP21 and MN23, which can be approximated by:

[0062] Equation 4,

[0063]

[0064] where λp is the channel modulation coefficient of the power transistor MP21, and I is the current flowing through the power transistor MP1.

[0065] Equation 5,

[0066]

[0067] where λ n is the channel modulation coefficient of the power transistor MP1, and I is the current flowing through the power transistor MN3.

[0068] According to Equations 3 and 4, therefore, one implementation method to improve PM is to directly increase the current I. However, this will limit the application of LDO in low static power consumption scenarios due to the large static current. That is, in low static power consumption LDO, the impedance of the EA output node is usually large.

[0069] Another implementation method can add a pair of resistors R43 and R44 at the 5-tube EA, as shown in Figure 4 Since the output impedance of the first stage circuit becomes the parallel impedance of resistor R4, the output impedance of power transistor MP1, and the output impedance of power transistor MN3, the output impedance at the 5-tube EA can be reduced. Obviously, the current I in Figure 4 is smaller than Figure 2The current I in the branch of resistor R43 and resistor R44 is smaller. However, the branch of resistor R43 and resistor R44 introduces a current, which is determined by resistor R43 and resistor R44 when voltage V0 and voltage V1 are constant, and the branch current cannot be independently regulated. Therefore, the output impedance at the 5-tube EA and the branch current of resistor R43 / resistor R44 are not independently controlled, and in some applications, it is difficult to obtain resistor R43 and resistor R44 to simultaneously meet the requirements of low static power consumption and LDO stability, especially considering that the static voltage may change greatly under PVT (process, voltage and temperature three variables), which may cause the static current to change greatly.

[0070] It should be noted that, Figure 2 and Figure 4 The input pair in the 5-tube structure in the above can be replaced by a PMOS input pair to improve the matching of the LDO, or a SSF (Super-Source-Follower) can be added to push the corresponding pole frequency of the power tube gate node (as shown in Figure 5 , the power tube MN54 and the power tube MN55 are added), or a folded structure is used as shown in Figure 6 and Figure 7 (the input pair can also be an NMOS input pair, which is not limited here), or a 9-tube push-pull structure is used to improve the transient response and reduce the voltage margin requirement, which is not limited here.

[0071] In summary, due to the existence of a large off-chip capacitor, the main pole of the LDO with large load current is usually located at the output node of the error amplifier. In order to meet the stability condition and phase margin condition, an example embodiment is to achieve by increasing the static bias current in the branch of the EA. However, this will increase the static power consumption of the LDO, which cannot meet the demand of long standby time in portable devices. Another example embodiment is to parallel a resistor at the output node of the EA to reduce the output impedance at this point, however, the output impedance at this point and the current on the resistor are coupled together, which makes it difficult to balance the stability (small output impedance requires small parallel resistor) and low static power consumption requirement (low power consumption requires large resistor).

[0072] The present application provides an LDO circuit with an off-chip capacitor.

[0073] Please refer to Figure 1 , in an embodiment of the present application, the LDO circuit with an off-chip capacitor comprises:

[0074] an LDO power output end for connecting a load with an off-chip capacitor;

[0075] a bias voltage input end for inputting a bias voltage;

[0076] a reference voltage input end VREF for inputting a reference voltage;

[0077] The LDO feedback control loop comprises an LDO power transistor MP0, a feedback network 03, an error amplifier 01 and a source follower 02; wherein,

[0078] The LDO power transistor MP0 is connected with the LDO power supply output end and the source follower 02 respectively;

[0079] The feedback network 03 is connected with the error amplifier 01 and the LDO power transistor MP0 respectively, and the feedback network 03 is used for outputting a corresponding feedback voltage according to the output voltage of the LDO power transistor MP0;

[0080] The error amplifier 01 is connected with the bias voltage input end and the reference voltage input end VREF respectively, and is connected with the LDO power transistor MP0 through the source follower 02; the error amplifier 01 adjusts the current size flowing through the LDO power transistor MP0 based on the bias voltage, the reference voltage and the feedback voltage;

[0081] The static branch 04 is connected with the bias voltage input end and the error amplifier 01 respectively; the static branch 04 comprises a first resistor R1 which is arranged in parallel with the error amplifier 01, so as to reduce the equivalent output impedance of the output node of the error amplifier 01; the static branch 04 also controls the static current size flowing through the first resistor R1 based on the bias voltage;

[0082] The dynamic branch 05 is connected with the error amplifier 01 and the LDO power transistor MP0 through the source follower 02; the dynamic branch 05 adjusts the dynamic current size flowing through the error amplifier 01 based on the current size flowing through the LDO power transistor MP0.

[0083] In the embodiment, the LDO power supply output end is connected with a load with an off-chip capacitor. In an embodiment, please refer to Figure 1 , the load with the off-chip capacitor is equivalent to the parallel connection of an off-chip capacitor branch and a load branch, the off-chip capacitor branch is equivalent to the series connection of an equivalent series resistance ESR and a capacitor C L , and the load branch is equivalent to a load resistance R L . It can be understood that the LDO circuit connected with the load with the off-chip capacitor can improve the PSR capability and transient response of the LDO circuit. Wherein, the LDO power supply output end is used for providing the load with the low-noise voltage required by the load.

[0084] In this embodiment, by decoupling the static current of the static branch 04 and the output impedance of the error amplifier 01, independent regulation of the static current of the static branch 04 and the output impedance of the error amplifier 01 is realized, so that the LDO circuit with an off-chip capacitor can meet the high stability requirement in the large load current scenario, and also take into account the low static power consumption design requirement in the no-load state, thereby improving the adaptability and overall performance of the LDO in a wide load range.

[0085] Specifically, the LDO circuit includes an LDO feedback control loop, a static branch 04, and a dynamic branch 05. The LDO feedback control loop includes three circuits, the first circuit is an error amplifier 01, and the second circuit is a source follower 02. The power tube in the source follower 02 can be provided with a small gate capacitance and a small output impedance, so that the high output impedance node of the first circuit is separated from the large capacitance node of the LDO power output end, thereby improving the sub-pole frequency, so that the LDO is more stable and has a wider bandwidth when the capacitance at the LDO output is certain. The third circuit includes an LDO power tube MP0 and a feedback network 03. In the LDO feedback control loop, the error amplifier 01 is connected to the controlled end of the LDO power tube MP0 through the source follower 02. When the output voltage of the LDO power tube MP0 is detected to be greater than the reference voltage according to the feedback voltage, the current flowing through the LDO power tube MP0 is reduced to reduce the output voltage of the LDO power tube MP0; when the output voltage of the LDO power tube MP0 is detected to be less than the reference voltage according to the feedback voltage, the current flowing through the LDO power tube MP0 is increased to increase the output voltage of the LDO power tube MP0. The bias voltage input end provides a bias voltage, so that the amplifying tube in the error amplifier 01 works in the correct region, thereby realizing the amplifying function. The amplifying tube can be a MOS tube or a BJT tube, etc., which is not limited here. In this way, when the LDO circuit is connected to the power supply, a stable voltage can be output to the load through the LDO power tube MP0 and the LDO power output end.

[0086] In the embodiment, when the LDO circuit is in an idle state, the current flowing through the LDO power tube MP0 is zero, and at this time, the equivalent output impedance of the output node of the error amplifier 01 is reduced through the static branch 04. Specifically, the static branch 04 includes a first resistor R1 arranged in parallel with the error amplifier 01. Since the parallel resistor has the effect of reducing the equivalent impedance, the impedance of the output node of the error amplifier 01 can be appropriately reduced by adjusting the resistance value of the first resistor R1. In addition, the static branch 04 can dynamically adjust the static current flowing through the first resistor R1 by receiving a controlled bias voltage. This enables the LDO to significantly reduce the current flowing through the first resistor R1 under idle conditions, thereby effectively reducing the static power consumption of the entire LDO circuit. Specifically, the current regulation function can be realized through a current mirror structure, which generates a reference current using a bias voltage and proportionally copies the current to the branch where the first resistor R1 is located, so that the static current flowing through the first resistor can be maintained at a very low level while ensuring the stability of the circuit bias. In this way, the embodiment realizes independent regulation of the equivalent output impedance of the output node of the error amplifier 01 and the static current of the static branch under idle conditions by setting the static branch 04, while ensuring the stability of the LDO circuit, effectively meeting the needs of low-power application scenarios. It should be noted that in some power-sensitive application scenarios, such as mobile devices or battery-powered systems, the static power consumption of the LDO circuit directly affects the energy efficiency of the overall system. Compared with the prior art, the embodiment can realize the unification of high performance and low power consumption of the LDO circuit without sacrificing stability and response speed by inputting a controlled bias voltage and setting a parallel first resistor R1, thereby improving the adaptability and practicality in complex application environments.

[0087] It should be noted that the equivalent output impedance of the output node of the error amplifier 01 is an equivalent impedance viewed from the output node of the error amplifier 01. The first resistor R1 is arranged in parallel with the error amplifier 01, and at this time, the equivalent impedance of the output node can be regarded as the parallel value of the output impedance of the error amplifier 01 itself and the first resistor R1, thereby effectively reducing the output impedance of the entire output node.

[0088] It should be noted that according to formula four and formula five, the current flowing through the error amplifier 01 is inversely proportional to the equivalent output impedance of the output node of the error amplifier 01, therefore, by increasing the current flowing through the error amplifier 01, the equivalent output impedance of the output node of the error amplifier 01 can be effectively reduced, thereby improving the stability and transient response capability of the LDO circuit. In the embodiment, the dynamic branch 05 is connected to the LDO power tube MP0 through the source follower 02, for example, the amplifying tube in the dynamic branch 05 can form a current mirror structure with the LDO power tube MP0, so that the dynamic current in the dynamic branch 05 can change proportionally with the change of the output current of the LDO power tube MP0. Therefore, when the required current of the load increases, the dynamic branch 05 can increase the current flowing through the error amplifier 01 according to the output current of the LDO power tube MP0, thereby reducing the equivalent output impedance of the output node of the error amplifier 01. Compared with the prior art, the embodiment can still maintain good stability and fast response capability when facing large load current scenarios, thereby better meeting the performance requirements under large load current conditions.

[0089] In the present application, by decoupling the static current of the static branch 04 and the output impedance of the error amplifier 01, independent regulation of the static current of the static branch 04 and the output impedance of the output node of the error amplifier 01 is realized. In the LDO feedback control loop, the error amplifier 01 compares the reference voltage with the feedback voltage to adjust the LDO power tube MP0 driven by the source follower 02, thereby realizing stable control of the output voltage. The static branch 04 includes a first resistor R1 connected in parallel with the error amplifier 01, which can reduce the equivalent output impedance of the output node of the error amplifier 01. At the same time, the static branch 04 can control the size of the static current flowing through the first resistor according to the input bias voltage, thereby effectively reducing the static power consumption of the LDO circuit under no-load conditions. The dynamic branch 05 is connected to the LDO power tube MP0 through the source follower 02, for example, can form a current mirror structure with the LDO power tube MP0, so that its current changes proportionally with the change of the output current of the LDO power tube MP0. In this way, when the load current increases, the dynamic branch 05 can increase the current flowing through the error amplifier 01, thereby further reducing the equivalent output impedance of the output node of the error amplifier 01, improving the stability and transient response performance of the LDO circuit under large load conditions. Compared with the prior art, the present application decouples the static current of the static branch 04 and the output impedance of the error amplifier 01, while maintaining the low static power consumption of the LDO circuit, realizing high stability and high performance output in a wide load range, effectively balancing the design requirements of system stability and low power consumption.

[0090] Please refer to Figure 1In an embodiment of the present application, the bias voltage input end includes a first bias voltage input end VBP1, a second bias voltage input end VBN2, and a third bias voltage input end VBN3, and the error amplifier 01 includes a first amplification tube MP1, a second amplification tube MP2, a third amplification tube MP3, a fourth amplification tube MP4, a fifth amplification tube MP5, a sixth amplification tube MN6, a seventh amplification tube MN7, an eighth amplification tube MN8, and a ninth amplification tube MN9.

[0091] The first end of the first amplification tube MP1, the first end of the second amplification tube MP2, and the second end of the third amplification tube MP3 are connected, the controlled end of the third amplification tube MP3 is connected with the first bias voltage input end VBP1, the first end of the third amplification tube MP3, the first end of the fourth amplification tube MP4, and the first end of the fifth amplification tube MP5 are connected with the power end of the LDO circuit with an external capacitor, the second end of the first amplification tube MP1, the first end of the sixth amplification tube MN6, and the second end of the eighth amplification tube MN8 are connected, the controlled end of the second amplification tube MP2 is connected with the reference voltage input end VREF, the second end of the second amplification tube MP2, the first end of the seventh amplification tube MN7, and the second end of the ninth amplification tube MN9 are connected, the controlled end of the first amplification tube MP1 is connected with the feedback network 03, the controlled end of the fourth amplification tube MP4, the controlled end of the fifth amplification tube MP5, the second end of the fourth amplification tube MP4, and the second end of the sixth amplification tube MN6 are connected, the second end of the fifth amplification tube MP5 is connected with the second end of the seventh amplification tube MN7, the controlled end of the sixth amplification tube MN6 and the controlled end of the seventh amplification tube MN7 are connected with the second bias voltage input end VBN2, the controlled end of the eighth amplification tube MN8 and the controlled end of the ninth amplification tube MN9 are connected with the third bias voltage input end VBN3, and the first end of the eighth amplification tube MN8 and the first end of the ninth amplification tube MN9 are grounded.

[0092] In the embodiment, any one or more of the first amplification tube MP1, the second amplification tube MP2, the third amplification tube MP3, the fourth amplification tube MP4, and the fifth amplification tube MP5 can be a PMOS tube, wherein the gate of the PMOS tube is the controlled end of the amplification tube, the source of the PMOS tube is the first end of the amplification tube, and the drain of the PMOS tube is the second end of the amplification tube. Any one or more of the sixth amplification tube MN6, the seventh amplification tube MN7, the eighth amplification tube MN8, and the ninth amplification tube MN9 can be an NMOS tube. Wherein the gate of the NMOS tube is the controlled end of the amplification tube, the source of the NMOS tube is the first end of the amplification tube, and the drain of the NMOS tube is the second end of the amplification tube.

[0093] In this embodiment, the error amplifier 01 is a 9-tube structure and is connected to three bias voltage inputs. The first to third bias voltage inputs are used to set appropriate quiescent operating points for each amplifier tube, ensuring that the error amplifier 01 can operate normally under different load conditions. The first amplifier tube MP1 and the second amplifier tube MP2 form a differential input pair, which can compare the feedback voltage with the reference voltage to generate a differential signal output; the third amplifier tube MP3 inputs the first bias voltage, wherein the first bias voltage is a common source current source for the differential pair, determining the operating current of the input stage; the fourth to ninth amplifier tubes MN9 form a multi-stage current mirror, which is used to improve the transient response and reduce the voltage margin requirement, and realize fine control of the current flowing through the LDO power tube MP0.

[0094] In this embodiment, the fourth amplifier tube MP4, the sixth amplifier tube MN6 and the eighth amplifier tube MN8 form one current branch of the error amplifier 01, and the fifth amplifier tube MP5, the seventh amplifier tube MN7 and the ninth amplifier tube MN9 form another current branch of the error amplifier 01. When the LDO circuit has a large load current, the dynamic current of the dynamic branch 05 is increased to the two branches of the error amplifier 01, which can further reduce the output impedance of the output node of the error amplifier 01, push up the pole frequency corresponding to the output node of the error amplifier 01, and thus improve the unity gain bandwidth of the LDO circuit and improve its stability.

[0095] Please refer to Figure 1 In an embodiment of the present application, the static branch 04 further includes a tenth amplifier tube MP10 and an eleventh amplifier tube MN11.

[0096] In this embodiment, one end of the first resistor R1 is connected to the power supply end of the LDO circuit with an external capacitor, the other end of the first resistor R1 is connected to the first end of the tenth amplifier tube MP10, the controlled end of the tenth amplifier tube MP10, the second end of the tenth amplifier tube MP10, the second end of the eleventh amplifier tube MN11 and the second end of the fifth amplifier tube MP5 are connected, the first end of the eleventh amplifier tube MN11 is grounded, and the controlled end of the eleventh amplifier tube MN11 is connected to the third bias voltage input VBN3.

[0097] In this embodiment, the tenth amplifier tube MP10 can be a PMOS tube, wherein the gate of the PMOS tube is the controlled end of the tenth amplifier tube MP10, the source of the PMOS tube is the first end of the tenth amplifier tube MP10, and the drain of the PMOS tube is the second end of the tenth amplifier tube MP10. The eleventh amplifier tube MN11 can be an NMOS tube, wherein the gate of the NMOS tube is the controlled end of the eleventh amplifier tube MN11, the source of the NMOS tube is the first end of the eleventh amplifier tube MN11, and the drain of the NMOS tube is the second end of the eleventh amplifier tube MN11.

[0098] In this embodiment, the equivalent output impedance of the error amplifier 01 output node can be controlled by the width-to-length ratio of the first resistor R1 and the diode-connected MOS transistor (tenth amplifier transistor MP10). In this embodiment, to obtain the influence of the static branch 04 on the output impedance of the error amplifier 01 output node, the output impedance viewed from the drain of the diode-connected tenth amplifier transistor MP10 is analyzed. Its connection diagram and small-signal analysis diagram are shown below. Figure 8 As shown, gm and rout MP10 The transconductance and output impedance of the tenth amplifier transistor MP10 are respectively given. The test voltage source and test current for the output impedance analysis are V. X and I X Then we have:

[0099] Formula 6

[0100] [I X -g m ·(V X -I X .R1)]·rout MP10 +I X ·R1=V X

[0101] After approximation using Formula Six, the output impedance R of the tenth amplifier transistor MP10 when viewed from the drain upwards can be obtained. out for:

[0102] Formula 7

[0103] R out =V X / I X ≈R1

[0104] When the LDO circuit is unloaded, the output impedance of the error amplifier 01 output node can be controlled by the static branch 04, while the static current I... R The error amplifier 01 is controlled by a current mirror controlled by a third bias voltage, thus allowing independent control of its current I and output impedance under no-load conditions. Specifically, the output impedance of the output node of the error amplifier 01 can be expressed as:

[0105] Formula 8

[0106] Rout = rout MP5 ||(gm MN7 ·rout MN7 ·rout MN9 )||rout MN11 ||R1

[0107] Among them, rout MP5 ,rout MN7, rout MN9 , rout MN7 , rout R , rout

[0108] Thus, the embodiment can reduce the equivalent output impedance of the output node of the error amplifier 01 through the static branch 04 composed of the first resistor R1, the tenth amplifier MP10 and the eleventh amplifier MN11. In addition, the current I R through the first resistor R1 can be controlled based on the third bias voltage, the eighth amplifier MN8, the eleventh amplifier MN11 and the current mirror composed of other amplifiers. Therefore, the embodiment can enhance the stability of the LDO circuit and reduce the static power consumption of the LDO circuit under the no-load condition.

[0109] Please refer to Figure 1 In an embodiment of the present application, the dynamic branch 05 includes a twelfth amplifier MP12, a thirteenth amplifier MN13, a fourteenth amplifier MN14, a fifteenth amplifier MN15 and a sixteenth amplifier MN16.

[0110] The controlled end of the twelfth amplifier MP12 is connected with the controlled end of the LDO power transistor MP0, the first end of the twelfth amplifier MP12 is connected with the power supply end of the LDO circuit with an off-chip capacitor, the second end of the twelfth amplifier MP12, the second end of the fifteenth amplifier MN15, the controlled end of the fifteenth amplifier MN15, the controlled end of the fourteenth amplifier MN14 and the controlled end of the thirteenth amplifier MN13 are connected, the second end of the thirteenth amplifier MN13 is connected with the first end of the sixth amplifier MN6, the second end of the fourteenth amplifier MN14 is connected with the first end of the seventh amplifier MN7, and the first end of the thirteenth amplifier MN13, the first end of the fourteenth amplifier MN14 and the first end of the fifteenth amplifier MN15 are grounded.

[0111] In the embodiment, the twelfth amplifier MP12 can be a PMOS transistor, wherein the gate of the PMOS transistor is the controlled end of the twelfth amplifier MP12, the source of the PMOS transistor is the first end of the twelfth amplifier MP12, and the drain of the PMOS transistor is the second end of the twelfth amplifier MP12. Any one or more of the thirteenth amplifier MN13, the fourteenth amplifier MN14, the fifteenth amplifier MN15 and the sixteenth amplifier MN16 can be an NMOS transistor, wherein the gate of the NMOS transistor is the controlled end of the amplifier, the source of the NMOS transistor is the first end of the amplifier, and the drain of the NMOS transistor is the second end of the amplifier.

[0112] In the embodiment, when the LDO circuit is not in the no-load state, the output impedance of the output node of the error amplifier 01 can be further reduced by the dynamic branch 05 composed of the twelfth amplification tube MP12, the thirteenth amplification tube MN13, the fourteenth amplification tube MN14 and the fifteenth amplification tube MN15, thereby ensuring the stability of the LDO under a large load current. The twelfth amplification tube MP12 and the LDO power tube MP0 form a current mirror structure, the current of the dynamic branch 05 is in a proportional relationship with the current of the LDO power tube MP0, and the current Idyn of the dynamic branch 05 can adjust the current I flowing through the error amplifier 01. Therefore, under the condition of a large load current, the current I of the error amplifier 01 also increases accordingly, which reduces the equivalent output impedance of the output node of the error amplifier 01 and improves the stability of the LDO circuit under a large load current.

[0113] Please refer to Figure 1 In an embodiment of the present application, the source follower 02 includes the sixteenth amplification tube MN16, the seventeenth amplification tube MN17 and the eighteenth amplification tube MN18.

[0114] The first end of the sixteenth amplification tube MN16 is connected to the power supply end of the LDO circuit with an external capacitor, the controlled end of the sixteenth amplification tube MN16, the second end of the sixteenth amplification tube MN16, the first end of the seventeenth amplification tube MN17 and the controlled end of the LDO power tube MP0 are connected, the controlled end of the seventeenth amplification tube MN17 is connected to the second end of the fifth amplification tube MP5, the second end of the seventeenth amplification tube MN17 is connected to the second end of the eighteenth amplification tube MN18, the controlled end of the eighteenth amplification tube MN18 is connected to the third bias voltage input end VBN3, and the first end of the eighteenth amplification tube MN18 is grounded.

[0115] In the embodiment, the source follower 02 composed of the sixteenth amplification tube MN16, the seventeenth amplification tube MN17 and the eighteenth amplification tube MN18 can separate the output node of the error amplifier 01 from the large external capacitor node, thereby increasing the sub-pole frequency, making the LDO circuit more stable and wider under the condition of a certain external capacitor at the output of the LDO circuit, and meeting the demand of high-performance LDO application scenarios.

[0116] It should be noted that, in order to push up the pole frequency corresponding to the power tube gate node, the source follower 02 can increase the SSF circuit as shown in Figure 5 For example, a nineteenth amplification tube and a twentieth amplification tube can be additionally provided, wherein the second end of the nineteenth amplification tube is connected to the controlled end of the sixteenth amplification tube MN16, the controlled end of the nineteenth amplification tube is connected to the second end of the seventeenth amplification tube MN17, the first end of the nineteenth amplification tube is connected to the second end of the twentieth amplification tube, the controlled end of the twentieth amplification tube is connected to the controlled end of the nineteenth amplification tube, and the first end of the twentieth amplification tube is grounded.

[0117] Please refer to Figure 1 In an embodiment of the present application, the feedback network 03 comprises a second resistor RF1 and a third resistor RF2.

[0118] The second resistor RF1 has one end connected to the output terminal of the LDO power transistor MP0, and the other end and one end of the third resistor RF2 are connected to the controlled terminal of the first amplifier transistor MP1, and the other end of the third resistor RF2 is grounded.

[0119] In this embodiment, the second resistor RF1 and the third resistor RF2 together form a voltage dividing circuit, which can output a corresponding feedback voltage to the error amplifier 01 according to the output voltage of the LDO power transistor MP0. The error amplifier 01 can accurately control the output of the LDO power transistor MP0 according to the feedback voltage and the reference voltage, so that the output voltage of the LDO power transistor MP0 remains stable.

[0120] The present application also provides a chip comprising an LDO circuit with an off-chip capacitor. The specific structure of the LDO circuit with an off-chip capacitor is referred to the above embodiments. Since the chip uses all the technical solutions of the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0121] The above is only an exemplary embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation made by referring to the content of the present application specification and drawings, or direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. An LDO circuit with off-chip capacitance, characterized by, The application relates to an LDO power supply output end for connecting a load with an off-chip capacitor, a bias voltage input end for inputting a bias voltage, a reference voltage input end for inputting a reference voltage, an LDO feedback control loop including an LDO power tube, a feedback network, an error amplifier and a source follower, wherein the LDO power tube is connected with the LDO power supply output end and the source follower; the feedback network is connected with the error amplifier and the LDO power tube, and outputs a corresponding feedback voltage according to the output voltage of the LDO power tube; the error amplifier is connected with the bias voltage input end and the reference voltage input end, and is connected with the LDO power tube through the source follower; the error amplifier adjusts the current flowing through the LDO power tube based on the bias voltage, the reference voltage and the feedback voltage; a static branch is connected with the bias voltage input end and the error amplifier, and includes a first resistor connected with the error amplifier in parallel to reduce the equivalent output impedance of the error amplifier output node; the static branch also controls the static current flowing through the first resistor based on the bias voltage; a dynamic branch is connected with the error amplifier and the LDO power tube through the source follower; the dynamic branch adjusts the current flowing through the error amplifier based on the current flowing through the LDO power tube. The bias voltage input end includes a first bias voltage input end, a second bias voltage input end and a third bias voltage input end; the error amplifier includes a first amplifier tube, a second amplifier tube, a third amplifier tube, a fourth amplifier tube, a fifth amplifier tube, a sixth amplifier tube, a seventh amplifier tube, an eighth amplifier tube and a ninth amplifier tube. ​ ​ ​ ​ ​ ​ ​ ​ 2. The LDO circuit with off-chip capacitance of claim 1, wherein, ​ The first end of the first amplification tube, the first end of the second amplification tube and the second end of the third amplification tube are connected, the controlled end of the third amplification tube is connected with the first bias voltage input end, the first end of the third amplification tube, the first end of the fourth amplification tube and the first end of the fifth amplification tube are connected with the power supply end of the LDO circuit with the band off-capacitor, the second end of the first amplification tube, the first end of the sixth amplification tube and the second end of the eighth amplification tube are connected, the controlled end of the second amplification tube is connected with the reference voltage input end, the second end of the second amplification tube, the first end of the seventh amplification tube and the second end of the ninth amplification tube are connected, the controlled end of the first amplification tube is connected with the feedback network, the controlled end of the fourth amplification tube, the controlled end of the fifth amplification tube, the second end of the fourth amplification tube and the second end of the sixth amplification tube are connected, the second end of the fifth amplification tube is connected with the second end of the seventh amplification tube, the controlled end of the sixth amplification tube and the controlled end of the seventh amplification tube are connected with the second bias voltage input end, the controlled end of the eighth amplification tube and the controlled end of the ninth amplification tube are connected with the third bias voltage input end, and the first end of the eighth amplification tube is grounded with the first end of the ninth amplification tube.

3. The LDO circuit with off-chip capacitance of claim 2, wherein, The static branch further comprises a tenth amplification tube and an eleventh amplification tube; The first end of the first resistance is connected with the power supply end of the LDO circuit with the band off-capacitor, the other end of the first resistance is connected with the first end of the tenth amplification tube, the controlled end of the tenth amplification tube, the second end of the tenth amplification tube, the second end of the eleventh amplification tube and the second end of the fifth amplification tube are connected, the first end of the eleventh amplification tube is grounded, and the controlled end of the eleventh amplification tube is connected with the third bias voltage input end.

4. The LDO circuit with off-chip capacitance of claim 2, wherein, The dynamic branch comprises a twelfth amplification tube, a thirteenth amplification tube, a fourteenth amplification tube, a fifteenth amplification tube and a sixteenth amplification tube; The controlled end of the twelfth amplification tube is connected with the controlled end of the LDO power tube, the first end of the twelfth amplification tube is connected with the power supply end of the LDO circuit with the band off-capacitor, the second end of the twelfth amplification tube, the second end of the fifteenth amplification tube, the controlled end of the fifteenth amplification tube, the controlled end of the fourteenth amplification tube and the controlled end of the thirteenth amplification tube are connected, the second end of the thirteenth amplification tube is connected with the first end of the sixth amplification tube, the second end of the fourteenth amplification tube is connected with the first end of the seventh amplification tube, and the first end of the thirteenth amplification tube, the first end of the fourteenth amplification tube and the first end of the fifteenth amplification tube are grounded.

5. The LDO circuit with off-chip capacitance of claim 2, wherein, The source follower comprises a sixteenth amplification tube, a seventeenth amplification tube and an eighteenth amplification tube; The first end of the sixteenth amplification tube is connected with the power supply end of the LDO circuit with the strap external capacitor, the controlled end of the sixteenth amplification tube, the second end of the sixteenth amplification tube, the first end of the seventeenth amplification tube and the controlled end of the LDO power tube are connected, the controlled end of the seventeenth amplification tube is connected with the second end of the fifth amplification tube, the second end of the seventeenth amplification tube is connected with the second end of the eighteenth amplification tube, the controlled end of the eighteenth amplification tube is connected with the third bias voltage input end, and the first end of the eighteenth amplification tube is grounded.

6. The LDO circuit with off-chip capacitance of claim 2, wherein, The feedback network comprises a second resistor and a third resistor; The one end of the second resistor is connected with the output end of the LDO power tube, the other end of the second resistor and the one end of the third resistor are connected with the controlled end of the first amplification tube, and the other end of the third resistor is grounded.

7. The LDO circuit with off-chip capacitance of claim 2, wherein, Any one or more of the first amplification tube, the second amplification tube, the third amplification tube, the fourth amplification tube and the fifth amplification tube is a PMOS tube; any one or more of the sixth amplification tube, the seventh amplification tube, the eighth amplification tube and the ninth amplification tube is an NMOS tube.

8. The LDO circuit with off-chip capacitance of claim 3, wherein, The tenth amplification tube is a PMOS tube, and the eleventh amplification tube is an NMOS tube.

9. The LDO circuit with off-chip capacitance of claim 4, wherein, The twelfth amplification tube is a PMOS tube, and any one or more of the thirteenth amplification tube, the fourteenth amplification tube, the fifteenth amplification tube and the sixteenth amplification tube is an NMOS tube.

10. A chip, characterized by The LDO circuit with the strap external capacitor comprises the LDO circuit with the strap external capacitor as claimed in any one of claims 1 to 9.

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