Data storage system, data storage method and computer readable storage medium

Abstract

The invention relates to a data storage system, a data storage method and a computer readable storage medium. The data storage system according to one aspect of the present application comprises: a processing unit for sending one or more data acquisition requests, the data acquisition requests comprising one or more addresses cached by the data requested to be acquired; the first data cache region comprises one or more data cache units which are in communication connection; the one or more data caching units receive a data acquisition request from the processing unit, selectively acquire a first type of data from the memory unit based on a first address in the data acquisition request and cache the first type of data; and the second data cache region is configured to receive a data acquisition request from the processing unit, acquire second type data from the memory unit based on a second address in the data acquisition request and cache the second type data.

Description

TECHNICAL FIELD

[0001] The present application relates generally to computer technology, and more particularly to a data storage system, a data storage method and a computer readable storage medium. BACKGROUND

[0002] The development of computer technology has led to a large amount of data, which needs to be stored in a certain form in a storage system. In the whole life cycle from generation to extinction of data, there are different input and output access characteristics in different stages. For example, in the data generation stage, data needs to be written into the storage system at high speed; in the data analysis stage, data needs to be read out from the storage system at high speed to participate in the calculation.

[0003] Current storage systems are generally divided into consistent storage systems and non-consistent storage systems. Consistent storage systems refer to a distributed system in which all nodes access data in strict consistency model, ensuring real-time consistency of data, and having the advantage of high affinity. However, the consistent storage system has high management complexity of data, and is prone to live lock and dead lock problems. Non-consistent storage systems allow data to exist differently on different nodes within a certain time, which usually adopts the eventual consistency model, that is, data will eventually reach a consistent state, but not necessarily in real time. However, the data affinity of the non-consistent storage system is poor, and the average access delay is large. SUMMARY

[0004] In order to solve or at least alleviate one or more of the above problems, the following technical solutions are provided.

[0005] According to a first aspect of the present application, a data storage system is provided, the data storage system comprising: a processing unit configured to send one or more data acquisition requests, the data acquisition request comprising one or more addresses of cached data requested to be acquired; a first data cache area comprising one or more communicatively connected data cache units, the one or more data cache units receiving the data acquisition request from the processing unit and selectively acquiring first type data from a memory unit and caching the first type data based on a first address in the data acquisition request; and a second data cache area configured to receive the data acquisition request from the processing unit and acquire second type data from the memory unit and cache the second type data based on a second address in the data acquisition request.

[0006] According to an embodiment of the present application, the one or more addresses of cached data requested to be acquired are used to indicate that the data requested to be acquired is first type data or second type data.

[0007] According to the data storage system of any one of the preceding embodiments or any one of the preceding embodiments, the processing unit is configured to: determine the requested data as first type data or second type data based on a frequency at which the requested data is shared by one or more processing nodes; determine to send the one or more data fetch requests to the first data cache area based on the determination of the requested data as first type data; and determine to send the one or more data fetch requests to the second data cache area based on the determination of the requested data as second type data.

[0008] According to the data storage system of any one of the preceding embodiments or any one of the preceding embodiments, the data storage system further comprises a control unit, the first data cache area comprises a first data cache unit and a second data cache unit, and the control unit is connected between the first data cache area and the memory unit and configured to: fetch first type data corresponding to a first address from the memory unit and send the first type data to the first data cache unit in response to the first address in the data fetch request received by the first data cache unit; and control the first data cache unit to send first type data corresponding to the first address to the second data cache unit in response to the first address in the data fetch request received by the second data cache unit.

[0009] According to the data storage system of any one of the preceding embodiments or any one of the preceding embodiments, the control unit is further configured to: determine an order in which the first data cache unit and the second data cache unit receive data fetch requests corresponding to the first address; and fetch first type data corresponding to the first address from the memory unit and send the first type data to the first data cache unit based on the order, and control the first data cache unit to send first type data corresponding to the first address to the second data cache unit.

[0010] According to the data storage system of any one of the preceding embodiments or any one of the preceding embodiments, the processing unit is further configured to: send the data fetch requests corresponding to the first type data and the data fetch requests corresponding to the second type data to the first data cache area and the second data cache area, respectively, via independent channels.

[0011] According to the data storage system of any one of the preceding embodiments or any one of the preceding embodiments, the one or more communicatively connected data cache units are configured to cache first type data corresponding to different addresses, respectively, at the same time.

[0012] According to the data storage system of any one of the preceding embodiments, the first data cache region and the second data cache region share a bandwidth of the memory unit.

[0013] According to the data storage system of any one of the preceding embodiments, the second data cache region comprises: a first data cache unit configured to receive a data fetch request from the processing unit and fetch second type data from the memory unit directly based on a second address in the data fetch request and cache the second type data; and a second data cache unit configured to receive a data fetch request from the processing unit and fetch second type data from the memory unit directly based on a third address in the data fetch request and cache the second type data.

[0014] According to the data storage system of any one of the preceding embodiments, the processing unit comprises one or more cores of a multi-core processor, and the memory unit is a double data rate synchronous dynamic random access memory.

[0015] According to a second aspect of the present application, there is provided a data storage method, the method comprising: sending one or more data fetch requests, the data fetch request comprising one or more addresses of cached data to be fetched; selectively fetching first type data from a memory unit based on a first address in the data fetch request and caching the first type data to a first data cache region, the first data cache region comprising one or more communicatively connected data cache units; and fetching second type data from the memory unit based on a second address in the data fetch request and caching the second type data to a second data cache region.

[0016] According to the data storage method of any one of the preceding embodiments, the one or more addresses of cached data to be fetched are used to indicate that the data to be fetched is first type data or second type data.

[0017] According to the data storage method of any one of the preceding embodiments, sending one or more data fetch requests comprises: determining the data to be fetched as first type data or second type data based on a frequency at which the data to be fetched is shared by one or more processing nodes; determining to send the one or more data fetch requests to the first data cache region based on determining the data to be fetched as first type data; and determining to send the one or more data fetch requests to the second data cache region based on determining the data to be fetched as second type data.

[0018] According to the data storage method of any one of the preceding embodiments or the embodiment of the present application, wherein the first data cache area comprises a first data cache unit and a second data cache unit, and the selectively obtaining the first type data from the memory unit and caching the first type data to the first data cache area based on the first address in the data obtaining request comprises: obtaining the first type data corresponding to the first address from the memory unit and sending the first type data to the first data cache unit for caching in response to the first address in the data obtaining request received by the first data cache unit; and controlling the first data cache unit to send the first type data corresponding to the first address to the second data cache unit for caching in response to the first address in the data obtaining request received by the second data cache unit.

[0019] According to the data storage method of any one of the preceding embodiments or the embodiment of the present application, wherein the method further comprises: determining the order in which the first data cache unit and the second data cache unit receive the data obtaining request corresponding to the first address; and based on the order, obtaining the first type data corresponding to the first address from the memory unit and sending the first type data to the first data cache unit, and controlling the first data cache unit to send the first type data corresponding to the first address to the second data cache unit.

[0020] According to the data storage method of any one of the preceding embodiments or the embodiment of the present application, wherein sending one or more data obtaining requests comprises: sending the data obtaining request corresponding to the first type data and the data obtaining request corresponding to the second type data to the first data cache area and the second data cache area respectively via independent channels.

[0021] According to the data storage method of any one of the preceding embodiments or the embodiment of the present application, wherein the one or more communicatively connected data cache units are configured to cache the first type data corresponding to different addresses respectively at the same time.

[0022] According to the data storage method of any one of the preceding embodiments or the embodiment of the present application, wherein the first data cache area and the second data cache area share the bandwidth of the memory unit.

[0023] According to the data storage method of any one of the preceding embodiments or the embodiment of the present application, wherein the second data cache area comprises a first data cache unit and a second data cache unit, and the method further comprises: based on a second address in the data obtaining request, directly obtaining the second type data from the memory unit and caching the second type data; and based on a third address in the data obtaining request, directly obtaining the second type data from the memory unit and caching the second type data.

[0024] According to a third aspect of the present application, a computer readable storage medium is provided, and the computer readable storage medium stores instructions, and when the instructions are executed by a processor, the processor performs the data storage method according to the second aspect of the present application.

[0025] The data storage scheme according to one or more embodiments of the present application can identify the type of the requested data by the address in the data acquisition request, and acquire and cache the requested data by using different data caching strategies and data caching areas, thereby improving data affinity and reducing data access delay. The data storage scheme according to one or more embodiments of the present application has the advantages of cost saving, simple control, easy implementation, etc. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above and / or other aspects and advantages of the present application will become more apparent and more readily appreciated by referring to the following detailed description in conjunction with the accompanying drawings, in which like reference numerals refer to like elements throughout the drawings. In the drawings:

[0027] Figure 1 A structural block diagram of a data storage system according to one or more embodiments of the present application is shown.

[0028] Figure 2 A structural block diagram of a data storage system according to one or more embodiments of the present application is shown.

[0029] Figure 3 A flowchart of a data storage method according to one or more embodiments of the present application is shown. DETAILED DESCRIPTION

[0030] The present application will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the application are shown. The present application may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0031] In the context of the present application, terms such as "comprising" and "including" mean that the technical solution of the present application does not exclude the presence of other elements or steps not directly or explicitly described in the specification and claims.

[0032] In the context of the present application, unless otherwise specified, terms such as "first" and "second" do not mean the order of the elements in time, space, size, etc., but only distinguish the elements.

[0033] In the context of the present application, "connected" is to be understood as including the case where two units are directly connected, and the case where two units are connected via one or more intermediate units. In the context of the present application, "address" is to be understood as including the case where data is cached at a certain address, and the case where data is cached in a range of addresses.

[0034] In the following, various exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 A structural block diagram of a data storage system according to one or more embodiments of the present application is shown.

[0036] As shown in FIG. 1, the data storage system 100 includes a processing unit 110, a first data cache region 120 and a second data cache region 130 communicatively connected with the processing unit 110, and a memory unit 140 communicatively connected with the first data cache region 120 and the second data cache region 130. Figure 1 The processing unit 110 is configured to send one or more data fetch requests to the first data cache region 120 and / or the second data cache region 130, the data fetch requests including one or more addresses at which data requested to be fetched is cached. Optionally, the one or more addresses at which the data requested to be fetched is cached is used to indicate that the data requested to be fetched is first type data or second type data.

[0037] Optionally, the processing unit 110 can be configured to determine the data requested to be fetched as the first type data or the second type data based on a frequency at which the data requested to be fetched is shared by one or more processing nodes, to select to send the one or more data fetch requests to the first data cache region 120 based on the data requested to be fetched being determined as the first type data, and to select to send the one or more data fetch requests to the second data cache region 130 based on the data requested to be fetched being determined as the second type data. Optionally, the processing unit 110 can include one or more cores of a multi-core processor, each of which can send one or more data fetch requests to the first data cache region 120 and / or the second data cache region 130.

[0038] Optionally, the processing unit 110 can be configured to determine the data requested to be fetched as the first type data or the second type data based on a frequency at which the data requested to be fetched is shared by one or more processing nodes, to select to send the one or more data fetch requests to the first data cache region 120 based on the data requested to be fetched being determined as the first type data, and to select to send the one or more data fetch requests to the second data cache region 130 based on the data requested to be fetched being determined as the second type data. Optionally, the processing unit 110 can include one or more cores of a multi-core processor, each of which can send one or more data fetch requests to the first data cache region 120 and / or the second data cache region 130.

[0039] In one embodiment, the requested data can be determined as first type data when the requested data is shared by one or more processing nodes at a low frequency, and the requested data can be determined as second type data when the requested data is shared by one or more processing nodes at a high frequency. In one embodiment, the first type data can be implemented as non-shared data, and the second type data can be implemented as shared data. Shared data refers to data shared among multiple processes, threads or systems, which can be accessed and modified by multiple entities simultaneously. Non-shared data refers to data belonging to a single process or thread, which is not accessed by other processes or threads. Illustratively, taking a neural network model as an example, data involved in various training tasks and application tasks (e.g., image data input to the neural network model, intermediate data generated by computation, etc.) can be implemented as first type data, and parameter information of the neural network model (e.g., weight values of various layers (e.g., convolutional layer, pooling layer, fully connected layer, normalization layer, etc.)), code information, command information (e.g., let command, const command, class command, etc.), output data of partial computing nodes can be implemented as second type data.

[0040] In one embodiment, the processing unit 110 can be configured to send data access requests corresponding to the first type data and data access requests corresponding to the second type data to the first data cache region 120 and the second data cache region 130, respectively, via independent channels. In one embodiment, the first data cache region 120 and the second data cache region 130 can share the bandwidth of the memory unit 140.

[0041] The first data cache region 120 includes one or more communicatively connected data cache units (not shown in the figure), which receive data access requests from the processing unit 110 and selectively access the first type data from the memory unit 140 based on the first address in the data access request and cache the first type data. Figure 1

[0042] In one embodiment, the first data cache region 120 can include a first data cache unit and a second data cache unit, and the data storage system 100 can further include a control unit (not shown in the figure), which is configured to perform address coherency and data transfer between the first data cache unit and the second data cache unit. Figure 1

[0043] ​​In one embodiment, the control unit can be connected between the first data cache region 120 and the memory unit 140 and configured to, for multiple data fetch requests for the same address, perform the following operations: when a first data cache unit of the first data cache region 120 receives a data fetch request requesting to fetch data cached at a first address, the control unit can fetch first type data corresponding to the first address from the memory unit 140 and send the first type data to the first data cache unit; when a second data cache unit of the first data cache region 120 receives a data fetch request requesting to fetch data cached at the first address, the control unit can control the first data cache unit to send the first type data corresponding to the first address to the second data cache unit.

[0044] In one embodiment, the control unit can be configured to determine an order in which the first data cache unit and the second data cache unit of the first data cache region 120 receive data fetch requests corresponding to the same address (e.g., the first address), and select, based on the order, to fetch first type data corresponding to the first address from the memory unit 140 and send the first type data to the first data cache unit, or to control the first data cache unit to send the first type data corresponding to the first address to the second data cache unit. Illustratively, for multiple data fetch requests for the same first address, when the first data cache unit receives a data fetch request corresponding to the first address before the second data cache unit, the control unit can fetch first type data corresponding to the first address from the memory unit 140 and send the first type data to the first data cache unit, and then can control the first data cache unit to send the first type data corresponding to the first address to the second data cache unit. In one embodiment, the one or more communicatively connected data cache units are configured to cache first type data corresponding to different addresses at the same time, respectively.

[0045] By performing same-address order preservation and data transfer between the first and second data cache units through the aforementioned control unit, the shared state settings in the MESI protocol can be omitted, thereby reducing the complexity of data management and ensuring data manageability. Since there is no need to manage the shared state of data across multiple data cache units, the risk of livelock or deadlock is further reduced. The MESI protocol is a cache coherence protocol and one of the most commonly used protocols supporting write-back caches. The letters M, E, S, and I in the MESI protocol represent the four exclusive states of a marked cache line: Modified (M), Exclusive (E), Shared (S), and Invalidated (I). In the shared state, when data in the cache needs to be updated, it cannot be directly modified; instead, a request must first be broadcast to all other CPU cores to invalidate the cache data in those cores before updating the current cache data.

[0046] The second data cache area 130 is configured to receive a data acquisition request from the processing unit 110 and acquire second type data from the memory unit 140 based on the second address in the data acquisition request and cache the second type data.

[0047] Optionally, the second data cache area 130 may include a first data cache unit and a second data cache unit. Figure 1 (Not shown in the image), the first data cache unit is configured to receive a data acquisition request from the processing unit 110 and directly acquire second type data from the memory unit 140 based on the second address in the data acquisition request and cache the second type data. The second data cache unit is configured to receive a data acquisition request from the processing unit 110 and directly acquire second type data from the memory unit 140 based on the third address in the data acquisition request and cache the second type data. The second address and the third address in the data acquisition request are used to indicate that the data to be acquired is second type data.

[0048] In one embodiment, memory cell 140 may be implemented as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). Alternatively, memory cell 140 may also be implemented as Synchronous Dynamic Random Access Memory (SDRAM) and Rambus Dynamic Random Access Memory (RDRAM).

[0049] The data storage system according to one or more embodiments of the present application can identify the type of the requested data through the address in the data acquisition request, and acquire and cache the requested data by using different data caching strategies and data caching areas, thereby improving data affinity and reducing data access delay. The data storage system according to one or more embodiments of the present application can reduce system complexity while having the advantages of high data affinity and high bandwidth, and can meet the demand for high-speed data processing.

[0050] The specific implementation of the data storage system according to one or more embodiments of the present application will be described in detail below. Figure 2 The specific implementation of the data storage system according to one or more embodiments of the present application will be described in detail below.

[0051] Figure 2 The structure block diagram of the data storage system according to one or more embodiments of the present application is shown.

[0052] As shown in Figure 2 The data storage system 200 includes a processing core 210, a data cache unit 220 and a data cache unit 230 connected with the processing core 210 in communication, a control unit 240 connected with the data cache unit 220 in communication, and a memory unit 250 connected with the control unit 240 and the data cache unit 230 in communication.

[0053] The processing core 210 is configured to send one or more data acquisition requests to the data cache unit 220 and / or the data cache unit 230, wherein the data acquisition request includes one or more addresses of the cached data requested to be acquired. Optionally, the one or more addresses of the cached data requested to be acquired are used to indicate that the requested data is first type data or second type data. Referring to Figure 2 The processing core 210 can send a data acquisition request corresponding to the first address to the data cache unit 220 for requesting to acquire the first type data, and the processing core 210 can send a data acquisition request corresponding to the second address to the data cache unit 230 for requesting to acquire the second type data. As Figure 2As shown, processing core 210 can be configured to send data retrieval requests corresponding to the first type of data and data retrieval requests corresponding to the second type of data to data cache unit 220 and data cache unit 230 respectively via independent channels. By using address identification to determine whether the requested data is of the first type or the second type, the data retrieval request does not need to be sent to each of data cache unit 220 and data cache unit 230, thereby improving the energy efficiency of the storage system. Sending data retrieval requests to each processing core 210 via an independent channel significantly improves the performance of non-real-time shared data and greatly reduces the overall design complexity of the system. In addition, sending data retrieval requests to data cache unit 220 and / or data cache unit 230 via an independent channel for each processing core 210 can reduce the average access latency of the system.

[0054] Continue as Figure 2 As shown, multiple data cache units 220 can be configured as follows: Figure 1 The first data cache region 120 and the plurality of data cache units 230 shown herein can be configured as follows: Figure 1 The second data cache area 130 shown can be communicatively connected between multiple data cache units 220 and multiple data cache units 230.

[0055] Each of the plurality of data cache units 220 may include a request node for receiving a data fetch request from the processing core 210 and selectively fetching a first type of data from the memory unit 250 based on a first address in the data fetch request via control unit 240, which is used for preserving the same address and transferring data between the plurality of data cache units 220.

[0056] In one embodiment, the control unit 240 can be configured to perform the following operations for multiple data acquisition requests to the same address: when the address of the cached data requested in the data acquisition request received by the first data cache unit 220 is a first address, the first type of data corresponding to the first address can be acquired from the memory unit 250 and the first type of data can be sent to the first data cache unit 220; when the address of the cached data requested in the data acquisition request received by the second data cache unit 220 is also a first address, the first data cache unit 220 can be controlled to send the first type of data corresponding to the first address to the second data cache unit 220.

[0057] In one embodiment, the control unit 240 may be configured to determine the order in which the first data cache unit 220 and the second data cache unit 220 receive data acquisition requests corresponding to the same address (e.g., a first address), and based on the order, select to acquire first type data corresponding to the first address from memory unit 250 and send the first type data to the first data cache unit 220, or select to control the first data cache unit 220 to send the first type data corresponding to the first address to the second data cache unit 220. For example, for multiple data acquisition requests to the same first address, when the first data cache unit 220 receives a data acquisition request corresponding to the first address before the second data cache unit 220, the control unit 240 may acquire the first type data corresponding to the first address from memory unit 250 and send the first type data to the first data cache unit 220, and then control the first data cache unit 220 to send the first type data corresponding to the first address to the second data cache unit 220. In one embodiment, the multiple data cache units 220 are configured to cache first type data corresponding to different addresses at the same time.

[0058] By performing same-address order preservation and data transfer between multiple data buffer units 220 through the control unit 240, the setting of shared state in the MESI protocol can be omitted, thereby reducing the complexity of data management and ensuring data manageability. Since there is no need to manage the shared state of data in multiple data buffer units 220, the risk of livelock or deadlock is further reduced.

[0059] Each of the multiple data cache units 230 may include a shared node for receiving data fetch requests from processing core 210 and requesting second type data from memory unit 250 based on a second address in the data fetch request. Figure 2 As shown, the shared node of each of the multiple data cache units 230 can be used to receive data acquisition requests from the processing core 210 and directly acquire second type data from the memory unit 250 based on the second address in the data acquisition request.

[0060] pass Figure 2 The design of the data caching unit 220 and data caching unit 230 shown herein facilitates the software to classify, read, and cache the data types involved in the task. For example, the data caching unit 220 can be used to obtain data that needs to be changed (e.g., data involved in various training tasks and application tasks), and the data caching unit 230 can be used to obtain data that does not need to be changed (e.g., various instruction data, such as the weight values ​​of various layers in a neural network model), thereby improving the memory access performance of the system.

[0061] Memory cell 250 can be implemented as a combination of one or more of DDR SDRAM, SDRAM and RDRAM.

[0062] It should be noted that, Figure 2 The number of processing cores 210, data cache units 220, and data cache units 230 shown is merely exemplary. Without departing from the spirit and scope of this application, the number of processing cores 210, data cache units 220, and data cache units 230 can be set to a greater number than... Figure 2 More or less as shown.

[0063] Figure 3 A flowchart illustrating a data storage method according to one or more embodiments of this application is shown. Figure 3 The steps shown can be achieved using the above methods. Figures 1-2 The data storage system is described in the text.

[0064] like Figure 3 As shown, in step S301, one or more data acquisition requests are sent, the data acquisition requests including one or more addresses where the requested data is cached.

[0065] Optionally, one or more addresses cached for the requested data are used to indicate whether the requested data is of type 1 or type 2.

[0066] In step S303, a first type of data is selectively retrieved from a memory unit based on a first address in the data retrieval request and the first type of data is cached in a first data cache area, the first data cache area including one or more communicatively connected data cache units.

[0067] In step S305, second type data is obtained from the memory unit based on the second address in the data acquisition request and the second type data is cached in the second data cache area.

[0068] In one embodiment, one or more communicatively connected data cache units are configured to cache first type data corresponding to different addresses simultaneously. In another embodiment, the first data cache region and the second data cache region share the bandwidth of the memory unit.

[0069] In one embodiment, the requested data can be determined to be either a first type of data or a second type of data based on the frequency with which the requested data is shared by one or more processing nodes. Based on determining that the requested data is the first type of data, one or more data retrieval requests can be sent to a first data cache area. Based on determining that the requested data is the second type of data, one or more data retrieval requests can be sent to a second data cache area.

[0070] In one embodiment, the first data cache region may include a first data cache unit and a second data cache unit. In step S303, in response to a first address in a data retrieval request received by the first data cache unit, first type data corresponding to the first address may be retrieved from a memory unit and sent to the first data cache unit for caching; and in response to a first address in a data retrieval request received by the second data cache unit, the first data cache unit may be controlled to send the first type data corresponding to the first address to the second data cache unit for caching. In one embodiment, the order in which the first data cache unit and the second data cache unit receive the data retrieval request corresponding to the first address may be determined, and the first type data corresponding to the first address may be retrieved from the memory unit based on the order and sent to the first data cache unit, and the first data cache unit may be controlled to send the first type data corresponding to the first address to the second data cache unit.

[0071] In one embodiment, data acquisition requests corresponding to the first type of data and data acquisition requests corresponding to the second type of data can be sent to the first data cache area and the second data cache area via independent channels, respectively.

[0072] In one embodiment, the second data cache region may include a first data cache unit and a second data cache unit, which may directly retrieve and cache the second type of data from the memory unit based on the second address in the data retrieval request, and may also directly retrieve and cache the second type of data from the memory unit based on the third address in the data retrieval request.

[0073] The data storage method according to one or more embodiments of this application can identify the type of data requested by the address in the data acquisition request, and utilize different data caching strategies and data caching areas to acquire and cache the requested data, thereby improving data affinity and reducing data access latency. The data storage method according to one or more embodiments of this application can reduce system complexity while possessing the advantages of high data affinity and high bandwidth, thus meeting the needs of high-speed data processing.

[0074] Alternatively, this application can also be implemented as a computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform a data storage method according to one aspect of this application. The computer-readable medium referred to in this application includes various types of computer storage media, and can be any available medium accessible to a general-purpose or special-purpose computer. For example, a computer-readable medium may include RAM, ROM, EPROM, E2PROM, registers, hard disk, removable disk, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage device, or any other temporary or non-temporary medium capable of carrying or storing desired program code units having an instruction or data structure form and accessible by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. As used herein, disks typically magnetically copy data, while discs optically copy data using lasers. Combinations of the above should also be included within the scope of protection of computer-readable media. An exemplary storage medium is coupled to a processor so that the processor can read and write information from / to the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and storage media can reside as discrete components in the user terminal.

[0075] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art can conceive of other feasible variations or substitutions based on the technical scope disclosed in this application, and such variations or substitutions are all covered within the scope of protection of this application. Where there is no conflict, the embodiments and features described in these embodiments can also be combined with each other.

Claims

1. A data storage system, characterized in that, The data storage system includes: A processing unit is configured to send one or more data acquisition requests, wherein the data acquisition request includes one or more addresses where the requested data is cached; A first data cache region includes one or more communicatively connected data cache units, which receive data acquisition requests from the processing unit and selectively acquire and cache first type data from memory units based on a first address in the data acquisition request; and A second data cache area is configured to receive a data acquisition request from the processing unit and acquire a second type of data from the memory unit based on a second address in the data acquisition request and cache the second type of data.

2. The data storage system according to claim 1, wherein one or more addresses cached by the requested data are used to indicate that the requested data is a first type of data or a second type of data.

3. The data storage system according to claim 1, wherein the processing unit is configured to: The data to be requested is determined to be either a first type of data or a second type of data based on the frequency with which the data is shared by one or more processing nodes. Based on determining that the requested data is a first type of data, the one or more data retrieval requests are sent to the first data cache area. as well as Based on determining that the requested data is of the second type, the one or more data retrieval requests are sent to the second data cache area.

4. The data storage system according to claim 1, wherein the data storage system further includes a control unit, the first data cache area includes a first data cache unit and a second data cache unit, and the control unit is connected between the first data cache area and the memory unit and configured to: In response to the first address in the data retrieval request received by the first data cache unit, first type data corresponding to the first address is retrieved from the memory unit and the first type data is sent to the first data cache unit; and In response to the first address in the data acquisition request received by the second data cache unit, the first data cache unit is controlled to send the first type of data corresponding to the first address to the second data cache unit.

5. The data storage system according to claim 4, wherein the control unit is further configured to: Determine the order in which the first data cache unit and the second data cache unit receive data retrieval requests corresponding to the first address; and Based on the order, the system retrieves first type data corresponding to the first address from the memory unit and sends the first type data to the first data cache unit, and controls the first data cache unit to send the first type data corresponding to the first address to the second data cache unit.

6. The data storage system according to claim 1, wherein the processing unit is further configured to: The data acquisition request corresponding to the first type of data and the data acquisition request corresponding to the second type of data are respectively sent to the first data cache area and the second data cache area via independent channels. The one or more data buffer units connected in communication are configured to buffer first type data corresponding to different addresses at the same time. The first data cache region and the second data cache region share the bandwidth of the memory unit. The second data cache area includes: A first data caching unit is configured to receive a data acquisition request from the processing unit and directly acquire second type data from the memory unit based on a second address in the data acquisition request and cache the second type data. as well as The second data caching unit is configured to receive a data retrieval request from the processing unit and, based on a third address in the data retrieval request, directly retrieve the second type of data from the memory unit and cache the second type of data. The processing unit includes one or more cores of a multi-core processor, and the memory unit is a double-data-rate synchronous dynamic random access memory.

7. A data storage method, characterized in that, The method includes: Send one or more data retrieval requests, wherein the data retrieval requests include one or more addresses where the requested data is cached; Based on the first address in the data retrieval request, first type data is selectively retrieved from memory units and cached in a first data cache area, the first data cache area comprising one or more communicatively connected data cache units; and The second type of data is retrieved from the memory unit based on the second address in the data retrieval request, and the second type of data is cached in the second data cache area.

8. The data storage method according to claim 7, wherein one or more addresses cached for the requested data are used to indicate whether the requested data is a first type of data or a second type of data. Sending one or more data retrieval requests includes: The data to be requested is determined to be either a first type of data or a second type of data based on the frequency with which the data is shared by one or more processing nodes. Based on determining that the requested data is a first type of data, the one or more data retrieval requests are sent to the first data cache area. as well as Based on determining that the requested data is of the second type, the one or more data retrieval requests are sent to the second data cache area. The first data cache area includes a first data cache unit and a second data cache unit. Selectively retrieving first type data from a memory unit and caching the first type data in the first data cache area based on the first address in the data retrieval request includes: In response to the first address in the data retrieval request received by the first data caching unit, first type data corresponding to the first address is retrieved from the memory unit and the first type data is sent to the first data caching unit for caching; and In response to the first address in the data retrieval request received by the second data caching unit, the first data caching unit is controlled to send the first type of data corresponding to the first address to the second data caching unit for caching. The method further includes: Determine the order in which the first data cache unit and the second data cache unit receive data retrieval requests corresponding to the first address; and Based on the order, the system retrieves first type data corresponding to the first address from the memory unit and sends the first type data to the first data cache unit, and controls the first data cache unit to send the first type data corresponding to the first address to the second data cache unit.

9. The data storage method according to claim 7, wherein sending one or more data acquisition requests includes: The data acquisition request corresponding to the first type of data and the data acquisition request corresponding to the second type of data are respectively sent to the first data cache area and the second data cache area via independent channels. The one or more data buffer units connected in communication are configured to buffer first type data corresponding to different addresses at the same time. The first data cache region and the second data cache region share the bandwidth of the memory unit. The second data cache area includes a first data cache unit and a second data cache unit, and the method further includes: Based on the second address in the data retrieval request, directly retrieve the second type of data from the memory unit and cache the second type of data; and The second type of data is directly obtained from the memory unit based on the third address in the data acquisition request, and the second type of data is cached.

10. A computer-readable storage medium storing instructions, characterized in that, When the instruction is executed by the processor, the processor performs the data storage method according to any one of claims 7-9.

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