Data writing method and device, equipment, storage medium and program product

Abstract

The invention discloses a data writing method and device, equipment, a storage medium and a program product. The data writing method comprises the steps that a writing request for a target cache line is received; the write request is used for writing data into an effective byte position of the target cache line; under the condition that it is determined that at least one invalid byte position exists in the target cache line based on the write request, encoding the at least one invalid byte position to obtain an invalid byte code; the invalid byte code comprises a first mask used for determining the position of one invalid byte in the target cache line; writing the data into the effective byte position, and storing the first mask; wherein under the condition that the number of the invalid byte positions is at least two, the invalid byte code further comprises a second mask; the first mask and all second masks are used for determining positions of all invalid bytes. In this way, additional overhead for storing byte masks may be reduced.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of data processing technology, and in particular to a data writing method, apparatus, device, storage medium, and program product. Background Technology

[0002] In computer devices, caching is a high-speed data storage mechanism used to temporarily store frequently accessed data, reducing access to slower storage devices (such as hard drives) and thus improving data access speed and system performance. As a data storage unit, caching operates at the cache line level. However, when a cache receives a write request, each write request may not necessarily write a complete cache line. A common solution is to store a byte mask for each cache line, marking which bytes are valid and which are invalid. This method of storing byte masks requires significant additional area overhead. Summary of the Invention

[0003] In view of this, embodiments of this application provide at least one data writing method, apparatus, device, storage medium, and program product.

[0004] The technical solution of this application embodiment is implemented as follows: On one hand, embodiments of this application provide a data writing method, the data writing method comprising: receiving a write request for a target cache line; the write request being used to write data to a valid byte position of the target cache line; if it is determined based on the write request that there is at least one invalid byte position in the target cache line, encoding the at least one invalid byte position to obtain an invalid byte encoding; the invalid byte encoding including a first mask for determining an invalid byte position in the target cache line; writing the data to the valid byte position and storing the first mask; wherein, if there are at least two invalid byte positions, the invalid byte encoding further includes a second mask; the first mask and all second masks are used to determine all invalid byte positions.

[0005] On the other hand, embodiments of this application provide a data writing device, the data writing device comprising: a receiving module, an encoding module, and a writing module; wherein, the receiving module is configured to receive a write request for a target cache line; the write request is configured to write data to a valid byte position of the target cache line; the encoding module is configured to encode the at least one invalid byte position in the target cache line, based on the write request, to obtain an invalid byte encoding; the invalid byte encoding includes a first mask for determining an invalid byte position in the target cache line; the writing module is configured to write the data to the valid byte position and store the first mask; wherein, when there are at least two invalid byte positions, the invalid byte encoding further includes a second mask; the first mask and all second masks are used to determine all invalid byte positions.

[0006] In another aspect, embodiments of this application provide an electronic device, including a memory and a processor. The memory stores a computer program that can run on the processor, and the processor executes the program to implement some or all of the steps in the above-described method.

[0007] In another aspect, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above-described method.

[0008] In another aspect, embodiments of this application provide a computer program product, including a computer program or instructions, which, when executed by a processor, implement some or all of the steps in the above-described method.

[0009] In this embodiment, the invalid byte encoding corresponding to the target cache line is determined based on the write request. Data is written to the valid byte position, the second mask is written to the invalid byte position of the target cache line, and the first mask is stored. Thus, only one additional first mask corresponding to an invalid byte position needs to be stored. The second masks corresponding to other invalid byte positions are written to the invalid byte positions of the target cache line. The invalid byte positions in the target cache line can be determined using the first and second masks, thereby effectively reducing the additional area overhead introduced by storing byte masks.

[0010] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0012] Figure 1A This is a schematic diagram of a byte mask; Figure 1B A schematic diagram illustrating the implementation process of a data writing method provided in this application embodiment; Figure 2 A schematic diagram of the implementation process of a data writing method provided in this application embodiment. Figure 2 ; Figure 3 A schematic diagram of the implementation process of a data writing method provided in this application embodiment. Figure 3 ; Figure 4 A schematic diagram of the implementation process of a data writing method provided in this application embodiment. Figure 4 ; Figure 5 A schematic diagram of the implementation process of a data writing method provided in this application embodiment. Figure 5 ; Figure 6 A schematic diagram of a compression mask provided for an embodiment of this application; Figure 7 This is a schematic diagram illustrating the process of writing cached data in an embodiment of this application. Figure 8 This is a schematic diagram of the composition structure of a data writing device provided in an embodiment of this application; Figure 9 This is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0016] This application provides a method that can be executed by a processor of an electronic device. The electronic device can refer to a server, laptop computer, tablet computer, desktop computer, smart TV, set-top box, mobile device (such as a mobile phone, portable video player, personal digital assistant, dedicated messaging device, portable gaming device), or any other device with data processing capabilities.

[0017] Figure 1A This is a schematic diagram of a byte mask. For example... Figure 1A As shown, the initial target cache line consists of 8 byte positions, byte 0 to byte 7. The initial byte mask is 00000000, indicating that each byte position in the initial target cache line is invalid and no data has been written. Upon receiving a write request for the target cache line, data is written to byte 0 and byte 2 of the initial target cache line, changing byte 0 and byte 2 from invalid to valid byte positions. Therefore, the bits corresponding to byte 0 and byte 2 in the byte mask after the data is written are changed from 0 to 1, indicating that byte 0 and byte 2 are valid in the target cache line after the data is written; the remaining byte positions have not been written, and the bits corresponding to the remaining byte positions in the byte mask after the data is written remain 0.

[0018] The size of the byte mask is 1 / 8 of the total size of the target cache line. The storage of the byte mask, like the database of the target cache line, needs to be stored in static random-access memory (SRAM). Therefore, when using the byte mask to record the mask, it will always bring an additional 1 / 8 of the area loss (each byte is 8 bits, which means 8 bits of data correspond to 1 bit of mask).

[0019] To reduce the additional area overhead introduced by storing byte masks, embodiments of this application provide a data writing method that can determine the invalid byte encoding corresponding to the target cache line based on the write request, write data to the valid byte position, write a second mask to the invalid byte position of the target cache line, and store the first mask. In this way, only the first mask for one invalid byte position needs to be stored, and the second masks for other invalid byte positions are written to the invalid byte positions of the target cache line, effectively reducing the additional area overhead introduced by storing byte masks. By determining one invalid byte position in the target cache line using the first mask and determining the adjacent next invalid byte position using the second mask, the invalid byte positions in the target cache line can be accurately determined using both the first and second masks.

[0020] Figure 1B A schematic diagram illustrating the implementation flow of a data writing method provided in this application embodiment is shown below. Figure 1B As shown, the method includes the following steps S101 to S103: Step S101: Receive a write request for the target cache line; the write request is used to write data to the valid byte position of the target cache line.

[0021] The target cache line is the cache line corresponding to the write request in the cache. There are multiple cache lines in the cache. Upon receiving a write request, the write request includes the address of the target cache line, and the target cache line can be determined from the cache based on the write request.

[0022] A write request is a request to write cached data, used to write data to valid byte positions in the target cache line. Typically, each write request does not write a complete cache line, but only a portion of the cache line's byte positions. For example, a cache line may consist of 8 byte positions (byte0 to byte7), and the write request indicates that data be written to byte0 and byte5 of the cache line.

[0023] The number of byte positions in the target cache line can be set according to requirements. For example, the target cache line may include 8 byte positions byte0 to byte7, or it may include 128 byte positions byte0 to byte127.

[0024] The valid byte position is the byte position in the target cache line where data is to be written. Upon receiving a write request, the byte position where data needs to be written can be determined based on the write request, and this byte position is then designated as the valid byte position.

[0025] Step S102: If it is determined based on the write request that there is at least one invalid byte position in the target cache line, the at least one invalid byte position is encoded to obtain an invalid byte encoding; the invalid byte encoding includes a first mask for determining an invalid byte position in the target cache line.

[0026] Invalid byte positions refer to byte positions in the target cache line where no data has been written. For example, the target cache line includes 8 byte positions byte0 to byte7. The write request indicates that data should be written to byte0 and byte5 of the target cache line, therefore byte1 to byte4 and byte6 are invalid byte positions.

[0027] In some embodiments, before a write request, all byte positions in the target cache line are invalid byte positions. Based on the write request, some valid byte positions corresponding to the write request can be determined, and byte positions in the target cache line other than some valid byte positions are determined as invalid byte positions.

[0028] In some embodiments, before the write request, some byte positions in the target cache line are already invalid. Based on these invalid byte positions, the current valid byte positions in the target cache line can be determined. Combined with the valid byte positions corresponding to the write request, the final valid byte positions can be obtained. Based on the final valid byte positions, the final invalid byte positions are determined from the target cache line.

[0029] The invalid byte encoding is a byte encoding obtained by encoding at least one invalid byte position. The invalid byte encoding includes a first mask used to determine an invalid byte position in the target cache line.

[0030] In some embodiments, an invalid byte position is determined to exist in the target cache line based on a write request. For example, the target cache line includes 8 byte positions byte0 to byte7. Based on the write request, byte3 is determined to be an invalid byte position. Byte3 is encoded using 4 bits to obtain a first mask 0011.

[0031] In some embodiments, at least two invalid byte positions are determined to exist in the target cache line based on the write request. For example, the target cache line includes eight byte positions byte0 to byte7. Based on the write request, byte3 and byte5 are determined to be invalid byte positions. Byte3 and byte5 are encoded using 4 bits to obtain invalid byte codes 0011 and 0101. The first mask can be the encoding of any invalid byte position. The first mask can be 0011 or 0101. An invalid byte position in the target cache line can be determined using the first mask.

[0032] Step S103: Write the data into the valid byte position and store the first mask.

[0033] In some embodiments, when there is only one invalid byte position, the data is written to the valid byte position, and the first mask is stored. The valid byte position corresponding to the write request can be determined based on the write request; when there is only one invalid byte position, the encoding corresponding to the invalid byte position is the first mask.

[0034] The first mask is stored in a storage area outside the target cache line. For example, the first mask is stored in SRAM.

[0035] For example, the target cache line includes 8 byte positions byte0 to byte7. Based on the write request, byte1 to byte7 are determined to be valid byte positions, therefore the invalid byte position is byte0. byte0 is encoded to obtain a first mask 0000. Data is written to the valid byte positions byte1 to byte7, and the first mask 0000 is stored.

[0036] Where there are at least two invalid byte positions, the invalid byte encoding further includes a second mask; the first mask and all second masks are used to determine all invalid byte positions.

[0037] In some embodiments, invalid byte encoding is used to determine all invalid byte positions, that is, the invalid byte positions in the target cache line can be determined by the first mask and the second mask. For example, the first mask is 0100, indicating that byte 4 is an invalid byte position, and the second mask 0101 is stored in byte 4, indicating that the next invalid byte position adjacent to byte 4 is byte 5, and so on, so that all invalid byte positions in the target cache line can be obtained.

[0038] For example, the target cache line includes 8 byte positions byte0 to byte7. Based on the write request, byte0 to byte3 are determined to be valid byte positions, therefore invalid byte positions are byte4 to byte7. Bytes 4 to byte7 are encoded to obtain 0100, 0101, 0110, and 0111. With the first mask being 0100, 0101, 0110, and 0111 are the second mask. Data is written to the valid byte positions byte0 to byte3, 0101, 0110, and 0111 are written to the corresponding invalid byte positions, and the first mask 0100 is stored.

[0039] In this embodiment, the invalid byte encoding corresponding to the target cache line is determined based on the write request. Data is written to the valid byte position, the second mask is written to the invalid byte position of the target cache line, and the first mask is stored. In this way, only the first mask for one invalid byte position needs to be stored, and the second masks for other invalid byte positions are written to the invalid byte positions of the cache line. The invalid byte positions in the target cache line can be determined by the first mask and the second mask, thereby effectively reducing the additional area overhead introduced by storing byte masks.

[0040] In some embodiments, the first mask is used to store the first invalid byte position, and the second mask stored at the first invalid byte position is used to indicate the second invalid byte position, which is the next invalid byte position adjacent to the first invalid byte position.

[0041] Here, when there are at least two invalid byte positions, the first mask and the second mask can be understood as locating all invalid byte positions by means of a linked list.

[0042] In some possible implementations, the first mask can serve as the first pointer to the linked list, encoding the position of the first invalid byte (e.g., byte0 is encoded as 0000). If there are multiple invalid byte positions, a second mask is stored inside each invalid byte position (except the last one). Each second mask acts as a pointer, encoding the value of the next invalid byte position in the linked list.

[0043] For example, suppose a cache line has 8 bytes (Byte0 to Byte7). After a write request, Byte1, Byte2, and Byte5 are valid bytes (written data), while Byte0, Byte3, Byte4, Byte6, and Byte7 are invalid bytes, encoded as 0000, 0011, 0100, 0110, and 0111 respectively. The position of the first invalid byte, encoded as 0000 (Byte0), is used as the first mask. In the storage space of the first invalid byte (Byte0), the code 0011 of the next invalid byte (Byte3) is stored; this is the first second mask. In the storage space of the second invalid byte (Byte3), the code 0100 of the next invalid byte (Byte4) is stored; this is the second second mask. In the storage space of the third invalid byte (Byte4), the code 0110 of the next invalid byte (Byte6) is stored; this is the third second mask. In the storage space of the fourth invalid byte (Byte6), the code 0111 of the next invalid byte (Byte7) is stored; this is the fourth second mask. Thus, based on the first mask and the four second masks, the positions of all invalid bytes in the cache line can be determined.

[0044] In some embodiments, the invalid byte encoding further includes a termination mask, which is stored at the last invalid byte position among the at least one invalid byte positions.

[0045] Here, the last invalid byte position in at least one invalid byte position can store a termination mask, which can be a special chain end marker. For example, in the storage space of the last invalid byte (Byte7) in the above example, a special chain end marker (such as 1111, 1000, etc., different from the second mask) is stored.

[0046] In some embodiments, the first mask is stored in byte mask bits associated with the target cache line.

[0047] The byte mask is an additional external storage space reserved for each cache line, containing a small, fixed byte mask. It can be understood that the byte mask is directly associated with a cache line; that is, there is a one-to-one correspondence between the byte mask and the cache line.

[0048] In some embodiments, if it is determined based on the write request that the invalid byte position exists in the target cache line, the byte mask bit is used to store a first mask.

[0049] In some embodiments, if it is determined based on the write request that the invalid byte position does not exist in the target cache line, the byte mask bit is used to store a termination mask.

[0050] Here, when all byte positions in the target cache line have been written with valid data, there are no invalid byte positions in the cache line. In order to clearly identify this special state of "all valid", a predefined termination mask (such as 1111, 1000, etc., different from the second mask) can be written into the "byte mask bit" of the cache line.

[0051] It is understandable that this byte mask bit can directly indicate whether there are invalid bytes in the cache line. That is, by determining whether this byte mask bit is a terminating mask, it can be determined whether there are invalid bytes in the cache line.

[0052] In some embodiments, the invalid byte encoding includes N sequential second masks, and the target cache line includes N+1 sequential invalid byte positions, wherein the nth second mask is stored in the nth invalid byte position, and n and N are positive integers, where n is less than or equal to N.

[0053] Here, there is a strict correspondence between the number of second masks (N) and the number of invalid byte positions (N+1), and the storage order of the masks is completely consistent with the physical order of the invalid bytes.

[0054] For example, suppose a cache line has 8 bytes (Byte0 to Byte7). After a write request, 4 invalid byte positions are generated (N+1=4), in address order: Byte1 (1st), Byte3 (2nd), Byte5 (3rd), and Byte7 (4th). Since there are 4 invalid byte positions, the number of second masks is N=3 (i.e., 4-1). Therefore, we can obtain 3 second masks: The first second mask: encodes the address of the second invalid byte (Byte3), which is stored in the first invalid byte (Byte1).

[0055] The second mask: encodes the address of the third invalid byte (Byte5), which is stored in the second invalid byte (Byte3).

[0056] The third second mask: encodes the address of the fourth invalid byte (Byte7), which is stored in the third invalid byte (Byte5).

[0057] At this point, the first mask stored in the byte mask bit points to the head node of the linked list, that is, the first invalid byte (Byte1), while the tail node of the linked list (the fourth invalid byte Byte7) stores a termination mask, indicating the end of the linked list.

[0058] Thus, by using only an external first mask, all invalid byte positions can be accurately traversed and located based on the chain formed by the first and second masks.

[0059] Figure 2 A schematic diagram of the implementation process of a data writing method provided in this application embodiment. Figure 2 This method can be executed by the processor of an electronic device. Based on Figure 1B The data writing method may further include steps S201 to S203, combining... Figure 2 The steps shown are explained.

[0060] Step S201: Perform a hit check on the write request.

[0061] Upon receiving a write request, a cache hit check is performed to determine if the write request hits the cache. If the write request hits the cache, the target cache line corresponding to the write request already exists in the cache, and the write operation needs to be performed based on the existing target cache line. If the write request misses the cache, the target cache line corresponding to the write request does not exist in the cache, a new target cache line needs to be determined from the cache, and the write operation needs to be performed based on the new target cache line.

[0062] In some embodiments, a write request has a corresponding address, which includes an index, a tag, and a block offset. Each cache line in the cache also has a corresponding address. The corresponding target cache line can be found in the cache using the index in the address of the write request. By determining whether the address tag in the write request matches the address tag of the target cache line, it is determined whether the corresponding target cache line exists in the cache, and a hit check result is obtained.

[0063] The hit check result includes whether the write request hits the target cache line or not.

[0064] Step S202: If the hit check result indicates that the target cache line was not hit, determine the position of the invalid byte in the target cache line based on the position of the valid byte in the write request.

[0065] Here, if the hit check result indicates that the target cache line was not hit, the corresponding target cache line does not exist in the cache before the write request. The position of the invalid byte in the target cache line can be determined directly based on the position of the valid byte in the write request.

[0066] Among them, a "target cache line not hit" means that the corresponding target cache line does not exist in the cache before the write request. Therefore, the position of the invalid byte in the target cache line can be determined directly based on the write request.

[0067] In some embodiments, the write request includes the valid byte position for data writing, and after obtaining the valid byte position, the invalid byte position can be determined from the target cache line.

[0068] For example, the target cache line includes byte0 to byte7. Based on the write request, the valid byte positions are determined to be byte0 to byte5. Therefore, the invalid byte positions are determined to be byte6 and byte7.

[0069] In this embodiment of the application, when the hit check result indicates that the target cache line has not been hit, the position of the invalid byte in the target cache line is determined based on the position of the valid byte in the write request. Thus, when the target cache line is not hit, the accurate position of the invalid byte can be determined based on the write request.

[0070] Step S203: If the hit check result indicates that the target cache line has been hit, determine the position of the invalid byte in the target cache line based on the position of the valid byte in the write request and the original invalid byte encoding of the target cache line.

[0071] Here, if the hit check result indicates that the target cache line has been hit, there is a corresponding target cache line before the write request. Therefore, it is necessary to determine the original invalid byte position of the target cache line based on the original invalid byte encoding of the target cache line, and then determine the original valid byte position of the target cache line. Finally, the final invalid byte position is determined by combining the original valid byte position and the valid byte position of the write request.

[0072] Figure 3 A schematic diagram of the implementation process of a data writing method provided in this application embodiment. Figure 3 This method can be executed by the processor of an electronic device. Based on Figure 2 , Figure 2 Step S203 can be updated to steps S301 and S302, combining Figure 3 The steps shown are explained.

[0073] Step S301: Based on the original invalid byte encoding, determine the position of the original valid byte in the target cache line.

[0074] After obtaining the original invalid byte encoding, the original invalid byte position can be determined based on the original invalid byte encoding, and the original valid byte position can be determined based on the original invalid byte position.

[0075] In some embodiments, where the original invalid byte encoding includes the original first mask, at least one original invalid byte position in the target cache line is determined based on the original invalid byte encoding; and the original valid byte position in the target cache line is determined based on the at least one original invalid byte position.

[0076] In some embodiments, when the original invalid byte encoding only includes the original termination mask, the target cache line is determined to be entirely composed of original valid byte positions.

[0077] For example, the target cache line includes bytes 0 to 7. The original invalid byte encoding includes a first mask 0001, three second masks 0010, 0100, and 0101, and a termination mask 1000. Based on the first mask 0001, an invalid byte position byte1 is determined; based on the second mask 0010, an invalid byte position byte2 is determined; based on the second mask 0100, an invalid byte position byte4 is determined; and based on the second mask 0101, an invalid byte position byte5 is determined. Therefore, the original valid byte positions are byte0, byte3, byte6, and byte7.

[0078] Step S302: Based on the original valid byte position and the valid byte position in the write request, determine the invalid byte position in the target cache line.

[0079] The write request includes the position of the valid bytes of the data to be written. After obtaining the original position of the valid bytes, the position of the invalid bytes of the target cache line can be determined.

[0080] For example, the target cache line includes bytes 0 through 7, the original valid byte positions are byte 0 and byte 3, and the valid byte positions in the write request are byte 2 and byte 4. Therefore, the invalid byte positions in the target cache line are byte 1, byte 5, and byte 6.

[0081] In some embodiments, the original valid byte position and the valid byte position in the write request are consistent. In this case, it is not necessary to recalculate the invalid byte position in the target cache line. The data can simply be written to the valid byte position.

[0082] In this embodiment, if the hit check result indicates a hit on the target cache line, the original invalid byte encoding of the target cache line is read; based on the original invalid byte encoding, the original valid byte position in the target cache line is determined; based on the original valid byte position and the valid byte position in the write request, the invalid byte position in the target cache line is determined. Thus, when the target cache line is hit, determining the final invalid byte position through the original valid byte position yields an accurate invalid byte position.

[0083] Figure 4 A schematic diagram of the implementation process of a data writing method provided in this application embodiment. Figure 4 This method can be executed by the processor of an electronic device. Based on Figure 3 , Figure 3 Step S301 can be updated to steps S401 to S402, combining Figure 4 The steps shown are explained.

[0084] Step S401: If the original invalid byte encoding includes the original first mask, determine at least one original invalid byte position in the target cache line based on the original invalid byte encoding.

[0085] The original invalid byte encoding includes the original first mask, which indicates that there is at least one original invalid byte position in the target cache line.

[0086] In some embodiments, the original invalid byte encoding includes an original first mask, based on which an original invalid byte position can be determined in the target cache line.

[0087] In some embodiments, the original invalid byte encoding includes an original first mask and at least one original second mask. An original invalid byte position can be determined based on the original first mask, and at least one more original invalid byte position can be determined based on the at least one original second mask. For example, the original first mask is 0100, and the original second masks are 0101 and 0110. 0100 corresponds to byte 4, 0101 corresponds to byte 5, and 0110 corresponds to byte 6. Therefore, the original invalid byte positions are byte 4, byte 5, and byte 6.

[0088] Step S402: Determine the original valid byte position in the target cache line based on the at least one original invalid byte position.

[0089] In this process, after obtaining at least one original invalid byte position, the original valid byte position can be determined based on all byte positions of the target cache line and at least one original invalid byte position.

[0090] For example, the target cache line includes byte0 to byte7, and at least one original invalid byte position includes byte0 to byte3, therefore the original valid byte positions are byte4 to byte7.

[0091] In this embodiment of the application, when the original invalid byte encoding includes the original first mask, the original valid byte position can be determined by the original invalid byte position, thus obtaining the accurate original valid byte position.

[0092] Figure 5 A schematic diagram of the implementation process of a data writing method provided in this application embodiment. Figure 5 This method can be executed by the processor of an electronic device. Based on Figure 3 , Figure 3 Step S301 in the above can be updated to step S501, which will combine Figure 5 The steps shown are explained.

[0093] Step S501: If the original invalid byte encoding only includes the original termination mask, determine that all positions of the target cache line are original valid bytes.

[0094] Among them, the original first mask and the original second mask in the original invalid byte encoding can determine the original invalid byte position. When the original invalid byte encoding only includes the original termination mask, it can be determined that all target cache lines are original valid byte positions.

[0095] For example, the target cache line includes byte0 to byte7, and the original termination mask is 1000. If only 1000 is read, it is determined that byte0 to byte7 of the target cache line are all original valid byte positions.

[0096] In this embodiment, when the original invalid byte encoding only includes the original stop mask, the target cache line is determined to be entirely composed of original valid byte positions. Thus, based on the original stop mask, the original valid byte positions can be accurately obtained.

[0097] In some embodiments, encoding the at least one invalid byte position to obtain an invalid byte encoding includes: determining the number of encoding bits based on the byte length of the target cache line; and encoding the at least one invalid byte position based on the number of encoding bits to obtain an invalid byte encoding.

[0098] The byte length refers to the number of byte positions in the target cache line. For example, the target cache line includes bytes 0 to 7, with a byte length of 8.

[0099] In some embodiments, by formula To determine the number of encoded bits. For example, the target cache line includes bytes 0 to 7, has a byte length of 8, and the number of encoded bits is determined to be 4.

[0100] In some embodiments, if an invalid byte position exists in the target cache line, the invalid byte position is encoded based on the number of encoded bits. For example, if the invalid byte position is byte3, encoding byte3 yields 0011.

[0101] In some embodiments, if there is no invalid byte position in the target cache line, the invalid byte is encoded as a stop mask. The stop mask is obtained by encoding based on the number of bits. For example, if the number of bits is 4, the stop mask is 1000.

[0102] In this embodiment, the number of encoded bits is determined based on the byte length of the target cache line, and then the invalid byte encoding is obtained based on the number of encoded bits. In this way, an accurate invalid byte encoding can be obtained.

[0103] The following describes the application of the data writing method provided in the embodiments of this application in a real-world scenario.

[0104] As a data storage unit, the cache operates at the granularity of cache lines (corresponding to the target cache line in the above embodiment). However, when the cache receives write data, each write request may not necessarily write a complete cache line. The current common technical solution is to additionally store a corresponding bytemask for each cache line to mark which bytes are valid.

[0105] When writing data to a cached data block using relevant techniques, for an 8-byte cached data block (byte0 to byte7), the byte mask is set to 8 bits. If no data has been written to the current cached data block, the byte mask is 00000000. The mask bits corresponding to the byte positions where data is to be written are set to 1, and the remaining bits are set to 0. For example... Figure 1A As shown, when data is written to byte0 and byte2, the bits in the byte mask corresponding to byte0 and byte2 are set to 1, and the bits in the byte mask corresponding to the other byte positions are set to 0.

[0106] Figure 6 This is a schematic diagram of a compression mask provided in an embodiment of this application. This embodiment uses a compression mask to reduce the additional area overhead introduced for storing cache masks. When writing data to a cache data block, this embodiment uses a linked list to store the mask corresponding to the invalid byte position. The byte mask only needs to store the mask for the first invalid byte position (corresponding to the first mask in the above embodiment), and the masks for subsequent invalid byte positions (corresponding to the second mask in the above embodiment) are stored in the corresponding data bits of the cache data block. An additional high-order bit (corresponding to the termination mask in the above embodiment) is set to indicate the termination of the linked list, meaning that all subsequent data is valid. This method is called a compression format, and the original byte mask is a decompression format.

[0107] like Figure 6As shown, for an initial cache line (bytes 0 to byte 7) of 8 bytes (corresponding to the target cache line in the above embodiment), the initial byte mask (corresponding to the first mask in the above embodiment) is set to 4 bits. The initial cache line contains no valid data. After writing data to byte 0 and byte 2 in the cache line, byte 1, byte 3 to byte 7 are identified as invalid byte positions. Using a linked list, the mask for the first invalid byte position byte 1 (corresponding to the first mask in the above embodiment) is stored in the byte mask after the data is written, and the position is encoded as 0001 using 4 bits. Based on the byte mask, the first invalid byte position byte 1 is determined, and the second invalid byte position byte 3 is encoded as 0011 using 4 bits and stored in the invalid byte position byte 1 in the cache line. Based on byte 1, the second invalid byte position byte 3 is determined. And so on, the sixth invalid byte position byte 7 is encoded as 0111 using 4 bits and stored in the invalid byte position byte 6 in the cache line. An additional 4 bits of 1000 (corresponding to the termination mask in the above embodiment) are set to indicate the termination of the linked list and stored in the invalid byte position byte7 in the cached data block. The byte masks 0001 to 1000 corresponding to all invalid byte positions are stored sequentially in the byte mask and the corresponding invalid byte positions in the cached data block. The write request data is stored in byte0 and byte2 to obtain the compressed format.

[0108] In this case, 0001 is stored in the byte mask, indicating that byte position byte1 in the cached data block is invalid; 0011 is stored in byte1, indicating that byte position byte3 in the cached data block is invalid; and so on, 1000 is stored in byte7, indicating that byte7 in the cached data block is the last invalid byte position.

[0109] Figure 7 This is a schematic diagram illustrating the process of writing cached data according to an embodiment of this application. Given that a portion of the current cached data block has been written, taking an 8-byte cached data block as an example, the process of writing cached data is as follows: Step S701: Start the process of writing cached data; Step S702: Determine whether the write request hits the target cache line; Specifically, address matching is performed between the address of the write request and the address of the target cache line in the cache (corresponding to the hit check in the above embodiment) to obtain the address matching result; based on the address matching result, it is determined whether the write request hits the target cache line. If the address of the write request matches the address of the target cache line in the cache, it is determined that the write request hits the target cache line; if the address of the write request does not match the address of the target cache line in the cache, it is determined that the write request does not hit the target cache line.

[0110] Step S703: Calculate the compression format based on the current byte mask; During address determination, the data after compressing the byte mask is calculated in parallel. If the write request misses the target cache line, the current byte mask is 0000. The compressed mask data is determined based on the target byte position corresponding to the write request. For example, if the target byte position corresponding to the write request is byte1 and byte3, then the invalid byte positions of the target cache line are byte0, byte2, byte4 to byte7. The calculated mask data (corresponding to the invalid byte encoding in the above embodiment) is 0000→0010→0100→0101→0110→0111→1000. The 0000 in the mask data needs to be stored in the byte mask, and 0010, 0100, 0101, 0110, 0111, and 1000 need to be stored sequentially in byte0, byte2, byte4 to byte7.

[0111] Step S704: Write the cached data and the corresponding mask data; In the case where a write request misses the target cache line, based on the compression format calculated in step S703 and the target byte position corresponding to the write request, the cached data and mask data of the write request are written into the target cache line and the byte mask. The cached data is written to the target byte position of the target cache line, and the first mask in the mask data is stored in the byte mask. The other masks in the mask data are sequentially written to the invalid byte positions of the target cache line. For example, the valid bytes in the target cache line are byte1 and byte3, and the invalid bytes are byte0, byte2, byte4 to byte7. The mask for the first invalid byte, 0000, is stored in the byte mask. Based on the byte mask, the invalid byte byte0 is determined, and the mask for the next invalid byte, 0010, is stored in byte0. This continues until 1000 is stored in byte7.

[0112] Step S705: If the write request hits the target cache line, determine whether the highest bit of the byte mask is 1; In the case where a write request hits the target cache line, the address of the target cache line exists in the cache. In this case, it is necessary to determine the position of the valid byte in the target cache line at this time through the byte mask corresponding to the target cache line.

[0113] In the case where the most significant bit of the byte mask is 1, the target cache line contains all complete data (all byte positions are valid), and step S704 is executed. Based on the write request, the cached data is written to the target byte position of the target cache line (this can be either overlaying the original cached data or replacing the original cached data). At this time, the mask stored in the byte mask remains unchanged at 1000.

[0114] Step S706: If the highest bit of the byte mask is not 1, read the original cached data block and byte mask, and calculate the decompression mode.

[0115] In this scenario, when the most significant bit of the byte mask is not 1, valid data is written to some byte positions in the target cache line, and the mask corresponding to invalid bytes is written to others. By reading the cached data and byte mask from the original target cache line, the positions of valid and invalid bytes in the original target cache line can be determined, thus obtaining the decompression mode. For example, if the cached data in the original target cache line is byte0 (valid), byte1 (valid), byte2 (valid), 0100, 0101, 0110, 0111, 1000, and the original byte mask is 0011, after reading the cached data and byte mask from the original target cache line, it can be determined that byte0, byte1, and byte2 are valid, while bytes3 to byte7 are invalid, i.e., the decompression mode is 00000111.

[0116] Step S707: Combine the original decompressed byte mask and the written byte mask to recalculate the compression format.

[0117] After obtaining the decompressed byte mask, the positions of valid and invalid bytes in the current target cache line can be determined. Combined with the target byte position corresponding to the write request, the positions of valid and invalid bytes in the target cache line after writing cached data can be determined. Based on the positions of valid and invalid bytes in the target cache line, the mask data can be determined, thus obtaining the compressed format. For example, if the decompressed byte mask is 00000111, it can be determined that byte0, byte1, and byte2 are valid in the target cache line, while bytes3 to byte7 are invalid. If the write request requires writing bytes3 and byte7, it is determined that byte0, byte1, byte2, byte3, and byte7 are valid in the target cache line, while bytes4 to byte6 are invalid. Therefore, the mask data is 0100→0101→0110→1000. The 0100 in the mask data needs to be stored in the byte mask, and 0101, 0110, and 1000 need to be stored sequentially in bytes4 to byte6.

[0118] Step S708: Based on the recalculated compression format, write the cached data and the corresponding mask data.

[0119] After determining the compression format, based on the compression format and the target bytes corresponding to the write request, the cached data and mask data of the write request are written into the target cache line and byte mask. The cached data is written into the target byte position of the target cache line, the first mask in the mask data is stored in the byte mask, and the other masks in the mask data are sequentially written into the invalid byte positions of the target cache line.

[0120] The embodiments of this application can reduce the storage consumption for byte masks in the cache. Taking an 8-byte cache data block as an example, the additional storage is reduced from 1 / 8 to 1 / 16. For a 128-byte cache data block, the additional storage is reduced from 1 / 8 to 1 / 128.

[0121] In this embodiment, the additional storage for the byte mask calculated by the relevant scheme is always 1 / 8; in this application, the number of bits for additional storage is... Then, the cached data block is converted to bits (bytes multiplied by 8). Dividing the two gives the extra cost of storing the byte mask. Therefore, the longer the cached data block, the more significant the benefit. Current mainstream graphics processing units (GPUs) typically use 128-byte cached data blocks, so the extra cost is only 1 / 128.

[0122] In this embodiment, the cache data mask is stored in a compressed format to reduce additional area overhead; a linked list is used to store the mask information using invalid cache data bits; when writing data in the cache, the mask needs to be compressed and decompressed.

[0123] Based on the foregoing embodiments, this application provides a data writing device, which includes the included units and the modules included in each unit, which can be implemented by a processor in an electronic device; of course, it can also be implemented by specific logic circuits; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0124] Figure 8 This is a schematic diagram of the composition structure of a data writing device provided in an embodiment of this application, as shown below. Figure 8 As shown, the data writing device 800 includes: a receiving module 810, an encoding module 820, and a writing module 830, wherein: The receiving module 810 is configured to receive a write request for a target cache line; the write request is used to write data to the valid byte position of the target cache line. Encoding module 820 is configured to encode the at least one invalid byte position in the target cache line when it is determined based on the write request that there is at least one invalid byte position in the target cache line, to obtain an invalid byte encoding; the invalid byte encoding includes a first mask for determining an invalid byte position in the target cache line. The writing module 830 is used to write the data to the valid byte position and store the first mask; wherein, when there are at least two invalid byte positions, the invalid byte encoding further includes a second mask; the first mask and all second masks are used to determine all invalid byte positions.

[0125] In some embodiments, the first mask is used to store the first invalid byte position, and the second mask stored at the first invalid byte position is used to indicate the second invalid byte position, which is the next invalid byte position adjacent to the first invalid byte position.

[0126] In some embodiments, the invalid byte encoding further includes a termination mask, which is stored at the last invalid byte position among the at least one invalid byte positions.

[0127] In some embodiments, the first mask is stored in byte mask bits associated with the target cache line.

[0128] In some embodiments, if it is determined based on the write request that the invalid byte position does not exist in the target cache line, the byte mask bit is used to store a termination mask.

[0129] In some embodiments, the invalid byte encoding includes N sequential second masks, and the target cache line includes N+1 sequential invalid byte positions, wherein the nth second mask is stored in the nth invalid byte position, and n and N are positive integers, where n is less than or equal to N.

[0130] In some embodiments, the receiving module 810 is further configured to perform a hit check on the write request; if the hit check result indicates that the target cache line was not hit, determine the position of an invalid byte in the target cache line based on the position of a valid byte in the write request; if the hit check result indicates that the target cache line was hit, determine the position of an invalid byte in the target cache line based on the position of a valid byte in the write request and the original invalid byte encoding of the target cache line.

[0131] In some embodiments, the receiving module 810 is further configured to determine the position of the original valid byte in the target cache line based on the original invalid byte encoding; and to determine the position of the invalid byte in the target cache line based on the original valid byte position and the position of the valid byte in the write request.

[0132] In some embodiments, the receiving module 810 is further configured to, when the original invalid byte encoding includes the original first mask, determine at least one original invalid byte position in the target cache line based on the original invalid byte encoding; and determine the original valid byte position in the target cache line based on the at least one original invalid byte position.

[0133] In some embodiments, the receiving module 810 is further configured to determine that the target cache line consists entirely of original valid bytes when the original invalid byte encoding only includes the original termination mask.

[0134] In some embodiments, the encoding module 820 is further configured to determine the number of encoding bits based on the byte length of the target cache line; and to encode the at least one invalid byte position based on the number of encoding bits to obtain invalid byte encoding.

[0135] The descriptions of the apparatus embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the apparatus provided in this application can be used to perform the methods described in the method embodiments above. For technical details not disclosed in the apparatus embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0136] It should be noted that, in the embodiments of this application, if the above-described methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0137] This application provides an electronic device, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0138] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0139] This application provides a computer program including computer-readable code, wherein when the computer-readable code is executed in an electronic device, a processor in the electronic device performs some or all of the steps in the above-described method.

[0140] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0141] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0142] Figure 9 This is a hardware entity diagram of an electronic device provided in an embodiment of this application, such as... Figure 9 As shown, the hardware entity of the electronic device 900 includes a processor 901 and a memory 902, wherein the memory 902 stores a computer program that can run on the processor 901, and the processor 901 executes the program to implement the steps in the method of any of the above embodiments.

[0143] The memory 902 stores computer programs that can run on the processor. The memory 902 is configured to store instructions and applications that can be executed by the processor 901. It can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data and video communication data) in the processor 901 and various modules in the electronic device 900. It can be implemented by flash memory or random access memory (RAM).

[0144] The processor 901 executes the steps of any of the above methods when executing the program. The processor 901 typically controls the overall operation of the electronic device 900.

[0145] This application provides a computer storage medium that stores one or more programs, which can be executed by one or more processors to implement the steps of the methods described in any of the above embodiments.

[0146] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0147] The aforementioned processor can be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that other electronic devices can also implement the functions of the aforementioned processor, and this application does not specifically limit the specific implementation.

[0148] The aforementioned computer storage media / memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; or it can be various terminals that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0149] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0150] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0151] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0152] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0153] Furthermore, in the various embodiments of this application, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0154] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the data writing methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0155] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A data writing method, characterized in that, The data writing method includes: Receive a write request for a target cache line; the write request is used to write data to a valid byte position in the target cache line; If, based on the write request, it is determined that there is at least one invalid byte position in the target cache line, the at least one invalid byte position is encoded to obtain an invalid byte encoding; the invalid byte encoding includes a first mask for determining an invalid byte position in the target cache line. Write the data to the valid byte position and store the first mask; Where there are at least two invalid byte positions, the invalid byte encoding further includes a second mask; the first mask and all second masks are used to determine all invalid byte positions.

2. The data writing method according to claim 1, characterized in that, The first mask is used to store the position of the first invalid byte, and the second mask stored at the position of the first invalid byte is used to indicate the position of the second invalid byte, which is the next invalid byte position adjacent to the position of the first invalid byte.

3. The data writing method according to claim 2, characterized in that, The invalid byte encoding also includes a termination mask, which is stored in the last invalid byte position among the at least one invalid byte positions.

4. The data writing method according to claim 1, characterized in that, The first mask is stored in byte mask bits associated with the target cache line.

5. The data writing method according to claim 4, characterized in that, If it is determined based on the write request that the invalid byte position does not exist in the target cache line, the byte mask bit is used to store the termination mask.

6. The data writing method according to claim 1, characterized in that, The invalid byte encoding includes N sequential second masks, and the target cache line includes N+1 sequential invalid byte positions, wherein the nth second mask is stored in the nth invalid byte position, and n and N are positive integers, where n is less than or equal to N.

7. The data writing method according to claim 1, characterized in that, The data writing method further includes: Perform a hit check on the write request; If the hit check result indicates that the target cache line was not hit, the position of the invalid byte in the target cache line is determined based on the position of the valid byte in the write request; If the hit check result indicates that the target cache line has been hit, the position of the invalid byte in the target cache line is determined based on the position of the valid byte in the write request and the original invalid byte encoding of the target cache line.

8. The data writing method according to claim 7, characterized in that, Determining the position of the invalid byte in the target cache line based on the position of the valid byte in the write request and the original invalid byte encoding of the target cache line includes: Based on the original invalid byte encoding, determine the position of the original valid byte in the target cache line; Based on the original valid byte position and the valid byte position in the write request, the invalid byte position in the target cache line is determined.

9. The data writing method according to claim 8, characterized in that, Determining the position of the original valid byte in the target cache line based on the original invalid byte encoding includes: If the original invalid byte encoding includes the original first mask, at least one original invalid byte position in the target cache line is determined based on the original invalid byte encoding; Based on the at least one original invalid byte position, determine the original valid byte position in the target cache line.

10. The data writing method according to claim 8, characterized in that, Determining the position of the original valid byte in the target cache line based on the original invalid byte encoding includes: If the original invalid byte encoding only includes the original termination mask, then the target cache line is determined to be entirely composed of original valid byte positions.

11. The data writing method according to any one of claims 1 to 10, characterized in that, Encoding the at least one invalid byte position to obtain the invalid byte encoding includes: The number of encoded bits is determined based on the byte length of the target cache line; Based on the number of encoded bits, the position of the at least one invalid byte is encoded to obtain the invalid byte encoding.

12. A data writing device, characterized in that, The data writing device includes a receiving module, an encoding module, and a writing module; wherein... The receiving module is configured to receive a write request for a target cache line; the write request is configured to write data to a valid byte position in the target cache line. The encoding module is configured to encode the at least one invalid byte position in the target cache line when it is determined based on the write request that there is at least one invalid byte position in the target cache line, thereby obtaining an invalid byte encoding; the invalid byte encoding includes a first mask for determining an invalid byte position in the target cache line. The writing module is used to write the data to the valid byte position and store the first mask; wherein, when there are at least two invalid byte positions, the invalid byte encoding further includes a second mask; the first mask and all second masks are used to determine all invalid byte positions.

13. An electronic device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the data writing method according to any one of claims 1 to 11.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the data writing method according to any one of claims 1 to 11.

15. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by the processor, they implement the steps of the data writing method according to any one of claims 1 to 11.

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