State machine jump control method, JTAG (Joint Test Action Group) state machine controller and system
By configuring and parsing target instructions on a host computer, and combining software and hardware methods, the problems of slow response speed and difficulty in expansion of JTAG state machines are solved, achieving fast and stable state transitions and flexible expansion capabilities.
Patent Information
- Application Number
- CN202511082957.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-01
- Publication Date
- 2025-11-18
AI Technical Summary
Existing JTAG state machines have slow and unstable state transition response speeds, making it difficult to flexibly expand to support various state transition requirements. Pure software implementations have low speeds, while pure hardware implementations consume large resources and are difficult to expand.
The target instruction is configured and parsed by the host computer, and the JTAG state machine circuit jumps according to the parsing result. Combined with software and hardware implementation, it supports a variety of state jump requirements, responds quickly and expands flexibly.
It achieves fast and stable state transition response, supports multiple state transition requirements, avoids problems of resource consumption and long development cycle, and is adaptable to different target chips.
Smart Images
Figure CN120973418A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technology, and in particular to a state machine transition control method, a JTAG state machine controller, and a system. Background Technology
[0002] JTAG (Joint Test Action Group) is a standardized test and debugging technology. Its core is to enable the testing, configuration, and debugging of integrated circuits (ICs), printed circuit boards (PCBs), and systems through a unified interface and protocol. The core of the JTAG architecture is the Test Access Port (TAP) and related test logic. The TAP controller is a 16-state synchronous finite JTAG state machine. It controls state transitions and coordinates the transmission flow of instructions and data through the logic value of the TMS (Test Mode Select) signal on the rising edge of the TCK (Test Clock). There are two implementation methods: one is a pure software approach, which generates JTAG timings through I / O simulation, but this method has slow state transition response; the other is a pure hardware implementation, which only supports limited state transitions for already supported instructions and is difficult to extend with new instructions. Summary of the Invention
[0003] Therefore, it is necessary to provide a state machine transition control method, a JTAG state machine controller, a system, and a computer device to address the above-mentioned technical problems, which supports various different state transition requirements and has a fast state transition response.
[0004] A state machine transition control method, applied to a host computer, includes: Obtain the target instruction configured on the host computer, wherein the target instruction represents the target jump path of the JTAG state machine circuit; The target instruction is parsed to obtain the parsing result supported by the JTAG state machine circuit; The parsing result is sent to the JTAG state machine circuit, and the parsing result is used to instruct the JTAG state machine circuit to perform a state transition according to the target transition path.
[0005] A JTAG state machine controller, comprising: A register is used to receive the parsing result sent by the host computer; the parsing result includes the target jump path of the JTAG state machine circuit; the target jump path is obtained by parsing the target instruction configured in the host computer. The JTAG state machine circuit is connected to the register and is used to perform state transitions according to the target transition path to generate the test access port signal corresponding to the target chip.
[0006] A state machine transition control system, the system comprising a host computer and a JTAG state machine controller connected to the host computer; The host computer is used to acquire a target instruction configured on the host computer, the target instruction representing a target jump path of the JTAG state machine circuit; and The target instruction is parsed to obtain the parsing result supported by the JTAG state machine circuit; The JTAG state machine controller is used to perform state transitions according to the target transition path and generate a test access port signal corresponding to the target chip.
[0007] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of an embodiment of a state machine transition control method.
[0008] A computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of an embodiment of a state machine transition control method.
[0009] A computer program product includes a computer program that, when executed by a processor, implements the steps of an embodiment of a state machine transition control method.
[0010] The aforementioned state machine transition control method, JTAG state machine controller, and system configure and parse target instructions via a host computer. The JTAG state machine circuit then performs transitions based on the parsed results, delegating the instruction configuration steps to the host computer. This allows for flexible instruction configuration and supports different state transition requirements. Furthermore, using the JTAG state machine circuit for transitions ensures fast response times. By combining hardware and software approaches, the system solves the problems of slow speed and unstable cycles inherent in purely software implementations, while also enabling flexible expansion without altering logic resources. It can generate corresponding test sequences for different target chips. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 This is an application environment diagram of the state machine transition control method in one embodiment; Figure 2 This is a flowchart illustrating a state machine transition control method in one embodiment; Figure 3 This is a schematic diagram of the structure of a JTAG state machine controller in one embodiment; Figure 4 This is a schematic diagram of the state machine transition control system in one embodiment; Figure 5 This is a schematic diagram of state transitions in one embodiment; Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0013] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.
[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0015] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly. The connection can be a direct connection or an indirect connection.
[0016] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.
[0017] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0018] It is understood that the "data acquisition" operation in the embodiments of this application includes, but is not limited to, the following implementation methods: directly reading the raw data pre-stored in the device; or the indirect acquisition method after data collection, conversion and processing.
[0019] The state machine transition control method provided in this application can be applied to, for example... Figure 1 In the application environment. Figure 1 This diagram illustrates the application environment of a state machine transition control method in one embodiment. The host computer refers to a computer device with data processing capabilities and a user interface, used to configure and control the operation of lower-level hardware devices. The host computer 100 can be, but is not limited to, various MCUs (Microcontroller Units), CPUs (Central Processing Units), personal computers, laptops, smartphones, tablets, and portable wearable devices. The JTAG state machine controller 200 can specifically be an FPGA (Field-Programmable Gate Array). The JTAG state machine controller 200 includes a JTAG state machine circuit 210. The FPGA is used to connect to the target chip 300 for testing the target chip 300. The core of the JTAG architecture is the Test Access Port (TAP) and related test logic.
[0020] The Test Access Port (TAP) includes four mandatory signals and one optional signal: TCK (Test Clock): The test clock synchronizes all JTAG operations and is independent of the system clock.
[0021] TMS (Test Mode Select): Test mode selection, which controls the state transition of the TAPJTAG state machine through level changes (0 / 1).
[0022] TDI (Test Data In): Test data input, serial transmission of commands and data into the IC.
[0023] TDO (Test Data Out): Test data output, serially transmitting the test results or status inside the IC.
[0024] TRST (Test Reset, optional): Asynchronous reset signal (active low), initializes the TAP controller to its initial state.
[0025] The TAP controller is a 16-state synchronous finite JTAG state machine that controls state transitions and coordinates the transmission flow of instructions and data through the logic value of the TMS signal on the rising edge of TCK.
[0026] Traditional software-based state transition implementations require IO simulation of TMS, TCK, TDO, and TDI timings, resulting in slow inversion rates and inability to support high-speed communication. Furthermore, the signal period may be unstable due to software scheduling. Hardware-based implementations, where the host computer sends an instruction and the slave computer parses it to obtain a fixed path, offer relatively fixed state transitions, supporting only a limited number of supported instructions and not complete state transitions. Expanding to include more instructions requires enabling the slave computer to parse the instruction and modifying its logic (e.g., FPGA) for resynthesis. Each modification requires firmware burning and other steps, leading to long development cycles and high costs. Supporting an even larger number of instructions consumes even more resources. Therefore, to address these issues, this application proposes a state machine transition control method that offers higher speed and more stable signal periods than pure software solutions, is more flexibly expandable than pure hardware solutions, and can support target chips with different timing and state transition requirements.
[0027] like Figure 2 The diagram shown is a flowchart of a state machine transition control method in one embodiment, including the following steps: Step 202: Obtain the target instruction configured on the host computer. The target instruction represents the target jump path of the JTAG state machine circuit.
[0028] The target instruction refers to the specific operation command configured by the user through the host computer. This command defines the state transition behavior that the JTAG state machine circuit should execute. The target instruction includes information such as the starting state, the target state, and the transition conditions. It refers to a digital circuit designed based on the principle of a finite JTAG state machine, capable of switching between different states according to changes in the input signal.
[0029] JTAG state machine circuits are digital circuits designed based on the principles of finite JTAG state machines, capable of switching between different states according to changes in input signals. JTAG state machine circuits include, but are not limited to, hardware components such as sequential logic circuits, combinational logic circuits, register banks, and control units. JTAG state machine circuits can support arbitrary path transitions.
[0030] A target jump path refers to a sequence of state transitions that a JTAG state machine circuit traverses from its current state to a target state. Each jump path corresponds to a complete business logic flow or operation sequence. There is a one-to-one correspondence between target instructions and target jump paths.
[0031] The host computer receives user commands for configuration operations through a graphical user interface. Users can select preset state transition templates on the interface or manually input specific transition rules. For example, users can configure commands like "State A → State B → State C," or complex transition logic with conditional judgments, such as "If input signal X is high, transition from State A to State B; otherwise, transition to State C." The host computer converts the user-configured information into a target command data packet, which includes fields such as source state identifier, target state identifier, and transition condition parameters.
[0032] Step 204: Parse the target instruction to obtain the parsing result supported by the JTAG state machine circuit.
[0033] The parsing result refers to the standardized data structure obtained after parsing. This data structure contains state paths, state identifiers, transition conditions, control signals, and other information that can be directly recognized by the JTAG state machine circuit. The parsing result is usually represented in binary code, control words, or other machine code.
[0034] Specifically, the host computer's built-in instruction parsing engine performs syntax verification and semantic analysis on the received target instruction. The parsing engine first checks if the instruction format is correct, and then verifies the validity of the jump path (e.g., whether there are loops, undefined states, etc.). When the instruction format is correct and the path is valid, the target instruction is parsed to obtain the parsing result supported by the JTAG state machine circuit, and this parsing result includes the target jump path of the JTAG state machine circuit.
[0035] Step 206: Send the parsing result to the JTAG state machine circuit. The parsing result is used to instruct the JTAG state machine circuit to perform state transitions according to the target transition path.
[0036] Specifically, the host computer sends the parsing result to the JTAG state machine circuit through the bus protocol. After receiving the parsing result, the JTAG state machine circuit directly performs the state transition according to the target transition path in the parsing result.
[0037] In this embodiment, the host computer configures and parses the target instruction. The JTAG state machine circuit can then jump according to the parsing result, delegating the instruction configuration steps to the host computer. This makes instruction configuration flexible and supports different state jump requirements. Furthermore, using the JTAG state machine circuit to implement jumps ensures fast state jump response. By combining hardware and software, the slow speed and unstable cycle of pure software implementation are solved, while also allowing for flexible expansion without changing logic resources. Corresponding test sequences can be generated for different target chips.
[0038] In one embodiment, the target transition path includes a loop path and a number of loops; sending a parsing result to the JTAG state machine circuit, the parsing result being used to instruct the JTAG state machine circuit to perform state transitions according to the target transition path, includes: Send the parsing result to the JTAG state machine circuit. The parsing result is used to instruct the JTAG state machine circuit to repeat the loop according to the loop path for the specified number of loops.
[0039] The target transition path includes the loop path and the number of loop iterations. The loop path refers to a continuous sequence of states that needs to be repeatedly executed during JTAG state machine transitions. A loop path typically contains a start state and an end state. When the JTAG state machine reaches the end state, it automatically returns to the start state to restart execution, forming a closed-loop structure. The number of loop iterations refers to the predetermined number of times the loop path needs to be executed. The number of loop iterations can be a finite positive integer or an infinite number (usually represented by a special identifier). When the number of loop iterations is a finite value, the JTAG state machine will exit the loop path after completing the specified number of iterations and continue executing subsequent transition logic. For example, if 1010 needs to loop 9 times, then the loop path is 1011, and the number of iterations is 9. Stopping the loop means that the JTAG state machine will not return to the start state of the loop path after completing the predetermined number of iterations.
[0040] Specifically, the target instruction configured by the host computer includes the encapsulated loop path and loop count. After parsing it, the host computer obtains the loop path and loop count supported by the JTAG state machine circuit. For example, if the loop path is 1011 and the loop count is 9, then the actual running result of the JTAG state machine circuit is 101110111011…1011, which contains nine 1011s. The JTAG state machine circuit then loops according to the loop path for the specified number of loops and then stops. Subsequently, it can jump according to the subsequent target jump path, or it can reconfigure the path.
[0041] In this embodiment, the target jump path includes a loop path and a loop count. The parsing result is sent to the JTAG state machine circuit. The parsing result is used to instruct the JTAG state machine circuit to loop the loop path for the specified number of times and then stop the loop. By configuring the hardware through software, the number of loops can be precisely controlled, avoiding errors that may occur with the software count, ensuring the accuracy of the loop execution, and also avoiding infinite loops.
[0042] In one embodiment, the state machine transition control method further includes: obtaining a target instruction updated on the host computer, and sending the target instruction to the JTAG state machine circuit, wherein the target instruction is used to instruct the JTAG state machine circuit to continue transitioning according to the updated target transition path after the loop stops.
[0043] In this context, the updated target instruction refers to a new jump instruction reconfigured by the user via the host computer during or after the execution of the JTAG state machine. The updated target instruction can be a modification of the original jump path (the next action) or entirely new jump logic. The updated target instruction represents the updated target jump path.
[0044] Specifically, during or before the JTAG state machine circuit completes its loop, the host computer can receive new configuration instructions from the user. This update operation can be triggered by an external event or a preset time point. After receiving the updated target instruction, the host computer parses it and generates a new parsing result. This update process can occur at any stage of the JTAG state machine circuit's loop execution, including during loop execution or after loop completion. When the JTAG state machine circuit completes the preset number of loops and stops looping, if it receives the updated parsing result, it will immediately continue executing the state transition according to the updated target transition path.
[0045] Optionally, the host computer can send an update notification to the JTAG state machine circuit via an interrupt mechanism. Upon receiving the notification, the JTAG state machine circuit suspends its current operation, loads the new parsing result, and then executes a new jump path starting from the specified state.
[0046] In this embodiment, the target instruction updated on the host computer is obtained and sent to the JTAG state machine circuit. This target instruction instructs the JTAG state machine circuit to continue jumping according to the updated target jump path after the loop stops, which can avoid infinite loops. Furthermore, the host computer can flexibly configure instructions, supporting dynamic updates of jump paths during operation. This allows the JTAG state machine to flexibly adjust its execution logic according to real-time conditions or external events, greatly enhancing the system's adaptability. When an execution anomaly is detected or the control strategy needs to be adjusted, the execution path can be quickly corrected through the update instruction, improving the system's fault tolerance and self-recovery capabilities.
[0047] In one embodiment, such as Figure 3 The diagram shown is a structural schematic of a JTAG state machine controller in one embodiment, including: Register 302 is used to receive the parsing result sent by the host computer; the parsing result includes the target jump path of the JTAG state machine circuit; the target jump path is obtained by parsing the target instruction configured in the host computer; JTAG state machine circuit 304, connected to the register, is used to perform state transitions according to the target transition path and generate corresponding test access port signals.
[0048] In this embodiment, the host computer configures and parses the target instruction. The JTAG state machine circuit can jump according to the parsing result, and the instruction configuration steps are handed over to the host computer, making the instruction configuration flexible. Furthermore, the jump is implemented by the JTAG state machine circuit. Through the combination of hardware and software, the problems of slow speed and unstable cycle of pure software implementation are solved. It can also be flexibly expanded without changing the logic resources, and corresponding test sequences can be generated for different target chips.
[0049] In one embodiment, the target jump path includes a loop path and a number of loops; the JTAG state machine circuit is used to loop the loop path for the specified number of loops and then stop the loop.
[0050] In this embodiment, the target jump path includes a loop path and a loop count. The parsing result is sent to the JTAG state machine circuit. The parsing result is used to instruct the JTAG state machine circuit to loop the loop path for the specified number of times and then stop the loop. By configuring the hardware through software, the loop count can be precisely controlled, avoiding errors that may occur with the software count and ensuring the accuracy of the loop execution. It also avoids infinite loops and supports target chips with different timing and state jump requirements.
[0051] In one embodiment, the register is used to receive the target instruction updated on the host computer; the JTAG state machine circuit is used to continue jumping according to the updated target jump path after stopping the loop, based on the updated target received instruction.
[0052] In this embodiment, the target instruction updated on the host computer is obtained and sent to the JTAG state machine circuit. This target instruction instructs the JTAG state machine circuit to continue jumping according to the updated target jump path after the loop stops, which can avoid infinite loops. Furthermore, the host computer can flexibly configure instructions, supporting dynamic updates of jump paths during operation. This allows the JTAG state machine to flexibly adjust its execution logic according to real-time conditions or external events, greatly enhancing the system's adaptability. When an execution anomaly is detected or the control strategy needs to be adjusted, the execution path can be quickly corrected through the update instruction, improving the system's fault tolerance and self-recovery capabilities.
[0053] In one embodiment, a JTAG state machine transition system includes a host computer and a JTAG state machine controller connected to the host computer. The host computer is used to obtain the target instruction configured on the host computer. The target instruction represents the target jump path of the JTAG state machine circuit; and The target instruction is parsed to obtain the parsing results supported by the JTAG state machine circuit. The JTAG state machine controller is used to perform state transitions according to the target transition path and generate test access port signals corresponding to the target chip.
[0054] In this embodiment, the host computer configures and parses the target instruction. The JTAG state machine circuit can jump according to the parsing result, and the instruction configuration steps are handed over to the host computer, making the instruction configuration flexible. Furthermore, the jump is implemented by the JTAG state machine circuit. Through the combination of hardware and software, the problems of slow speed and unstable cycle of pure software implementation are solved. It can also be flexibly expanded without changing the logic resources, and corresponding test sequences can be generated for different target chips.
[0055] In one embodiment, such as Figure 4 The diagram shown is a schematic diagram of the state machine transition control system in one embodiment. Figure 4 The system includes a host computer 410, a JTAG state machine controller 420, and a target chip 430. The JTAG state machine controller 420 includes a register 4201, a JTAG state machine circuit 4202, a transmit-side FIFO buffer 4203, and a receive-side FIFO buffer 4204. The registers can be AXI (Advanced Extensible Interface) registers. The transmit-side FIFO buffer 4203 and the receive-side FIFO buffer 4204 are used to allow the host computer to send clk (clock signal) and Rst_n (reset signal) to the JTAG state machine controller 420 via AXI. Register 4201 receives the parsing result sent by the host computer 410, which includes the target jump path of the JTAG state machine circuit. The JTAG state machine circuit 4202 performs state jumps according to the target jump path, generating the corresponding test access port signals for the target chip, including TMS, TCK, TDO, and TDI.
[0056] Figure 5 Chinese explanation Figure 4 The jump logic of the JTAG state machine circuit. For example... Figure 5 The diagram shown illustrates state transitions in one embodiment. The core is the implementation of the JTAG state machine. Since devices with JTAG interfaces have an internal TAPJTAG state machine, the host (FPGA) uses the TMS to drive the transitions of the TAPJTAG state machine within the target chip to achieve IR and DR transmission. The host implements a JTAG state machine internally to generate the TMS, TCK, TDO, and TDI timing sequences, ensuring that the JTAG state machine states of the slave target chip are consistent with the JTAG state machine states of the host. The following is a description of each state.
[0057] (1) When the host computer writes 1 to cr1_irrst, the FPGA will generate a flag bit with a width equal to the loop_irrst_valid configuration value. When this flag bit is 1, the TMS output is 1, causing the slave state machine to return to Test-Logic-Reset. After the reset is complete, the state automatically jumps to RUN_TEST_IDLE, and the TMS output is 0. (Regardless of the current state machine state, keeping TMS 1 for 5 TCK cycles will allow it to return to the Test_Logic_Reset state.) (2) When the state machine is in RUN_TEST_IDLE, the host computer can control the register to configure the direction of each node in the next round. For example, the register configuration cr_select_dr_scan determines whether the next state of SELECT_DR_SCAN is CAPTURE_DR or SELECT_IR_SCAN. After configuring the direction of each node, the path of one round of state machine operation is determined. After completing the configuration, write 1 to cr2_run and the state machine will start running. Otherwise, it will remain in the RUN_TEST_IDLE state. A special case of a loop needs to be considered, where, after configuration, the state transitions to either (RUN_TEST_IDLE -> SELECT_DR_SCAN -> CAPTURE_DR -> SHIFT_DR -> EXIT1_DR -> PAUSE_DR -> EXIT2_DR -> SHIFT_DR -> ...) or (RUN_TEST_IDLE -> SELECT_DR_SCAN -> CAPTURE_DR -> SHIFT_DR -> EXIT1_DR -> PAUSE_DR -> EXIT2_DR -> UPDATE_DR -> SELECT_DR_SCAN -> ...) ...) forms a loop, so the configurations cr_pause_dr_cfg, cr_pause_ir_cfg, and loop_pause_stop are added to indicate whether it is necessary to stop at the PAUSE_DR or PAUSE_IR state at the loop_pause_stop time to modify the subsequent state path. If the path configured before run will not form a loop, cr_pause_dr_cfg and cr_pause_ir_cfg can be set to 0. If the path configured before run will form a loop, cr_pause_dr_cfg or cr_pause_ir_cfg must be set to 1 to break the loop. After reaching the PAUSE_DR or PAUSE_IR state at the loop_pause_stop time, TCK transmission is paused, and TMS keeps outputting 0. After the host computer reconfigures the subsequent state transition path, cr2_run is written to the register to configure 1, and the system runs according to the newly configured state, thus exiting the state loop situation.
[0058] (3) After the state machine starts running from the RUN_TEST_IDLE state, it remains in the RUN_TEST_IDLE state until the number of cycles assigned to loop_run_idle is reached, and then the state jumps to SELECT_DR_SCAN.
[0059] (4) Before writing cr2_run, the host computer needs to configure cr_select_dr_scan. If it is configured as 1, it means that DR is being processed, and the status jumps from SELECT_DR_SCAN to CAPTURE_DR, and the TMS outputs 0. If it is configured as 0, it means that IR is being processed, and the status jumps to SELECT_IR_SCAN, and the TMS outputs 1.
[0060] (5) In the CAPTURE_DR state, the host computer can pre-configure cr_capture_dr. If the configuration is 0 (default), the state jumps to SHIFT_DR and TMS outputs 0. If the configuration is 1, the state jumps to EXIT1_DR and TMS outputs 1.
[0061] (6) In the SHIFT_DR state, if the pre-configured length has not been completely sent, the SHIFT_DR state is maintained and the TMS outputs 0. If the sending is completed, the state jumps to EXIT1_DR and the TMS outputs 1.
[0062] (7) In the EXIT1_DR state, if the cr2_psdr pre-configured by the host computer is 1, the state jumps to PAUSE_DR and the TMS outputs 0. If it is configured to 0, the state jumps to UPDATE_DR and the TMS outputs 1.
[0063] (8) In the PAUSE_DR state, the host computer can pre-configure loop_pause_dr, which represents the number of cycles to be held in the PAUSE_DR state. If the number of cycles is not reached, PAUSE_DR is maintained and TMS outputs 0. If the number of cycles is reached, the state jumps to EXIT2_DR and TMS outputs 1.
[0064] (9) In the EXIT2_DR state, the host computer can pre-configure cr_exit2_dr. If it is configured as 1, the state jumps to SHIFT_DR and TMS outputs 0. If it is configured as 0 (default), the state jumps to UPDATE_DR and TMS outputs 1.
[0065] (10) In the UPDATE_DR state, the host computer can pre-configure cr_update_dr. If it is configured as 0 (default), the state will jump to RUN_TEST_IDLE and TMS will output 0. If it is configured as 1, the state will jump to SELECT_DR_SCAN and TMS will output 1.
[0066] (11) In the SELECT_IR_SCAN state, the host computer can pre-configure cr_select_ir_scan. If it is configured as 0 (default), the state will jump to CAPTURE_IR and TMS will output 0. If it is configured as 1, the state will jump to TEST_LOGIC_RESET and TMS will output 1.
[0067] (12) In the CAPTURE_IR state, the host computer can pre-configure cr_capture_ir. If the configuration is 0 (default), the state will jump to SHIFT_IR and TMS will output 0. If the configuration is 1, the state will jump to EXIT1_IR and TMS will output 1.
[0068] (13) In the SHIFT_IR state, if the pre-configured length has not been sent, the SHIFT_IR state is maintained and the TMS outputs 0. If the sending is completed, the state jumps to EXIT1_IR and the TMS outputs 1.
[0069] (14) In the EXIT1_IR state, if the cr2_psir pre-configured by the host computer is 1, the state jumps to PAUSE_IR and the TMS outputs 0. If it is configured to 0, the state jumps to UPDATE_IR and the TMS outputs 1.
[0070] (15) In the PAUSE_IR state, the host computer can pre-configure loop_pause_ir, which represents the number of cycles to be held in the PAUSE_IR state. If the number of cycles is not reached, PAUSE_IR is maintained and TMS outputs 0. If the number of cycles is reached, the state jumps to EXIT2_IR and TMS outputs 1.
[0071] (16) In the EXIT2_IR state, the host computer can pre-configure cr_exit2_ir. If it is configured as 1, the state will jump to SHIFT_IR and TMS will output 0. If it is configured as 0 (default), the state will jump to UPDATE_IR and TMS will output 1.
[0072] (17) In the UPDATE_IR state, the host computer can pre-configure cr_update_ir. If it is configured as 0 (default), the state will jump to RUN_TEST_IDLE and TMS will output 0. If it is configured as 1, the state will jump to SELECT_DR_SCAN and TMS will output 1.
[0073] By configuring jump paths through the host computer, all the jumps mentioned above can be flexibly supported, solving the problem that some target chips cannot support state jumps (such as state jumps RUN_TEST_IDLE -> SELECT_DR_SCAN -> CAPTURE_DR -> EXIT1_DR -> UPDATE_DR –> ……). At the same time, it does not require reprogramming the hardware, which solves the problems of slow speed and unstable cycle of pure software implementation, and allows for flexible expansion without changing the logic resources. It can generate corresponding test sequences for different target chips.
[0074] It should be understood that, although the above Figure 2The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the exact order indicated by the arrows or numbers. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0075] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a state machine transition control method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, a trackball, or a touchpad located on the computer device casing, or an external keyboard, touchpad, or mouse, etc. Those skilled in the art will understand that... Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0076] Those skilled in the art will understand that Figure 6The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0077] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described method embodiments.
[0078] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method embodiments.
[0079] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the above-described method embodiments.
[0080] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0081] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A state machine transition control method, characterized in that, Applications in host computers include: Obtain the target instruction configured on the host computer, wherein the target instruction represents the target jump path of the JTAG state machine circuit; The target instruction is parsed to obtain the parsing result supported by the JTAG state machine circuit; The parsing result is sent to the JTAG state machine circuit, and the parsing result is used to instruct the JTAG state machine circuit to perform a state transition according to the target transition path.
2. The method according to claim 1, characterized in that, The target jump path includes a loop path and a number of loops; Sending the parsing result to the JTAG state machine circuit, the parsing result being used to instruct the JTAG state machine circuit to perform a state transition according to the target transition path, includes: The parsing result is sent to the JTAG state machine circuit, and the parsing result is used to instruct the JTAG state machine circuit to repeat the loop a certain number of times according to the loop path.
3. The method according to claim 2, characterized in that, The method further includes: The target instruction updated on the host computer is obtained, and the target instruction is sent to the JTAG state machine circuit. The target instruction is used to instruct the JTAG state machine circuit to continue jumping according to the updated target jump path after stopping the loop.
4. A JTAG state machine controller, characterized in that, include: The register is used to receive the parsing results sent by the host computer. The analysis results include the target jump path of the JTAG state machine circuit; The target jump path is obtained by parsing the target instruction configured on the host computer; The JTAG state machine circuit is connected to the register and is used to perform state transitions according to the target transition path to generate the test access port signal corresponding to the target chip.
5. The JTAG state machine controller according to claim 4, characterized in that, The target jump path includes a loop path and a number of loops; The JTAG state machine circuit is used to cycle the specified number of times according to the loop path and then stop the loop.
6. The JTAG state machine controller according to claim 5, characterized in that, The register is used to receive the target instruction updated on the host computer; The JTAG state machine circuit is used to continue jumping according to the updated target jump path after stopping the loop, based on the updated target receiving instruction.
7. A state machine transition control system, characterized in that, The system includes a host computer and a JTAG state machine controller connected to the host computer; The host computer is used to acquire the target instruction configured on the host computer, the target instruction representing the target jump path of the JTAG state machine circuit; as well as The target instruction is parsed to obtain the parsing result supported by the JTAG state machine circuit; The JTAG state machine controller is used to perform state transitions according to the target transition path and generate a test access port signal corresponding to the target chip.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 3.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 3.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 3.