Memory fault detection system and method, electronic equipment and storage medium

Abstract

The invention relates to a memory fault detection system and method, electronic equipment and a storage medium, and is applied to a system-on-chip (SoC), the system comprises a user interface module used for receiving a memory fault detection algorithm indicated by a user, and the memory fault detection algorithm is stored in an external storage of the SoC; the algorithm loading module is used for loading the memory fault detection algorithm from the external storage and storing the memory fault detection algorithm in an algorithm slot of the memory access control module when the operating system exits, and the algorithm slot is located in an on-chip static memory of the SoC; and the memory access control module is used for executing the memory fault detection algorithm so as to perform memory fault detection on a double data rate (DDR) memory. According to the embodiment of the invention, comprehensive detection of the DDR memory can be realized.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a memory fault detection system and method, an electronic device and a storage medium. BACKGROUND

[0002] Double Data Rate (DDR) memory is a crucial component in a System on Chip (SoC). Its main function is to provide high-speed data storage and access capabilities, ensuring smooth data read and write operations for various programs and functions in the SoC. The correctness of the DDR memory is crucial for the stable operation of the SoC, as any memory fault can cause program crashes, data loss or system performance degradation.

[0003] To ensure the correctness of the DDR memory and the stability of the system running on the SoC, the system on chip needs to perform memory fault detection to check and identify possible errors and problems in the memory. Through memory fault detection, the system can discover and correct certain types of errors (such as bit flips), or identify damaged memory cells and isolate or replace them. This ensures that the SoC can rely on reliable data storage and access mechanisms during operation, thereby improving the stability and reliability of the system.

[0004] However, in the related art, based on the original hardware memory detection of the memory controller, the detection algorithm is written in the memory controller, the detection algorithm is relatively single, and the flexibility and adaptability are poor, which cannot cope with the complex application scenarios of the existing SoC; and based on the memory detection algorithm of the system startup loader and the operating system, since the running of the system startup loader and the operating system itself needs to occupy part of the memory space, the memory detection cannot cover all the memory space, and the memory detection is not comprehensive enough. SUMMARY

[0005] The present disclosure proposes a memory fault detection technical solution.

[0006] According to an aspect of the present disclosure, a memory fault detection system is provided, applied to a system on chip (SoC), comprising:

[0007] a user interface module configured to receive a user-indicated memory fault detection algorithm, wherein the memory fault detection algorithm is stored in an external storage of the SoC;

[0008] an algorithm loading module configured to load the memory fault detection algorithm from the external storage and store it in an algorithm slot of a memory access control module when an operating system exits, wherein the algorithm slot is located in an on-chip static memory of the SoC;

[0009] The memory access control module is configured to execute the memory fault detection algorithm to perform memory fault detection on a double data rate (DDR) memory.

[0010] In a possible implementation, the system further includes:

[0011] A chip state detection module is configured to detect and manage the working state of the SoC, disable the memory detection function when the chip is running an operating system, and detect whether the state of the SoC meets the memory fault detection starting condition when the operating system exits, and start the memory access control module and the algorithm loading module if the detection condition is met.

[0012] In a possible implementation, the system further includes:

[0013] A system takeover module is configured to retain the power-on state of the hardware resource for memory fault detection when the operating system exits, and start the chip state detection module.

[0014] In a possible implementation, the system takeover module restores the chip environment required for running the operating system and the system startup loader before the operating system is ready to start.

[0015] In a possible implementation, the user interface module is configured to receive a user-defined memory fault detection algorithm and save it to the external storage, and / or receive a user-inputted identification of a preset memory fault detection algorithm and save the memory fault detection algorithm corresponding to the identification to the external storage.

[0016] In a possible implementation, the user interface module is configured to receive a user-indicated identification of the memory fault detection algorithm and save it to a direct access object storage (DAOS) data structure, and / or,

[0017] The user interface module is configured to receive a user-indicated execution parameter of the memory fault detection algorithm and save it to a direct access object storage (DAOS) data structure.

[0018] The execution parameter includes any one or more of the following: an execution order of the memory fault detection algorithm; a number of repeated executions; a start address of a memory to be checked; and an end address of the memory to be checked.

[0019] In a possible implementation, the algorithm loading module accesses the DAOS data structure in the external storage, determines the key information of the executable algorithm, and sends the key information to the memory access control module.

[0020] The memory access control module determines the memory fault detection algorithm to be executed based on the key information in the received DAOS data structure, and notifies the algorithm loading module to perform loading or preloading operation;

[0021] The algorithm loading module loads the memory fault detection algorithm to be executed.

[0022] The memory access control module executes the loaded memory fault detection algorithm according to the execution parameters in the DAOS data structure.

[0023] In a possible implementation, the memory access control module uses the memory fault detection algorithm to perform multi-channel DDR fault detection on the memory based on the memory interleaver; and / or, closes the memory interleaving function of the DDR channel, and uses the memory fault detection algorithm to perform single-channel DDR fault detection on the memory.

[0024] In a possible implementation, the memory access control module terminates the DDR fault detection task after the algorithm completes the DDR fault detection task.

[0025] In the case where the operating system needs to resume execution, the memory access control module stops executing the current memory detection task and clears the executed instructions in the CPU in response to a reset signal of the CPU.

[0026] In a possible implementation, when the algorithm slots of the memory access control module are sufficient to load all the memory fault detection algorithms to be executed, the algorithm loading module loads all the memory fault detection algorithms to be executed into the algorithm slots at one time.

[0027] When the algorithm slots of the memory access control module are insufficient, the algorithm loading module only loads the first memory fault detection algorithm to be executed; during the execution of the memory fault detection algorithm, the algorithm loading module swaps out the memory fault detection algorithm that will not be used in a short period of time in the algorithm slots, and swaps in the memory fault detection algorithm to be executed.

[0028] In a possible implementation, when the memory fault detection algorithm executed by the memory access control module fails, the memory access control module obtains specific fault memory information through an algorithm return value, and writes the fault memory information into an external persistent storage, so that the operating system can bypass the corresponding fault memory address according to the fault memory information, and avoid the fault memory address from being used by an application program.

[0029] According to an aspect of the present disclosure, a memory fault detection method applied to a system on chip (SoC) is provided, comprising:

[0030] The user interface module receives a user-indicated memory fault detection algorithm, which is stored in external storage of the SoC;

[0031] The algorithm loading module loads the memory fault detection algorithm from the external storage and stores it in an algorithm slot of the memory access control module when the operating system exits, the algorithm slot being located in on-chip static memory of the SoC;

[0032] The memory access control module executes the memory fault detection algorithm to perform memory fault detection on a double data rate (DDR) memory.

[0033] In a possible implementation, the method further includes:

[0034] The chip state detection module detects and manages the working state of the SoC, and disables the memory detection function when the chip is running the operating system; and detects whether the state of the SoC meets the memory fault detection starting condition when the operating system exits, and starts the memory access control module and the algorithm loading module if the detection condition is met.

[0035] In a possible implementation, the method further includes:

[0036] The system takeover module keeps the power-on state of hardware resources for memory fault detection when the operating system exits, and starts the chip state detection module.

[0037] In a possible implementation, the method further includes: the system takeover module restores a chip environment required by the operating system and the system startup loader before the operating system is ready to start.

[0038] In a possible implementation, the method further includes: the user interface module receives a user-defined memory fault detection algorithm and saves it to the external storage; and / or receives an identification of a preset memory fault detection algorithm input by the user and saves a memory fault detection algorithm corresponding to the identification to the external storage.

[0039] In a possible implementation, the method further includes: the user interface module receives an identification of the memory fault detection algorithm indicated by the user and saves it to a direct access object storage (DAOS) data structure; and / or the user interface module receives execution parameters of the memory fault detection algorithm indicated by the user and saves them to the DAOS data structure.

[0040] The execution parameters include any one or more of the following: execution order of the memory fault detection algorithm; number of repeated executions; start address of the memory to be checked; and end address of the memory to be checked.

[0041] In a possible implementation, the method further includes that the algorithm loading module accesses the DAOS data structure in the external storage, determines the key information of the executable algorithm, and sends the key information to the memory access control module.

[0042] The memory access control module determines the memory fault detection algorithm to be executed based on the key information in the received DAOS data structure, and notifies the algorithm loading module to perform the loading or preloading operation.

[0043] The algorithm loading module loads the memory fault detection algorithm to be executed.

[0044] The memory access control module executes the loaded memory fault detection algorithm according to the execution parameters in the DAOS data structure.

[0045] In a possible implementation, the method further includes that the memory access control module performs multi-channel DDR fault detection on the memory by using the memory fault detection algorithm based on the memory interleaver, and / or closes the memory interleaving function of the DDR channel, and performs single-channel DDR fault detection on the memory by using the memory fault detection algorithm.

[0046] In a possible implementation, the method further includes that the memory access control module terminates the DDR fault detection task after the algorithm completes the DDR fault detection task.

[0047] In the case where the operating system needs to resume execution, the memory access control module stops executing the current memory detection task and clears the executed instructions in the CPU in response to a reset signal of the CPU.

[0048] In a possible implementation, the method further includes that, in the case where the algorithm slots of the memory access control module are sufficient to load all the memory fault detection algorithms to be executed, the algorithm loading module loads all the memory fault detection algorithms to be executed into the algorithm slots at one time.

[0049] In the case where the algorithm slots of the memory access control module are insufficient, the algorithm loading module only loads the first memory fault detection algorithm to be executed; and during the execution of the memory fault detection algorithm, the algorithm loading module swaps out the memory fault detection algorithm that will not be used in a short period of time in the algorithm slots, and swaps in the memory fault detection algorithm to be executed.

[0050] In a possible implementation, the method further includes: in a case where the memory access control module fails in executing a memory fault detection algorithm, the memory access control module acquires specific fault memory information through an algorithm return value, and writes the fault memory information into an external persistent storage, so that the operating system bypasses a corresponding fault memory address according to the fault memory information, to avoid the fault memory address from being used by an application program.

[0051] According to an aspect of the present disclosure, an electronic device is provided, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute the above method.

[0052] According to an aspect of the present disclosure, a computer-readable storage medium is provided, which stores computer program instructions, the computer program instructions being executed by a processor to implement the above method.

[0053] In the embodiments of the present disclosure, a user indicates a memory fault detection algorithm through a user interface module, then an algorithm loading module loads the memory fault detection algorithm from the external storage when the operating system exits, and stores the memory fault detection algorithm in an algorithm slot of a memory access control module, and the memory access control module executes the memory fault detection algorithm. Thus, when performing memory fault detection on a DDR memory, the user can specify the memory fault detection algorithm through the user interface module, which is flexible and adaptable, and can meet complex application scenarios of a SoC. In addition, the algorithm slot of the memory access control module is located in an on-chip static memory of the SoC, that is, when executing the memory fault detection algorithm, no DDR memory space is occupied, and comprehensive detection of the DDR memory can be implemented. Moreover, the memory fault detection is performed when the operating system exits, and idle-time detection of the DDR memory is implemented.

[0054] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0055] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the technical solutions of the present disclosure.

[0056] Figure 1 A framework diagram of a system on chip is shown according to an embodiment of the present disclosure.

[0057] Figure 2 A framework diagram of a memory fault detection system is shown according to an embodiment of the present disclosure.

[0058] Figure 3 A block diagram of a memory failure detection system according to an embodiment of the disclosure is shown.

[0059] Figure 4 A block diagram of a memory failure detection method according to an embodiment of the disclosure is shown.

[0060] Figure 5 A block diagram of an electronic device according to an embodiment of the disclosure is shown. DETAILED DESCRIPTION

[0061] Various exemplary embodiments, features and aspects of the disclosure will be explained in detail below with reference to the accompanying drawings. The same reference numerals are used throughout the drawings to refer to functional elements having the same or similar functions. Although various aspects of the embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically noted.

[0062] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0063] The term "and / or" used herein only means a relationship of association, and can mean three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" used herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, and C can mean including any one or more elements selected from a set consisting of A, B, and C.

[0064] In addition, in order to better illustrate the disclosure, numerous specific details are given in the detailed description below. It will be understood by those skilled in the art that the disclosure can be implemented without certain specific details. In some examples, methods, means, elements and circuits well known to those skilled in the art are not described in detail in order to highlight the main idea of the disclosure.

[0065] The existing memory fault detection systems have certain defects and limitations. The original hardware memory detection of the memory controller does not consider the influence of the memory interleaver. The memory interleaver is designed to optimize memory access performance and can map continuous memory addresses to different memory channels to realize parallel access and load balancing. However, such mapping can make it difficult for the hardware memory detection module to simulate and test all possible memory access modes, and its adaptability and flexibility are poor. Moreover, it supports limited algorithms, usually only a few algorithms, which limits the breadth and depth of fault detection. In contrast, the memory detection scheme based on the operating system and the bootloader can usually provide richer and more flexible algorithm selection to cope with different types of memory faults.

[0066] However, the bootloader-based memory detection cannot detect the memory region occupied by itself because the bootloader needs to run in memory. This can cause some memory faults to be missed, thereby reducing the accuracy of detection. Moreover, the bootloader-based memory detection can only be performed at the system startup stage, which means it cannot perform long-term, continuous memory monitoring and testing. Therefore, this scheme may not be able to find memory faults that only occur under certain conditions or after a long time of running.

[0067] The operating system-based memory detection scheme also has the problem of limited detection range. Similar to the bootloader, the operating system also needs to occupy a certain amount of memory space when running, which causes this part of memory to be unable to be detected. In addition, as the operating time of the operating system increases, more memory will be allocated to running processes and applications, thereby further reducing the available detection memory space.

[0068] In the embodiments of the present disclosure, the user interface module receives the memory fault detection algorithm indicated by the user, and then the algorithm loading module loads the memory fault detection algorithm from the external storage when the operating system exits and stores it in the algorithm slot of the memory access control module. The memory access control module executes the memory fault detection algorithm. Thus, when detecting the memory fault of the DDR memory, the user can specify the memory fault detection algorithm through the user interface module, which has strong flexibility and adaptability and can meet the complex application scenarios of the SoC. In addition, the algorithm slot of the memory access control module is located in the on-chip static memory of the SoC, that is, no DDR memory space is occupied when the memory fault detection algorithm is executed, and the comprehensive detection of the DDR memory can be realized. Moreover, the memory fault detection is run when the operating system exits, which realizes the idle-time detection of the DDR memory.

[0069] SoC is an integrated circuit that integrates multiple functional modules on a chip. It not only contains central processing unit, memory, input and output interface and other hardware modules, but also can integrate graphics processor, communication module, sensor and other functions. SoC contains all hardware and software to complete a certain function, which is a small computer system. By integrating multiple functional units, the system is more compact, efficient, and reduces communication overhead between different chips.

[0070] In one example, the SoC to which the present application is applied is as shown in Figure 1 Figure 1 A framework diagram of a system on chip is shown according to an embodiment of the present disclosure. As shown in Figure 1 The SoC contains multiple running cores and a certain capacity of on-chip static memory. The typical capacity of the static memory can be between 128KB and 4096KB. The SoC running core CPU can execute memory write and read instructions, which are reached by the memory interleaver and the on-chip bus to the specific DDR memory channel, and realize the read and write of the DDR memory particles. The typical bit width of each DDR memory channel is between 8 bits and 32 bits, and is connected with one or more DDR memory particles located outside the chip.

[0071] The memory fault detection algorithm can detect and identify potential problems in the DDR memory, and check whether the data in the memory is complete, readable, and whether the memory hardware itself has a fault by performing a series of detection operations such as data verification, address scanning and error identification.

[0072] Figure 2 A framework diagram of a memory fault detection system according to an embodiment of the present disclosure is shown. The system is applied to a system on chip SoC, as shown in Figure 2 The memory fault detection system comprises:

[0073] A user interface module 11 is configured to receive a user-indicated memory fault detection algorithm, wherein the memory fault detection algorithm is stored in an external storage of the SoC;

[0074] An algorithm loading module 12 is configured to load the memory fault detection algorithm from the external storage and store it in an algorithm slot of a memory access control module when an operating system exits, wherein the algorithm slot is located in an on-chip static memory of the SoC;

[0075] The memory access control module 13 is configured to execute the memory fault detection algorithm to perform memory fault detection on a double data rate DDR memory.

[0076] ​The external storage can be a storage device or medium external to the SoC, and is used to store data or programs persistently. The external storage can be a storage device such as a flash memory, a hard disk, etc., which can provide a larger storage space compared with the memory in the SoC, and can facilitate the read and write operations of data.

[0077] The double data rate (DDR) memory is a computer memory technology, and is the memory where the program is located when the computer system is running.

[0078] The user interface module can be located in the operating system, and is used to interact with the user. The user interface module allows the user to interact with the system, and provides a channel for input and output. At any time point during the running of the operating system, the user can interact with the user interface module. The user operations supported by the user interface module can be various, for example, the user can input a custom memory fault detection algorithm, or select a default algorithm, in addition, the user can also input specific algorithm parameters, which can be referred to possible implementation manners provided by the present disclosure, and details are not described herein.

[0079] The user can select or input a memory fault detection algorithm through a user interface (such as a software interface, a command line, etc.), which will be used for subsequent memory fault detection. For example, the user can select the "parity check algorithm" as the memory fault detection algorithm from a drop-down menu in the software interface, or the user can manually input the memory fault detection algorithm through the command line.

[0080] When the operating system exits, the algorithm loading module obtains the memory fault detection algorithm selected by the user from the external storage of the SoC, and loads it into the algorithm slot in the on-chip static memory of the SoC. For example, when the user turns off the computer, the operating system exits, at this time, the algorithm loading module reads the "parity check algorithm" file from the external hard disk, and stores it in the static memory of the SoC.

[0081] It should be noted that the exit of the operating system herein can be the shutdown or hibernation of the operating system, etc., which does not need to use the memory.

[0082] After the algorithm loading is completed, the memory access control module performs a detection operation on the DDR memory according to the loaded memory fault detection algorithm, and checks whether there is a fault or error. In the above example, the memory access control module uses the "parity check algorithm" to check each data block in the DDR memory, marks any data block that fails the check, and stores the result in the error log.

[0083] In the embodiments of the present disclosure, the memory fault detection system is used to realize the function of detecting the fault of the DDR memory on the system on chip (SoC). Thus, when detecting the memory fault of the DDR memory, the user can specify the memory fault detection algorithm through the user interface module, which has high flexibility and adaptability and can meet the complex application scenarios of the SoC. In addition, the algorithm slot of the memory access control module is located in the on-chip static memory of the SoC, that is, when executing the memory fault detection algorithm, the DDR memory space is not occupied, and the comprehensive detection of the DDR memory can be realized. Moreover, the memory fault detection is performed when the operating system exits, and the idle-time detection of the DDR memory is realized.

[0084] In a possible implementation, the system further includes a chip state detection module configured to detect and manage the working state of the SoC, disable the memory detection function when the chip is running the operating system, detect whether the SoC state meets the memory fault detection starting condition when the operating system exits, and start the memory access control module and the algorithm loading module when the detection condition is met.

[0085] The chip state detection module is responsible for monitoring and managing the working state of the SoC, and ensuring that the chip can perform corresponding operations in different working stages. After the SoC is powered on, the firmware in the SoC can load the chip state detection module. The module can reside in the on-chip static memory and occupy no more than one fourth of the total capacity of the static memory. By default, the module will not be executed during the chip startup process. After the chip state detection module is loaded, the SoC will continue to perform the normal startup process and enter the operating system.

[0086] The chip state detection module can monitor whether the SoC is running the operating system, in the idle state, or has exited the operating system in real time. When the operating system is running, various hardware resources on the SoC are usually managed by the operating system and perform corresponding tasks, and thus the memory fault detection is not performed to avoid interfering with the normal operation of the operating system.

[0087] When the operating system exits, the chip state detection module detects whether the SoC state meets the memory fault detection starting condition, and starts the memory access control module and the algorithm loading module when the detection starting condition is met. For example, the chip state detection module detects whether the register configuration of the DDR memory channel and the DDR memory particle meets the requirement, and detects whether the on-chip bus system and the memory interleaver work normally. When it is determined that the register configuration of all DDR memory channels and DDR memory particles meets the requirement and the on-chip bus system and the memory interleaver work normally, the memory access control module and the algorithm loading module are started.

[0088] In the embodiments of the present disclosure, the memory fault detection function can be disabled when the operating system is running, so as to avoid interfering with the normal operation of the system. Meanwhile, when the operating system exits and the SoC state meets the detection condition, the memory access control module and the algorithm loading module can be automatically started to comprehensively and accurately detect the faults of the DDR memory. This mechanism not only improves the stability of the system, but also ensures the effectiveness and safety of the memory fault detection.

[0089] In a possible implementation, the system further includes a system takeover module configured to, when the operating system exits, maintain the power-on state of the hardware resources for memory fault detection, and start the chip state detection module.

[0090] In a possible implementation, the system takeover module, before the operating system is ready to start, restores the chip environment required by the operating system and the system startup loader.

[0091] The system takeover module is configured to, when the operating system exits or shuts down, ensure that the hardware resources for memory fault detection remain in the power-on state, and restore the necessary chip environment before the operating system is ready to restart.

[0092] The hardware resources for memory fault detection may be, for example, DDR channels, CPU cores, on-chip static memories, on-chip buses, and part of peripherals (such as external storage). When the operating system exits, the system takeover module maintains the power-on state of the DDR channels, CPU cores, on-chip static memories, on-chip buses, and part of peripherals, so that these hardware resources will not be completely powered off due to the exit of the operating system, thereby ensuring that these resources can quickly recover to the working state in the subsequent memory fault detection process.

[0093] In addition, although the system takeover module maintains the power-on state of part of the hardware resources, appropriate measures are also taken to reduce the power consumption of the system to prolong the life of the device and the battery life, which is particularly important in mobile devices or embedded systems.

[0094] Specifically, when starting the chip state detection module, the system takeover module can load the entry address of the chip state detection module into the return address register of the CPU, and execute a privileged instruction to exit the operating system and return to the CPU. Since the return address register stores the entry address of the chip state detection module, the CPU will start executing the chip state detection module.

[0095] Before the operating system is ready to restart, the system takeover module is responsible for restoring the chip environment required for running the operating system and the system bootloader. For example, initializing necessary hardware resources, configuring memory and bus, etc., to ensure that the operating system can be successfully started and normally run.

[0096] In addition, the system takeover module also interacts with the chip state detection module to provide the state information of the current operating system. So that the chip state detection module can determine when to start the memory fault detection function.

[0097] In the embodiments of the present disclosure, through the system takeover module, the power-on state of the key hardware resources can be maintained when the operating system exits or shuts down, so that these resources can quickly recover to the working state in the subsequent memory fault detection process. Before the operating system is ready to restart, the system takeover module restores the necessary chip environment to ensure the smooth start and operation of the operating system, thereby improving the stability and reliability of the system.

[0098] In a possible implementation, the user interface module is configured to receive a user-defined memory fault detection algorithm and save it to the external storage; and / or receive a user inputted identification of a preset memory fault detection algorithm and save the memory fault detection algorithm corresponding to the identification to the external storage.

[0099] The user interface module can receive the algorithm inputted by the user and save it to the external storage, and the user can specify the algorithm to be used for memory fault detection in the future.

[0100] When the user inputs the memory fault detection algorithm, the user can customize the memory fault detection algorithm, that is, the user can write the memory fault detection algorithm by himself / herself, and then compile the algorithm into corresponding assembly code, and input the user interface module through a command line tool or a web tool.

[0101] The user-defined memory fault detection algorithm can meet the following specifications, and the user needs to follow the specific algorithm specifications:

[0102] The algorithm includes three input parameters: the start address A1 of the memory to be checked, the end address A2, and a user-defined parameter set;

[0103] The output of the algorithm should be a list of integer numbers, which is used to represent the detection result. If no memory fault is detected, 0 value is output, otherwise, the list of memory addresses with faults is output;

[0104] During the execution of the algorithm, it can only access the memory addresses between A1 and A2, and cannot access other addresses.

[0105] To ensure that the algorithm provided by the user is compliant and will not cause unexpected behavior or errors during system execution, the user interface module will validate the algorithm. During validation, the user interface module will provide an unused memory region as a test environment for the algorithm. The algorithm is executed in this memory region and its behavior is monitored in real time. If the algorithm attempts to access addresses outside the specified address range, validation fails and the user is notified to modify the algorithm to be compliant.

[0106] For algorithms that pass validation, the algorithm can be packaged for easy loading and execution during subsequent memory fault detection processes. During packaging, the algorithm code, metadata, and other necessary information can be combined into a file or data package.

[0107] The packaged algorithm is then saved to a specific location in external storage. This specific location is a simple and directly indexable location so that the memory access control module and the algorithm loading module can quickly find and load the algorithm. At the same time, this location should also be secure to prevent unauthorized access and modification.

[0108] In addition, the user interface module also supports the use of preset algorithms. Preset algorithms are standard or commonly used memory fault detection algorithms provided by the system or third parties, and users can select and use them through simple commands or numbers. For example, users can select preset algorithms through command lines or web tools, and the user interface module will load the corresponding preset algorithms to the appropriate storage location for subsequent use according to the user's selection.

[0109] In one possible implementation, the user interface module is configured to receive an identification of the memory fault detection algorithm indicated by the user and save the identification to a Direct Access Object Storage (DAOS) data structure; and / or the user interface module is configured to receive an execution parameter of the memory fault detection algorithm indicated by the user and save the execution parameter to the DAOS data structure; the execution parameter includes: an execution order of the memory fault detection algorithm; a number of repeated executions; a starting address of the memory to be checked; and an ending address of the memory to be checked.

[0110] In the external persistent storage, multiple algorithms can be saved, including user-defined algorithms and preset algorithms. The user can select which algorithms should be loaded and executed through the user interface module. The basis for selection can be the performance, accuracy, and applicable scenarios of the algorithm, and the present disclosure does not make specific limitations. The user can specify the algorithm by inputting the identification of the memory fault detection algorithm, and the user interface module receives the identification and saves it to the Direct Access Object Storage (Detect Algorithms Order and Sequence, DAOS) data structure.

[0111] The user can also input specific parameters required by the selected algorithm, and additionally, the user can specify additional parameters for each algorithm. The user interface module receives these parameters and saves them to the DetectAlgorithms Order and Sequence (DAOS) data structure for the algorithm loading module to identify and load the algorithms.

[0112] The user can also specify the running order between multiple algorithms to build a complex detection process composed of multiple algorithms to meet specific needs or scenarios. The user interface module uses the DAOS data structure to save and manage this order information. The DAOS data structure is a data structure specially designed to describe the algorithm order and dependency relationship, which enables the memory access control module and the algorithm loading module to easily identify and execute the user-specified algorithm process.

[0113] In the embodiments of the present disclosure, through the implementation of the user interface module, the memory fault detection system provides a flexible and easy-to-use interface for users, enabling users to easily define, manage, select, and use memory fault detection algorithms. At the same time, through functions such as specification verification, packaging storage, and parameter management, the correctness and compliance of the algorithms are ensured, and the accuracy and reliability of memory fault detection are improved. Different needs of different users are met, and the flexibility and adaptability of the memory fault detection system are improved.

[0114] In a possible implementation, the algorithm loading module accesses the DAOS data structure in the external storage, determines the key information of the executable algorithm, and sends it to the memory access control module; the memory access control module determines the memory fault detection algorithm to be executed based on the key information in the received DAOS data structure, and notifies the algorithm loading module to perform loading or preloading operations; the algorithm loading module loads the memory fault detection algorithm to be executed; and the memory access control module executes the loaded memory fault detection algorithm according to the execution parameters in the DAOS data structure.

[0115] The algorithm loading module is used to read algorithms and related management information from external storage to provide the required algorithm resources for the memory access control module. Specifically, the algorithm loading module accesses the DAOS data structure in the external storage, which contains the key information of all available algorithms, such as the unique identifier of the algorithm, the storage location of the algorithm, the dependency relationship of the algorithm, the execution order, etc. The algorithm loading module can extract the key information of the algorithm and send the key information to the memory access control module, so that the memory access control module can determine the algorithm to be executed based on the key information.

[0116] The memory access control module receives the key information in the DAOS data structure from the algorithm loading module, and then determines the memory fault detection algorithm to be executed based on the received key information, and notifies the algorithm loading module to perform loading or preloading operation. Through preloading, the system performance can be optimized to ensure that the algorithm is ready in the memory when it is really needed to execute.

[0117] If the algorithm slots of the memory access control module are sufficient to load all the algorithms that need to be executed, the algorithm loading module will load them all at once. If the algorithm slots are insufficient, the algorithm loading module will only load the first one to be executed, and then use a replacement strategy to replace the algorithm in the algorithm slot that will not be used in the short term, and replace it with the algorithm that will be executed soon.

[0118] After the algorithm loading module completes the loading or preloading, the memory access control module will execute the loaded memory fault detection algorithm according to the execution parameters in the DAOS data structure.

[0119] When a new memory fault detection algorithm needs to be executed, the memory access control module will select the appropriate algorithm based on the information in the DAOS data structure, and notify the algorithm loading module to load the algorithm. During execution, if it needs to switch to another algorithm or execute a combination of multiple algorithms, the memory access control module will schedule the execution of the algorithm based on the algorithm dependency relationship in the DAOS data structure and the user-specified order.

[0120] In the embodiments of the present disclosure, through the cooperative work of the algorithm loading module and the memory access control module, the memory fault detection system can flexibly load, execute and schedule the memory fault detection algorithm. The DAOS data structure provides the key information and decision basis for the two modules, ensuring the correct execution of the algorithm and the efficient operation of the system. In addition, the DAOS data structure is simple and directly indexable, so that the memory access control module and the algorithm loading module can quickly find and load the algorithm, improving the memory fault detection efficiency.

[0121] In a possible implementation manner, the memory access control module performs multi-channel DDR fault detection on the memory by using the memory fault detection algorithm based on the memory interleaver; and / or, closes the memory interleaving function of the DDR channel, and performs single-channel DDR fault detection on the memory by using the memory fault detection algorithm.

[0122] Through the cooperation with the memory interleaver, the memory access control module can implement the multi-channel and single-channel fault detection of the DDR memory. The memory interleaver is used for managing the data distribution and access among the plurality of DDR channels, and can disperse the data to different DDR channels to improve the parallelism and bandwidth of the memory access. Meanwhile, the interleaver is also responsible for ensuring the correct synchronization and consistency of the data among different channels.

[0123] In the case that the memory access control module enables the multi-channel fault detection of the DDR, the memory interleaver disperses the data to the plurality of DDR channels to ensure that each channel has data to access, and the memory access control module simultaneously sends access requests to the plurality of DDR channels to read or write data in a parallel manner.

[0124] In the parallel access process, the memory access control module uses the memory fault detection algorithm to check and detect the data of each channel. Although the presence of the memory interleaver makes the memory access physically dispersed, logically, the memory addresses of all the DDR channels can still be represented continuously. This means that at the software level, the memory access is still continuous, and only the physical access at the actual hardware level becomes dispersed. Therefore, the memory fault detection algorithm can perform parallel detection on the DDR memory based on the logically continuous representation of the memory addresses, and can be less affected by the memory interleaver compared with the original hardware memory detection of the memory controller, and has better adaptability.

[0125] In some cases, it can be necessary to perform fault detection on a single DDR channel. At this time, the memory access control module can close the memory interleaving function of the DDR channel, and perform the read or write operation of the data on the single DDR channel to be detected to check and detect the DDR memory of the channel.

[0126] In the embodiments of the present disclosure, by combining the memory interleaver and the memory access control module, the multi-channel and single-channel DDR fault detection can be flexibly performed.

[0127] In a possible implementation, the memory access control module terminates the DDR fault detection task after the algorithm completes the DDR fault detection task; in the case that the operating system needs to resume execution, the memory access control module stops executing the current memory detection task in response to a reset signal of the CPU, and clears the instructions executed in the CPU.

[0128] In the memory fault detection process, when the memory access control module completes the DDR fault detection task, it is judged that the DDR fault detection is normally completed. At this time, the memory access control module can actively terminate the DDR fault detection task and no longer execute any instructions related to the memory detection.

[0129] The strategy of the DDR fault detection task can be various. In an example, the detection strategy can be single detection, that is, the algorithms selected by the user are executed once in the specified order. In an example, the detection strategy can be multiple detection, that is, the algorithms selected by the user are executed multiple times in the specified order, and the specific number of times can be specified by the user. In an example, the detection strategy can be unlimited detection, that is, the algorithms selected by the user are repeatedly executed in the specified order, and the number of repetitions has no upper limit.

[0130] When the DDR fault detection task is actively terminated, the DDR fault detection algorithm execution in the memory access control module is terminated, and all resources related to the DDR fault detection are closed. In addition, a shutdown signal can be sent to the on-chip power management system. After the on-chip power management system receives the shutdown signal, the power-off operation is started, and each power domain on the chip is gradually turned off, and finally the chip is completely shut down.

[0131] In addition, the DDR fault detection task also has a pre-emptive exit. Specifically, in some cases, the operating system may need to resume execution immediately, for example, the user requests an operation that needs to enter the operating system. When the operating system needs to resume execution, the external hardware will send a reset signal to the CPU. This reset signal will cause the CPU to stop the current execution. At this time, the firmware will execute according to the default path, load the Bootloader and the operating system. During the reset process, the instructions being executed in the CPU are automatically cleared, and the DDR-related registers are reinitialized, ensuring that the memory detection task is completely terminated.

[0132] At this time, the memory access control module needs to respond to the reset signal of the CPU, stop the current DDR fault detection task, and clear the instructions currently executing in the CPU to ensure that the state of the CPU is clean.

[0133] In the embodiments of the present disclosure, the memory access control module can normally exit after completing the DDR fault detection task, or pre-emptively exit when the operating system needs to resume execution. This flexible exit mechanism ensures the reliability of memory detection and the stability of the operating system.

[0134] In a possible implementation, when the algorithm slots of the memory access control module are sufficient to load all the memory fault detection algorithms that need to be executed, the algorithm loading module loads all the memory fault detection algorithms that need to be executed into the algorithm slots at one time; when the algorithm slots of the memory access control module are insufficient, the algorithm loading module only loads the first memory fault detection algorithm that needs to be executed; during the execution of the memory fault detection algorithm, the algorithm loading module swaps out the memory fault detection algorithm that will not be used in the short term in the algorithm slots, and swaps in the memory fault detection algorithm that will be executed soon.

[0135] In this implementation, the algorithm loading module loads the memory fault detection algorithms according to the number and state of the algorithm slots of the memory access control module. Specifically, when the algorithm slots of the memory access control module are sufficient to load all the memory fault detection algorithms that need to be executed, the algorithm loading module loads all the memory fault detection algorithms that need to be executed into the algorithm slots at one time. In this way, it can be ensured that all the algorithms can be quickly called during the memory fault detection process, improving the detection efficiency.

[0136] However, in some cases, the algorithm slots of the memory access control module may not be sufficient to load all the memory fault detection algorithms that need to be executed at the same time. In this case, the algorithm loading module can only load the memory fault detection algorithms that need to be executed first. As the memory fault detection process proceeds, the algorithm loading module can dynamically manage the algorithms in the algorithm slots. Specifically, the algorithm loading module can swap out the memory fault detection algorithms that will not be used in the short term in the algorithm slots, and swap in the memory fault detection algorithms that will be executed soon. This dynamic management strategy can effectively utilize the limited algorithm slot resources, ensuring the continuity and efficiency of the memory fault detection process.

[0137] For example, assume that the memory access control module has 3 algorithm slots, and there are 5 memory fault detection algorithms that need to be executed. At the beginning of the detection, the algorithm loading module will first load the first 3 algorithms into the algorithm slots. When the first algorithm is executed, the algorithm loading module will load the fourth algorithm into the algorithm slots, while swapping out the first algorithm that has been executed. In this way, even if the number of algorithm slots is limited, it can be ensured that all the algorithms that need to be executed can be loaded and executed in turn.

[0138] In the embodiments of the present disclosure, by dynamically managing the algorithm slots of the memory access control module through the algorithm loading module, the limited algorithm slot resources can be effectively utilized, and the continuity and efficiency of the memory fault detection process can be ensured. When the algorithm slots are sufficient, loading all the algorithms at one time can reduce the time overhead of algorithm switching and improve the detection efficiency; when the algorithm slots are insufficient, the dynamic replacement strategy can ensure that the algorithm slots always load the algorithms that will be executed soon, avoiding detection interruption due to insufficient algorithm slots. This flexible algorithm loading and management mechanism enables the memory fault detection system to efficiently complete the memory fault detection task under different hardware resource conditions, improving the adaptability and reliability of the system.

[0139] In a possible implementation, in a case where the memory access control module fails in executing the memory fault detection algorithm, the memory access control module obtains specific fault memory information through an algorithm return value, and writes the fault memory information into an external persistent storage, so that the operating system bypasses a corresponding fault memory address according to the fault memory information, to avoid the fault memory address being used by an application program.

[0140] When executing the memory fault detection algorithm, the memory access control module monitors the execution result of the algorithm in real time. If a certain memory fault detection algorithm fails in execution, the memory access control module can obtain specific fault memory information through an algorithm return value. The fault memory information can include a fault memory address, a fault type (such as a bit flip, a short circuit, or an open circuit fault), and other related diagnostic information.

[0141] After obtaining the fault memory information, the memory access control module can write the information into an external persistent storage. The external persistent storage can be a storage device or medium outside the SoC, such as a flash memory, a hard disk, and the like. The external persistent storage is a non-volatile storage medium, and can ensure that the fault memory information can be retained after system restart or shutdown.

[0142] By writing the fault memory information into the external persistent storage, the operating system can read the information at startup, and bypass a corresponding fault memory address according to the fault memory information. In this way, the application program can be prevented from using the fault memory address, thereby preventing problems such as program crashes, data loss, or system performance degradation caused by memory faults. For example, the operating system can set a memory region that is prohibited from being accessed in a memory management unit (MMU), or skip the fault memory address when allocating memory.

[0143] In the embodiments of the present disclosure, by obtaining and recording the fault memory information when the memory fault detection algorithm fails, the memory access control module can effectively identify and mark the fault memory address. Writing the fault memory information into the external persistent storage ensures that the information can be retained after system restart or shutdown, thereby providing an important reference for memory management of the operating system. The operating system can bypass a corresponding fault memory address according to the fault memory information, to avoid the fault memory address being used by an application program, thereby improving the stability and reliability of the system, effectively preventing the influence of memory faults on system operation, and enhancing the fault tolerance of the system to memory faults.

[0144] An application scenario of the embodiments of the present disclosure is described below. Figure 3 A structure diagram of a memory fault detection system provided by the present disclosure is shown. As shown in FIG. 1, the memory fault detection system includes a memory access control module 100 and an operating system 200. Figure 3As shown, in this application scenario, the memory fault detection system includes a memory access control module, an algorithm loading module, a user interface module, a chip state detection module, and a system takeover module.

[0145] The memory access control module is used to execute memory fault detection algorithms. It is equipped with at least one algorithm slot for storing the memory detection algorithm to be executed. When there are multiple algorithms to be executed, they can be executed according to the user-defined execution order.

[0146] The algorithm loading module is used to load specific memory detection algorithms from external persistent storage and place them in the algorithm slot of the memory access control module, so that when the memory detection task needs to be executed, the corresponding algorithm is ready.

[0147] The user interface module is used to receive user input information. For example, the user can customize the memory detection algorithm through the user interface module and save it to the external persistent storage; in addition, the user can also specify the execution order and the number of repetitions of the algorithm to meet the detection needs in different scenarios. This module is usually integrated into the operating system to provide a convenient operation interface for the user.

[0148] The chip state detection module is used to monitor and manage the working state of the system-level chip. When the chip is running the operating system or business application, the module will disable the memory detection function to ensure that the normal operation of the system is not disturbed. When the operating system enters the sleep or exit state, the module will start the memory access control module and the algorithm loading module to execute the memory detection task.

[0149] The system takeover module is used to prompt the chip state detection module of the current operating system state and ensure that the entire chip does not completely power off after the operating system exits. This module will keep the power-on state of the DDR channel, CPU core, on-chip static memory, on-chip bus and part of the peripherals, while reducing the power consumption of the system. When the operating system is ready to start, the system takeover module will be responsible for restoring the chip environment to ensure that the operating system and Bootloader can be loaded and run smoothly.

[0150] These five modules work together at different software levels to achieve the goal of memory detection and control system. Through cooperative work, it ensures that the system will not be disturbed by the memory detection task when it is running normally, and when the operating system is in sleep or exit state, it can efficiently perform memory detection to ensure the stability and reliability of the system. This modular design makes the system more flexible and extensible, and can adapt to different scenarios of memory detection needs.

[0151] In a possible implementation, the memory fault detection system can be implemented by electronic devices such as terminal devices and servers. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, or the like. The system can be implemented by a processor invoking computer-readable instructions stored in a memory.

[0152] In addition, the disclosure also provides a memory fault detection method, an electronic device, a computer-readable storage medium, and a program, which can be used to implement any of the memory fault detection systems provided by the disclosure. For details, refer to the corresponding description in the method part and the corresponding description in the method part, which will not be described here.

[0153] According to an aspect of the disclosure, a memory fault detection method is provided, applied to a system on chip (SoC), Figure 4 A block diagram of the memory fault detection method according to an embodiment of the disclosure is shown as follows, Figure 4 As shown, the method comprises:

[0154] In step S21, a user interface module receives a user-indicated memory fault detection algorithm, which is stored in an external storage of the SoC;

[0155] In step S22, an algorithm loading module loads the memory fault detection algorithm from the external storage when an operating system exits, and stores the memory fault detection algorithm in an algorithm slot of a memory access control module, which is located in an on-chip static memory of the SoC;

[0156] In step S23, the memory access control module executes the memory fault detection algorithm to perform memory fault detection on a double data rate (DDR) memory.

[0157] In a possible implementation, the method further comprises:

[0158] A chip state detection module detects and manages the working state of the SoC. When the chip is running an operating system, the memory detection function is disabled. When the operating system exits, the chip state detection module detects whether the state of the SoC meets the memory fault detection starting condition, and starts the memory access control module and the algorithm loading module if the detection condition is met.

[0159] In a possible implementation, the method further comprises:

[0160] A system takeover module retains the power-on state of the hardware resources for memory fault detection when the operating system exits, and starts the chip state detection module.

[0161] In a possible implementation, the method further includes: the system takeover module restoring a chip environment required by the operating system and the system startup loader before the operating system is ready to start.

[0162] In a possible implementation, the method further includes: the user interface module receiving a memory fault detection algorithm customized by a user and saving the memory fault detection algorithm to the external storage; and / or, receiving an identification of a preset memory fault detection algorithm input by the user and saving the memory fault detection algorithm corresponding to the identification to the external storage.

[0163] In a possible implementation, the method further includes: the user interface module receiving an identification of the memory fault detection algorithm indicated by the user and saving the identification to a direct access object storage (DAOS) data structure; and / or, the user interface module receiving an execution parameter of the memory fault detection algorithm indicated by the user and saving the execution parameter to the DAOS data structure.

[0164] The execution parameter includes any one or more of the following: an execution order of the memory fault detection algorithm; a number of times of repeated execution; a start address of memory to be checked; and an end address of memory to be checked.

[0165] In a possible implementation, the method further includes: the algorithm loading module accessing the DAOS data structure in the external storage, determining key information of an executable algorithm, and sending the key information to the memory access control module.

[0166] The memory access control module determines a memory fault detection algorithm to be executed based on the key information in the received DAOS data structure, and notifies the algorithm loading module to perform a loading or preloading operation.

[0167] The algorithm loading module loads the memory fault detection algorithm to be executed.

[0168] The memory access control module executes the loaded memory fault detection algorithm according to the execution parameter in the DAOS data structure.

[0169] In a possible implementation, the method further includes: the memory access control module performing, based on a memory interleaver, multi-channel DDR fault detection on the memory by using the memory fault detection algorithm; and / or, closing a memory interleaving function of a DDR channel and performing single-channel DDR fault detection on the memory by using the memory fault detection algorithm.

[0170] In a possible implementation, the method further includes: the memory access control module terminating the DDR fault detection task after the algorithm completes the DDR fault detection task.

[0171] In the case that the operating system needs to resume execution, the memory access control module stops executing the current memory detection task and clears the instructions executed in the CPU in response to a reset signal of the CPU.

[0172] In a possible implementation, the method further includes: in the case that the algorithm slots of the memory access control module are sufficient to load all the memory fault detection algorithms that need to be executed, the algorithm loading module loads all the memory fault detection algorithms that need to be executed into the algorithm slots at one time.

[0173] In the case that the algorithm slots of the memory access control module are insufficient, the algorithm loading module only loads the first memory fault detection algorithm that needs to be executed; during the execution of the memory fault detection algorithm, the algorithm loading module swaps out the memory fault detection algorithm that will not be used in a short period of time in the algorithm slots and swaps in the memory fault detection algorithm that will be executed soon.

[0174] In a possible implementation, the method further includes: in the case that the memory fault detection algorithm executed by the memory access control module fails, the memory access control module acquires specific fault memory information through an algorithm return value and writes the fault memory information into an external persistent storage, so that the operating system bypasses the corresponding fault memory address according to the fault memory information to avoid the fault memory address being used by an application program.

[0175] The method has specific technical association with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware operation efficiency or execution effect (including reducing data storage amount, reducing data transmission amount, improving hardware processing speed, etc.), so as to obtain the technical effect of improving the internal performance of the computer system in line with the natural law.

[0176] The embodiment of the disclosure further proposes a computer readable storage medium having computer program instructions stored thereon, the computer program instructions being executed by a processor to implement the above method. The computer readable storage medium can be a volatile or non-volatile computer readable storage medium.

[0177] The embodiment of the disclosure further proposes an electronic device, including: a processor; a memory for storing processor executable instructions; wherein the processor is configured to invoke the instructions stored by the memory to execute the above method.

[0178] The embodiments of the present disclosure further provide a computer program product, comprising computer readable code or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code is executed in a processor of an electronic device, the processor in the electronic device performs the above method.

[0179] The electronic device can be provided as a terminal, a server or other forms of devices.

[0180] Figure 5 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. For example, the electronic device 1900 can be provided as a server or a terminal device. Referring to Figure 5 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932, for storing instructions executable by the processing component 1922, such as an application program. The application program stored in the memory 1932 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above method.

[0181] The electronic device 1900 can also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 can operate based on an operating system stored in the memory 1932, such as Microsoft Windows Server TM , Apple's graphical user interface-based operating system (Mac OSX TM ), multi-user multi-process computer operating system (Unix TM ), free and open source Unix-like operating system (Linux TM ), open source Unix-like operating system (FreeBSD TM ) or the like.

[0182] In an exemplary embodiment, a non-volatile computer readable storage medium, such as the memory 1932 including computer program instructions executable by the processing component 1922 of the electronic device 1900 to complete the above method, is also provided.

[0183] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0184] Computer readable storage media can be tangible storage media which can retain and store instructions for use by an instruction execution device. Computer readable storage media can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0185] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0186] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0187] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0188] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other data storage device. When the computer readable program instructions are loaded into the computer and other programmable data processing apparatus, a series of operational steps are implemented that provide processes such that the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0189] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0190] The flow diagrams and the block diagrams in the drawings are presented to illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical functions ("instructions"). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0191] The computer program product can be embodied by a hardware, software or a combination thereof. In an optional embodiment, the computer program product is embodied by a computer storage medium. In another optional embodiment, the computer program product is embodied by a software product, such as a software development kit (SDK) or the like.

[0192] The above description of the various embodiments is intended to be illustrative in all aspects, rather than being restrictive. The same or similar features and / or functions can be used in other embodiments, and the description of the various embodiments is intended to be illustrative in all aspects, rather than being restrictive.

[0193] Those skilled in the art can understand that the sequence numbers of the above-described method steps in the specific embodiments do not mean strict execution sequence and do not constitute any limitation to the implementation process. The specific execution sequence of the steps should be determined according to the functions and possible inherent logical relationship of the steps.

[0194] If the technical solutions of the present application involve personal information, the product applying the technical solutions of the present application has been explicitly informed of the personal information processing rules before processing the personal information, and has obtained the personal independent consent. If the technical solutions of the present application involve sensitive personal information, the product applying the technical solutions of the present application has obtained the personal independent consent before processing the sensitive personal information, and at the same time meets the requirement of "explicit consent". For example, at the personal information collection device such as camera, a clear and prominent mark is set to inform that it has entered the personal information collection range and will collect personal information. If the individual voluntarily enters the collection range, it is considered to agree to collect personal information. Or on the device for processing personal information, through the pop-up information or by asking the individual to upload his personal information, the individual's authorization is obtained under the condition that the device uses obvious mark / information to inform the individual of the personal information processing rules. The personal information processing rules can include personal information processor, personal information processing purpose, processing method and personal information type, etc.

[0195] The above has described various embodiments of the present disclosure, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles, practical application or improvement of technology in the market of the embodiments, or to enable other ordinary skilled in the art to understand the embodiments disclosed herein.

Claims

1. A memory fault detection system, characterized in that, Applications in System-on-Chip (SoC) include: The user interface module is used to receive a memory fault detection algorithm indicated by the user, and the memory fault detection algorithm is stored in the external storage of the SoC. An algorithm loading module is used to load the memory fault detection algorithm from the external storage when the operating system exits, and store it in the algorithm slot of the memory access control module, wherein the algorithm slot is located in the on-chip static memory of the SoC. The memory access control module is used to execute the memory fault detection algorithm to detect memory faults in double data rate (DDR) memory.

2. The system according to claim 1, characterized in that, The system also includes: The chip status detection module is used to detect and manage the working status of the SoC. When the chip is running an operating system, the memory detection function is disabled. When the operating system exits, the module detects whether the SoC status meets the memory fault detection start conditions, and if the detection conditions are met, the memory access control module and the algorithm loading module are started.

3. The system according to claim 1, characterized in that, The system also includes: The system takeover module is used to retain the power-on state of the hardware resources used for memory fault detection when the operating system exits, and to start the chip status detection module.

4. The system according to claim 3, characterized in that, The system takeover module restores the chip environment required to run the operating system and system bootloader before the operating system is ready to start.

5. The system according to claim 1, characterized in that, The user interface module is used to receive user-defined memory fault detection algorithms and save them to the external storage; and / or to receive user-inputted identifiers of preset memory fault detection algorithms and save the memory fault detection algorithms corresponding to the identifiers to the external storage.

6. The system according to claim 1, characterized in that, The user interface module is configured to receive the identifier of the memory fault detection algorithm indicated by the user and save it to the Direct Access Object Memory (DAOS) data structure; and / or, The user interface module is used to receive the execution parameters of the memory fault detection algorithm indicated by the user and save them to the Direct Access Object Memory (DAOS) data structure. The execution parameters include any one or more of the following: the execution order of the memory fault detection algorithm; The number of times it is repeated; The starting address of the memory to be checked; The memory termination address to be checked.

7. The system according to claim 1, characterized in that, The algorithm loading module accesses the DAOS data structure in external storage, determines the key information of the executable algorithm, and sends it to the memory access control module. The memory access control module determines the memory fault detection algorithm to be executed based on the key information in the received DAOS data structure, and notifies the algorithm loading module to perform loading or preloading operations. The algorithm loading module loads the memory fault detection algorithm to be executed; The memory access control module executes the loaded memory fault detection algorithm according to the execution parameters in the DAOS data structure.

8. The system according to claim 1, characterized in that, The memory access control module, based on the memory interleaver, uses the memory fault detection algorithm to perform multi-channel DDR fault detection on the memory; and / or, disables the memory interleaver function of the DDR channel and uses the memory fault detection algorithm to perform single-channel DDR fault detection on the memory.

9. The system according to claim 1, characterized in that, The memory access control module terminates the DDR fault detection task after the algorithm has completed the DDR fault detection task. If the operating system needs to resume execution, the memory access control module responds to the CPU's reset signal, stops executing the current memory detection task, and clears the instructions being executed in the CPU.

10. The system according to claim 1, characterized in that: If the algorithm slots of the memory access control module are sufficient to load all memory fault detection algorithms that need to be executed, the algorithm loading module loads all memory fault detection algorithms that need to be executed into the algorithm slots at once. If the memory access control module has insufficient algorithm slots, the algorithm loading module will only load the memory fault detection algorithm that needs to be executed first. During the execution of the memory fault detection algorithm, the algorithm loading module will swap out the memory fault detection algorithm that will not be used in the short term from the algorithm slot and replace it with the memory fault detection algorithm that is about to be executed.

11. The system according to claim 1, characterized in that, If the memory fault detection algorithm executed by the memory access control module fails, the memory access control module obtains the specific fault memory information through the algorithm return value and writes the fault memory information into external persistent storage so that the operating system can bypass the corresponding fault memory address based on the fault memory information and prevent the fault memory address from being used by the application.

12. A memory fault detection method, characterized in that, Applications in System-on-Chip (SoC) include: The user interface module receives a memory fault detection algorithm specified by the user, and the memory fault detection algorithm is stored in the external storage of the SoC. When the operating system exits, the algorithm loading module loads the memory fault detection algorithm from the external storage and stores it in the algorithm slot of the memory access control module, which is located in the on-chip static memory of the SoC. The memory access control module executes the memory fault detection algorithm to detect memory faults in Double Data Rate (DDR) memory.

13. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to implement the method of claim 12.

14. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method of claim 12.

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