Table look-up method based on RISC-V architecture, electronic equipment, readable medium and program product

Abstract

The invention provides a table look-up method based on an RISC-V architecture, and the method comprises the steps: receiving a virtual address sent by a processor, and looking up a secondary conversion bypass buffer L2TLB; under the condition that a leaf page table corresponding to the virtual address is hit in the L2TLB, a target physical address corresponding to the virtual address and access protection information and safety information of the target physical address are returned to the first-level conversion bypass buffer L1TLB, and the access protection information and the safety information of the target physical address are stored in the L2TLB. The invention further provides electronic equipment, a readable medium and a program product.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, in particular to a table lookup method based on RISC-V architecture, electronic device, readable medium and program product. BACKGROUND

[0002] The security of the fifth generation reduced instruction set (Reduced Instruction Set Compute-five, RISC-V) is implemented based on the CoVE framework, and the essence is to protect the security components through isolation. The CoVE architecture supports a trusted execution security manager (TSM) through an instruction set architecture (ISA) and non-ISA extension, and provides time and space isolation for security applications to avoid being accessed by a host operating system (HostOS) or a hypervisor.

[0003] In the CoVE framework, the access protection extension of the supervisor domain is programmed by the root domain security manager (RDSM) in the M mode for the operation of the supervisor domain. The machine-level memory protection table (SMMPT) module enables the RDSM to program the permission of the physical addressable memory (or device mapping area) for the addressable remote sensor high-speed channel (Hart) or device running in the supervisor domain, that is, the RDSM limits and manages the access of the memory protection table (MPT). Any physical addressable area access occurring in the supervisor domain context needs to accept access check. Therefore, in the security mode, the RDSM not only converts the virtual address, but also needs to check the security access permission of the physical address. However, at present, the page table query is too frequent, which reduces the working efficiency of memory management. SUMMARY

[0004] The present disclosure provides a table lookup method based on RISC-V architecture, electronic device, readable medium and program product.

[0005] In a first aspect, the present disclosure provides a table lookup method based on RISC-V architecture, comprising:

[0006] The receiving processor sends a virtual address, and the L2TLB is searched;

[0007] In a case where the virtual address corresponds to a leaf page table in the L2TLB, a target physical address corresponding to the virtual address, access protection information and security information of the target physical address are returned to an L1TLB, and the access protection information and the security information of the target physical address are stored in the L2TLB.

[0008] In a second aspect, the embodiments of the present disclosure provide an electronic device, including a memory and a processor, the memory stores a computer program executable by the processor, and the computer program is executed by the processor to implement any one of the table lookup methods based on the RISC-V architecture provided by the embodiments of the present disclosure.

[0009] In a third aspect, the embodiments of the present disclosure provide a computer readable medium, which stores a computer program, and the computer program is executed by a processor to implement any one of the table lookup methods based on the RISC-V architecture provided by the embodiments of the present disclosure.

[0010] In a fourth aspect, the embodiments of the present disclosure provide a computer program product, which includes a computer program, and the computer program is executed by a processor to implement any one of the table lookup methods based on the RISC-V architecture provided by the embodiments of the present disclosure.

[0011] The table lookup method based on the RISC-V architecture provided by the embodiments of the present disclosure receives a virtual address sent by a processor, searches an L2TLB, and in a case where the virtual address corresponds to a leaf page table in the L2TLB, not only the target physical address can be obtained, but also the access protection information and the security information of the target physical address can be obtained, and the security information and the address protection information of the physical address do not need to be obtained by searching the table again, so that the number of times of searching the table can be reduced, the time of searching the table can be reduced, and the memory management efficiency can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0012] In the drawings of the embodiments of the present disclosure:

[0013] Figure 1 A flowchart of a memory management unit for address conversion in the related art is shown;

[0014] Figure 2 A flowchart of a table lookup method based on the RISC-V architecture provided by the embodiments of the present disclosure is provided;

[0015] Figure 3A look-up flowchart of an MPT module is shown;

[0016] Figure 4 A flowchart of another look-up method based on the RISC-V architecture provided by the embodiments of the present disclosure is shown.

[0017] Figure 5 A composition block diagram of an electronic device provided by the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0018] To make the skilled in the art better understand the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below in combination with the drawings.

[0019] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0020] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification, illustrate the embodiments of the present disclosure and together with the detailed description serve to explain the present disclosure. The above and other features and advantages of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings.

[0021] In the case of no conflict, each embodiment of the present disclosure and each feature in the embodiments can be combined with each other.

[0022] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. As used in the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in the present disclosure, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used in the present disclosure, the terms "comprises", "comprised of", "comprising", and "comprised" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise defined, all terms used in the present disclosure, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in a generally used dictionary should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined in the present disclosure.

[0024] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configuration formed based on the manufacturing process. Therefore, the regions exemplified in the drawings have a schematic property, and the shape of the regions shown in the drawings exemplifies a specific shape of the region of the element, but is not intended to be restrictive.

[0025] Figure 1 A flowchart showing an address translation procedure of a memory management unit in the related art is shown. As shown in Figure 1 the memory management unit performs the steps of converting between a virtual address and a physical address include:

[0026] Step S101, converting the virtual address to a target physical address.

[0027] In the A region, a table lookup is performed based on a virtual address (VA), a physical page number (PPN) of the MPT, and a supervisor domain identifier (SDID) to obtain a target physical address. When virtualization is enabled, a first-level table lookup and a second-level table lookup are performed. When virtualization is not enabled, only the first-level table lookup is performed. The embodiments of the present disclosure are described taking the case of enabling virtualization as an example.

[0028] Step S102, performing a PMP query on the target physical address to determine whether the target physical address has corresponding read / write / execute permissions.

[0029] The physical address and its access permission attribute are stored in the register of the PMP module. The target physical address is found in the register of the PMP module, and the access permission attribute of the target physical address is used to determine whether the target physical address has corresponding read / write / execute permissions. If the read / write / execute permissions exist, the target physical address passes the protection check; if the read / write / execute permissions do not exist, the access fails, and the target physical address is not allowed to be accessed.

[0030] Step S103, performing an MPT query on the target physical address to determine whether the target physical address is safe.

[0031] If the system has the demand for secure applications, the MPT module performs a security check on the target physical address. If the target physical address is safe, the target physical address passes the security check; if the target physical address is not safe, the access fails, and the target physical address is not allowed to be accessed.

[0032] After the above steps S101 to S103, not only the address translation is completed, i.e., the target physical address is obtained, but also the protection check and the security check of the target physical address are completed.

[0033] It should be noted that when virtualization is not enabled, the security check and the protection check can also be performed after the first-level table lookup.

[0034] In the RISC-V architecture Sv48+Sv48x4 mode, each page table walk (PTW) requires approximately three memory protection table (MPT) queries during the virtual address to physical address conversion process. Moreover, after the last PTW query retrieves the main physical address leaf page table, a security access check of the final leaf page table is required. Therefore, a complete physical address query requires approximately 99 page table queries, and the table lookup takes a lot of time.

[0035] In the secure mode, the lookup time of the two-level translation bypass cache L2TLB is longer. The page table walk (PTW) query request is initiated by the bypass cache and queries the page table entry (PTE) data in the memory space. This process also requires multiple cycles, which increases the time overhead of the virtual address to physical address conversion and reduces the efficiency of memory management.

[0036] In a first aspect, the embodiments of the present disclosure provide a table lookup method based on the RISC-V architecture.

[0037] Figure 2 A flowchart of a table lookup method based on the RISC-V architecture is provided for the embodiments of the present disclosure. As shown in Figure 2

[0038] In step S201, a virtual address sent by a processor is received, and a two-level translation bypass cache L2TLB is searched.

[0039] The processor in the system sends a virtual address to the MMU. After receiving the virtual address, the MMU searches for the virtual address in the L2TLB and determines whether the leaf page table can be found.

[0040] In step S202, in the case that the leaf page table corresponding to the virtual address is hit in the L2TLB, the target physical address corresponding to the virtual address, the access protection information and the security information of the target physical address are returned to the one-level translation bypass cache L1TLB, and the access protection information and the security information of the target physical address are stored in the L2TLB.

[0041] ​In the embodiments of the present disclosure, the access protection information and the security information of the target physical address are stored in the L2TLB, the access protection information and the security information of the target physical address can be obtained while the leaf page table is directly hit in the L2TLB, and the hit rate of the L2TLB can reach more than 90%, so the probability of hitting the access protection information and the security information of the target physical address can also reach more than 90%, the time of querying the MPT_SRAM module and the MPT module is saved, and thus the working efficiency of the memory management unit is improved.

[0042] In the embodiments of the present disclosure, the MPT module is based on the RISC-V Supervisor Domains Access Protection architecture v0.1.2 version, which supports the bare mode and the smmpt56 mode, wherein the bare mode is to not start the security mode check, and the security mode switching can be performed as needed, and the smmpt56 mode is to start the security mode check, and has the judgment of the read, write and execution permissions, and provides the security check judgment based on the permissions. The embodiments of the present disclosure provide a regulation that the table lookup method is applicable to all high-performance processors supporting the SMMPT security architecture.

[0043] Figure 3 A table lookup flowchart of an MPT module is shown. As shown in Figure 3 If the security table queried by the MPTL3 is of the table type and is not the final leaf page table entry, the lookup result of the MPTL3 does not belong to the MPT security permission check range, and points to the next level of the security page table position. The data returned by the MPTL2 and the MPTL1 can be leaf entries, and the leaf entry information can be backfilled into the L2TLB and the MPT_SRAM.

[0044] The embodiments of the present disclosure are independent for the lookup of the security page table and the storage of the security information corresponding to the physical address, and the final security information is not only stored in the MPT_SRAM but also stored in the L2TLB, and the relative coupling of the MPT and the L2TLB is realized, so that when the system issues a virtual address to query the L2TLB page table, the target physical address is hit, and the security check result can also be obtained at the same time, and the table lookup time in the security scenario is shortened.

[0045] In some embodiments, the table lookup method provided by the embodiments of the present disclosure further includes:

[0046] In the case that the leaf page table is not hit in the L2TLB, the intermediate physical address which needs to be looked up is calculated, and the intermediate physical address is subjected to security check and address protection PMP check, wherein the intermediate physical address is the address of the page table in which the target physical address is stored.

[0047] In the case of missing the leaf page table in the L2 TLB, the intermediate physical address that needs to be looked up is calculated, and the embodiment does not limit the way of calculating the intermediate physical address. After obtaining the intermediate physical address, a security check and an address protection PMP check are performed on the intermediate physical address to obtain the security access permission of the intermediate physical address.

[0048] In the case of failing to perform the security check on the intermediate physical address, a page table walk PTW query request of the MPT is initiated to the intermediate physical address to obtain a first leaf page table, and the first leaf page table includes the security information of the intermediate physical address.

[0049] In some embodiments, after obtaining the first leaf page table, the security information of the intermediate physical address is further stored in a random memory SRAM of the L2 TLB and the memory protection page MPT.

[0050] In the case that the intermediate physical address has access permission, a PTW query request of a page table entry PTE is initiated to the intermediate physical address to obtain a second leaf page table, and the second leaf page table includes the access protection information of the target physical address.

[0051] In some embodiments, after obtaining the second leaf page table, the access protection information of the target physical address is further stored in the L2 TLB.

[0052] In some embodiments, the address protection PMP check on the intermediate physical address includes: querying the access protection information of the intermediate physical address in a register of the PMP; and determining whether the intermediate physical address has access permission based on the access protection information of the intermediate physical address.

[0053] It should be noted that if the PMP check fails, the security check is no longer performed.

[0054] In the embodiment of the disclosure, the access protection information of the intermediate physical address is stored in the register of the PMP, and whether the intermediate physical address has access permission can be determined according to the access protection information of the intermediate physical address.

[0055] In some embodiments, the security check on the intermediate physical address includes: in the case of finding the security information of the intermediate physical address in the random memory SRAM of the memory protection page MPT, judging the security of the intermediate physical address based on the security information.

[0056] In some embodiments, in the case of finding the security information of the target physical address in the random memory SRAM of the memory protection page MPT, the security information and the access protection information of the target physical address are stored in the L2 TLB after obtaining the first leaf page table.

[0057] In some embodiments, in the case that the security information of the target physical address is not found in the random memory SRAM of the memory protection page MPT, after the PMP performs the access protection check on the intermediate physical address, the PTW query request of the MPT and the PTW query request of the PTE are initiated.

[0058] For better understanding of the present disclosure, the following will be combined with the accompanying drawings to describe the present disclosure in detail. Figure 4 The table lookup method is described in detail.

[0059] Figure 4 A flowchart of another table lookup method based on the RISC-V architecture provided by an embodiment of the present disclosure is shown. As shown in the figure, the table lookup method based on the RISC-V architecture includes: Figure 4

[0060] Step S401, receiving a miss virtual address (miss VA) sent by a processor, and searching a level 2 translation lookaside buffer (L2TLB).

[0061] Step S402, in the case of a direct hit (hit) leaf page table, the access protection information and the security information of the physical address corresponding to the virtual address are directly returned to the L1TLB.

[0062] Step S403, in the case of a miss (miss) leaf page table in the L2TLB, the virtual address is sent to a trusted service manager (TSM), the TSM calculates an intermediate physical address that needs to be looked up, and sends the intermediate physical address to a PMP module and an MPT_SRAM.

[0063] Step S404, the PMP module performs a protection check on the intermediate physical address.

[0064] Step S405, searching for the intermediate physical address in the SRAM, and checking whether the security check on the intermediate physical address has been performed in a previous transaction.

[0065] If the security information of the intermediate physical address can be found in the SRAM, the result of the PTW query of the PMP needs to be waited for. The security information and the result of the PTW query are sent to the L2TLB storage.

[0066] Step S406, the MPT module does not find the intermediate physical address in the SRAM, and after the protection check of the PMP on the intermediate physical address, the PTW query request of the MPT is initiated to obtain a first leaf page table.

[0067] Step S407, after the protection check of the PMP on the intermediate physical address, the PTW query of the PTE is initiated to obtain a second leaf page table.

[0068] ​

[0068] Step S408, the security information and access protection information of the intermediate physical address are stored in the L2 TLB, and the conversion of the virtual address to the physical address and the related information are returned to the L1 TLB.

[0069] After the above steps S401 to S408, the relative coupling of the MPT and the L2 TLB is realized.

[0070] Table 1 is different scenarios of table lookup and backfilling after the relative coupling of the MPT and the L2 TLB is realized.

[0071]

[0072] In Table 1, scenario A is that the L2 TLB misses the page table, and the MPT_SRAM also does not store the security information of the physical address, then the PTE_ PTW query and the MPT_ PTW query are initiated, and the returned page table and security table read / write / execution information need to be stored in the L2 TLB and the MPT_SRAM.

[0073] Scenario B is that the L2 TLB misses the page table, and the MPT_SRAM stores the PPN information of the next level MPT walk table of the physical address, then the PTE_ PTW query and the MPT_ PTW query are initiated, and the returned page table and security table read / write / execution information need to be stored in the L2 TLB and the MPT_SRAM.

[0074] Scenario C is that the L2 TLB misses the page table, and the MPT_SRAM stores the security information of the physical address, then the PTE_ PTW query is initiated, and the returned page table and security table read / write / execution information need to be stored in the L2 TLB.

[0075] Scenario D is that the L2 TLB hits the TABLE type page table, and the MPT_SRAM does not store the security information of the physical address, then the PTE_ PTW query and the MPT_ PTW query are initiated, and the returned page table and security table read / write / execution information need to be stored in the L2 TLB and the MPT_SRAM.

[0076] Scenario E is that the L2 TLB hits the TABLE type page table, and the MPT_SRAM stores the PPN information of the next level MPT walk table of the physical address, then the PTE_ PTW query and the MPT_ PTW query are initiated, and the returned page table and security table read / write / execution information need to be stored in the L2 TLB and the MPT_SRAM.

[0077] Scenario F is that the L2 TLB hits the TABLE type page table, and the MPT_SRAM stores the security information of the physical address, then the PTE_ PTW query is initiated, and the returned page table and security table read / write / execution information need to be stored in the L2 TLB.

[0078] Scenario G is a L2 TLB hit leaf page table, and the MPT_SRAM does not store the security information of the physical address, so there is no need to initiate a PTE PTW query and an MPT PTW query, and there is no need to store the returned page table and security table read / write / execute information into the L2 TLB and the MPT_SRAM.

[0079] As can be seen from Table 1, in scenario G, during the address translation process, the MPT_SRAM no longer needs to be accessed, and the security information of the physical address can be directly obtained from the L2 TLB, and the access permission is judged. If the L2 TLB and the MPT are completely independent lookup and storage systems, and the L2 TLB and the MPT have both found the final leaf page table, then the L2 TLB needs 3 clock cycles to query, and the MPT_SRAM also needs 3 clock cycles to query, and a total of 6 clock cycles are needed, while the table lookup method provided by the present disclosure only needs 3 clock cycles to complete the L2 TLB query, and the query time is shortened by 50%, thereby reducing the lookup time of the virtual address to the physical address, and improving the memory management efficiency.

[0080] The table lookup method provided by the embodiments of the present disclosure is suitable for a trusted execution environment (Trusted execution environment, TEE) based on the RSIC-V architecture, and is suitable for a system on a chip (SOC) or other security application scenarios based on the RSIC-V architecture required by a data security scenario of different hypervisor domains.

[0081] In a second aspect, the embodiments of the present disclosure provide an electronic device.

[0082] Figure 5 A block diagram of an electronic device provided by an embodiment of the present disclosure is shown. As shown in the figure, Figure 5 The electronic device provided by an embodiment of the present disclosure includes a processor 501 and a memory 502; the memory 502 stores a computer program executable by the processor 501, and the computer program is executed by the processor 501 to implement any one of the table lookup methods based on the RISC-V architecture provided by the embodiments of the present disclosure.

[0083] In some embodiments, the electronic device further includes an I / O interface (read / write interface) 503 connected between the processor 501 and the memory 502, which can realize the information interaction between the memory 502 and the processor 501, including but not limited to a data bus (Bus) and the like.

[0084] The processor is a device with data processing capability, including but not limited to a central processing unit (CPU) and the like; the memory is a device with data storage capability, including but not limited to a random access memory (RAM, more specifically SDRAM, DDR, etc.), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), and a flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, and can realize information interaction between the memory and the processor, including but not limited to a data bus (Bus) and the like.

[0085] Those of ordinary skill in the art can understand that the functional modules / units in all or some of the steps, systems, and devices disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0086] The embodiments of the present disclosure further provide a computer readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the lookup table methods based on the RISC-V architecture described in the above embodiments.

[0087] The embodiments of the present disclosure further provide a computer program product comprising a computer program, which, when executed by a processor, implements any of the lookup table methods based on the RISC-V architecture described in the above embodiments.

[0088] In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be executed by several physical components in cooperation.

[0089] Those of ordinary skill in the art can understand that the functional modules / units in all or some of the steps, systems, and devices disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0090] In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be executed by several physical components in cooperation.

[0091] Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or hardware, or a combination of software and / or hardware. Such software can be distributed on computer readable media, which can comprise computer storage media (or non-transitory media), and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes all computer-readable media in which data, such as computer readable instructions, data structures, program modules or other data, is programmatically implemented in any method or technology for storage of information. Computer storage media includes, but is not limited to, random access memory (RAM), non-volatile memory (e.g., read-only memory (ROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or other memory technologies); portable, compact disc read-only memory (CD-ROM), digital versatile discs (DVDs), or other optical storage; magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices; or any other medium that can be used to store the desired information and that can be accessed by a computer. Further, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term "modulated data signal" means a signal that has one or more of its characteristics changed or set in a manner so as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared, and other wireless media.

[0092] The present disclosure has disclosed example embodiments, and although the specific terms are employed, they are used in a generic descriptive sense only and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics or / and elements described in connection with a particular embodiment can be used in conjunction with other embodiments unless otherwise explicitly stated. Accordingly, it will be understood that various changes in form and details can be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A table lookup method based on RISC-V architecture, characterized in that, include: Receive the virtual address sent by the processor and look up the L2TLB (Level 2 Translation Bypass Buffer). If the leaf page table corresponding to the virtual address is hit in the L2TLB, the target physical address corresponding to the virtual address, the access protection information and security information of the target physical address are returned to the first-level translation bypass buffer L1TLB, and the access protection information and security information of the target physical address are stored in the L2TLB.

2. The method according to claim 1, characterized in that, Also includes: If the leaf page table is not hit in the L2TLB, the intermediate physical address that needs to be looked up is calculated, and the intermediate physical address is subjected to security checks and address protection PMP checks. The intermediate physical address is the address of the page table where the target physical address is located. If a security check of the intermediate physical address is not possible, an MPT page table traversal PTW query request is initiated to the intermediate physical address to obtain a first leaf page table, which includes the security information of the intermediate physical address. If the intermediate physical address has access permissions, a PTW query request for the page table entry PTE is initiated to the intermediate physical address to obtain the second leaf page table, which includes the access protection information of the target physical address.

3. The method according to claim 2, characterized in that, The address protection PMP check performed on the intermediate physical address includes: The access protection information of the intermediate physical address is queried in the register of the PMP; Whether the intermediate physical address has access permissions is determined based on the access protection information of the intermediate physical address.

4. The method according to claim 2, characterized in that, After obtaining the second leaf page table, the process also includes: The access protection information of the target physical address is stored in the L2TLB.

5. The method according to claim 2, characterized in that, The security check on the intermediate physical address includes: If the security information of the intermediate physical address is found in the SRAM of the memory protected page (MPT), the security of the intermediate physical address is determined based on the security information.

6. The method according to claim 2, characterized in that, After obtaining the first leaf page table, the process also includes: The security information of the intermediate physical address is stored in the random access memory (SRAM) of the L2TLB and the memory protection page (MPT).

7. The method according to claim 2, characterized in that, If the security information of the target physical address is found in the random access memory (SRAM) of the memory protection page (MPT), after obtaining the first leaf page table, the security information of the target physical address and the access protection information are stored together in the L2TLB. And / or, if the security information of the target physical address is not found in the random access memory (SRAM) of the memory protection page (MPT), after the PMP performs an access protection check on the intermediate physical address, it initiates a PTW query request for the MPT and a PTW query request for the PTE.

8. An electronic device, characterized in that, It includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the table lookup method based on the RISC-V architecture as described in any one of claims 1 to 7.

9. A computer-readable medium, characterized in that, The device stores a computer program that, when executed by a processor, implements the table lookup method based on the RISC-V architecture as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the table lookup method based on the RISC-V architecture as described in any one of claims 1 to 7.

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