Backplane and electronic devices

Abstract

This disclosure provides a backplane and an electronic device. The backplane includes a system slot, a peripheral slot, and a link switching circuit. The system slot is used to connect a system module, and the peripheral slot is used to connect a peripheral module. The link switching circuit is used to connect an upstream transmission line associated with the system module accessed through the system slot, and to connect a downstream transmission line accessed through the peripheral slot to the peripheral module. The link switching circuit is also used to establish or disconnect a physical connection between the upstream and downstream transmission lines, and to establish or disconnect a physical connection between downstream transmission lines corresponding to different peripheral modules.

Description

Technical Field

[0001] This invention relates to the field of signal measurement, and in particular to a backplane and electronic device. Background Technology

[0002] Modular instrument architecture standards, such as PCI Extensions for Instrumentation (PXI), PCI Extensions for Instrumentation express (PXIe), and Advanced Telecom Computing Architecture Extensions for Instrumentation (AXIe), form the foundation for modular instrumentation. Modular instruments are the core platform in modern test, measurement, and automation. They achieve high-speed data interconnection between functional modules through standardized bus technologies. Modular instrument architecture standards employ different bus protocols to achieve interconnection between modules. For example, the PXI / PXIe standard is based on the Peripheral Component Interconnect (PCI) / Peripheral Component Interconnect express (PCIe) protocol, the LAN Extensions for Instrumentation (LXI) bus is based on the Local Area Network (LAN) protocol, while the AXIe bus integrates both LAN and PCIe protocols. These instruments are widely used in aerospace, communications, semiconductor testing, and industrial automation, where high performance and flexibility are critical requirements. Currently, with increasingly complex testing needs, higher demands are being placed on the flexibility of data exchange between modules, the diversity of protocols, and the real-time performance of data transmission. Summary of the Invention

[0003] This disclosure provides a backplane and electronic devices.

[0004] According to a first aspect of the present disclosure, a backplane is provided, the backplane including a system slot, a peripheral slot, and a link switching circuit; the system slot is used to connect a system module, and the peripheral slot is used to connect a peripheral module;

[0005] The link switching circuit is used to connect the upstream transmission line associated with the system module accessed through the system slot, and to connect the downstream transmission line accessed through the peripheral slot to the peripheral module.

[0006] The link switching circuit is also used to establish or disconnect the physical connection between the upstream transmission line and the downstream transmission line, and to establish or disconnect the physical connection between the downstream transmission lines corresponding to different peripheral modules.

[0007] In some embodiments, the link switching circuit is specifically used for at least one of the following:

[0008] The first upstream transmission line connecting the system module;

[0009] A second upstream transmission line is connected, wherein the second upstream transmission line is obtained by extending the third upstream transmission line corresponding to the system module through a transmission switching module.

[0010] In some embodiments, the link switching circuit is specifically used for one of the following:

[0011] Establish a first physical connection between one set of upstream transmission lines and at least two sets of downstream transmission lines, wherein the established first physical connection is used for the system module to fan out data to the at least two sets of connected downstream transmission lines;

[0012] Establish a second physical connection between one set of first downstream transmission lines and at least two sets of second downstream transmission lines. The established second physical connection is used to allow the first peripheral module corresponding to the first downstream transmission line to fan out data to the at least two sets of second downstream transmission lines.

[0013] A third physical connection is established between a first set of downstream transmission lines, a set of upstream transmission lines, and at least a second set of downstream transmission lines. The established third physical connection is used to allow a first peripheral module corresponding to the first downstream transmission line to fan out data to the connected set of upstream transmission lines and the at least a second set of downstream transmission lines.

[0014] In some embodiments, the link switching circuit is specifically used for:

[0015] Based on the switch configuration information, establish or disconnect the physical connection between the upstream transmission line and the downstream transmission line, and establish or disconnect the physical connection between the downstream transmission lines corresponding to different peripheral modules.

[0016] In some embodiments, the switch configuration information is sent by the system module to the link switching circuit via a control transmission line, and / or

[0017] The switch configuration information is obtained by the link switching circuit from an external source through a communication interface.

[0018] In some embodiments, the physical connection between the upstream transmission line and the downstream transmission line is a protocol-agnostic physical connection; and / or

[0019] The physical connection between the downstream transmission lines corresponding to the different peripheral modules is a protocol-agnostic physical connection.

[0020] In some embodiments, the link switching circuit further includes a signal repeater for signal compensation of at least one of the following:

[0021] The signal transmitted over the physical connection between the upstream transmission line and the downstream transmission line;

[0022] The signals transmitted on the physical connection between the downstream transmission lines corresponding to different peripheral modules.

[0023] In some embodiments, the link switching circuit is specifically used to control whether the signal repeater performs the signal compensation based on transmission configuration information.

[0024] In some embodiments, there are M link switching circuits, and the M link switching circuits are divided into N layers, where N is a positive integer greater than or equal to 2.

[0025] In this configuration, each link switching circuit of the nth layer link switching circuit is connected to at least one of the link switching circuits of the (n+1)th layer link switching circuit, where n is a positive integer less than N, the number of link switching circuits of the nth layer is greater than or equal to the number of link switching circuits of the (n+1)th layer, the 1st layer link switching circuit is used to connect at least one of the upstream transmission line and the downstream transmission line, and the Nth layer link switching circuit is used to connect at least one of the upstream transmission line and the downstream transmission line.

[0026] In some embodiments, the number of the nth layer link switching circuits is greater than the number of the (n+1)th layer link switching circuits;

[0027] Each link switching circuit in the (n+1)th layer is connected to at least two link switching circuits in the nth layer.

[0028] In some embodiments, the upstream transmission line includes an upstream data bus; the downstream transmission line includes a downstream data bus.

[0029] According to a second aspect of the present disclosure, an electronic device is provided, the electronic device including the backplane described in the first aspect.

[0030] This disclosure provides a backplane and an electronic device. The backplane includes a system slot, a peripheral slot, and a link switching circuit. The system slot is used to connect a system module, and the peripheral slot is used to connect a peripheral module. The link switching circuit is used to connect an upstream transmission line associated with the system module accessed through the system slot, and a downstream transmission line accessed through the peripheral slot. The link switching circuit is also used to establish or disconnect a physical connection between the upstream and downstream transmission lines, and to establish or disconnect a physical connection between downstream transmission lines corresponding to different peripheral modules. By establishing or disconnecting the physical connection between the upstream and downstream transmission lines, and between the downstream transmission lines, on the one hand, physical connections can be directly established between modules, enabling direct transmission between modules, meeting the requirements of low-latency data transmission, and adapting to the needs of different scenarios. On the other hand, it can realize physical connections between system modules and different peripheral modules, as well as physical connections between different peripheral modules. The physical connections between modules are no longer fixed, improving the flexibility of connections. Attached Figure Description

[0031] Figure 1 A schematic diagram of a modular equipment structure Figure 1 ;

[0032] Figure 2 A schematic diagram of a modular equipment structure Figure 2 ;

[0033] Figure 3 This is a schematic diagram of a backplate structure according to an exemplary embodiment. Figure 1 ;

[0034] Figure 4 This is a schematic diagram of a link switching circuit structure according to an exemplary embodiment. Figure 1 ;

[0035] Figure 5 This is a schematic diagram of a backplate structure according to an exemplary embodiment. Figure 2 ;

[0036] Figure 6 This is a schematic diagram of a link switching circuit structure according to an exemplary embodiment. Figure 2 ;

[0037] Figure 7 This is a schematic diagram of a link switching circuit structure according to an exemplary embodiment. Figure 3 ;

[0038] Figure 8 This is a schematic diagram of a link switching circuit structure according to an exemplary embodiment. Figure 4 ;

[0039] Figure 9 A schematic diagram of a modular equipment structure Figure 3 ;

[0040] Figure 10 This is a schematic diagram of a daughter card module structure according to an exemplary embodiment. Figure 1 ;

[0041] Figure 11 This is a schematic diagram of a daughter card module structure according to an exemplary embodiment. Figure 2 ;

[0042] Figure 12 This is a schematic diagram of a daughter card module structure according to an exemplary embodiment. Figure 3 ;

[0043] Figure 13 This is a schematic diagram of a daughter card module structure according to an exemplary embodiment. Figure 4 ;

[0044] Figure 14 This is a schematic diagram of a backplate structure according to an exemplary embodiment. Figure 3 . Detailed Implementation

[0045] To make the technical solution and beneficial effects of the present invention more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0046] This disclosure is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0047] In each of the disclosed embodiments, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0048] The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure.

[0049] In this disclosure, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular or a plural expression.

[0050] In the embodiments disclosed herein, "multiple" refers to two or more.

[0051] In some embodiments, the terms “at least one of”, “one or more”, “a plurality of”, “multiple”, etc., may be used interchangeably.

[0052] In some embodiments, the notation "at least one of A and B", "A and / or B", "A in one case, B in another", "A in one case, B in another", etc., may include the following technical solutions depending on the situation: in some embodiments, A (A is executed regardless of B); in some embodiments, B (B is executed regardless of A); in some embodiments, execution is selected from A and B (A and B are selectively executed); in some embodiments, both A and B are executed. The same applies when there are more branches such as A, B, C, etc.

[0053] In some embodiments, the notation "A or B" may include the following technical solutions, depending on the situation: in some embodiments, A (execution of A regardless of B); in some embodiments, B (execution of B regardless of A); in some embodiments, selective execution from A and B (A and B are selectively executed). The same applies when there are more branches such as A, B, and C.

[0054] The prefixes "first," "second," etc., used in the embodiments of this disclosure are merely for distinguishing different descriptive objects and do not impose restrictions on the position, order, priority, value, or content of the descriptive objects. The description of the descriptive objects should be found in the claims or the context of the embodiments, and the use of prefixes should not constitute unnecessary restrictions. For example, if the descriptive object is a "field," the ordinal numbers preceding "field" in "first field" and "second field" do not restrict the position or order of the "fields." "First" and "second" do not restrict whether the "fields" they modify are in the same message, nor do they restrict the order of "first field" and "second field." Similarly, if the descriptive object is a "level," the ordinal numbers preceding "level" in "first level" and "second level" do not restrict the priority between "levels." Furthermore, the value of the descriptive object is not limited by ordinal numbers and can be one or more. For example, in "first device," the value of "device" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the object being described is "device", then "first device" and "second device" can be the same device or different devices, and their types can be the same or different. Similarly, if the object being described is "information", then "first information" and "second information" can be the same information or different information, and their content can be the same or different.

[0055] In some embodiments, “including A,” “containing A,” “for indicating A,” and “carrying A” can be interpreted as directly carrying A or indirectly indicating A.

[0056] In some embodiments, terms such as “…”, “determine…”, “in the case of…”, “when…”, “when…”, “if…”, etc. can be used interchangeably.

[0057] In some embodiments, the terms “greater than,” “greater than or equal to,” “not less than,” “more than,” “more than or equal to,” “not less than,” “higher than,” “higher than or equal to,” “not lower than,” and “above” can be used interchangeably, as can the terms “less than,” “less than or equal to,” “not greater than,” “less than,” “less than or equal to,” “not more than,” “lower than,” “lower than or equal to,” “not higher than,” and “below”.

[0058] Furthermore, each element, each row, or each column in the table of this disclosure can be implemented as an independent embodiment, and any combination of any element, any row, or any column can also be implemented as an independent embodiment.

[0059] Example 1

[0060] In related technologies, the backplane design of modular instruments such as oscilloscopes and network analyzers faces bottlenecks. Their interconnection solutions mostly rely on dedicated packet switching chips (such as PCIe switches or LAN switches). This architecture inherently limits data transmission to specific packet switching protocols. Therefore, for streaming protocols requiring deterministic latency and higher real-time performance (such as JESD204B / C), existing backplanes cannot provide flexible, software-configurable switching capabilities. Even if some standards (such as AXIe's Local bus) support such connections, they are limited to fixed point-to-point interconnections between adjacent modules, lacking global scheduling capabilities. Furthermore, the physical connection between the switching chip and peripheral module slots on existing backplanes is fixed, meaning that specific pins on the slots can only be used for a single high-speed serial protocol. This prevents dynamic adjustment of the data transmission bandwidth between the peripheral module and the switching chip according to actual application scenarios, thus limiting the overall system's performance optimization and application flexibility.

[0061] Figure 1 This is a bus interconnection scheme for a PXIe (PCI eXtensions for Instrumentation) modular instrument backplane. The architecture mainly consists of the following core components: a system card, multiple peripheral modules (Slot1, Slot2, ..., Slot N) connected to the backplane via their respective slots, and a data exchange chip, such as a PCIe switch. The system card typically acts as the main controller of the entire system, managing and coordinating the work of other modules. Peripheral modules are functional modules that perform specific test and measurement tasks, such as data acquisition cards and signal generation cards. The PCIe switch is the hub of the entire data interaction, establishing connections with the system card and each peripheral module slot via a high-speed serial link. Specifically, the PCIe bus originating from the system card first connects to the uplink port of the PCIe switch, and then the switch connects to each peripheral module slot in a point-to-point manner through its multiple downlink ports. This star topology allows system modules to communicate with any peripheral module, and any two peripheral modules can exchange data via a PCIe switch chip. The entire system's communication protocol strictly adheres to the PCIe standard, with all data transmitted and routed on the bus in the form of PCIe packets. The advantages of this design are its clear structure and ability to fully leverage the mature PCIe ecosystem for high-speed data transmission.

[0062] The PXIe backplane bus interconnect scheme operates based on packet switching. When a module in the system (such as a system module or a peripheral module) needs to send data to another module, it first encapsulates the raw data into packets conforming to the PCIe protocol specification. These packets contain the source address, destination address, data payload, and other control information. Subsequently, the packets are sent to the PCIe switch chip through the module's PCIe interface. Upon receiving the packets, the PCIe switch chip parses the header information, particularly the destination address. Based on its internal routing table, the switch chip determines which downstream port the packet should be forwarded to—the slot where the target module resides. Finally, the packets are sent to the target module through the designated downstream port. The target module receives the packets, unpacks them, and extracts the valid data for processing. This mechanism allows for flexible communication between any modules within the system.

[0063] Figure 2 This is an AXIe (standard backplane bus interconnect solution), a more complex instrument bus architecture than PXIe. The core components of this solution include a system card and multiple peripheral module slots (Slot 1, Slot 2, ..., Slot 3). AXIe backplane, along with two different types of data switching chips: PCIe switches and LAN switches. Similar to PXIe systems, system modules and peripheral modules are mounted on the backplane via slots. However, the AXIe backplane provides a dual network for data switching. On one hand, it retains a PCIe-based control and data transmission plane similar to PXIe, where system modules and all peripheral modules are connected to the PCIe switch chip via their respective PCIe links, forming a PCIe switching network. This part is mainly used for system control, configuration, and high-speed data transmission that is not sensitive to latency. On the other hand, the AXIe specification introduces an Ethernet (LAN)-based data plane. System modules and all peripheral modules are also simultaneously connected to the LAN switch chip via independent physical links, forming a parallel Ethernet switching network. This dual-bus design allows AXIe systems to simultaneously utilize the high bandwidth of PCIe and the distributed network characteristics of LAN. Furthermore, the AXIe standard also defines the so-called "Local..." "bus" refers to a series of point-to-point high-speed links reserved on the backplane that directly connect adjacent slots, enabling communication between specific modules that require extremely high bandwidth and extremely low latency.

[0064] The AXIe backplane solution operates in a dual-plane parallel manner. For communications requiring tight operating system control or leveraging the existing PCIe driver ecosystem, the module will choose to exchange data via the PCIe plane. The process is exactly the same as the aforementioned PXIe system and will not be repeated here.

[0065] For applications requiring distributed, scalable, or long-distance communication, the module utilizes the LAN plane. In this case, data is encapsulated into Ethernet frames and sent to the LAN switching chip via the onboard network interface card (NIC). The LAN switching chip forwards the Ethernet frames to the target module based on the destination MAC address or IP address.

[0066] Both of the above architectures have limitations:

[0067] 1. Both of the aforementioned bus architectures, whether PCIe or LAN, are essentially based on packet switching protocols. This means they cannot well support streaming protocols that require deterministic latency, such as JESD204B / C. The queuing, arbitration, and routing processes of data in the switching chip introduce jitter and unpredictable latency, which is unacceptable for precise synchronization applications in fields such as RF sampling and coherent optical communication.

[0068] 2. While the above architecture provides a way to support point-to-point streaming (such as point-to-point transmission between system modules and peripheral modules), its connection relationships are physically fixed, typically only connecting two or a few physically adjacent slots. This greatly limits its application scope, making it impossible to achieve flexible, high-speed streaming data interconnection between any two peripheral modules, resulting in a lack of system configuration flexibility.

[0069] 3. In both of the above architectures, the high-speed serial pins on the peripheral module slots are rigidly allocated to PCIe or LAN switching chips. This rigid bandwidth allocation cannot be dynamically reconfigured according to task requirements, resulting in potential resource waste and performance bottlenecks. For example, it is impossible to bundle multiple PCIe channels between two peripheral modules to form a higher-bandwidth direct link, nor can some channels be redefined for other protocols, thus limiting the flexibility and scalability of the entire system.

[0070] Therefore, how to achieve low-latency data transmission between modules in modular instruments, how to achieve flexible allocation of point-to-point transmission between modules, and how to flexibly configure module pins are problems that urgently need to be solved.

[0071] Accordingly, embodiments of this disclosure propose a backplane, such as Figure 3 As shown, the backplane includes a system slot, a peripheral slot, and a link switching circuit; the system slot is used to connect a system module, and the peripheral slot is used to connect a peripheral module.

[0072] The link switching circuit is used to connect the upstream transmission line associated with the system module accessed through the system slot, and to connect the downstream transmission line accessed through the peripheral slot to the peripheral module.

[0073] The link switching circuit is also used to establish or disconnect the physical connection between the upstream transmission line and the downstream transmission line, and to establish or disconnect the physical connection between the downstream transmission lines corresponding to different peripheral modules.

[0074] Here, the backplane can be a backplane in architectures such as PXIe and AXIe. Backplanes can be used in modular measurement instruments.

[0075] The backplane may have system slots and peripheral slots for connecting system modules and peripheral modules, respectively. The backplane may also be used for at least the following purposes: connecting external power supplies for power distribution and management; providing synchronization and timing references; and providing mechanical structural support.

[0076] In one possible implementation, the system module and peripheral module can take the form of daughter cards. Therefore, the system module and peripheral module can also be collectively referred to as daughter card modules.

[0077] A system card can be a high-performance embedded processor, the core of which may be a CPU based on an x86 architecture, running a standard operating system such as Windows or Linux. The system card connects to peripheral modules via a backplane, using data buses such as PXIe or LAN buses. The system card integrates a bus controller. For example, it may integrate a PXIe root complex, serving as the starting point of the entire PCIe bus tree and responsible for bus enumeration, configuration, and management.

[0078] Peripheral modules (Slot 1...N) are modular instruments with different functions. Each peripheral module has its own hardware circuit designed according to its function (such as oscilloscope, signal source, etc.) and is connected to the peripheral slot on the backplane through a PXIe connector to realize power supply and data communication. Each peripheral module contains a bus endpoint, such as a PCIe endpoint device, for handling interaction with the PCIe bus.

[0079] Transmission lines are used to carry the data bus between system modules and peripheral modules. Transmission lines may include some transmission lines located on the system module; for example, some transmission lines located on the peripheral module and some transmission lines located on the backplane.

[0080] Here, the link switching circuit can be placed between the system module and the peripheral module. The link switching circuit can be used to connect the transmission line between the system module and the peripheral module.

[0081] In one possible implementation, the link switching circuit and system module may also include other electronic devices, such as bus transmission switching modules, signal coupling devices, and / or impedance matching devices.

[0082] In one possible implementation, other electronic devices, such as signal coupling devices and / or impedance matching devices, may also be placed between the link switching circuit and the peripheral module.

[0083] In one possible implementation, the upstream transmission line associated with the system module may include the transmission line between the link switching circuit and the system module.

[0084] In one possible implementation, the downstream transmission line of the peripheral module may include a transmission line between the link switching circuit and the peripheral module.

[0085] In one possible implementation, the upstream transmission line includes one or more physical electrical connection lines. The upstream transmission line may include at least one of the following: one or more single-ended lines, one or more sets of differential lines.

[0086] In one possible implementation, the downstream transmission line includes one or more physical electrical connection lines. The downstream transmission line may include at least one of the following: one or more single-ended lines, one or more sets of differential lines.

[0087] In some embodiments, the upstream transmission line includes an upstream data bus; the downstream transmission line includes a downstream data bus.

[0088] For example, the upstream data bus may include PCIe, LAN, JESD204B / C, etc. Similarly, the downstream data bus may also include PCIe, LAN, JESD204B / C, etc.

[0089] In one possible implementation, the upstream transmission line and the downstream transmission line can respectively include the control line and the data line in the data bus.

[0090] For example, one set of upstream transmission lines corresponds to one set of downstream transmission lines. The upstream transmission lines can include all transmission lines used to satisfy data bus transmission; for instance, the upstream transmission lines can include all transmission lines used for PCIe ×4 bus transmission. Similarly, the downstream transmission lines can include all transmission lines used to satisfy data bus transmission. A link switching circuit can connect the upstream transmission lines and the corresponding downstream transmission lines to enable data bus transmission.

[0091] Here, as Figure 4 As shown, the link switching circuit provides logical ports for connecting transmission lines. The link switching circuit can be a physical connection matrix used to establish direct, point-to-point physical signal paths between logical ports.

[0092] In one possible implementation, a logical port can correspond to one transmission line.

[0093] In one possible implementation, one logical port can correspond to one set of transmission lines.

[0094] In one possible implementation, the link switching circuit can establish a direct, point-to-point physical signal path between logic ports, based on the connection configuration of the upper-layer software.

[0095] For example, such as Figure 4 As shown, the connection configuration defines the connection relationships between the various logic ports within the link switching circuit. The physical switches within the link switching circuit (such as analog switches or cross-point switches) then establish a series of parallel, independent, end-to-end physical links according to instructions. These physical links are protocol-agnostic; they directly transmit the raw analog electrical signals without regard to the data protocol they carry. This is analogous to software-controlled "flying wires," allowing for the arbitrary establishment or dismantling of physical connections between different functional modules.

[0096] In one possible implementation, the link switching circuit is based on a hardware PCB design and uses a high-speed crosspoint switch chip array. These chips are analog devices specifically designed for signal routing. They can receive configuration signals to control the internal switch matrix, routing signals from any input port to any output port.

[0097] In one possible implementation, the link switching circuitry can be a dedicated ASIC or FPGA. In this implementation, a large number of input / output pins are connected via programmable interconnect logic, configured by an on-chip controller according to external instructions.

[0098] In some embodiments, the link switching circuit includes: a first port for connecting to the upstream transmission line; and a second port for connecting to the downstream transmission line.

[0099] Understandably, the first and second ports of a link switching circuit are determined based on the connected transmission lines. If a logic port of the link switching circuit is connected to an upstream transmission line, then that logic port is called the first port; if a logic port of the link switching circuit is connected to a downstream transmission line, then that logic port is called the second port.

[0100] The link switching circuit can be connected to at least one set of upstream transmission lines and at least one set of downstream transmission lines. The link switching circuit can realize the physical connection or disconnection between ports through physical switches, thereby realizing the physical connection or disconnection between upstream and downstream transmission lines, and / or the physical connection or disconnection between downstream transmission lines.

[0101] In one possible implementation, the link switching circuit can use a switch matrix to connect or disconnect any one set of upstream transmission lines and one set of downstream transmission lines.

[0102] In one possible implementation, the link switching circuit can use a switch matrix to connect or disconnect any two sets of downstream transmission lines.

[0103] For example, such as Figure 3 As shown, ports M1 to Mn+3 are the first ports, used to connect to the upstream transmission lines associated with the system modules. Ports S1 to Sn are the second ports, used to connect to the downstream transmission lines.

[0104] Here, the link switching circuit can establish or disconnect the physical connection between the upstream transmission line and the downstream transmission line. For example, upstream transmission line A1 is connected to port M1, downstream transmission line a1 is connected to port S1, and downstream transmission line a3 is connected to port S3. The link switching circuit can establish or disconnect the physical connection between the upstream and downstream transmission lines by establishing or disconnecting the connection between the ports (e.g., through a switch matrix). The link switching circuit can establish or disconnect the connection between upstream transmission line A1 and downstream transmission line a1. Similarly, the link switching circuit can establish or disconnect the connection between upstream transmission line A1 and downstream transmission line a3.

[0105] The link switching circuit can also establish or disconnect physical connections between downstream transmission lines corresponding to different peripheral modules. For example, downstream transmission line a3 is connected to port S3, downstream transmission line a4 is connected to port S4, downstream transmission line a7 is connected to port S7, and downstream transmission line an is connected to port Sn. The link switching circuit can establish or disconnect physical connections between downstream transmission lines by establishing or disconnecting connections between ports (e.g., through a switch matrix). The link switching circuit can establish or disconnect the connection between downstream transmission line a3 and downstream transmission line a7. Similarly, the link switching circuit can establish or disconnect the connection between downstream transmission line a4 and downstream transmission line an.

[0106] The switch configuration information is obtained by the link switching circuit from an external source through a communication interface.

[0107] In some embodiments, the physical connection between the upstream transmission line and the downstream transmission line is a protocol-agnostic physical connection; and / or the physical connection between the downstream transmission lines corresponding to the different peripheral modules is a protocol-agnostic physical connection.

[0108] Here, the physical connection can be a physical electrical connection. Data transmission over a physical connection does not require forwarding, thus meeting the requirements for low-latency data transmission.

[0109] By establishing or disconnecting physical connections between the upstream and downstream transmission lines, and between the downstream transmission lines themselves, the system achieves several advantages. Firstly, it enables direct physical connections between modules, facilitating direct data transmission and meeting the demands of low-latency data transmission, thus adapting to diverse scenarios. Secondly, it allows for physical connections between system modules and different peripheral modules, as well as between different peripheral modules themselves. The physical connections between modules are no longer fixed, increasing connection flexibility.

[0110] In some embodiments, the link switching circuit is specifically used for at least one of the following:

[0111] The first upstream transmission line connecting the system module;

[0112] A second upstream transmission line is connected, wherein the second upstream transmission line is obtained by extending the third upstream transmission line corresponding to the system module through a transmission switching module.

[0113] Here, as Figure 5 As shown, the upstream transmission line may include a first upstream transmission line (indicated by arrow A) and / or a second upstream transmission line (indicated by arrows B and C).

[0114] The first upstream transmission line can be a transmission line connecting to the system module, with one end connected to the system module and the other end connected to the link switching circuit. For example, Figure 5The first upstream transmission line of the system module (indicated by arrow A), such as the JESD204B / C bus, can be directly connected to the first port of the link switching circuit. The downstream transmission lines of the peripheral slots (downstream transmission lines a1, a3, a4, a5, and an) are directly connected to the second port of the link switching circuit. The link switching circuit can establish or disconnect the physical connection between the first upstream transmission line and the downstream transmission lines (any one of downstream transmission lines a1, a3, a4, a5, and an). In this way, a direct physical connection can be established between the system module and the peripheral module, enabling direct transmission between modules, meeting the requirements for low-latency data transmission, and adapting to the needs of different scenarios.

[0115] The system module can extend the data bus via a transport switching module. The transport switching module can be used to forward data packets transmitted on the data bus. For example, the transport switching module may include a PCIe bus switch, and / or a LAN bus switch / router, etc. The system module can be connected to the transport switching module via a third upstream transmission line, allowing the transport switching module to extend multiple second upstream transmission lines.

[0116] Each second upstream transmission line can be connected to the first port of the link switching circuit, and the corresponding downstream transmission line can be connected to the second port of the link switching circuit. The link switching circuit enables the physical connection and disconnection between the second upstream transmission line and its corresponding downstream transmission line.

[0117] For example, such as Figure 5 As shown, the third upstream transmission line of the system module (the first LAN data bus indicated by arrow B') is expanded into multiple second upstream transmission lines (the second LAN data buses indicated by arrow B) through a LAN switch. The second upstream transmission lines are directly connected to the first port of the link switching circuit. The downstream transmission lines of the peripheral slots (downstream transmission line b2 and downstream transmission line b5) are directly connected to the second port of the link switching circuit. The link switching circuit can establish or disconnect the physical connection between the second upstream transmission line and the downstream transmission line (either downstream transmission line b2 or downstream transmission line b5). The third upstream transmission line (the first PCIe data bus indicated by arrow C') is expanded into multiple second upstream transmission lines (the second PCIe data buses indicated by arrow C) through a PCIe switch. Similar to the LAN data bus, these will not be described in detail here.

[0118] In this way, physical connections between system modules and different peripheral modules, as well as physical connections between different peripheral modules, can be realized. The physical connections between modules are no longer fixed, which improves the flexibility of the connection.

[0119] In some embodiments, the link switching circuit is specifically used for one of the following:

[0120] Establish a first physical connection between one set of upstream transmission lines and at least two sets of downstream transmission lines, wherein the established first physical connection is used for the system module to fan out data to the at least two sets of connected downstream transmission lines;

[0121] Establish a second physical connection between one set of first downstream transmission lines and at least two sets of second downstream transmission lines. The established second physical connection is used to allow the first peripheral module corresponding to the first downstream transmission line to fan out data to the at least two sets of second downstream transmission lines.

[0122] A third physical connection is established between a first set of downstream transmission lines, a set of upstream transmission lines, and at least a second set of downstream transmission lines. The established third physical connection is used to allow a first peripheral module corresponding to the first downstream transmission line to fan out data to the connected set of upstream transmission lines and the at least a second set of downstream transmission lines.

[0123] Here, a first downstream transmission line can be connected to a first peripheral module, and a set of second downstream transmission lines can be connected to a second peripheral module. Thus, one first peripheral module can connect to multiple second peripheral modules. The established third physical connection is used for the first peripheral module to fan out data to the multiple connected second peripheral modules.

[0124] The link switching circuit in this embodiment can also connect one set of upstream transmission lines to multiple sets of downstream transmission lines simultaneously, or connect one set of first downstream transmission lines to multiple sets of second downstream transmission lines simultaneously, or connect one set of first downstream transmission lines to both upstream and second downstream transmission lines simultaneously. This enables multicast or broadcast data transmission.

[0125] For example, one set of upstream transmission lines can be connected to a data transmission endpoint (such as a system module), and one set of downstream transmission lines can be connected to a data transmission endpoint (such as a peripheral module). One set of upstream transmission lines can correspond to one set of downstream transmission lines. One set of upstream transmission lines and one set of downstream transmission lines can satisfy the transmission requirements of a type of data bus, such as satisfying the transmission requirements of a PCIe (×4, ×8, or ×16) bus. Therefore, the connection between one set of upstream transmission lines and one set of downstream transmission lines can satisfy point-to-point data transmission, such as transmission between a system module and a peripheral module.

[0126] For example, the upstream transmission line can be used to carry JESD204B / C protocol data transmission. The upstream transmission line of the system module can be simultaneously connected to the downstream transmission lines of multiple peripheral modules through a link switching circuit. In this way, the system module can broadcast data through the transmission line, enabling simultaneous data transmission to multiple peripheral modules and improving data transmission efficiency. Similarly, one set of first downstream transmission lines can be simultaneously connected to multiple sets of second downstream transmission lines, or one set of first downstream transmission lines can be simultaneously connected to the upstream and second downstream transmission lines. These are similar and will not be elaborated further here.

[0127] In some embodiments, the link switching circuit is specifically used for:

[0128] Based on the switch configuration information, establish or disconnect the physical connection between the upstream transmission line and the downstream transmission line, and establish or disconnect the physical connection between the downstream transmission lines corresponding to different peripheral modules.

[0129] In one possible implementation, switch configuration information can be used to indicate the connection relationship between at least two ports on a link switching circuit.

[0130] In one possible implementation, the switch matrix in the link switching circuit can be controlled by a controller to switch on and off to establish or disconnect a physical connection.

[0131] In one possible implementation, the link switching circuit may include a controller that controls the switch matrix. The controller can communicate with the outside world through a communication interface located within the link switching circuit to obtain switch configuration information.

[0132] In some embodiments, the switch configuration information is sent by the system module to the link switching circuit via a control transmission line, and / or the switch configuration information is obtained by the link switching circuit from an external source via a communication interface.

[0133] System modules or external devices can send switch configuration information to the link switching circuit via a communication interface. External devices may include external host computers, etc.

[0134] In one possible implementation, the switch configuration information can be user-configurable.

[0135] In one possible implementation, the switch configuration information may be determined by the system module based on at least one of the following: the system module and peripheral module connected to the backplane; the configuration of the system module; the configuration of the peripheral module; and the currently executed service.

[0136] The communication interface can include SPI, I2C, etc., and is not limited here.

[0137] Here, a specific example is provided for detailed explanation. Figure 5 An innovative modular instrument backplane design scheme is proposed. This scheme innovatively adds a physical signal bridging layer of link switching circuits between traditional switching chips (such as PCIe_Switch and LAN_Switch) and peripheral slots. Here, PCIe_Switch refers to the switching chip for the PCIe bus, and LAN_Switch refers to the switching chip for the LAN bus. The modular instrument architecture under this scheme includes: a system module, multiple peripheral slots (Slot 1, Slot 2, ..., Slot N), traditional PCIe and LAN switching chips, and link switching circuits. In the diagram, identifiers such as M1 to Mn+1 and S1 to Sn+3 represent logical ports, which can be connected to (system slots) to connect the system module, various peripheral slots, PCIe switching chips, or LAN switching chips. The link switching circuit, as a configurable physical connection matrix, has the core function of establishing direct, point-to-point physical signal paths between these logical ports based on the switching configuration information of the upper-layer software. Figure 5 As shown, several flexible connection methods are illustrated: M1 is connected to S1, enabling direct connection between the system module and peripheral module 1 based on the JESD204B / C protocol; M2 is connected to S2, connecting another part of the channel of peripheral module 1 to the LAN switching chip to support LAN protocol communication; S3 is connected to S7, enabling direct communication between peripheral module 1 and peripheral module 3 based on the JESD204B / C protocol; S4 is connected to Sn, enabling direct communication between peripheral module 2 and peripheral module N based on the JESD204B / C protocol; S6 is connected to Mn+1, connecting the channel of peripheral module 3 to the PCIe switching chip. Furthermore, the connections of Sn+2 and Sn+3 indicate that the link switching circuit can also support other types of high-speed serial protocols.

[0138] Link switching circuits provide configurable physical layer switching capabilities. Before system startup, the system module or master controller can send switch configuration information to the link switching circuit via an independent communication interface (such as SPI, I2C, etc.). The switch configuration information defines the connection relationships between the ports within the link switching circuit. Once configured, the physical switches (such as analog switches or cross-point switches) within the link switching circuit establish a series of parallel, independent, end-to-end physical links according to the instructions. These links are protocol-agnostic; they directly transmit raw analog electrical signals without regard to the data protocol carried. This is analogous to software-controlled "flying wires," allowing the establishment or removal of physical connections between different functional modules. For example, when M1 is configured to connect with S1, a physical direct connection is formed between the system module and peripheral module 1, which is ideal for transmitting streaming protocols like JESD204B / C, which have extremely high requirements for latency and signal integrity. Meanwhile, other modules in the system can establish different connections through link switching circuits. For example, peripheral module 3 can be connected to the PCIe switching chip for traditional packet-switched communication. This design completely breaks away from the constraints of fixed physical connections and single protocols in existing technologies. It allows the backplane to simultaneously support packet-based protocols (such as PCIe and LAN) and stream-based protocols (such as JESD204B / C), and can flexibly establish connections between any modules and dynamically allocate data transmission bandwidth according to application requirements. For example, multiple physical channels of one peripheral module can be configured to be directly connected to another peripheral module to form an ultra-high bandwidth private bus, which is impossible with existing technologies.

[0139] for Figure 5 In the implementation of each module, the connector pins of the system module and peripheral module are no longer fixed to specific switching chips, but can be connected to the ports of the link switching circuit. The PCIe_Switch and LAN_Switch can still be standard commercial switching chips, but they also act as a "client" device of the link switching circuit, establishing a connection with the peripheral module through the ports of the link switching circuit. Figure 5 The logic ports such as M1 and S1 physically correspond to one or more sets of high-speed differential signal pairs (TX / RX pairs) on the link switching circuit chip or PCB module. For example, one logic port may represent a x4 link, i.e., 4 pairs of transmit (TX) and 4 pairs of receive (RX) differential signals. The system module communicates with the controller on the link switching circuit through low-speed serial interfaces such as SPI, I2C, or UART to upload the switching configuration information of the connection matrix, thereby realizing the software definition of the entire backplane interconnect topology.

[0140] In some embodiments, the link switching circuit further includes a signal repeater for signal compensation of at least one of the following:

[0141] The signal transmitted over the physical connection between the upstream transmission line and the downstream transmission line;

[0142] The signals transmitted on the physical connection between the downstream transmission lines corresponding to different peripheral modules.

[0143] Signal repeaters can be configured based on the ports of link switching circuits. For example, a signal repeater can be configured for the output port of each link switching circuit.

[0144] In one possible implementation, a signal repeater is used to compensate for signal quality degradation caused by signal transmission on the transmission line.

[0145] When a signal is transmitted along a transmission line, its quality deteriorates, such as amplitude attenuation. Therefore, signal repeaters can be installed in link switching circuits to compensate for signal quality degradation.

[0146] For example, when the transmission path for high-speed signals is long, a signal repeater can be used. The link switching circuit compensates for signal attenuation in the high-frequency part through its internal equalization circuit, such as a continuous time linear equalization (CTLE), and restores the signal amplitude through amplification circuits (such as a limiting amplifier), thereby optimizing the eye diagram of the output signal and reducing the bit error rate.

[0147] In some embodiments, the link switching circuit is specifically used to control whether the signal repeater performs the signal compensation based on transmission configuration information.

[0148] Here, the controller in the link switching circuit can control whether the signal repeater performs the signal compensation based on the transmission configuration information.

[0149] In one possible implementation, transmission configuration information is used to indicate whether signal compensation is performed on at least one connection established by the link switching circuit.

[0150] For example, transmission configuration information can directly indicate whether signal compensation is required for the connection between port 1 and port 2 of the link switching circuit. This transmission configuration information can be sent to the controller by the system module or external devices via the communication interface.

[0151] In one possible implementation, the transmission configuration information is used to indicate at least one of the following: the type of signal transmitted (e.g., control signal, data signal, bus type, etc.) on at least one connection established by the link switching circuit; and the path length of the transmitted signal on at least one connection established by the link switching circuit. Based on the transmission configuration information, the controller can determine which transmission lines require signal compensation and which do not.

[0152] Different transmission lines have different effects on the signal. Generally, the length of the transmission line is positively correlated with its effect on the signal. If the transmission line is short, its effect on the signal is small, so no compensation is needed. However, since signal repeaters may introduce time delays when compensating for signal delays, they may not meet the required signal delay specifications.

[0153] Therefore, by controlling whether the signal repeater performs signal compensation through transmission configuration information, it is possible to adapt to different signal transmission conditions. On the one hand, signals that require compensation can be compensated, thereby optimizing the eye diagram of the output signal and reducing the bit error rate; on the other hand, signals that do not require compensation can be left uncompensated, reducing negative impacts on the signal and ensuring signal quality.

[0154] For example, Figure 6This section describes the internal structure and implementation principle of a link switching circuit. The core of the link switching circuit is a configurable cross-connect matrix, and the circuit includes multiple ports (pins). These pins can be bidirectional (input / output) or unidirectional. For example, a link switching circuit may consist of multiple input pins (Input PIN 1, ..., Input PIN N) and multiple output pins (Output PIN 1, ..., Output PIN N). A programmable switching network is established between the input and output pins. The link switching circuit also includes a controller and a communication interface. The controller receives external configuration commands (such as switch configuration information, transmission configuration information, etc.) and controls the state of the switching network accordingly. The communication interface provides the controller with a channel to communicate with external controllers (such as system modules or external devices). An important optional component is a signal repeater (also called a re-driver), which is placed on the path of each output pin. The input pins receive high-speed serial signals from modules such as system modules, peripheral modules, or transmission switching modules (switching chips), while the output pins send the routed and selectively processed signals to the target module. The controller connects to each intersection of the switching network via internal control lines, enabling precise connection of any input pin signal to any one or more output pins. The communication interface can be a standard SPI, UART, or I2C protocol interface, ensuring easy integration with the main control system. The re-driver, acting as a signal conditioning unit, shapes and amplifies the signal after long-distance transmission to compensate for losses and improve signal quality. Based on this design method, the link switching circuit of this invention can configure point-to-point signal connections, as well as point-to-multipoint signal connections in multicast or broadcast modes. Figure 6 The "w / o Re-driver" option indicates whether a signal repeater is used or not.

[0155] The link switching circuit operates based on a direct physical layer signal routing mechanism. First, the external host system sends configuration data (transmission switching module) to the controller inside the link switching circuit via a communication interface. This data explicitly defines the desired connection topology, for example, specifying "routing the signal from Input PIN 5 to Output PIN 8". After receiving and parsing this configuration data, the controller generates corresponding control signals and applies them to the switching elements of the cross-connect matrix. This creates a low-impedance physical path between Input PIN 5 and Output PIN 8, allowing high-speed analog signals to pass directly with minimal distortion and delay. For each output pin, the controller can also decide whether to enable a re-driver on its path based on configuration information (such as transmission configuration information). Re-driver can be enabled when high-speed SerDes signals (such as PCIe Gen4 or 100G Ethernet) need to be transmitted and the transmission path is long. The re-driver compensates for signal attenuation in the high-frequency range through its internal equalization circuitry (such as CTLE) and restores the signal amplitude through amplification circuitry, thereby optimizing the eye diagram of the output signal and reducing the bit error rate. Conversely, when transmitting low-speed control signals, or in certain deterministic latency applications with extremely stringent latency requirements (where the re-driver itself introduces a slight delay), the re-driver can be disabled, allowing the signal to bypass the unit directly. This flexible, protocol-independent physical layer switching capability enables the link switching circuit to support arbitrary routing from DC signals to high-speed serial signals of tens of Gbps, and allows for signal quality optimization as needed.

[0156] Regarding the implementation of each component, input / output pins can be either single-ended or differential signal pins to accommodate different types of signal transmission requirements. For example, for high-speed protocols such as PCIe and JESD204B / C, differential pins (a pair of pins representing a TX or RX channel) are typically used to obtain better noise immunity. For ordinary GPIO or control signals, single-ended pins can be used. The cross-connect matrix can consist of a large number of CMOS analog switches or more specialized RF switch arrays. These switches need to have extremely low insertion loss and excellent bandwidth characteristics when on, and extremely high isolation when off. The controller can be a small microcontroller (MCU) core or a finite state machine implemented in an FPGA. It is responsible for parsing instructions received through the communication interface, managing internal configuration registers, and ultimately driving the switch matrix. The communication interface is a standard digital logic interface that can be easily connected to the SPI, I2C, or UART peripherals of any host chip. Signal repeaters (re-drivers) can utilize high-speed signal conditioning chips, such as the SerDes Re-driver. These chips integrate continuous-time linear equalizers (CTLEs), limiting amplifiers, and other circuitry, allowing for programmable settings to address different channel losses and achieve optimal signal compensation. The entire link switching circuit can be designed as a standalone PCB or highly integrated into a single ASIC or FPGA chip for higher density and performance.

[0157] In some embodiments, there are M link switching circuits, and the M link switching circuits are divided into N layers, where N is a positive integer greater than or equal to 2.

[0158] In this configuration, each link switching circuit of the nth layer link switching circuit is connected to at least one of the link switching circuits of the (n+1)th layer link switching circuit, where n is a positive integer less than N, the number of link switching circuits of the nth layer is greater than or equal to the number of link switching circuits of the (n+1)th layer, the 1st layer link switching circuit is used to connect at least one of the upstream transmission line and the downstream transmission line, and the Nth layer link switching circuit is used to connect at least one of the upstream transmission line and the downstream transmission line.

[0159] Here, M link switching circuits can form a large-scale switching matrix.

[0160] The connection between each link switching circuit of the nth layer link switching circuit and at least one of the link switching circuits of the (n+1)th layer link switching circuits may include at least one port of each link switching circuit of the nth layer link switching circuit and at least one port of the link switching circuit of the (n+1)th layer link switching circuits. Here, the connection between the link switching circuits may include a physical connection, such as an electrical connection implemented by a wire.

[0161] In one possible implementation, each link switching circuit of the nth layer link switching circuit is connected to each link switching circuit of the (n+1)th layer link switching circuit.

[0162] For example, such as Figure 7 The four link switching circuits constitute a two-layer link switching circuit; each link switching circuit in the first-layer link switching circuit is connected to each link switching circuit in the second-layer link switching circuit.

[0163] In one possible implementation, the first number of ports of each link switching circuit of the nth layer link switching circuit for connecting to the (n+1)th layer link switching circuit is less than or equal to the second number of ports of each link switching circuit of the nth layer link switching circuit for connecting to the upstream transmission line and / or the downstream transmission line.

[0164] In one possible implementation, the third number of ports of each link switching circuit of the (n+1)th layer link switching circuit for connecting the nth layer link switching circuit is less than or equal to the fourth number of ports of each link switching circuit of the (n+1)th layer link switching circuit for connecting the upstream transmission line and / or the downstream transmission line.

[0165] Since the link switching circuit can establish physical connections between ports, the port of the first-level link switching circuit can be physically connected to the port of the Nth-level link switching circuit through the physical connections between the link switching circuits of each layer.

[0166] By establishing a multi-layer link switching circuit, the number of ports used to connect upstream and / or downstream transmission lines can be expanded.

[0167] In one possible implementation, the number of link switching circuits at each layer can be the same.

[0168] In one possible implementation, the number of link switching circuits at each layer may not be exactly the same.

[0169] For example, Figure 7 This paper demonstrates an application scheme that utilizes multiple link switching circuits to construct a switching matrix, aiming to solve the problem that the limited number of ports on a single link switching circuit chip cannot meet the interconnection requirements of large backplane systems. Figure 7 As shown, assume each link switching circuit (labeled as a link switching circuit) supports configurable connections of 16 input and 16 output ports. To construct an interconnect system supporting 32 ports, four such 16x16 link switching circuits can be arranged in a 2x2 matrix structure. As shown, the 32 system input ports are divided into two groups: the 16 input ports (Inputs 1-16) of link switching circuit 3 in layer 1 are connected to the two link switching circuits in layer 2 (each unit receives 8 inputs, or otherwise allocated); the 16 input ports (Inputs 17-32) of link switching circuit 4 in layer 1 are connected to the two link switching circuits in layer 2. Internal interconnections also exist between these four link switching circuits. Finally, the 32 system output ports are led out from these four units. Through this multi-level switching method, arbitrary connections between the 32 input ports and 32 output ports can be achieved, thereby expanding the supported number of interconnects from 16 to 32.

[0170] Figure 7 In the demonstrated switching matrix, a signal entering from the system input port first passes through the first-layer link switching circuit. The first-layer switching unit forwards the signal to the appropriate second-layer link switching circuit according to a routing algorithm. The second-layer link switching circuit then routes the signal to its final target system output port. For example, to establish a connection from Input 1 to Output 20, the control software needs to calculate a path traversing this two-stage switching matrix. This might mean that the signal from Input 1 first enters link switching circuit 3, is routed through link switching circuit 3 to one of its outputs 8-15, then outputs to one of its inputs 0-7 in link switching circuit 2, and finally outputs from its output 3. In this way, through the switching matrix, multiple small-scale link switching circuits are successfully combined into a large-scale logical switching unit. The complexity of the control software increases accordingly, as it must not only configure the connections within each link switching circuit but also coordinate the connections between different units to ensure correct path establishment and avoid conflicts.

[0171] The implementation of this solution primarily lies in the PCB design of the backplane and the algorithms of the control software. At the hardware level, layout space needs to be provided on the backplane for multiple link switching circuit chips or modules, and the interconnection traces between them need to be designed. These traces between chips are also high-speed serial links, requiring strict signal integrity design. At the software level, a more advanced routing controller is needed. When a user requests to establish a connection (e.g., from source slot A to destination slot B), this controller needs to run a routing algorithm to find an available physical path in the current multi-level switching network topology. This may involve complex resource management to ensure that connection requests across the entire switching matrix can be satisfied. The algorithm needs to consider how to allocate intermediate link resources to maximize the total throughput of the switching network and avoid congestion. This hierarchical, matrix design can be recursively extended; theoretically, arbitrarily large-scale interconnection networks can be constructed by adding more link switching circuits and switching stages.

[0172] A deeper exploration of the technical implications of this matrix scheme reveals the powerful scalability of the link switching circuit technology proposed in this invention. This is a crucial criterion for evaluating the long-term value of a fundamental technology. In the real-world modular instrument market, chassis sizes and slot counts vary widely, ranging from small chassis with a few slots to large chassis with 18, 21, or even more slots. If a backplane technology can only serve systems of a specific scale, its application will be severely limited. This matrix scheme demonstrates that link switching circuits can serve as standardized "building blocks," meeting the needs of systems of different sizes through a modular approach. This scalability allows backplane designs based on this invention to smoothly cover the entire product line, from low-end to high-end. Furthermore, this architecture provides flexibility and reliability. For example, in some designs, the system's fault tolerance can be improved by providing redundant paths on inter-stage links. If a link switching circuit or an inter-stage link fails, the routing algorithm can dynamically recalculate the path, bypassing the failure point and ensuring continuous system operation. This scalability and reliability make this invention not only an innovative point solution but also a systemic architecture capable of supporting the future development of modular instrument platforms.

[0173] In some embodiments, the number of the nth layer link switching circuits is greater than the number of the (n+1)th layer link switching circuits;

[0174] Each link switching circuit in the (n+1)th layer is connected to at least two link switching circuits in the nth layer.

[0175] Here, the N-layer link switching circuits can form a tree structure. For example... Figure 8As shown, the transmission lines connected to the first layer can eventually converge to the Nth layer. Alternatively, the transmission lines of the Nth layer can extend to the first layer. Through tree structure bits, the transmission lines (upstream input lines and / or downstream input lines) connected to the Nth layer link switching circuit can achieve physical connection with the transmission lines (upstream input lines and / or downstream input lines) connected to the first layer link switching circuit.

[0176] For example, the upstream transmission line can be connected to the link switching circuit of layer N, and the downstream transmission line can be connected to the link switching circuit of layer 1. In this way, the data bus of the system module can be extended to multiple peripheral modules.

[0177] Figure 8 One important extended application of link switching circuits is the tree structure, whose main goal is to greatly expand the number of selectable interconnected input ports for an output port. This structure exhibits typical hierarchical convergence characteristics. At the bottom layer (leaf nodes), there are a large number of system input ports. These input ports are grouped and connected to multiple link switching circuits in the first layer. The outputs of the first-layer link switching circuits then converge and connect to a smaller number of second-layer link switching circuits. This process can be repeated multiple times, with each level having fewer link switching circuits than the next, eventually converging to one or a few root node link switching circuits, from which the final system output port is derived. Through this tree-like cascaded structure, a single output port located at the root node can be selectively connected to any system input port in the leaf node layer through software configuration, thereby achieving large-scale "multiple-to-one" functionality.

[0178] The working logic of this tree-structured application scheme is essentially to construct a huge, reconfigurable multiplexer tree. When a specific input signal (e.g., the signal from sensor number 50) needs to be connected to a single analysis module (connected to the System Output), the control system issues a series of configuration instructions. These instructions program each link switching circuit along the unique path from that specific input to the root output. For example, at the first level, the link switching circuit connected to input number 50 is configured to route that input to its output port towards the second level. At the second level, the corresponding link switching circuit is configured to continue passing this signal from the first level upwards. This process proceeds level by level, until finally, at the root node's link switching circuit, the signal is selected and routed to the final System Output port. By changing the configuration of the link switching circuits at each level, the input source being monitored by the System Output can be switched within nanoseconds or microseconds. This architecture is particularly suitable for applications that require rapid polling, selection, or monitoring of signals from a massive number of signal sources.

[0179] The implementation of this scheme also places specific requirements on hardware layout and software control. On the hardware side, the backplane PCB needs to be laid out with a large number of link switching circuit chips and their hierarchical connections according to a tree topology. From the leaf node to the root node, the interconnect bandwidth of each level may need to be planned according to the degree of signal convergence. On the software side, the control logic is simpler than a matrix structure. To establish a connection, it is only necessary to determine a unique path from the leaf to the root and configure all switching units on that path. The software needs to maintain an address mapping table to map the logical numbers of system input ports to their physical locations in the tree structure, in order to quickly generate configuration instructions. For example, when a user requests "connect input port X", the software queries the address table to find the leaf node switch where X is located and the path to the root node, and then configures all switches on the path sequentially.

[0180] This in-depth analysis of the technical value of the tree-structured approach reveals its highly efficient hardware implementation for solving the problem of "data selection" rather than "data exchange." Unlike matrix structures that require arbitrary point-to-point connections, tree structures are more targeted in resource utilization, specifically optimizing for "many-to-one" communication. This mode is prevalent in many practical test and measurement applications. For example, in a large-scale semiconductor wafer testing system, a high-precision measurement unit (connected to the root node) might be needed to rapidly and sequentially test the electrical characteristics of hundreds or thousands of test points (connected to leaf nodes) on the wafer. Using this approach, rapid hardware-level switching can be achieved, far exceeding the speed of software-controlled multiple relays or addressing using upper-layer protocols. Another example is in the field of communication signal monitoring, where a demodulation analyzer (root node) needs to be able to select one signal (leaf node) from hundreds or thousands of frequency bands captured in real time for in-depth analysis. The tree-structured link switching circuit network can construct a hardware-level RF or IF signal selection matrix, enabling seamless signal switching and monitoring. Therefore, this solution demonstrates the high adaptability of the technology of the present invention, and can solve specific technical problems most efficiently through different topologies according to different application requirements.

[0181] Example 2

[0182] In any of the modular instruments described in the above embodiments, after multi-channel high-speed data acquisition, massive amounts of data need to be transmitted between different modules for real-time processing, or the data needs to be transmitted to external devices via high-speed interfaces such as optical fibers. However, a common challenge currently exists: although backplane standards such as PXIe or AXIe provide very high theoretical transmission bandwidth, the number of available high-speed serial interfaces (Serdes I / O) on the main processor (such as FPGA) on the system module and / or peripheral module is limited. More importantly, the physical connection between these chip I / Os and module slot pins cannot be changed once it is completed in the hardware design phase. This fixed connection method leads to serious resource bottlenecks and design rigidity, preventing the board from fully utilizing the bandwidth provided by the backplane, and also preventing the flexible reallocation and routing of data streams according to different test tasks. This results in a significant reduction in system performance in specific application scenarios, and may even prevent the implementation of certain functions that require a large number of I / O resources.

[0183] like Figure 9This diagram illustrates a typical high-speed bus connection scheme for modular instrument service boards based on the AXIe protocol. The diagram depicts three adjacent peripheral modules (or a combination of peripheral and system modules): labeled peripheral module N-1, peripheral module N, and peripheral module N+1, interconnected via a shared backplane. Each peripheral module's processor utilizes an FPGA chip, responsible for data acquisition, processing, and transmission. Figure 9 The diagram clearly indicates that the FPGA chip has a total SerDes (serializer / deserializer) channel capacity of 24 transmit (TX) channels (24T) and 24 receive (RX) channels (24R). These channels are allocated for two main data links: a PCIe / LAN bus for communication with the system controller and a local bus for direct data exchange between adjacent boards. Specifically, in the connection configuration shown in the diagram, the FPGA for peripheral module N divides its SerDes resources: one part is used for PCIe / LAN connections, and the other part is used for the Local Bus. Specifically, it connects to peripheral module N-1 via 8 transmit channels (as shown by arrow T1) and to peripheral module N+1 via another 8 transmit channels (as shown by arrow T2). In contrast, peripheral module N-1's FPGA is configured with 16 receive channels (16R) (as shown by arrow R1) to receive data from peripheral module N, while peripheral module N+1 is configured with 16 receive channels (16R) (as shown by arrow R2) to receive data from peripheral module N. These connections are implemented through fixed physical traces on the peripheral module PCB (printed circuit board), and cannot be changed once the hardware design and manufacturing are completed. This static connection method clearly exposes the limitations of existing technology.

[0184] Figure 9In this system, the fixed physical connections of peripheral modules severely limit the system's flexibility and performance. This hardware-based static routing method means that data paths cannot be changed once determined during the PCB design phase. Although the instrument backplane (e.g., the AXIe standard) itself can provide extremely high transmission bandwidth, such as the 16-Lane Local Bus and 16-Lane PCIe / LAN bus shown in the figure, the FPGA chips on the peripheral modules have limited SerDes IO resources, and the physical connections between these resources and the backplane connectors are fixed, preventing full utilization of the bandwidth provided by the backplane. Specifically, when peripheral module N needs to communicate with a single neighbor (N-1 or N+1) with maximum bandwidth, because its physical connection to each neighbor is only designed as an 8-Lane, it cannot achieve full bandwidth transmission of 16-Lanes, resulting in a 50% performance loss. Similarly, when data needs to be broadcast to two neighbors, each neighbor can only receive an 8-Lane data stream. Furthermore, if a new functional interface, such as a high-speed optical module, needs to be introduced, but there is no pre-reserved and wired SerDes IO on the FPGA, this function cannot be implemented unless the entire peripheral module hardware is redesigned and manufactured. This rigid design not only leads to system performance bottlenecks but also greatly increases development costs and time, making it unable to adapt to complex and ever-changing test and measurement needs.

[0185] As the core processing unit, the FPGA chip can be programmed using hardware description languages ​​such as Verilog or VHDL to implement specific data processing and interface control logic. This involves loading the fixed logic code into the FPGA's internal SRAM to define its functionality. However, the connection between the FPGA's physical pins (including high-speed SerDes IO) and other components on the PCB is achieved through BGA (Ball Grid Array) packaging and soldering; this connection is permanent. The instrument backplane is implemented as a multi-layered, high-density PCB integrating multiple standardized connectors (such as the AXIe standard Zone2 connector) and adhering to strict impedance control and signal integrity design specifications to support reliable transmission of high-speed differential signals. The traces on the backplane define the interconnect topology between the slots, such as the Local Bus connection between adjacent slots in the diagram. The connection between peripheral modules is implemented by connecting the FPGA's SerDes IO pins to PXIe or AXIe connectors on the board edge via carefully designed, length-matched differential traces on their respective PCBs. Once these traces are etched onto the PCB, their paths and destinations are fixed. For example, the 16 pairs of SerDes differential signal lines used for the Local Bus on the FPGA of peripheral module N in the figure are physically divided into two groups during PCB design. One group of 8 pairs is connected to the connector pins leading to peripheral module N-1, and the other group of 8 pairs is connected to the connector pins leading to peripheral module N+1. This physical hard connection is the root cause of the lack of system flexibility.

[0186] Figure 9The architecture shown reveals its inherent rigid constraints. First, the FPGA is the core of the system; although its internal logic is programmable, the number of its physical I / O interfaces is limited. The FPGA chip has 24T and 24R (i.e., 24 pairs of differential transmit channels and 24 pairs of differential receive channels), with 24T and 24R representing the upper limit of high-speed transceiver resources available to the FPGA chip in the diagram. Second, the labels "8T8R," "16T," and "16R" are key to understanding resource allocation. "8T8R" indicates that FPGA N allocates 8 transmit channels each for communication with the Local Buses of N-1 and N+1. The "16R" (16 receive channels) on N-1 and N+1 indicates that in this specific application, even though the FPGAs of N-1 and N+1 have the capability to receive 16-lane data, the physical wiring of peripheral module N only provides it with 8-lane data sources, resulting in wasted resources. Furthermore, the "Local bus" is a direct-connect bus between boards, distinct from the "PCIe / LAN" bus connected to the system controller. It is designed specifically for low-latency, high-bandwidth communication between adjacent boards. Although the backplane in the diagram provides a physical channel capacity of "16 lanes" for the Local bus, the hardware design of peripheral module N splits it into two 8-lane links. This design decision is fixed at the hardware level. A "lane" typically refers to a pair of differential signal lines (TX+ and TX-, or RX+ and RX-), used to transmit one bit of high-speed serial data. Therefore, "16 lanes" means 16 pairs of differential lines, capable of transmitting 16 bits of data in parallel, with a bandwidth twice that of "8 lanes". The bottleneck of the entire system is not the transmission capacity of the backplane, nor the processing power of the FPGA, but the unchangeable PCB trace between the FPGA physical pins and the backplane connector. It acts like a physical distributor soldered onto the circuit board, allocating the FPGA's valuable I / O resources in a fixed way, thus leading to the performance limitations and functional deficiencies in the aforementioned scenarios.

[0187] Therefore, how to achieve flexible allocation of module signal lines in modular instruments to meet different transmission requirements is an urgent problem to be solved.

[0188] This disclosure proposes a first sub-card module, such as... Figure 10 As shown, the first daughter card module is used to be coupled to the backplane via a first daughter card slot on the backplane; the first daughter card module includes a first data transmission module and a link switching circuit;

[0189] The link switching circuit is used to connect the target transmission line of the first data transmission module and to connect at least two sets of candidate transmission lines. The candidate transmission lines are used to couple to the second sub-card module through the first sub-card slot. Each set of candidate transmission lines corresponds to a second sub-card slot, and the second sub-card slot is used to couple to the second sub-card module.

[0190] The link switching circuit is also used to establish or disconnect the physical connection between the target transmission line and the candidate transmission line.

[0191] Here, the backplane can be a backplane in architectures such as PXIe and AXIe. Backplanes can be used in modular measurement instruments.

[0192] The backplane may have system slots and peripheral slots for connecting system modules and peripheral modules, respectively. The backplane may also serve at least the following purposes: connecting to an external power supply for power distribution and management; providing synchronization and timing references; and providing mechanical structural support. Specific implementations of the system modules and peripheral modules are as described in any of the above embodiments and will not be repeated here.

[0193] The daughter card module can be connected to the backplane via a daughter card slot. The daughter card module may include system modules and / or peripheral modules.

[0194] In one possible implementation, the first and second sub-card modules are used simply to distinguish different sub-card modules. Without contradiction, the first sub-card module can also be the second sub-card module, and vice versa.

[0195] In one possible implementation, both the first and second sub-card modules are peripheral modules.

[0196] In one possible implementation, at least one of the first sub-card module and the second sub-card module is a system module, and at least one of the first sub-card module and the second sub-card module is a peripheral module.

[0197] The first data transmission module is used to realize data transmission through the physical connection between the target transmission line and the candidate transmission line. The first data transmission module can be the processor of the daughter card module, such as an FPGA.

[0198] The transmission line is used to carry the data bus between the first daughter card module and the second daughter card module. The transmission line may include a portion of the transmission line located on the daughter card module and a portion of the transmission line located on the backplane.

[0199] Here, the link switching circuit can be located in the first daughter card module. The first daughter card module can be used at least to connect the transmission line between the first daughter card module and the second daughter card module.

[0200] In one possible implementation, other electronic devices, such as bus transmission switching modules, signal coupling devices, and / or impedance matching devices, can also be provided between the link switching circuit and the daughter card module.

[0201] In one possible implementation, the target transmission line may include a transmission line between a link switching circuit and a first daughter card module.

[0202] In one possible implementation, the candidate transmission line is located in the first daughter card module. The candidate transmission line may include the link switching circuit of the first daughter card module and the portion of the transmission line located in the first daughter card module between the second daughter card module and the first daughter card module.

[0203] In one possible implementation, the second daughter card module is connected to the candidate transmission line via a backplane. For example, the FPGA of the second daughter card module is connected to the candidate transmission line via the second daughter card slot, the backplane, and the first daughter card slot.

[0204] In one possible implementation, multiple daughter cards are connected to the link switching circuit backplane via their respective candidate transmission lines.

[0205] In one possible implementation, the target transmission line comprises one or more physical electrical connection wires. The target transmission line may include at least one of the following: one or more single-ended wires, one or more sets of differential wires.

[0206] In one possible implementation, the candidate transmission line comprises one or more physical electrical connection lines. The candidate transmission line may include at least one of the following: one or more single-ended lines, one or more sets of differential lines.

[0207] In some embodiments, the target transmission line and the candidate transmission line are used to carry a data bus. When a physical connection is established between the target transmission line and the candidate transmission line, data bus communication between the first sub-card module and the second sub-card module is realized.

[0208] For example, the data bus may include PCIe, LAN, JESD204B / C, etc.

[0209] In one possible implementation, the target transmission line and the candidate transmission line may respectively include the control line and the data line in the data bus.

[0210] For example, one set of target transmission lines can correspond to one set of candidate transmission lines. The target transmission lines can include all transmission lines used to satisfy data bus transmission; for instance, one set of upstream transmission lines can include all transmission lines used for PCIe x4 bus transmission. Similarly, one set of candidate transmission lines can include all transmission lines used to satisfy data bus transmission. A link switching circuit can connect one set of target transmission lines and the corresponding set of candidate transmission lines to enable connection between the target and candidate transmission lines, thus satisfying data bus transmission.

[0211] In one possible implementation, a set of target transmission lines may include multiple sets of sub-target transmission lines, and a set of candidate transmission lines may include multiple sets of sub-candidate transmission lines. Data bus communication between the first sub-card module and the second sub-card module can be connected on a unit of sub-transmission lines. For example, a set of sub-target transmission lines of the first sub-card module is connected to a set of sub-candidate transmission lines of the first sub-card module to achieve data bus carrying.

[0212] Here, as Figure 10 As shown, the link switching circuit provides logical ports for connecting transmission lines. The link switching circuit can be a physical connection matrix used to establish direct, point-to-point physical signal paths between logical ports.

[0213] In one possible implementation, a logical port can correspond to one transmission line.

[0214] In one possible implementation, one logical port can correspond to one set of transmission lines.

[0215] In one possible implementation, the link switching circuit can establish a direct, point-to-point physical signal path between logic ports, based on the connection configuration of the upper-layer software.

[0216] For example, such as Figure 10 As shown, the connection configuration defines the connection relationships between the various logic ports within the link switching circuit. The physical switches within the link switching circuit (such as analog switches or cross-point switches) then establish a series of parallel, independent, end-to-end physical links according to instructions. These physical links are protocol-agnostic; they directly transmit the raw analog electrical signals without regard to the data protocol they carry. This is analogous to software-controlled "flying wires," allowing for the arbitrary establishment or dismantling of physical connections between different functional modules.

[0217] In one possible implementation, the link switching circuit is based on a hardware PCB design and uses a high-speed crosspoint switch chip array. These chips are analog devices specifically designed for signal routing. They can receive configuration signals to control the internal switch matrix, routing signals from any input port to any output port.

[0218] In one possible implementation, the link switching circuitry can be a dedicated ASIC or FPGA. In this implementation, a large number of input / output pins are connected via programmable interconnect logic, configured by an on-chip controller according to external instructions.

[0219] In some embodiments, the link switching circuit includes: a first port for connecting to the target transmission line; and a second port for connecting to the candidate transmission line.

[0220] Understandably, the first and second ports of the link switching circuit are determined based on the connected transmission lines. If a logic port of the link switching circuit is connected to the target transmission line, then that logic port is called the first port; if a logic port of the link switching circuit is connected to a candidate transmission line, then that logic port is called the second port.

[0221] The link switching circuit can connect at least one set of target transmission lines and at least one set of candidate transmission lines. The link switching circuit can physically switch the ports to achieve physical connection or disconnection between the target transmission lines and candidate transmission lines.

[0222] In one possible implementation, the link switching circuit can achieve a physical connection between any one set of target transmission lines and one set of candidate transmission lines using a switching matrix.

[0223] For example, such as Figure 10 As shown, the transmission lines indicated by arrows x1 and x2 constitute one set of target transmission lines X for the first sub-card module. The transmission lines indicated by arrows y1 and y2 constitute one set of candidate transmission lines Y1. The transmission lines indicated by arrows y3 and y4 constitute another set of candidate transmission lines Y2. Candidate transmission line Y1 can be connected to the second sub-card module N-1, and candidate transmission line Y2 can be connected to the second sub-card module N+1.

[0224] Here, the link switching circuit can establish or disconnect the physical connection between the target transmission line and the candidate transmission line. For example, the link switching circuit establishes a physical connection between the target transmission line X and the candidate transmission line Y1, and disconnects the physical connection between the target transmission line X and the candidate transmission line Y2. Alternatively, the link switching circuit establishes a physical connection between the target transmission line X and the candidate transmission line Y2, and disconnects the physical connection between the target transmission line X and the candidate transmission line Y1. In this way, flexible connection between the target transmission line and the candidate transmission line can be achieved.

[0225] In one possible implementation, the physical connection between the target transmission line and the candidate transmission line is a protocol-agnostic physical connection.

[0226] Here, the physical connection can be a physical electrical connection. Data transmission over a physical connection does not require forwarding, thus meeting the requirements for low-latency data transmission.

[0227] The physical connection between the target transmission line and the candidate transmission line is established or disconnected through a link switching circuit. On the one hand, a direct physical connection can be established between the first daughter card module and the second daughter card module, enabling direct transmission between modules, meeting the requirements of low-latency data transmission, and adapting to the needs of different scenarios. On the other hand, physical connections can be realized between the first daughter card module and different second daughter card modules. The physical connection of the first daughter card module is no longer fixed, improving the flexibility of the connection and meeting the needs of different scenarios.

[0228] In some embodiments, the at least two sets of candidate transmission lines include a first set of candidate transmission lines and a second set of candidate transmission lines; the link switching circuit is specifically used for:

[0229] A physical connection is established between the target transmission line and the first group of candidate transmission lines, and the physical connection between the target transmission line and the second group of candidate transmission lines is disconnected. The established physical connection is used for data transmission between the first sub-card module and the second sub-card module corresponding to the first candidate transmission line.

[0230] Here, the link switching circuit can select one of at least two candidate transmission lines to establish a physical connection with the target transmission line, and disconnect the target transmission line from other candidate transmission lines. This allows the first daughter card module to use all its bandwidth for data transmission with a second daughter card module simultaneously, improving the data transmission rate.

[0231] For example, such as Figure 11The diagram illustrates a high-speed bus connection scheme. The core components consist of three adjacent daughter card modules (Second Daughter Card Module 1, First Daughter Card Module, and Second Daughter Card Module 2), where the First Daughter Card Module is the data transmitter and the Second Daughter Card Module 1 is the data receiver. Unlike existing technologies, an innovative physical signal switching module called a link switching circuit is introduced between the FPGA chip of the First Daughter Card Module and the connector on the instrument backplane. The diagram details the signal flow: data originates from the first data transmission module (e.g., the FPGA) on the First Daughter Card Module, which is configured with 16 transmit channels (16T) for data output. These signals first enter the link switching circuit. By software configuration, the link switching circuit sets its internal switching matrix to a specific state, which routes the signals from all 16 transmit channels of the FPGA completely and aggregatedly to the LocalBus link connected to the Second Daughter Card Module 1. Therefore, a high-speed data path with a bandwidth of up to 16 lanes is formed between the First Daughter Card Module and the Second Daughter Card Module 1. Meanwhile, the Local Bus link to the second daughter card module 2 is disconnected or empty under this configuration, and does not carry data from the FPGA. The second data transmission module (e.g., the FPGA) of the second daughter card module 1 is correspondingly configured with 16 receive channels (16R) to fully match and receive the data stream from this 16-lane. This scheme intuitively demonstrates the core advantage of the invention: by adding a configurable physical bridge, dynamic redirection of FPGA SerDes IO resources is achieved.

[0232] The working logic of this embodiment lies in decoupling the hard binding between the FPGA physical I / O and the backplane physical interface through a configurable intermediate switching layer, thereby achieving flexible reconfiguration of the data link. The system receives configuration instructions from the host computer, which define the data transmission topology and bandwidth requirements of the current task. After processing, the output is a high-performance physical data link optimized according to the instructions. The specific workflow is as follows: First, the host computer software generates corresponding configuration information based on the application scenario (e.g., in scenario 1, data from the first daughter card module needs to be transmitted to the second daughter card module 1 with maximum bandwidth). This configuration information is sent to the controller of the link switching circuit on the first daughter card module via a control bus (such as I2C or SPI). The controller parses the instructions and controls the analog switch matrix inside the link switching circuit to establish a new connection path. In this example, the controller operates the switches to connect all the input pins of the link switching circuit corresponding to the 16 transmit channels (16T) of the FPGA to the 16 output pins corresponding to the Local Bus leading to the second daughter card module 1. The signal flows upwards, with the high-speed serial data stream (16-lane) originating from the FPGA entering the link switching circuit. After passing through an internal physical switching path, with almost no protocol-level processing or delay, it is directly redirected to the new target port, namely the backplane interface connecting to N-1. Finally, the FPGA of the second daughter card module 1 receives the complete data stream through its 16 receive channels (16R). This series of operations successfully aggregates what would have been two separate 8-lane links in existing technology into a single 16-lane high-speed link, doubling the data transmission bandwidth and fully utilizing the hardware capabilities of the backplane and FPGA, thereby maximizing system performance.

[0233] In this embodiment, the implementation of each module reflects the reconfigurability of the hardware. The FPGA chip is implemented similarly to existing technologies, still serving as the core data source and processor, programmed using a hardware description language. However, the physical connection object for its SerDes IO is no longer a fixed backplane pin, but rather the input port of the link switching circuit, providing a basis for flexible signal output. The link switching circuit is the core of this embodiment, and its implementation can take two main forms. The first is a chip-level implementation based on discrete components or application-specific integrated circuits (ASICs). In this approach, the link switching circuit is a high-speed crosspoint switch IC, internally integrating a large-scale analog switch matrix, controller logic, and optional signal conditioning circuitry (such as a re-driver). This chip is soldered to the PCB of the daughter card module in BGA or QFN packages, located between the FPGA and the backplane connector, receiving configuration commands through a dedicated control interface (such as I2C, SPI). For example, a high-speed signal switch chip supporting 16x16 or higher ports can be used, with bandwidth meeting the SerDes signal rate requirements (such as several Gbps or even higher). The second implementation method is to directly implement it on the PCB board using high-density wiring and a high-speed analog multiplexer array. This method is less expensive, but may sacrifice signal integrity and integration. The Local Bus implementation still relies on a high-performance instrument backplane, such as the backplane defined by the AXIe or PXIe standards, which provides multiple physical pairs of differential transmission lines, forming a "highway" for communication between boards. The innovation of this embodiment lies in providing flexible ramps for entering and exiting this "highway," rather than having only fixed entrances and exits as in existing technologies.

[0234] A deeper analysis of the technical details in the diagram further highlights the ingenuity of this embodiment. The "FPGA" and its "16T" configuration in the diagram indicate that the capabilities of the data source are fully utilized. The key lies in the newly introduced "link switching circuit" module. Its position in the signal chain—after the FPGA and before the backplane—is the core of its functionality. It acts as a "physical layer router." The connections from the FPGA to the link switching circuit, and from the link switching circuit to the backplane connector, are pre-laid in the PCB design. For example, the 16 transmit channels of the FPGA are physically connected to the 16 input ports of the link switching circuit, while the 32 (or more) output ports of the link switching circuit are respectively connected to the 16-Lane Local Bus interfaces leading to N-1 and N+1. This "fully connected" or "hyper-connected" physical routing is the basis for achieving flexibility. When the software configures the link switching circuit, it selects and activates the required connections within these pre-defined physical paths. In Scenario 1, the configuration establishes a direct path from the 16 inputs of the FPGA to the 16 outputs of N-1, i.e., a "16-lane local bus". This process involves purely analog signal switching, without the parsing and forwarding of digital messages, resulting in extremely low latency, which is crucial for measurement applications requiring precise time-delay synchronization. Compared to the fixed 8-lane connections in existing technologies, this solution achieves dynamic bandwidth aggregation through simple software configuration, doubling system performance and resolving the performance bottleneck caused by the limited number of connections in Scenario 1, without requiring any hardware modifications.

[0235] In some embodiments, the link switching circuit is specifically used for:

[0236] A physical connection is established between the target transmission line and at least two sets of candidate transmission lines. The established physical connection is used for the first sub-card module to fan out data to the connected at least two sets of candidate transmission lines.

[0237] The link switching circuit in this embodiment can also connect one set of target transmission lines to multiple sets of candidate transmission lines simultaneously, thereby enabling multicast or broadcast data transmission.

[0238] For example, the target transmission line can be used to carry the transmission of JESD204B / C protocol data. The target transmission line of the first sub-card module can be connected to the candidate transmission lines of multiple second sub-card modules at the same time through the link switching circuit. In this way, the first sub-card module can broadcast data through the transmission line and transmit data to multiple second sub-card modules at the same time, thereby improving data transmission efficiency.

[0239] like Figure 12The high-speed bus connection scheme shown allows the first daughter card module to simultaneously transmit the same sampled data to adjacent second daughter card modules 1 and 2. For example... Figure 12 In the system shown, the core components include a first daughter card module, a second daughter card module 1, a second daughter card module 2, and an FPGA and link switching circuit located on the first daughter card module. The first data transmission module of the first daughter card module (using the FPGA as an example) serves as the data source, with its 16 transmit channels (16T) outputting high-speed serial data. The link switching circuit, configured by software, implements the "fan-out" or "broadcast" function of the signals. It replicates the 16 input signals from the FPGA and simultaneously routes them to two different sets of output ports. The first set of output ports connects to the Local Bus leading to the second daughter card module 1, forming a complete 16-Lane data link; the second set of output ports simultaneously connects to the Local Bus leading to the second daughter card module 2, also forming another independent 16-Lane data link. Therefore, the FPGAs of the second daughter card module 1 and the second daughter card module 2 (both configured as 16R, i.e., 16 receive channels) can simultaneously receive identical 16-Lane full-bandwidth data streams from the first daughter card module. This solution effectively addresses the performance bottleneck in existing technologies, where physical connectivity limits the bandwidth provided to each target when broadcasting data, typically to only 8 lanes.

[0240] This embodiment utilizes the signal replication and routing capabilities of the link switching circuit to achieve high-bandwidth data broadcasting from one point to many. The system receives a configuration command requesting that data be simultaneously distributed from one source (the FPGA of the first daughter card module) to multiple destinations (the second daughter card module 1 and the second daughter card module 2). After processing by the link switching circuit, the output is two parallel high-speed data streams with the same bandwidth as the source signals. The detailed workflow is as follows: The host computer generates a configuration command based on the broadcast requirements and sends it to the link switching circuit controller on the first daughter card module. Upon receiving the command, the controller configures its internal switching matrix to broadcast mode. In this mode, the signal from each input port (one of the 16T channels from the FPGA) is simultaneously connected to two different output ports by the internal signal distribution network. For example, the 16T channel signal from the FPGA of the first daughter card module will be simultaneously driven by the link switching circuit to the 16R pins connected to the second daughter card module 1 and the second daughter card module 2. This process applies equally to all 16 channels. Therefore, the 16-Lane data stream emitted from the FPGA is "cloned" into two identical data streams after entering the link switching circuit, and then transmitted to two adjacent daughter card modules along pre-designed physical paths. Ultimately, both the FPGAs of the second daughter card module 1 and the second daughter card module 2 can receive data at full 16-Lane bandwidth, doubling the total throughput of the system in broadcast applications compared to existing technologies, greatly improving data distribution efficiency and overall system performance.

[0241] The implementation of the first daughter card module's FPGA remains unchanged, responsible for generating a 16-lane raw data stream. The key lies in the implementation of the link switching circuit. To achieve signal fan-out, the link switching circuit must internally include signal buffers or drivers to ensure that signal quality (such as voltage swing and slew rate) does not significantly degrade when driving two loads (i.e., the transmission lines to the second daughter card module 1 and the second daughter card module 2). Therefore, in this application, using an integrated crosspoint switch chip as the link switching circuit is a more ideal implementation. These chips typically have built-in programmable input equalization and output pre-emphasis / de-emphasis functions, and their output drivers are designed with sufficient drive capability to support a 1:2 or higher fan-out ratio. For example, a high-performance SerDes Re-timer or Crosspoint Switch chip will explicitly specify its fan-out capability in its specifications. When the controller is configured for broadcast mode, the chip's internal signal paths automatically activate the corresponding buffers and driver circuits, losslessly replicating the input signal to multiple output channels. The FPGA implementation of the second sub-card module 1 and the second sub-card module 2 is also straightforward. Simply configure their SerDes interface to 16-channel receive mode (16R) to correctly receive and process broadcast data.

[0242] like Figure 12 This demonstrates point-to-multipoint bandwidth-maintaining broadcast capability. This means that each SerDes signal emitted from the FPGA undergoes a "one-to-two" physical process within the link switching circuit. This is challenging to implement at the analog signal level, requiring precise impedance matching and signal power compensation, which is why integrated switching chips are the preferred solution. This programmable fan-out capability is completely impossible with fixed PCB traces. Related technologies, to achieve similar functionality, must copy data at the FPGA level and output it through two independent 8-lane SerDes IOs, consuming more FPGA resources and limiting the bandwidth of each broadcast to the physical connections of the 8-lanes. This embodiment achieves full-bandwidth data broadcasting with extremely low resource overhead and zero FPGA logic modification through an external physical layer device—the link switching circuit—fully demonstrating its significant value in enhancing system functionality and performance.

[0243] In some embodiments, the target transmission line group 1 includes multiple sub-target transmission lines, and the candidate transmission line group 1 includes multiple sub-candidate transmission lines, wherein the sub-target transmission line group 1 corresponds to the sub-candidate transmission line group 1; the multiple sub-target transmission lines are at least used to connect the sub-candidate transmission lines corresponding to multiple second sub-card modules respectively.

[0244] The link switching circuit is specifically used to: establish or disconnect the physical connection between the sub-target transmission line and the sub-candidate transmission line.

[0245] Here, the link switching circuit can establish or disconnect physical connections on a per-sub-candidate transmission line and / or per-sub-target transmission line basis.

[0246] In one possible implementation, the link switching circuit can establish a physical connection between all sub-target transmission lines in a set of target transmission lines and all sub-candidate transmission lines in a set of candidate transmission lines.

[0247] For example, the target transmission line includes M groups of sub-target transmission lines, and each group of candidate transmission lines includes M groups of sub-candidate transmission lines, where M is an integer greater than or equal to 2. The link switching circuit can select one group of candidate transmission lines and connect the target transmission line containing the M groups of sub-target transmission lines to the candidate transmission line containing the M groups of sub-candidate transmission lines in a one-to-one correspondence.

[0248] In this way, all the transmission bandwidth of the target transmission line of the first daughter card module can be used for data transmission with the second daughter card module corresponding to the selected candidate transmission line, thereby increasing the transmission rate between the first daughter card module and the rotating second daughter card module.

[0249] In one possible implementation, the link switching circuit can establish physical connections between I groups of sub-target transmission lines in one group of target transmission lines and J groups of sub-candidate transmission lines, respectively. Here, I is an integer greater than or equal to 2, and J is an integer greater than or equal to 2. I is greater than or equal to J. Here, the sub-target transmission lines and sub-candidate transmission lines can be physically connected in a one-to-one correspondence.

[0250] For example, the I group of sub-target transmission lines can establish physical connections with the 1 group of sub-candidate transmission lines in the J group of candidate transmission lines, and the 1 group of sub-target transmission lines can be connected to the 1 group of sub-candidate transmission lines in the J group of candidate transmission lines.

[0251] For example, group I sub-target transmission lines can establish physical connections with sub-candidate transmission lines in group J, where J is less than I. Group I sub-target transmission lines are connected to group I sub-candidate transmission lines in group I. Group i sub-target transmission lines in group I can establish physical connections with sub-candidate transmission lines i in group I in a one-to-one correspondence.

[0252] In this way, the first daughter card module can establish physical connections with multiple sets of second daughter card modules, and the first daughter card module can transmit data with multiple sets of second daughter card modules simultaneously.

[0253] In some embodiments, the first sub-card module further includes a second data transmission module;

[0254] The link switching circuit is used to connect the external transmission line used by the second data transmission module for data transmission;

[0255] The link switching circuit is also used to establish or disconnect the physical connection between the target transmission line and the external transmission line.

[0256] Here, data transmission between daughter card modules can be achieved via a backplane. Daughter card modules can also communicate with each other or with external systems via a second data transmission module mounted on the daughter card module. For example, the second data transmission module may include an optical communication module. The second data transmission module may include an external transmission interface for data transmission. The first data transmission module of the daughter card module can transmit data to an external transmission module via an external transmission line.

[0257] The external transmission line may include the transmission line between the second data transmission module and the link switching circuit. It is understood that, similar in shape to the target transmission line, the external transmission line can be used to carry a data bus.

[0258] In one possible implementation, the external transmission line may also include multiple sub-external transmission lines for connecting to the sub-target transmission line. Connecting a sub-external transmission line to a sub-target transmission line enables data transmission.

[0259] In one possible implementation, the link switching circuit is also used to establish or disconnect a physical connection between the sub-target transmission line and the external transmission line.

[0260] like Figure 13 This is a high-speed bus connection scheme. The requirement in this scenario is that the first daughter card module needs to send the data it collects or processes to other chassis via a second data transmission module, such as an optical data interface (ODI) optical communication module, while possibly maintaining connectivity with adjacent boards. Figure 13The architecture of the first daughter card module is demonstrated. Besides the core first data transmission module (such as an FPGA) and link switching circuit, it also integrates an ODI optical communication module. This ODI module itself requires a 16-lane SerDes interface to support high-speed fiber optic transmission. On the PCB design of the first daughter card module, the 16 transmit channels (16T) of the FPGA are connected to the input of the link switching circuit, while the output of the link switching circuit is connected not only to the Local Bus interfaces leading to the second daughter card module 1 and the second daughter card module 2, but also to the 16-lane SerDes input of the ODI module. By configuring the link switching circuit through software, the 16-lane data stream output from the FPGA can be completely routed to the ODI module. After receiving the electrical signal, the ODI module converts it into an optical signal and transmits it to external devices or a chassis via fiber optic cable. Meanwhile, the diagram also schematically preserves the connection relationship between the first sub-card module and other sub-card modules (such as the second sub-card module 1 and the second sub-card module 2), indicating that the configuration of the link switching circuit can be very flexible. For example, while sending data to ODI, the broadcast function of the link switching circuit can be used to send data to the second sub-card module 1 and the second sub-card module 2 at the same time.

[0261] This embodiment utilizes a link switching circuit to dynamically multiplex and flexibly schedule the limited SerDes IO resources of the FPGA across multiple physical interfaces. The system receives a configuration command that redirects the data stream from the FPGA to an onboard but non-backplane interface (ODI optical module). After processing by the link switching circuit, the output is a temporary, high-bandwidth physical connection established between the FPGA and the ODI module. The workflow is as follows: When the application requires fiber optic transmission, the host computer software sends a configuration command to the link switching circuit. The controller of the link switching circuit parses the command and adjusts its internal switching matrix, disconnecting any existing connections to the Local Bus (or retaining existing connections via broadcast), and instead establishing a path from the FPGA's 16T input port to the ODI module's 16-Lane output port. After the data stream is generated by the FPGA, it is directly fed into the ODI module for electro-optical conversion via the physical switching of the link switching circuit, and finally transmitted through the fiber optic link. This solution addresses a critical problem in existing technologies: when the number of SerDes I / Os on an FPGA is already full due to inter-board communication requirements, adding a new high-speed interface (such as ODI) is impossible in traditional designs unless a more expensive FPGA with more SerDes I / Os is replaced and the PCB routing is redesigned. This embodiment, however, pre-connects the ODI module to the link switching circuit on the PCB, making the optical interface a "backup" physical port that can be "activated" when needed through software configuration, greatly enhancing the scalability of the daughter card module.

[0262] The implementation methods for each module are as follows: The ODI optical communication module is typically an integrated optical transceiver module, such as a module in a standard package like CFP, QSFP, or SFP+. It internally contains components such as a laser driver, laser, photodiode, and transimpedance amplifier, responsible for converting high-speed electrical signals to optical signals. In the PCB design, the electrical interface of the ODI module (usually multiple pairs of differential lines) is physically connected to the output port of the link switching circuit. The implementation methods for the FPGA and link switching circuit are similar to the aforementioned scenario. In particular, the link switching circuit, as a multi-port cross-point switch, requires a sufficient number of input and output ports to accommodate all potential connections. For example, a link switching circuit chip with 32 inputs and 48 outputs can easily route the 16T inputs of the first daughter card module FPGA to 16 outputs of the second daughter card module 1, 16 outputs of the second daughter card module 2, or 16 outputs of the ODI module, depending on the configuration. This "over-configuration" of ports is the physical basis for interface multiplexing. The implementation of the control software requires a configuration manager that can automatically generate the corresponding link switching circuit configuration stream based on the user's selection (e.g., selecting "fiber optic output mode" on the GUI interface) and download it to the target module via the I2C / SPI bus.

[0263] At the physical level, the second data transmission module, like the Local Bus interface, is just one of many "devices" connected to the output of the link switching circuit. The link switching circuit acts as a "manager" or "allocator" of the FPGA's high-speed I / O resources. While the FPGA's "16T" resources are fixed, the "service objects" of these 16 channels become dynamically selectable with the help of the link switching circuit. When inter-board communication is needed, they serve the Local Bus; when remote fiber optic transmission is required, they switch to serving the ODI module. During the PCB design phase, various high-speed interfaces (inter-board, external optical ports, other RF interfaces, etc.) can be proactively connected to the link switching circuit, providing abundant "connection possibilities." In practical applications, users determine which "actual connection" is used at a given time through software configuration. This "software-defined hardware connection" model completely breaks free from the constraints of "one-time design, lifetime connection" in existing technologies, enabling single daughterboard modules to adapt to more diverse task requirements, extending product lifecycles, and significantly reducing hardware iteration costs due to functional changes.

[0264] In some embodiments, the link switching circuit is further configured to connect the downstream transmission line of the first data transmission module and the upstream transmission line of the system module.

[0265] The link switching circuit is also used to establish or disconnect the physical connection between the downstream transmission line and the upstream transmission line. The link switching circuit is located in the first daughter card module.

[0266] Here, the first daughter card module can be a peripheral module. The upstream transmission line can include the transmission line between the link switching circuit and the system module. The downstream transmission line can include the transmission line between the link switching circuit and the first data transmission module.

[0267] In one possible implementation, the downstream transmission line and the target transmission line can be the same transmission line.

[0268] In one possible implementation, the upstream transmission line includes one or more physical electrical connection lines. The upstream transmission line may include at least one of the following: one or more single-ended lines, one or more sets of differential lines.

[0269] In one possible implementation, the downstream transmission line includes one or more physical electrical connection lines. The downstream transmission line may include at least one of the following: one or more single-ended lines, one or more sets of differential lines.

[0270] In some embodiments, the upstream transmission line includes an upstream data bus; the downstream transmission line includes a downstream data bus.

[0271] For example, the upstream data bus may include PCIe, LAN, JESD204B / C, etc. Similarly, the downstream data bus may also include PCIe, LAN, JESD204B / C, etc.

[0272] In one possible implementation, the link switching circuit and system module may also include other electronic devices, such as bus transmission switching modules, signal coupling devices, and / or impedance matching devices.

[0273] In one possible implementation, the upstream transmission line can be the transmission line of the system module after being extended by the bus transmission switching module.

[0274] In one possible implementation, the upstream transmission line can be a transmission line connected to the system module.

[0275] The link switching circuit is used to establish a physical connection between the downstream transmission line and the upstream transmission line, connecting the system module and the first daughter card module, enabling the first data transmission module of the system module and the first daughter card module to transmit data.

[0276] For example, the upstream transmission line can be the PCIe data bus of the system module, which is extended by the PCIe switch on the backplane to form a PCIe transmission line. The downstream transmission line can be the PCIe transmission line of the first daughter card module. The link switching circuit establishes the physical connection between the downstream transmission line and the upstream transmission line so that the system module and the first daughter card module can use the PCIe data bus to transmit data.

[0277] In one possible implementation, the downstream transmission line may include all or part of the target transmission line.

[0278] In one possible implementation, the downstream transmission line (i.e., the target transmission line) can be configured as a different data bus, such as PCIe, LAN, or JESD204B / C.

[0279] The link switching circuit can disconnect the physical connection between the downstream transmission line and the upstream transmission line, and establish a connection between the downstream transmission line and the candidate transmission line, enabling the first daughter card module and at least one second daughter card module to transmit data.

[0280] For example, the downstream transmission line can be configured as a PCIe data bus or a JESD204B / C data bus. When the link switching circuit establishes the upstream and downstream transmission lines, the downstream transmission line can be configured as a PCIe data bus, and the system module and the first daughter card module can use the PCIe data bus for data transmission. When the link switching circuit disconnects the upstream and downstream transmission lines and establishes a physical connection between the downstream transmission line (i.e., the target transmission line) and the candidate transmission line, the downstream transmission line can be configured as a JESD204B / C data bus, and the first daughter card module and at least one second daughter card module can use the JESD204B / C data bus for data transmission.

[0281] Thus, by establishing or disconnecting the physical connection between the downstream transmission line and the upstream transmission line, the link switching circuit can improve the flexibility of the transmission line connection of the first daughter card module and meet the needs of different scenarios.

[0282] In some embodiments, the downstream transmission line includes multiple sets of sub-downstream transmission lines, and the upstream transmission line includes multiple sets of sub-upstream transmission lines; one set of downstream transmission lines corresponds to one set of upstream transmission lines.

[0283] The link switching circuit is also used to establish or disconnect at least one set of physical connections between the sub-downstream transmission lines and the sub-upstream transmission lines.

[0284] Here, the link switching circuit can establish or disconnect physical connections on a per-sub-upstream transmission line and / or per-sub-downstream transmission line basis.

[0285] One set of downstream transmission lines and one set of upstream transmission lines constitute a physical connection.

[0286] For example, downstream and upstream transmission lines can form a 16-lane PCIe bus, and each set of sub-downstream and sub-upstream transmission lines can form an 8-lane PCIe bus. A link switching circuit disconnects the physical connection between one set of sub-downstream and sub-upstream transmission lines to allow that sub-downstream transmission line to be configured for other purposes, while the physical connection between the other set of sub-downstream and sub-upstream transmission lines forms an 8-lane PCIe bus for data transmission between the system module and the first daughter card module.

[0287] Establishing or disconnecting physical connections on a per-sub-candidate transmission line and / or per-sub-target transmission line basis can improve the flexibility of transmission line configuration and adapt to the needs of different scenarios.

[0288] In some embodiments, the link switching circuit is specifically used to: establish or disconnect the physical connection between the target transmission line and the candidate transmission line based on switch configuration information;

[0289] The switch configuration information is sent from the system module to the link switching circuit via a control transmission line; or

[0290] The switch configuration information is determined by the first data transmission module based on business requirements and sent to the link switching circuit.

[0291] The link switching circuit may include a controller and a communication interface. The controller is used to control the switch matrix in the link switching circuit to establish or disconnect physical connections. The controller can communicate with the outside world through the communication interface located within the link switching circuit to obtain switch configuration information.

[0292] The control transmission line is connected to the communication interface to obtain switch configuration information from the system module and / or the first data transmission module.

[0293] In one possible implementation, switch configuration information can be used to indicate the connection relationship between at least two ports on a link switching circuit.

[0294] The system module can send switch configuration information to the link switching circuit via the communication interface. The switch configuration information can be determined by the first data transmission module based on current service requirements, such as data transmission target and data transmission rate.

[0295] Here, the control transmission line can include SPI, I2C, etc., and is not limited to these.

[0296] The switch configuration information allows for flexible configuration of the switch settings, enabling different connection methods for transmission lines and meeting the needs of various application scenarios.

[0297] In some embodiments, the link switching circuit further includes a signal repeater for performing signal compensation on the signals transmitted over the physical connection between the target transmission line and the candidate transmission line.

[0298] Signal repeaters can be configured based on the ports of link switching circuits. For example, a signal repeater can be configured for the output port of each link switching circuit.

[0299] In one possible implementation, a signal repeater is used to compensate for signal quality degradation caused by signal transmission on the transmission line.

[0300] When a signal is transmitted along a transmission line, its quality deteriorates, such as amplitude attenuation. Therefore, signal repeaters can be installed in link switching circuits to compensate for signal quality degradation.

[0301] For example, when the transmission path for high-speed signals is long, a signal repeater can be used. The link switching circuit compensates for signal attenuation in the high-frequency part through its internal equalization circuit, such as a continuous time linear equalization (CTLE), and restores the signal amplitude through amplification circuits (such as a limiting amplifier), thereby optimizing the eye diagram of the output signal and reducing the bit error rate.

[0302] In some embodiments, the link switching circuit is specifically used to control whether the signal repeater performs the signal compensation based on transmission configuration information.

[0303] Here, the controller in the link switching circuit can control whether the signal repeater performs the signal compensation based on the transmission configuration information.

[0304] In one possible implementation, transmission configuration information is used to indicate whether signal compensation is performed on at least one connection established by the link switching circuit.

[0305] For example, transmission configuration information can directly indicate whether signal compensation is required for the connection between port 1 and port 2 of the link switching circuit. This transmission configuration information can be sent to the controller by the system module or external devices via the communication interface.

[0306] In one possible implementation, the transmission configuration information is used to indicate at least one of the following: the type of signal transmitted (e.g., control signal, data signal, bus type, etc.) on at least one connection established by the link switching circuit; and the path length of the transmitted signal on at least one connection established by the link switching circuit. Based on the transmission configuration information, the controller can determine which transmission lines require signal compensation and which do not.

[0307] Different transmission lines have different effects on the signal. Generally, the length of the transmission line is positively correlated with its effect on the signal. If the transmission line is short, its effect on the signal is small, so no compensation is needed. However, since signal repeaters may introduce time delays when compensating for signal delays, they may not meet the required signal delay specifications.

[0308] Therefore, by controlling whether the signal repeater performs signal compensation through transmission configuration information, it is possible to adapt to different signal transmission conditions. On the one hand, signals that require compensation can be compensated, thereby optimizing the eye diagram of the output signal and reducing the bit error rate; on the other hand, signals that do not require compensation can be left uncompensated, reducing negative impacts on the signal and ensuring signal quality.

[0309] Similar to Embodiment 1, the first daughter card module can also have multiple link switching circuits. These multiple link switching circuits can form a hierarchical structure, such as a switching matrix structure or a tree structure. Multiple link switching circuits can form different topologies for constructing arbitrarily large-scale interconnect networks and / or expanding data buses, etc. The specific implementation is similar to Embodiment 1 and will not be repeated here.

[0310] Two specific examples are provided in conjunction with the above embodiments.

[0311] Example 1:

[0312] Figure 5A simplified model of a modular instrument backplane is disclosed, comprising a system slot, multiple peripheral slots (peripheral slot 1, peripheral slot 2, ... peripheral slot n), and PCIe and LAN switching chips. A core component, the link switching circuitry, sits between all these elements, acting as a central, programmable interconnect hub. The arrows and lines in the diagram illustrate its full interconnect capability: the high-speed bus of any peripheral slot can be configured via software using the link switching circuitry to either "pass through" its signals to the PCIe switching chip (implementing standard PCIe device functionality), to the LAN switching chip (implementing network device functionality), or, more importantly, directly to any other peripheral slot. This architecture breaks away from the fixed, discrete bus structure of traditional backplanes, bringing all high-speed links together on a unified, flexible, and adjustable physical switching plane, thus achieving true full interconnect.

[0313] The working logic of this application scheme is as follows: When the system initializes according to a specific test scenario, the host computer software or system controller generates a configuration file (switch configuration information) defining the entire backplane interconnect topology. This file is sent to the link switching circuit, which programs its internal connection matrix. For example, in a data acquisition and processing application, the following configuration can be made: a direct point-to-point high-speed streaming link (such as JESD204B / C) is established between peripheral slot 1 (ADC card) and peripheral slot 2 (FPGA card) via the link switching circuit; simultaneously, another part of the interface of peripheral slot 2 (FPGA card) is connected to peripheral slot 3 (memory card) via the link switching circuit, forming the next stage of the processing pipeline; peripheral slot 2 itself also requires a control channel, so a few of its interfaces are also configured to connect to the PCIe switching chip for communication with the system card. In this configuration, high-speed data streams are efficiently transmitted between the ADC, FPGA, and memory card without passing through the packet switching chip, while system control still takes place in the standard PCIe network. This ability to separate and customize the data plane and control plane at the physical layer is key to realizing high-performance, complex test systems.

[0314] This application implementation is based on the aforementioned link switching circuit core module and a novel backplane integrating this module. Peripheral slots are standard modular instrument connectors, as defined by PXIe or AXIe specifications. All high-speed differential signal pairs (Lanes) of each slot are routed to the ports of the link switching circuit. PCIe and LAN switching chips also act as "client" devices for the link switching circuit, with their ports connected to it. The system software needs to include a configuration management module for the link switching circuit. This module provides a user interface or API that allows engineers to define the connections between slots and the bandwidth of each slot connected to the PCIe / LAN bus according to test requirements. This software module is responsible for translating the user's logical connection requirements into specific configuration instructions for the internal registers of the link switching circuit and sending them out via interfaces such as SPI or I2C. For example, a user might drag a line on the graphical interface to connect Slot 1 and Slot 5, and the software automatically calculates the required internal crossover points of the link switching circuit and generates the corresponding control codes.

[0315] Its value lies in endowing modular instrument backplanes with unprecedented "software-defined hardware" capabilities. In traditional architectures, the physical topology of the backplane cannot be changed once it is designed and manufactured. In this solution, however, the physical topology becomes dynamically adaptable. This brings significant benefits: First, it increases asset reusability. The same chassis and backplane can be configured today as a large-scale PCIe computing cluster for data analysis; tomorrow, it can be reconfigured as a multi-channel RF transceiver test system, with each channel synchronizing and exchanging data via a high-speed streaming bus. Hardware investment is protected to the greatest extent. Second, it optimizes system performance. Engineers can establish the shortest, lowest-latency direct connections for critical paths based on the application's data flow characteristics, avoiding bottlenecks and uncertainties caused by packet switching chips, thereby pushing the overall system performance to its limit. For example, in a scenario requiring parallel processing of a signal, the output of an input module (Slot 1) can be broadcast simultaneously to multiple processing modules (Slots 2, 3, and 4) via a one-to-many (1 to N) distribution function of a link switching circuit. This achieves parallel distribution of data at the physical layer, a feat difficult to achieve efficiently by any upper-layer protocol. This fine-grained, software-based control of physical layer connections can adapt to the needs of complex test and measurement.

[0316] Example 2:

[0317] Figure 14This involves adding a link switching circuit to the existing packet-switched backplane, creating a parallel, configurable streaming interconnect layer. This hybrid architecture aims to balance compatibility with legacy systems and the streaming demands of new applications, making it particularly suitable for systems with a large number of slots. In this architecture, traditional PCIe switches and / or LAN switches remain, connected to the system card and all peripheral module slots (Slot 1...N), forming a basic packet-switched data and control plane. This ensures system compatibility with existing PXIe or AXIe ecosystems. Building upon this, this embodiment adds a link switching circuit in parallel. A portion of the high-speed I / O channels from each peripheral module slot are routed to the ports of this link switching circuit. Thus, each peripheral module has two sets of data interfaces: one connecting to the traditional packet-switched network and the other to the configurable streaming network.

[0318] The working logic of this hybrid architecture is ingenious. Routine control and non-real-time data transmission tasks can continue to utilize the mature and reliable PCIe / LAN packet switching network. For example, the system card uses the PCIe switch to configure and monitor the status of various peripheral modules, or perform file transfers. This part of the operation is exactly the same as existing technologies. However, when the system requires high-performance streaming data transmission that is latency-sensitive and requires deterministic synchronization, the system card configures a link switching circuit through the control bus to establish a direct, point-to-point physical link between the corresponding peripheral modules. For example, if Slot 2, acting as a signal acquisition card, needs to transmit massive amounts of ADC sampling data to Slot 5, acting as a signal processing card, the system can configure a link switching circuit to directly connect the reserved streaming channels on Slot 2 and Slot 5. These two modules can then use this private link to transmit data using JESD204B / C or other high-speed streaming protocols, completely bypassing the PCIe / LAN switching network with its uncertain latency. The advantage of this approach lies in its incremental innovation, which can "add" a powerful, flexible, high-performance data flow channel to the system while maintaining the stability and compatibility of the existing architecture. This not only meets the needs of the next generation of instruments but also reduces the risk and cost of completely overturning the existing design.

[0319] In terms of implementation, this hybrid approach offers greater flexibility. The backplane PCB design needs to accommodate both the traditional switching chip and the newly added link switching circuitry. On the connector of each peripheral module slot, pins need to be grouped: some pins connect to the PCIe_Switch or LAN_Switch according to the standard, while others are specifically reserved for the link switching circuitry. For example, a slot can allocate x4 bandwidth to the PCIe_Switch while reserving another x4 or x8 bandwidth for the link switching circuitry. The size of the link switching circuitry can be configured according to actual needs, unlike the first approach which requires covering all channels; it only needs to meet the potential streaming requirements of the system, which helps control costs. The design of the system card and peripheral modules also needs to support this dual-interface mode. Typically, this can be achieved by using an FPGA on the card, where the SerDes transceiver can be flexibly allocated to the PCIe hard core or user-defined streaming protocol logic. At the system software level, corresponding drivers and APIs need to be developed so that the application can recognize and control these two different data paths, selecting the optimal transmission method based on task characteristics.

[0320] This embodiment also discloses an electronic device, which includes the backplane and / or first daughter card module described in any of the above embodiments.

[0321] In one possible implementation, the electronic equipment includes modular measurement instruments such as oscilloscopes, logic analyzers, and network analyzers.

[0322] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0323] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A backsheet characterized by, The backboard is applied to a modular measuring instrument, and the backboard comprises a system slot, a peripheral slot and a link switching circuit; the system slot is used for connecting a system module, and the peripheral slot is used for connecting a peripheral module; The link switching circuit is used for connecting an upstream transmission line associated with the system module accessed through the system slot and connecting a downstream transmission line of the peripheral module accessed through the peripheral slot; The link switching circuit is further used for establishing or disconnecting physical connections between the upstream transmission line and the downstream transmission line and between downstream transmission lines corresponding to different peripheral modules; The physical connection between the upstream transmission line and the downstream transmission line is a protocol-agnostic physical connection; and / or The physical connection between the downstream transmission lines corresponding to the different peripheral modules is a protocol-agnostic physical connection; The peripheral module comprises a first subcard module and a second subcard module; The first subcard module is used for being coupled with the backboard through a first subcard slot on the backboard; the first subcard module comprises a first data transmission module and a first link switching circuit; The first link switching circuit is used for connecting a target transmission line of the first data transmission module and connecting at least two groups of candidate transmission lines, wherein the candidate transmission lines are used for coupling a second subcard module through the first subcard slot, each group of the candidate transmission lines corresponds to a second subcard slot, and the second subcard slot is used for coupling a second subcard module; the first link switching circuit is used for establishing or disconnecting physical connections between the target transmission line and the candidate transmission lines; The first link switching circuit is further used for establishing physical connections between I groups of sub-target transmission lines in one group of the target transmission lines and J groups of sub-candidate transmission lines in one group of the candidate transmission lines, one group of sub-target transmission lines is connected with one group of sub-candidate transmission lines in one group of the candidate transmission lines, I is an integer greater than or equal to 2, J is an integer greater than or equal to 2, and I is greater than or equal to J; the first link switching circuit is further used for establishing or disconnecting physical connections between the sub-target transmission lines and the sub-candidate transmission lines.

2. The backsheet of claim 1, wherein The link switching circuit is specifically used for at least one of the following: connecting a first upstream transmission line of the system module; connecting a second upstream transmission line, wherein the second upstream transmission line is obtained by expanding a third upstream transmission line corresponding to the system module through a transmission switching module.

3. The backsheet of claim 1, wherein The link switching circuit is specifically used for: establishing a first physical connection between one group of upstream transmission lines and at least two groups of downstream transmission lines, wherein the established first physical connection is used for the system module to fan out data to the connected at least two groups of downstream transmission lines; establishing a second physical connection between one group of first downstream transmission lines and at least two groups of second downstream transmission lines, wherein the established second physical connection is used for a first peripheral module corresponding to the first downstream transmission line to fan out data to the connected at least two groups of second downstream transmission lines; establish a third physical connection between a first group of downstream transmission lines, a first group of upstream transmission lines and at least one group of second downstream transmission lines, the established third physical connection being used for the first group of downstream transmission lines to fan out data to the connected first group of upstream transmission lines and the at least one group of second downstream transmission lines.

4. The backsheet of claim 1 wherein, The link switching circuit is specifically configured to: establish or disconnect the physical connection between the upstream transmission lines and the downstream transmission lines based on switch configuration information, and establish or disconnect the physical connection between the downstream transmission lines corresponding to different peripheral modules.

5. The backplane of claim 4, wherein The switch configuration information is sent by a system module to the link switching circuit through a control transmission line, and / or The switch configuration information is obtained by the link switching circuit from the outside through a communication interface.

6. The backplane of claim 1, wherein The link switching circuit further comprises a signal repeater configured to perform signal compensation on at least one of: signals transmitted on the physical connection between the upstream transmission lines and the downstream transmission lines; and signals transmitted on the physical connection between the downstream transmission lines corresponding to different peripheral modules.

7. The backplane of claim 6, wherein The link switching circuit is specifically configured to control the signal repeater to perform the signal compensation based on transmission configuration information.

8. The backplane of any one of claims 1 to 7, wherein The link switching circuit has M link switching circuits, and the M link switching circuits are divided into N layers, where N is a positive integer greater than or equal to 2, wherein each link switching circuit of an nth layer of link switching circuits is connected to at least one link switching circuit of an (n+1)th layer of link switching circuits, where n is a positive integer less than N, the number of link switching circuits of the nth layer is greater than or equal to the number of link switching circuits of the (n+1)th layer, the first layer of link switching circuits is configured to connect at least one of the upstream transmission lines and the downstream transmission lines, and the Nth layer of link switching circuits is configured to connect at least one of the upstream transmission lines and the downstream transmission lines.

9. The backsheet of claim 8, wherein, The number of link switching circuits of the nth layer is greater than the number of link switching circuits of the (n+1)th layer. Each link switching circuit of the (n+1)th layer of link switching circuits is connected to at least two link switching circuits of the nth layer of link switching circuits.

10. The backsheet according to any of claims 1 to 7, characterized in that The upstream transmission lines comprise an upstream data bus, and the downstream transmission lines comprise a downstream data bus.

11. An electronic device, comprising: The electronic device comprises the backplane of any one of claims 1 to 10.

Images