Generation method of configurable instruction interface circuit for satellite and universal board card thereof

Abstract

The invention discloses a generation method of a configurable instruction interface circuit for a satellite and a universal board card thereof, and belongs to the technical field of satellite circuits. The universal board card comprises a magnetic latching relay, an opening instruction access line, a closing instruction access line, an instruction bus access line, an instruction return line and a configuration line; the on instruction access line, the off instruction access line, the instruction bus access line and the instruction return line can be electrically mounted based on specific requirements, and the configuration line can be configured in a short circuit based on specific requirements, so that instruction interface circuits capable of meeting corresponding specific requirements can be formed in different electric mounting and configuration modes. According to the invention, various specific requirements can be met to ensure the universality of satellite instruction types.

Description

Technical Field

[0001] This invention relates to the field of satellite circuit technology, and in particular to a method for generating a configurable command interface circuit for satellites and a general-purpose board thereof. Background Technology

[0002] With the rapid development of spacecraft, the forms of command interface circuits are becoming increasingly diverse. Currently, there are three main types of satellite command interface circuits: 28V / 12V transmitter-follower command interface, OC command interface with a 28V command bus and a wide-range command bus from 20V to 100V, and 28V / 12V matrix command interface. The magnetic latching relay in the command interface circuit, driven by externally or internally transmitted command pulses, controls the power supply and disconnection of the powered products through the opening and closing of its contacts.

[0003] However, the command interface circuits on satellites at present can only meet one specific requirement and have poor versatility. Summary of the Invention

[0004] This invention provides a method for generating a configurable instruction interface circuit for space applications and a general-purpose board thereof. The technical solution is as follows:

[0005] On the one hand, a general-purpose board for a configurable command interface circuit for satellites is provided, including: a magnetic latching relay, an on command access line, an off command access line, a command bus access line, a command return line, and a configuration line;

[0006] The open command access line, close command access line, command bus access line, and command return line can be electrically installed based on specific requirements. In addition, the configuration line can be short-circuited based on specific requirements to form a command interface circuit that can meet the corresponding specific requirements under different electrical installation and configuration methods.

[0007] On the other hand, a method for generating a configurable command interface circuit for satellites is provided, including:

[0008] A general-purpose board that forms the configurable command interface circuit for satellites as described above is prefabricated, and the completed general-purpose board is verified.

[0009] The electrical assembly and configuration methods are determined based on the specific requirements to be met, and the instruction interface circuit is formed on the verified general-purpose board according to the determined electrical assembly and configuration methods.

[0010] The technical solution provided by this invention can bring at least the following beneficial effects:

[0011] By pre-fabricating PCBs to form a universal board and verifying it, when a satellite receives specific requirements for the command interface circuit, the electrical assembly and configuration of the PCB can be determined based on these specific requirements. The command interface circuit is then formed on the verified PCB based on the determined electrical assembly and configuration. This solution saves time on board fabrication and verification, allowing for direct electrical assembly and configuration according to specific needs, thus ensuring the universality of various satellite command types. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a circuit diagram of a general-purpose board for a configurable command interface circuit for satellites, provided in an embodiment of the present invention.

[0014] Figure 2 This is a circuit diagram of an emitter-follower command interface provided in an embodiment of the present invention;

[0015] Figure 3 This is a circuit diagram of a 28V / 12V command bus interface provided in an embodiment of the present invention;

[0016] Figure 4 This is a circuit diagram of a 20V to 100V wide-range command bus interface provided in an embodiment of the present invention;

[0017] Figure 5 This is a circuit diagram of a shoot-follower matrix instruction interface provided in an embodiment of the present invention;

[0018] Figure 6 This is a circuit diagram of an OC matrix instruction interface provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] This invention provides a general-purpose board for a configurable command interface circuit for satellites, comprising: a magnetic latching relay, an on command access line, an off command access line, a command bus access line, a command return line, and a configuration line;

[0021] The open command access line, close command access line, command bus access line, and command return line can be electrically installed based on specific requirements. In addition, the configuration line can be short-circuited based on specific requirements to form a command interface circuit that can meet the corresponding specific requirements under different electrical installation and configuration methods.

[0022] In this embodiment of the invention, by fabricating the above-mentioned circuits on a general-purpose board and electrically assembling and configuring the above-mentioned circuits according to specific requirements, an instruction interface circuit that can meet the corresponding specific requirements can be formed under different electrical assembly and configuration methods.

[0023] In order to meet the various command interface circuits currently used on satellites, in one embodiment of the present invention, the command interface circuit formed to meet the corresponding specific requirements includes at least: a transmitter follower command interface circuit, a bus OC command interface circuit, and a matrix command interface circuit.

[0024] Please refer to Figure 1 The circuit diagram is shown on a general-purpose board for the instruction interface circuit, where the above three instruction interface circuits can be formed. The instruction access lines are in three groups.

[0025] The first and second groups of open command access lines each include two first series circuits and a first current limiting circuit. Each first series circuit is formed by two diodes connected in series. The anode of the first diode is connected to the open command access terminal, the cathode of the second diode is connected to one end of the first current limiting circuit, and the other end of the first current limiting circuit is connected to the positive terminal of the magnetic latching relay open command coil.

[0026] The third group of open command access lines all include two second series circuits; each second series circuit is formed by two diodes connected in series, the cathode of the first diode is connected to the open command access terminal, and the anode of the second diode is connected to the negative terminal of the open command coil of the magnetic latching relay.

[0027] The access lines for the shutdown command are in three groups;

[0028] The first and second groups of the off command access lines both include two third series circuits and a second current limiting circuit. Each third series circuit is formed by two diodes connected in series. The anode of the first diode is connected to the off command access terminal, the cathode of the second diode is connected to one end of the second current limiting circuit, and the other end of the second current limiting circuit is connected to the positive terminal of the off command coil of the magnetic latching relay.

[0029] The third group of off command access lines all include two fourth series circuits; each fourth series circuit is formed by two diodes connected in series, the cathode of the first diode is connected to the off command access terminal, and the anode of the second diode is connected to the negative terminal of the off command coil of the magnetic latching relay.

[0030] The command bus access line includes a first resistor and a second resistor. One end of the first resistor is connected to the command bus access terminal, and the other end of the first resistor is connected to the connection terminal of the first series circuit and the first current limiting circuit in the first group of the open command access lines. One end of the second resistor is connected to the command bus access terminal, and the other end of the second resistor is connected to the connection terminal of the third series circuit and the second current limiting circuit in the first group of the close command access lines.

[0031] The configuration line includes two configuration resistors connected in series, and one end of the configuration line is connected to the negative terminal of the magnetic latching relay open command coil, and the other end of the configuration line is connected to the negative terminal of the magnetic latching relay close command coil.

[0032] The command return line includes a first isolation diode and a second isolation diode; the anodes of the first isolation diode and the second isolation diode are both connected to the connection terminals of two configuration resistors, the cathode of the first isolation diode is connected to the external command return line terminal, and the cathode of the second isolation diode is connected to the internal command return line terminal.

[0033] In one embodiment of the present invention, to improve the reliability of the instruction interface circuit, there can be multiple magnetic latching relays. Preferably, there are three magnetic latching relays, and the three magnetic latching relays are connected in a redundant series-parallel connection. The connection method of the three magnetic latching relays K1, K2 and K3 is as follows: Figure 1 As shown.

[0034] In one embodiment of the present invention, both the first current limiting circuit and the second current limiting circuit are formed by two current limiting resistors connected in parallel.

[0035] The following is based on Figure 1 The components included in each of the above circuits will be described.

[0036] In the first set of open command access lines, the first series circuit is formed by diodes D1A and D2A connected in series, and the first current limiting circuit is formed by current limiting resistors R1A and R2A connected in parallel; the second series circuit is formed by diodes D3A and D4A connected in series.

[0037] In the second set of open command access lines, the first series circuit is formed by diodes D5A and D6A connected in series, and the first current limiting circuit is formed by current limiting resistors R3A and R4A connected in parallel; the second series circuit is formed by diodes D7A and D8A connected in series.

[0038] In the third group of open command access lines, the first second series circuit is formed by diode D9A and diode D10A connected in series, and the second second series circuit is formed by diode D11A and diode D12A connected in series.

[0039] In the first set of access lines for the shutdown command, the first third series circuit is formed by diodes D13A and D14A connected in series, and the second current limiting circuit is formed by current limiting resistors R5A and R6A connected in parallel; the second third series circuit is formed by diodes D15A and D16A connected in series.

[0040] In the second set of access lines for the shutdown command, the first third series circuit is formed by diodes D17A and D18A connected in series, and the second current limiting circuit is formed by current limiting resistors R7A and R8A connected in parallel; the second third series circuit is formed by diodes D19A and D20A connected in series.

[0041] In the third group of access lines for the command, the first fourth series circuit is formed by diodes D21A and D22A connected in series, and the second fourth series circuit is formed by diodes D23A and D24A connected in series.

[0042] The command bus connection line includes a first resistor R11A and a second resistor R12A;

[0043] The configuration circuit includes configuration resistors R9A and R10A connected in series;

[0044] The command return line includes the first isolation diode D25A and the second isolation diode D26A;

[0045] The contacts of the three magnetic latching relays K1, K2, and K3 are connected in series and parallel with redundancy as follows:

[0046] Network G (including but not limited to the gate of the switching MOSFET, the DC / DC enable terminal EN, or the secondary power supply) is connected to the OFF1 and OFF2 contacts of the magnetic latching relay K1 and the OFF1 contact of the magnetic latching relay K2. The SW1 contact of the magnetic latching relay K1 is connected to the OFF2 contact of the magnetic latching relay K2. The SW2 contact of the magnetic latching relay K1 is connected to the OFF1 contact of the magnetic latching relay K3. The SW1 contact of the magnetic latching relay K2 is connected to the OFF2 contact of the magnetic latching relay K3. The SW2 contact of the magnetic latching relay K2 is connected to the SW1 and SW2 contacts of the magnetic latching relay K3 and network S (including but not limited to the source stage of the switching MOSFET, the DC / DC enable terminal EN return line, or the secondary power supply output).

[0047] In this series-parallel redundant connection method, if one of the magnetic latching relays fails, the other two magnetic latching relays can complete the command switch, thereby improving the reliability of the command interface circuit.

[0048] The following sections describe the instruction interface circuits that meet specific requirements under different electrical assembly and configuration methods.

[0049] Type 1: Command Follower Interface Circuit

[0050] In this embodiment of the invention, the electrical assembly and configuration of the emitter-follower command interface circuit are as follows:

[0051] Magnetic latching relay assembly; configuration resistors R9A and R10A are shorted;

[0052] In the first and second groups of the opening command access line electrical assembly, one diode on the first series circuit in the first and second groups of the opening command access line is short-circuited;

[0053] In the first and second groups of the power command access line electrical equipment, one diode on the third series circuit in the first and second groups of the power command access line is shorted;

[0054] Other components are not electrically assembled.

[0055] Through this electrical assembly and configuration method, it is possible to form such as Figure 2 The output follower command interface circuit shown is shown.

[0056] Figure 2 The principle of the emitter-follower command interface circuit shown is as follows:

[0057] 1) If it is an external command, the external command is input to the positive terminal of the magnetic latching relay coil through the current limiting resistor, and output from the negative terminal of the magnetic latching relay coil, flowing through diode D24A to the external command return line.

[0058] 2) If it is an internal command, the internal command is input to the positive terminal of the magnetic latching relay coil through the current limiting resistor, and output from the negative terminal of the magnetic latching relay coil, flowing through diode D25A to the internal command return line.

[0059] 3) If both external and internal commands exist simultaneously, different sets of current-limiting resistors are used to increase reliability. Specifically, external commands are input through commands 1 and 2, while internal commands are input through commands 3 and 4. External commands are input to the positive terminal of the magnetic latching relay coil through the current-limiting resistor and output from the negative terminal, flowing through diode D24A back to the external command return line. Internal commands are input to the positive terminal of the magnetic latching relay coil through the current-limiting resistor and output from the negative terminal, flowing through diode D25A back to the internal command return line. This achieves isolation between external and internal commands.

[0060] 4) If the instruction is a 28V pulse instruction, then the coil voltage of the magnetic latching relay in this embodiment of the invention includes, but is not limited to, 12V. Taking a magnetic latching relay with a coil voltage of 12V as an example, the voltage is divided to 12V through a current limiting resistor and a coil resistor to drive the magnetic latching relay.

[0061] 5) If the instruction is a 12V pulse instruction, then the coil voltage of the magnetic latching relay in this embodiment of the invention includes, but is not limited to, 12V. Taking a magnetic latching relay with a coil voltage of 12V as an example, the magnetic latching relay can be directly driven.

[0062] 6) If both 28V pulse command and 12V pulse command exist simultaneously, then in this embodiment of the invention, the coil voltage of the magnetic latching relay includes, but is not limited to, 12V. Taking a magnetic latching relay with a coil voltage of 12V as an example, the 28V pulse command and the 12V pulse command need to be connected to different current-limiting resistors to divide the voltage to 12V to drive the magnetic latching relay.

[0063] The second type: Busbar OC command interface circuit

[0064] In this embodiment of the invention, the bus OC command interface circuit includes two forms: one is a 28V / 12V command bus interface circuit, and the other is a 20V~100V wide-range bus OC command interface circuit. These two forms of bus OC command interface circuits will be described below.

[0065] In the first form, the bus OC command interface circuit is a 28V / 12V command bus interface circuit.

[0066] In this embodiment of the invention, the electrical assembly and configuration method for forming the 28V / 12V command bus interface circuit is as follows:

[0067] The magnetic latching relay electrical assembly; the command bus connection line electrical assembly;

[0068] The first current limiting circuit device in the first group of the open command access line, and the second current limiting circuit device in the first group of the close command access line;

[0069] The third group of opening command access line electrical assembly, in which a diode on the second series circuit of the third group of opening command access line is shorted;

[0070] The third group of the power-off command access line electrical equipment, in which a diode on the fourth series circuit of the third group of the power-off command access line is shorted;

[0071] Other components are not electrically assembled.

[0072] Through this electrical assembly and configuration method, it is possible to form such as Figure 3 The 28V / 12V command bus interface circuit shown is shown.

[0073] Figure 3 The principle of the 28V / 12V command bus interface circuit shown is as follows:

[0074] 1) If an external command is received, the command bus is input through the positive terminal of the magnetic latching relay coil and output from the negative terminal of the magnetic latching relay coil, flowing through diodes D9A, D11A, D22A, and D24A to the return lines of external command 5 and external command 6.

[0075] 2) If an internal instruction is received, the instruction bus is input through the positive terminal of the magnetic latching relay coil and output from the negative terminal of the magnetic latching relay coil, flowing through diodes D9A, D11A, D22A, and D24A to the return lines of internal instruction 5 and internal instruction 6.

[0076] 3) If both external and internal commands exist simultaneously, the command bus inputs through the positive terminal of the magnetic latching relay coil and outputs from the negative terminal, flowing through diode D9A to the external command / internal command return line. The command bus inputs through the positive terminal of the magnetic latching relay coil and outputs from the negative terminal, flowing through diode D11A to the internal command return line.

[0077] 4) If it is a 28V command bus, the coil voltage of the magnetic latching relay in this embodiment of the invention includes, but is not limited to, 28V. Taking a magnetic latching relay with a coil voltage of 28V as an example, the 28V command bus directly drives the magnetic latching relay.

[0078] 5) If it is a 12V command bus, the coil voltage of the magnetic latching relay in this embodiment of the invention includes, but is not limited to, 12V. Taking a magnetic latching relay with a 12V coil voltage as an example, the 12V command bus directly drives the magnetic latching relay.

[0079] In the first form, the bus OC command interface circuit is a 20V to 100V wide-range bus OC command interface circuit.

[0080] To implement a 20V–100V wide-range bus OC command interface circuit, please refer to the following embodiment of the present invention. Figure 1 It may also include: a primary bus access line; the primary bus access line includes two transistors Q1-Q2, six configuration resistors R1-R6, and two Zener diodes Z1-Z2; configuration resistors R1 and R2 are connected in parallel to form a first parallel circuit, one end of the first parallel circuit is connected to the primary bus access terminal, and the other end of the first parallel circuit is connected to the cathode of Zener diode Z1 and the base of transistor Q1, and the anode of Zener diode Z1 is connected to the negative terminal of the magnetic latching relay opening command coil; configuration resistors R3 and R4 are connected in parallel to form a second parallel circuit, one end of the second parallel circuit is connected to The circuit is connected to the primary bus input terminal. The other end of the second parallel circuit is connected to the collector of transistor Q1 and the collector of transistor Q2. The emitter of transistor Q1 is connected to the positive terminal of the magnetic latching relay open command coil. Resistors R5 and R6 are connected in parallel to form a third parallel circuit. One end of the third parallel circuit is connected to the primary bus input terminal. The other end of the third parallel circuit is connected to the cathode of Zener diode Z2 and the base of transistor Q2. The anode of Zener diode Z2 is connected to the negative terminal of the magnetic latching relay close command coil. The emitter of transistor Q2 is connected to the positive terminal of the magnetic latching relay close command coil.

[0081] In one implementation, this primary bus can also be the command bus;

[0082] Among them, Zener diodes Z1 and Z2 can be selected to match the coil voltage of the magnetic latching relay.

[0083] Therefore, the electrical assembly and configuration method for forming a 20V~100V wide-range command bus interface circuit in this embodiment of the invention is as follows:

[0084] Electrical assembly for magnetic latching relays; electrical assembly for primary busbar connection lines;

[0085] The third group of opening command access line electrical assembly, in which a diode on the second series circuit of the third group of opening command access line is shorted;

[0086] The third group of the power-off command access line electrical equipment, in which a diode on the fourth series circuit of the third group of the power-off command access line is shorted;

[0087] Other components are not electrically assembled.

[0088] Through this electrical assembly and configuration method, it is possible to form such as Figure 4 The circuit shown is a 20V to 100V wide-range command bus interface circuit.

[0089] Figure 4 The principle of the 20V~100V wide-range command bus interface circuit shown is as follows:

[0090] 1) If it is an external command, the command bus / primary bus is input through current limiting resistors R1-R6, transistors Q1 and Q2, and the positive terminal of the magnetic latching relay coil. It is output from the negative terminal of the magnetic latching relay coil and flows through diodes D9A, D11A, D22A, and D24A to the return line of the external command.

[0091] 2) If it is an internal instruction, the instruction bus / primary bus is input through current-limiting resistors R1-R6, transistors Q1 and Q2, the positive terminal of the magnetic latching relay coil, and output through the negative terminal of the magnetic latching relay coil. The current flows through diodes D9A, D11A, D22A, and D24A to the return line of the internal instruction.

[0092] 3) If both external and internal commands exist simultaneously, the command bus / primary bus receives input from the positive terminals of transistors Q1 and Q2 and the magnetic latching relay coil through current-limiting resistors R1-R6, and outputs from the negative terminal of the magnetic latching relay coil. The current flows through diodes D9A and D22A to the return line of the external command. The command bus / primary bus receives input from the positive terminals of transistors Q1 and Q2 and the magnetic latching relay coil through current-limiting resistors R1-R6, and outputs from the negative terminal of the magnetic latching relay coil. The current flows through diodes D11A and D24A to the return line of the internal command.

[0093] 4) The command bus is a wide range bus of 20V to 100V. In this embodiment of the invention, the coil voltage of the magnetic latching relay includes, but is not limited to, 12V. Taking a magnetic latching relay with a coil voltage of 12V as an example, the command bus provides the working current to the Zener diodes Z1 and Z2 through resistors R1 and R2, R5 and R6. Zener diodes Z1 and Z2 are selected as 13V Zener diodes. The voltage at the positive and negative terminals of the coil is clamped to 13V minus the Ube voltage of the transistor. The current limiting resistors R3 and R4 ensure that the voltage is higher than 13V minus the Ube voltage of the transistor through the voltage division of the relay coil.

[0094] The third type: matrix instruction interface circuit

[0095] In this embodiment of the invention, the matrix instruction interface circuit includes two forms: one is a shoot-follower matrix instruction interface circuit, and the other is an OC matrix instruction interface circuit. These two forms of matrix instruction interface circuits will be described below.

[0096] In the first form, the matrix instruction interface circuit is a shoot-follow matrix instruction interface circuit.

[0097] In this embodiment of the invention, the electrical assembly and configuration method for forming the emitter-follower matrix instruction interface circuit is as follows:

[0098] Magnetic latching relay electrical assembly;

[0099] The first and second groups describe the electrical equipment for accessing the line with the opening command; the first and second groups describe the electrical equipment for accessing the line with the closing command.

[0100] The configuration line and the instruction return line are electrically connected, and the configuration resistor R9A and the configuration resistor R10A are shorted.

[0101] Other components are not electrically assembled.

[0102] Through this electrical assembly and configuration method, it is possible to form such as Figure 5 The illustrated shot-follower matrix instruction interface circuit.

[0103] Figure 5 The principle of the emitter-follower matrix instruction interface circuit shown is as follows:

[0104] 1) If it is a row-column matrix instruction in the shoot-follower matrix instruction, the instruction pulse is input through the current limiting resistors R1A and R2A, R5A and R6A, the positive terminal of the magnetic latching relay coil, and the negative terminal of the magnetic latching relay coil is output to the instruction return line.

[0105] 2) If it is a multi-row, one-column matrix instruction in the shoot-follow matrix instruction, taking two rows and one column as an example, instruction pulse 1 is input through current limiting resistors R1A and R2A, R5A and R6A, the positive terminal of the magnetic latching relay coil is input, and the negative terminal of the magnetic latching relay coil is output to the instruction return line. Instruction pulse 2 is input through current limiting resistors R3A and R4A, R7A and R8A, the positive terminal of the magnetic latching relay coil is input, and the negative terminal of the magnetic latching relay coil is output to the instruction return line.

[0106] In the first form, the matrix instruction interface circuit is an OC matrix instruction interface circuit;

[0107] In this embodiment of the invention, the electrical assembly and configuration method for forming the OC matrix instruction interface circuit is as follows:

[0108] The magnetic latching relay electrical assembly; the command bus connection line electrical assembly;

[0109] The first current limiting circuit device in the first group of the open command access line, and the second current limiting circuit device in the first group of the close command access line;

[0110] The third group of electrical installations for the open command access line includes a diode in the second series circuit of the open command access line that is short-circuited; the third group of electrical installations for the close command access line includes a diode in the fourth series circuit of the close command access line that is short-circuited.

[0111] Other components are not electrically assembled.

[0112] Through this electrical assembly and configuration method, it is possible to form such as Figure 6 The OC matrix instruction interface circuit shown.

[0113] Figure 6 The principle of the OC matrix instruction interface circuit shown is as follows:

[0114] 1) If it is a row-column matrix instruction in the OC matrix instruction, the instruction bus is input through the positive terminal of the magnetic latching relay coil and output through the negative terminal of the magnetic latching relay coil. It then passes through diode D9A to D22A to the return line of the external instruction.

[0115] 2) For a single-row, multi-column matrix instruction in an OC matrix instruction, taking one row and multiple columns as an example, the instruction bus is input through the positive terminal of the magnetic latching relay coil, output through the negative terminal of the magnetic latching relay coil, and goes through diode D9A to the return line of external instruction 5, and through diode D22A to the return line of off instruction 5. Similarly, the instruction bus is input through the positive terminal of the magnetic latching relay coil, output through the negative terminal of the magnetic latching relay coil, and goes through diode D11A to the return line of external instruction 6, and through diode D24A to the return line of off instruction 6.

[0116] The above describes the electrical assembly and configuration methods for different instruction interface circuits.

[0117] The embodiments of the present invention have at least the following beneficial effects:

[0118] 1. It has greater versatility, and can realize at least three mainstream satellite command interface circuits through different electrical installations and configurations.

[0119] 2. Wider compatibility: Each high-reliability command interface, through configuration, is compatible with various application conditions. For example, the high-reliability emitter-follower configuration command interface circuit can simultaneously receive 28V and 12V pulse commands, and can simultaneously receive external and internal commands. Isolation between internal and external commands is achieved through isolation diodes D24A and D25A. The high-reliability OC configuration command interface circuit is compatible with 28V command buses and a wide range of 20V to 100V command buses or primary buses, and can simultaneously receive external and internal commands. The high-reliability matrix configuration command interface circuit can simultaneously receive 28V or 12V pulse commands, and can also receive multiple pulse commands simultaneously.

[0120] 3. Higher reliability: All components adopt redundant design, and the failure of a single component will not affect the function of the command interface circuit, greatly improving the reliability of the satellite command circuit.

[0121] Secondly, embodiments of the present invention also provide a method for generating a configurable command interface circuit for satellites, the method comprising:

[0122] A general-purpose board for configurable command interface circuitry for satellites, as described above, is prefabricated, and the completed general-purpose board is verified.

[0123] The electrical assembly and configuration methods are determined based on the specific requirements to be met, and the instruction interface circuit is formed on the verified general-purpose board according to the determined electrical assembly and configuration methods.

[0124] Since general-purpose boards have manufacturing and verification cycles, if the board is manufactured and verified only after receiving specific requirements, it will require a long manufacturing and verification cycle, reducing the production efficiency of instruction interface circuits. Therefore, by manufacturing and verifying in advance, when specific requirements are received, the instruction interface circuit can be formed on the verified general-purpose board according to the electrical assembly and configuration method of the specific requirements, thus improving the production efficiency of instruction interface circuits that meet specific requirements.

[0125] It should be noted that, in this document, relational terms such as first, second, third, and fourth are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0126] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A general-purpose board for a configurable command interface circuit used in satellites, characterized in that, include: Magnetic latching relay, open command access line, close command access line, command bus access line, command return line, and configuration line; The open command access line, close command access line, command bus access line, and command return line can be electrically installed based on specific requirements. In addition, the configuration line can be short-circuited based on specific requirements to form a command interface circuit that can meet the corresponding specific requirements under different electrical installation and configuration methods.

2. The universal board for a configurable command interface circuit for satellites according to claim 1, characterized in that, The resulting instruction interface circuit that can meet specific requirements includes at least: an emitter-follower instruction interface circuit, a bus OC instruction interface circuit, and a matrix instruction interface circuit.

3. The universal board for a configurable command interface circuit for satellites according to claim 2, characterized in that, The open command access lines consist of three groups; The first and second groups of open command access lines each include two first series circuits and a first current limiting circuit. Each first series circuit is formed by two diodes connected in series. The anode of the first diode is connected to the open command access terminal, the cathode of the second diode is connected to one end of the first current limiting circuit, and the other end of the first current limiting circuit is connected to the positive terminal of the magnetic latching relay open command coil. The third group of open command access lines all include two second series circuits; each second series circuit is formed by two diodes connected in series, the cathode of the first diode is connected to the open command access terminal, and the anode of the second diode is connected to the negative terminal of the open command coil of the magnetic latching relay. The shutdown command access lines consist of three groups; The first and second groups of the off command access lines both include two third series circuits and a second current limiting circuit. Each third series circuit is formed by two diodes connected in series. The anode of the first diode is connected to the off command access terminal, the cathode of the second diode is connected to one end of the second current limiting circuit, and the other end of the second current limiting circuit is connected to the positive terminal of the off command coil of the magnetic latching relay. The third group of off command access lines all include two fourth series circuits; each fourth series circuit is formed by two diodes connected in series, the cathode of the first diode is connected to the off command access terminal, and the anode of the second diode is connected to the negative terminal of the off command coil of the magnetic latching relay. The command bus access line includes a first resistor and a second resistor. One end of the first resistor is connected to the command bus access terminal, and the other end of the first resistor is connected to the connection terminal of the first series circuit and the first current limiting circuit in the first group of the open command access lines. One end of the second resistor is connected to the command bus access terminal, and the other end of the second resistor is connected to the connection terminal of the third series circuit and the second current limiting circuit in the first group of the close command access lines. The configuration line includes two configuration resistors connected in series, and one end of the configuration line is connected to the negative terminal of the magnetic latching relay open command coil, and the other end of the configuration line is connected to the negative terminal of the magnetic latching relay close command coil. The command return line includes a first isolation diode and a second isolation diode; the anodes of the first isolation diode and the second isolation diode are both connected to the connection terminals of two configuration resistors, the cathode of the first isolation diode is connected to the external command return line terminal, and the cathode of the second isolation diode is connected to the internal command return line terminal.

4. The universal board for a configurable command interface circuit for satellites according to claim 3, characterized in that, The electrical assembly and configuration method for forming the emitter-follower command interface circuit is as follows: A magnetic latching relay is installed; the two configuration resistors in the configuration circuit are shorted. In the first and second groups of the opening command access line electrical assembly, one diode on the first series circuit in the first and second groups of the opening command access line is short-circuited; In the first and second groups of the power command access line electrical equipment, one diode on the third series circuit in the first and second groups of the power command access line is shorted; Other components are not electrically assembled.

5. The universal board for a configurable command interface circuit for satellites according to claim 3, characterized in that, The bus OC command interface circuit is a 28V / 12V command bus interface circuit; The electrical assembly and configuration method for forming the 28V / 12V command bus interface circuit is as follows: The magnetic latching relay electrical assembly; the command bus connection line electrical assembly; The first current limiting circuit device in the first group of the open command access line, and the second current limiting circuit device in the first group of the close command access line; The third group of opening command access line electrical assembly, in which a diode on the second series circuit of the third group of opening command access line is shorted; The third group of the power-off command access line electrical equipment, in which a diode on the fourth series circuit of the third group of the power-off command access line is shorted; Other components are not electrically assembled.

6. The universal board for a configurable command interface circuit for satellites according to claim 3, characterized in that, Also includes: A primary busbar access line is provided; the primary busbar access line includes two transistors Q1-Q2, six configuration resistors R1-R6, and two Zener diodes Z1-Z2; configuration resistors R1 and R2 are connected in parallel to form a first parallel circuit, one end of which is connected to the primary busbar access terminal, and the other end of which is connected to the cathode of Zener diode Z1 and the base of transistor Q1; the anode of Zener diode Z1 is connected to the negative terminal of the magnetic latching relay open command coil; configuration resistors R3 and R4 are connected in parallel to form a second parallel circuit, one end of which is connected to the primary busbar access terminal. At the bus input terminal, the other end of the second parallel circuit is connected to the collector of transistor Q1 and the collector of transistor Q2. The emitter of transistor Q1 is connected to the positive terminal of the magnetic latching relay open command coil. Resistors R5 and R6 are connected in parallel to form a third parallel circuit. One end of the third parallel circuit is connected to the primary bus input terminal, and the other end of the third parallel circuit is connected to the cathode of Zener diode Z2 and the base of transistor Q2. The anode of Zener diode Z2 is connected to the negative terminal of the magnetic latching relay close command coil, and the emitter of transistor Q2 is connected to the positive terminal of the magnetic latching relay close command coil. The bus OC command interface circuit is a 20V to 100V wide-range bus OC command interface circuit. The electrical assembly and configuration method for forming a 20V~100V wide-range command bus interface circuit is as follows: Electrical assembly for magnetic latching relays; electrical assembly for primary busbar connection lines; The third group of opening command access line electrical assembly, in which a diode on the second series circuit of the third group of opening command access line is shorted; The third group of the power-off command access line electrical equipment, in which a diode on the fourth series circuit of the third group of the power-off command access line is shorted; Other components are not electrically assembled.

7. The universal board for a configurable command interface circuit for satellites according to claim 3, characterized in that, The matrix instruction interface circuit is a shoot-follower matrix instruction interface circuit; The electrical assembly and configuration method for forming the emitter-follower matrix instruction interface circuit is as follows: Magnetic latching relay electrical assembly; The first and second groups describe the electrical equipment for accessing the line with the opening command; the first and second groups describe the electrical equipment for accessing the line with the closing command. The configuration line and the instruction return line are electrically connected, and the configuration resistor R9A and the configuration resistor R10A are shorted. Other components are not electrically assembled.

8. The universal board for a configurable command interface circuit for satellites according to claim 3, characterized in that, The matrix instruction interface circuit is an OC matrix instruction interface circuit; The electrical assembly and configuration method for forming the OC matrix instruction interface circuit is as follows: The magnetic latching relay electrical assembly; the command bus connection line electrical assembly; The first current limiting circuit device in the first group of the open command access line, and the second current limiting circuit device in the first group of the close command access line; The third group of electrical installations for the open command access line includes a diode in the second series circuit of the open command access line that is short-circuited; the third group of electrical installations for the close command access line includes a diode in the fourth series circuit of the close command access line that is short-circuited. Other components are not electrically assembled.

9. The universal board for a configurable command interface circuit for satellites according to any one of claims 3-8, characterized in that, There are three magnetic latching relays, and the three magnetic latching relays are connected in a redundant series-parallel connection. And / or, Both the first current limiting circuit and the second current limiting circuit are formed by two current limiting resistors connected in parallel.

10. A method for generating a configurable command interface circuit for satellites, characterized in that, include: A general-purpose board for satellite configurable command interface circuit as described in claim 3 is prefabricated, and the completed general-purpose board is verified. The electrical assembly and configuration methods are determined based on the specific requirements to be met, and the instruction interface circuit is formed on the verified general-purpose board according to the determined electrical assembly and configuration methods.

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