Chip temperature management method, computer program product, electronic device and storage medium

Abstract

The invention discloses a chip temperature management method, a computer program product, electronic equipment and a computer readable storage medium, and the method comprises the steps: obtaining a pre-constructed first incidence relation if a packaging technology of a to-be-adjusted packaging structure of a target chip belongs to a packaging technology of a preset type, constructing a target heat conduction equation based on the first incidence relation; the first incidence relation is the incidence relation among the heat transfer coefficient, the environment temperature and the chip power; and calculating the junction-to-environment thermal resistance of the to-be-adjusted packaging structure by using the target heat conduction equation so as to adjust the design information of the to-be-adjusted packaging structure based on the junction-to-environment thermal resistance, thereby realizing temperature management of the target chip. The time consumption of the thermal resistance calculation process can be reduced, and the calculation efficiency is improved, so that the design iteration speed of the chip packaging structure is accelerated, and efficient temperature management of the chip is realized.

Description

Technical Field

[0001] This application relates to the field of chip temperature management, and more particularly to a chip temperature management method, a computer program product, an electronic device, and a computer-readable storage medium. Background Technology

[0002] In the field of chip packaging design, thermal management is one of the core aspects of ensuring chip reliability and performance. The thermal resistance characteristics of the chip package structure are related to the chip's operating temperature, and the junction-to-environment thermal resistance of the chip package structure, as a key evaluation indicator of thermal resistance characteristics, characterizes the heat dissipation capability from the chip junction region to the environment within the chip package structure. During the design and optimization process of the chip package structure, engineers need to frequently calculate the junction-to-environment thermal resistance of different design schemes, and iteratively adjust the structural layout, geometric parameters, and materials of the chip package structure based on the calculation results to meet thermal reliability constraints and optimize thermal performance, thereby achieving management of the chip's operating temperature.

[0003] However, the existing thermal resistance calculation process is time-consuming and inefficient, which restricts the design iteration speed of chip packaging structure and results in low temperature management efficiency of the chip. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a chip temperature management method, a computer program product, an electronic device, and a computer-readable storage medium, the technical solutions of which are as follows:

[0005] According to a first aspect of this application, a chip temperature management method is provided, the method comprising:

[0006] If the packaging process of the target chip's packaging structure to be adjusted belongs to a preset type of packaging process, then a pre-constructed first correlation is obtained, and a target heat conduction equation is constructed based on the first correlation; the first correlation is the correlation between the heat transfer coefficient and the ambient temperature and the chip power;

[0007] The junction-to-ambient thermal resistance of the package structure to be adjusted is calculated using the target heat conduction equation, and the design information of the package structure to be adjusted is adjusted based on the junction-to-ambient thermal resistance to achieve temperature management of the target chip.

[0008] The first association relationship is constructed in the following way:

[0009] A thermal simulation model is constructed based on the design information related to the initial packaging structure of the initial chip, and a standard heat conduction equation is determined for the thermal simulation model. The initial packaging structure adopts the preset type of packaging process.

[0010] A second correlation between heat transfer coefficient and thermal resistance is obtained by fitting the standard heat conduction equation.

[0011] Using multiphysics simulation software, the thermal resistance of the thermal simulation model under several given simulation parameters is simulated to obtain several simulated thermal resistances; the simulation parameters include ambient temperature and chip power.

[0012] Based on the second correlation, the simulation parameters, and the simulation thermal resistance, the first correlation is fitted.

[0013] According to a second aspect of this application, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the method as described in the first aspect.

[0014] According to a third aspect of this application, an electronic device is provided, the electronic device comprising:

[0015] processor;

[0016] Memory used to store processor-executable instructions;

[0017] The processor is configured to implement the method as described in the first aspect.

[0018] According to a fourth aspect of this application, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method as described in the first aspect.

[0019] The technical solution provided in this application, for chip packaging structures belonging to the same type of packaging technology, pre-constructs a heat transfer coefficient (first correlation relationship) that can approximately represent the influence of fluids on chip heat dissipation (such as the influence of gases, liquids, etc.) during the design information iteration of the packaging structure. This influence of fluids on chip heat dissipation is obtained by simulating the initial packaging structure using the same type of packaging technology using existing multiphysics simulation software (such as ANSYS Icepak). That is, the process of determining this equivalent heat transfer coefficient (first correlation relationship) only needs to be performed once for the same type of packaging technology. When facing other packaging structures belonging to the same type of packaging technology (such as when the design information changes but the type of packaging technology remains unchanged), it can be reused to construct the corresponding heat conduction equation, and then the thermal resistance is calculated through the constructed heat conduction equation. It is not necessary to repeatedly rely on CFD software to simulate the influence of fluids on chip heat dissipation when the design information changes, thereby reducing the time consumption of the thermal resistance calculation process, improving the calculation efficiency, and thus accelerating the design iteration speed of chip packaging structures and realizing efficient temperature management of chips.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0022] Figure 1 This is a schematic diagram illustrating a specific application scenario of the related technology;

[0023] Figure 2 This is a schematic diagram of another specific application scenario of the related technology;

[0024] Figure 3 This is a schematic flowchart of a chip temperature management method according to an embodiment of this application;

[0025] Figure 4 This is a schematic diagram of the structure of a thermal simulation model according to an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art should fall within the scope of protection of this application.

[0028] In the field of chip packaging design, thermal management is one of the core aspects of ensuring chip reliability and performance. The thermal resistance characteristics of the chip package structure are related to the chip's operating temperature, and the junction-to-environment thermal resistance of the chip package structure is a key evaluation indicator of thermal resistance characteristics. It characterizes the heat dissipation capability from the chip junction region to the environment in the chip package structure. The chip junction region (usually called the PN junction region or space charge region) is a special region formed at the interface between P-type and N-type semiconductors. Its core function is to control the movement of charge carriers and realize functions such as unidirectional conductivity of semiconductor devices. As the core functional unit of semiconductor devices, the chip junction region can be customized to meet diverse needs from high-frequency switching to high-power withstand voltage by precisely controlling the depletion layer width, built-in electric field, and doping concentration. Its physical characteristics directly determine the performance boundary of the chip and are a key link in the "microscopic manipulation of the macroscopic" in semiconductor technology.

[0029] During the design and optimization of chip packaging structures, engineers need to frequently calculate the junction-to-environment thermal resistance of different design schemes. Based on the calculation results, they iteratively adjust the structural layout, geometric parameters, and materials of the chip packaging structure to meet thermal reliability constraints and optimize thermal performance, thereby managing the chip's operating temperature.

[0030] However, the existing thermal resistance calculation process is time-consuming and inefficient, which restricts the design iteration speed of chip packaging structure and results in low temperature management efficiency of the chip.

[0031] Specifically, such as Figure 1 As shown in the related technologies, a typical chip packaging structure can be composed of multiple layers of different materials stacked together. Its heat conduction path is relatively complex. Furthermore, during the design and optimization process of the chip packaging structure, it is impossible to measure the junction-to-environment thermal resistance of the chip packaging structure through actual experiments during the iterative adjustment stage of the chip packaging structure.

[0032] like Figure 2 As shown, related technologies typically rely on Computational Fluid Dynamics (CFD) software for finite element simulation analysis of chip packaging structures. CFD software is a specialized tool for solving physical processes such as fluid flow, heat transfer, and chemical reactions using numerical methods. Its core is to discretize fluid dynamics governing equations (such as the Navier-Stokes equations) and perform computer simulations. The core structure of CFD software can include: a preprocessing module for constructing geometric models and meshing, generating computational domains, and importing CAD models to optimize the discretization of complex geometries; a solver module for solving based on the laws of conservation of mass, momentum, and energy, combined with turbulence models (such as k-ε, LES) or chemical reaction models; and a post-processing module for visualizing parameters such as velocity, temperature, and pressure fields, generating streamline diagrams, contour plots, and animations, and supporting quantitative analysis (such as flow statistics and heat flux calculations).

[0033] In related technologies, finite element simulation analysis of chip packaging structures using CFD software requires repeated modeling and meshing of the entire standard test environment, including the air, whenever the design information of the chip packaging structure changes. This necessitates solving heat conduction and fluid dynamics equations within this environment. While CFD simulation analysis offers high accuracy, the process is time-consuming, and fluid dynamics simulations in CFD software often fail to converge. For the chip packaging structure design optimization phase, where rapid feasibility determination of the design scheme is crucial, frequent and repeated use of CFD simulation analysis cannot meet the computational efficiency requirements of engineering timelines, thus hindering efficient management of chip temperature.

[0034] To address the aforementioned problems, this application provides a chip temperature management method that reduces the time spent on thermal resistance calculation, improves computational efficiency, thereby accelerating the design iteration speed of chip packaging structures and achieving efficient chip temperature management. For example... Figure 3 As shown, the method includes the following steps:

[0035] S301. If the packaging process of the target chip's packaging structure to be adjusted belongs to a preset type of packaging process, then obtain the pre-built first correlation relationship and construct the target heat conduction equation based on the first correlation relationship.

[0036] The first correlation is the relationship between the heat transfer coefficient and the ambient temperature and the chip power.

[0037] S302. Calculate the junction-to-ambient thermal resistance of the package structure to be adjusted using the target heat conduction equation, and adjust the design information of the package structure to be adjusted based on the junction-to-ambient thermal resistance to achieve temperature management of the target chip.

[0038] The first association relationship is constructed in the following way:

[0039] A thermal simulation model is constructed based on design information related to the initial packaging structure of the initial chip, and a standard heat conduction equation is determined for the thermal simulation model. The initial packaging structure adopts the preset type of packaging process. A second correlation between heat transfer coefficient and thermal resistance is fitted using the standard heat conduction equation. Using multiphysics simulation software, the thermal resistance corresponding to the thermal simulation model under several given simulation parameters is simulated to obtain several simulated thermal resistances. The simulation parameters include ambient temperature and chip power. Based on the second correlation, the simulation parameters, and the simulated thermal resistance, a first correlation is fitted.

[0040] The technical solution provided in this application addresses the packaging structure of chips belonging to the same type of packaging process. During the design information iteration of the packaging structure, a heat transfer coefficient (first correlation relationship) that can be approximately equivalent to the influence of fluid on chip heat dissipation (such as the influence of gas, liquid, etc.) is pre-constructed. The influence of fluid on chip heat dissipation is obtained by simulating the initial packaging structure using the same type of packaging process using existing multiphysics simulation software (such as ANSYS Icepak). That is, the process of determining this equivalent heat transfer coefficient (first correlation relationship) only needs to be performed once for the same type of packaging process. When facing other packaging structures belonging to the same type of packaging process (such as when the design information changes but the type of packaging process remains unchanged), it can be reused to construct the corresponding heat conduction equation. Then, the thermal resistance is calculated through the constructed heat conduction equation, without having to repeatedly rely on CFD software to simulate the influence of fluid on chip heat dissipation when the design information changes. This reduces the time consumption of the thermal resistance calculation process, improves the calculation efficiency, and thus accelerates the design iteration speed of the chip packaging structure, achieving efficient temperature management of the chip.

[0041] It is understandable that a chip's packaging structure is a complex system composed of multiple functional components working together. Its core functions include protecting the chip, providing electrical connections, heat dissipation, and mechanical support. There are various specific implementations of a chip's packaging structure. As an example, a chip's packaging structure can include core functional components such as the chip, substrate, or lead frame. In addition, the chip's packaging structure can also include interconnect and electrical connection components such as wire bonding, solder balls / bumps, and through-silicon vias (TSVs); packaging materials and protective structures such as compound, protective layers, and filler materials; heat dissipation and mechanical support components such as heat dissipation structures and metal frame structures; and external connections and packaging forms such as pins / solder balls and the package shell. It is worth noting that the above description of specific implementations of chip packaging structures is only an illustrative example. In practical applications, other specific implementations are possible, and no specific limitations are imposed on them.

[0042] Understandably, the junction-to-environment thermal resistance (JTR) is a core parameter for evaluating the heat dissipation performance of a chip's packaging structure. It characterizes the resistance to heat transfer from the junction region of the semiconductor chip to the surrounding environment. JTR reflects the combined resistance to heat transfer caused by packaging materials, PCB layout, and airflow conditions. A lower JTR value indicates higher heat dissipation efficiency, thus it can be used to evaluate heat dissipation capabilities and compare the heat dissipation performance of different packaging designs. Junction-to-ambient thermal resistance (JTR) can be affected by a variety of factors, such as the thermal conductivity of the packaging material (e.g., metal packages have lower JTR than plastic packages), the size and structure of the package components (e.g., larger package area and higher pin density result in better heat diffusion paths and lower JTR), chip size (e.g., greater difference between chip and package size leads to higher diffusion thermal resistance and JTR), PCB design carrying the chip (e.g., high thermal conductivity of the board (e.g., adding thermal vias) can reduce JTR), airflow velocity (e.g., forced convection (e.g., fans) can significantly reduce JTR), and altitude (e.g., thin air at high altitudes reduces convection cooling efficiency and increases JTR). It is worth noting that the above descriptions of factors affecting JTR are merely illustrative; in practical applications, other influencing factors may exist, and no specific limitations are made regarding these.

[0043] Chip packaging structures can utilize various packaging processes. For example, one option is Dual In-line Package (DIP), which offers advantages such as low cost and ease of manual soldering, primarily used in traditional home appliances and industrial control equipment. Another example is Quad Flat Package (QFP), which boasts superior high-frequency performance and high pin density, mainly used in microcontrollers and communication chips. Yet another example is Ball Grid Array Package (BGA), which offers high density, excellent heat dissipation, and resistance to mechanical stress, primarily used in high-performance CPUs / GPUs and memory chips. Finally, another example is Chip Scale Package (CSP), which offers miniaturization, low power consumption, and high integration, primarily used in smartphones and IoT sensors.

[0044] If the packaging process of the target chip's package structure to be adjusted belongs to a preset type of packaging process, then the pre-built first correlation (the correlation between heat transfer coefficient and ambient temperature and chip power) is obtained. This can be understood as the initial package structure of the initial chip used to build the first correlation adopting a preset type of packaging process. Assuming that the preset type is the DIP type mentioned above, if it is necessary to calculate the junction-to-ambient thermal resistance of the target chip's package structure to be adjusted, and if the type of the packaging process of the package structure to be adjusted is also the DIP type, then the package structure to be adjusted can directly use the pre-built first correlation to calculate the junction-to-ambient thermal resistance without using CFD software for simulation analysis to calculate the junction-to-ambient thermal resistance, and without having to repeatedly build a new first correlation, i.e., the correlation between heat transfer coefficient and ambient temperature and chip power.

[0045] As an example, the target chip and the initial chip can be the same chip or different chips; there is no specific limitation on this.

[0046] The aforementioned thermal simulation model can include simulation information of various physical components characterizing the package structure. As an example, the thermal simulation model may include simulation information characterizing the package housing the initial chip, the PCB supporting the package, and the support structure supporting the PCB. However, this thermal simulation model does not include simulation information of the fluids in the environment where the initial package structure is located. As another example, the thermal simulation model may also exclude detailed physical components such as vias, wires, and thermocouples. By ignoring information about fluids and various detailed physical components, and only considering information about the essential physical components of the package structure, a highly simplified thermal simulation model can be established, thereby improving the efficiency of thermal simulation model construction. It is worth noting that the specific implementation of the simulation information included in the thermal simulation model described above is merely an exemplary demonstration. In practical applications, other specific implementations are possible, and no specific limitations are imposed on them.

[0047] The support structure used to support the PCB can be implemented in various ways. As an example, the support structure can be a support board in a standard test environment that conforms to the Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device) (JEDEC JESD51), or it can be other types of support structures. No specific limitation is made in this regard.

[0048] by Figure 4For example, taking the support structure mentioned above as a support board in the JEDEC JESD51 standard test environment, when the thermal simulation model includes simulation information characterizing the package containing the initial chip, the PCB carrying the package, and the support board, its visualization results can be as follows: Figure 4 As shown. As an example, thermal simulation models can exist in the form of three-dimensional models.

[0049] As an example, the JEDEC JESD51 standard defines various thermal testing environments, primarily including two key scenarios: natural convection environments (Still Air) and forced convection environments (Moving Air). The JEDEC JESD51 standard ensures the comparability of thermal resistance data for packages from different manufacturers by standardizing testing conditions. It helps engineers evaluate thermal solutions (such as TIM material selection and PCB layout) and also assists in reliability verification to predict whether chip junction temperatures exceed permissible thresholds.

[0050] The design information related to the initial package structure of the initial chip can have various specific implementations. As an example, this design information may include: the geometric shape information, dimensional information, and / or material parameter information of each component in the initial package structure of the initial chip. It is worth noting that the specific implementation of the design information described above is only an illustrative example. In practical applications, other specific implementations may exist, and no specific limitation is made on this.

[0051] The aforementioned multiphysics simulation software can have various specific implementations. As an example, this multiphysics simulation software can be ANSYS Icepak Thermal Analysis Software (ANSYS Icepak). The simulated thermal resistance is simulated by ANSYS Icepak software by incorporating fluid information into the aforementioned thermal simulation model. Using multiphysics simulation software such as ANSYS Icepak to perform a series of simulations, ANSYS Icepak can fully consider fluid dynamics calculations, turbulence, and radiation effects (by incorporating fluid information), thus ensuring that the heat transfer coefficient in the final constructed first correlation can be equivalent to the effects of convection and radiation generated by the fluid. It is worth noting that the above specific implementation of multiphysics simulation software is only an illustrative example; in practical applications, other specific implementations are possible, and no specific limitation is made.

[0052] Understandably, ANSYS Icepak software is a professional electronic heat dissipation and thermal management simulation tool developed by ANSYS. It is based on computational fluid dynamics (CFD) technology and focuses on solving complex thermal problems from the chip level to the system level.

[0053] There are multiple ways to calculate the junction-to-ambient thermal resistance of the target chip's package structure using the target heat conduction equation constructed based on the first correlation mentioned above. As an example, the target heat conduction equation can be solved using a finite element method to obtain the temperature distribution inside the package of the package structure to be adjusted, and then the junction-to-ambient thermal resistance of the package structure to be adjusted can be calculated based on the temperature distribution inside the package structure. It is worth noting that the above method of calculating the junction-to-ambient thermal resistance of the package structure to be adjusted using the target heat conduction equation is only an illustrative example. In practical applications, other calculation methods may exist, and no specific limitation is made here.

[0054] There are several ways to solve the target heat conduction equation using a finite element method (FEM) solver. As an example, the FEM solver can be a sparse matrix solver using the Portable, Extensible Toolkit for Scientific Computation (PETsc) library. It can be based on the sparse matrix solver from the PETsc library, combined with Algebraic Multigrid (AMG) preconditioners and the conjugate gradient method to solve the target heat conduction equation. The solver uses the sparse matrix solver from the PETsc library, which combines AMG preconditioners and the conjugate gradient method to solve the linear equation system, resulting in high solution efficiency and suitability for parallel computing. It is worth noting that the above method of solving the target heat conduction equation using a finite element method is only an illustrative example. In practical applications, other solution methods may exist, and no specific limitation is made.

[0055] There are several ways to calculate the junction-to-ambient thermal resistance of the package structure to be adjusted based on the temperature distribution inside the package. As an example, the highest temperature on the chip junction inside the package can be extracted based on the temperature distribution inside the package. Then, the junction-to-ambient thermal resistance of the package structure to be adjusted can be calculated based on the highest temperature on the chip junction, the ambient temperature of the package structure, and the power of the target chip. It is worth noting that the above method of calculating the junction-to-ambient thermal resistance of the package structure to be adjusted based on the temperature distribution inside the package is only an illustrative example. In practical applications, other calculation methods may exist, and no specific limitation is made.

[0056] This application embodiment also provides a specific calculation process for junction-to-environment thermal resistance. The calculation process is described below by way of example and includes:

[0057] A. Construct the above thermal simulation model.

[0058] B. Calibration and equivalent heat transfer coefficient h to convection and radiation effects eq :

[0059] ① First, construct the standard heat conduction equation for the thermal simulation model in step A, and then specify different heat transfer coefficients h in the standard heat conduction equation. eq Thermal simulation of the thermal simulation model can output results with different heat transfer coefficients h. eq The corresponding thermal resistances R, and based on different heat transfer coefficients h eq And their respective thermal resistances R, thus obtaining the thermal resistance R and heat transfer coefficient h of the thermal simulation model. eq The curve fitting relationship (fitting function):

[0060]

[0061] Where a and b are the fitting coefficients.

[0062] ② A series of simulations were performed using multiphysics simulation software such as ANSYS Icepak, which fully considered fluid dynamics calculations, turbulence, and radiation effects to obtain the ambient temperature T. a The relationship between power P and thermal resistance R;

[0063] ③ Combining the ambient temperature, power, and thermal resistance data from step ②, and the inverse function of the fitting function (1) from step ①, a series of ambient temperatures T can be obtained. a The heat transfer coefficient h corresponding to the combination of power P and heat transfer coefficient eq Based on this series of ambient temperatures T a The heat transfer coefficient h corresponding to the combination of power P and heat transfer coefficient eq The heat transfer coefficient h can be obtained. eq and simulation parameters (ambient temperature T) a The fitting formula for power P is:

[0064] h eq =C1+C2(T) a +αP) (2)

[0065] Where C1 and C2 are fitting coefficients, and α is a set empirical parameter.

[0066] C. Using formula (2) as the boundary condition for the surface heat conduction equation of the above thermal simulation model, the target heat conduction equation is constructed based on this:

[0067]

[0068] Where u(x) represents the temperature distribution, k(x) represents the thermal conductivity at various points in the thermal simulation model, and f represents the power density of the chip. Ω represents the directional derivative of temperature along the outward normal direction from the surface of the thermal simulation model, and Ω represents the solid region of the thermal simulation model. The surface of the thermal simulation model is represented. Then, the temperature distribution inside the package can be obtained by solving the target heat conduction equation (a combination of equation (2) and equation (3)) using a finite element solver.

[0069] D. Extract the highest temperature T on the chip junction using the obtained temperature distribution. j Thus, the thermal resistance R to the environment can be calculated. ja Its formula can be expressed as follows:

[0070]

[0071] It should be noted that step B above is a pre-calculated step, which only needs to be executed once on the same target type of packaging process. The formula for the obtained heat transfer coefficient (formula (2), i.e., the first correlation) can be used on all packaging structures with the same packaging process type as the target type. In the iterative optimization process of the design information of the packaging structure under the target type of packaging process, it is only necessary to modify the corresponding thermal simulation model according to the changes in design information, and then repeat steps C to D. In the above calculation process, the simulation speed of the thermal simulation model is much faster than that of the traditional method. Therefore, it can effectively accelerate the chip packaging design optimization process and achieve efficient chip temperature management.

[0072] Corresponding to the above method embodiments, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the chip temperature management method described in any of the embodiments above.

[0073] This application also provides an electronic device, such as Figure 5 As shown, the electronic device includes:

[0074] Processor 501;

[0075] Memory 502 is used to store processor-executable instructions;

[0076] The processor 501 is configured to implement the chip temperature management method described in any of the embodiments above.

[0077] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the chip temperature management method described in any of the embodiments above.

[0078] The above description is only a specific embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A chip temperature management method, characterized by, The method comprises: if the packaging process of the target chip to be adjusted belongs to a preset type of packaging process, a first correlation relationship is obtained, and a target heat conduction equation is constructed based on the first correlation relationship; the first correlation relationship is a correlation relationship between a heat transfer coefficient and an ambient temperature and a chip power; a junction-to-ambient thermal resistance of the packaging structure to be adjusted is calculated by using the target heat conduction equation, and design information of the packaging structure to be adjusted is adjusted based on the junction-to-ambient thermal resistance, so as to realize temperature management of the target chip; wherein the first correlation relationship is constructed by: constructing a thermal simulation model based on design information related to an initial packaging structure of an initial chip, and determining a standard heat conduction equation for the thermal simulation model, wherein the initial packaging structure adopts the preset type of packaging process; fitting a second correlation relationship between a heat transfer coefficient and a thermal resistance by using the standard heat conduction equation; simulating the thermal resistance of the thermal simulation model under a plurality of given simulation parameters by using a multi-physics field simulation software, to obtain a plurality of simulation thermal resistances; the simulation parameters include an ambient temperature and a chip power; fitting the first correlation relationship based on the second correlation relationship, the simulation parameters and the simulation thermal resistances.

2. The method of claim 1, wherein, The thermal simulation model comprises simulation information of a packaging body accommodating the initial chip, a PCB bearing the packaging body and a support structure supporting the PCB; The thermal simulation model does not include simulation information of a fluid in an environment in which the initial packaging structure is located.

3. The method of claim 1, wherein, The design information related to the initial packaging structure includes geometric shape information, size information and / or material parameter information of each component in the initial packaging structure.

4. The method of claim 1, wherein, The multi-physics field simulation software is ANSYS Icepak software, and the simulation thermal resistance is simulated by the ANSYS Icepak software after introducing fluid information for the thermal simulation model.

5. The method of claim 1, wherein, The calculation of the junction-to-ambient thermal resistance of the packaging structure to be adjusted by using the target heat conduction equation comprises: solving the target heat conduction equation by a finite element solver to obtain a temperature distribution inside a packaging body of the packaging structure to be adjusted; calculating the junction-to-ambient thermal resistance of the packaging structure to be adjusted based on the temperature distribution.

6. The method of claim 5, wherein, The finite element solver is a sparse matrix solver using a PETsc library; the solving of the target heat conduction equation by the finite element solver comprises: solving the target heat conduction equation by combining an algebraic multigrid (AMG) preconditioner and a conjugate gradient method based on the sparse matrix solver.

7. The method of claim 5, wherein, The calculation of the junction-to-ambient thermal resistance of the packaging structure to be adjusted based on the temperature distribution comprises: extracting a highest temperature on a chip junction inside the packaging body based on the temperature distribution, and calculating the junction-to-ambient thermal resistance based on the highest temperature, an ambient temperature in which the packaging structure to be adjusted is located and a chip power.

8. A computer program product comprising a computer program which, when executed by a processor, implements the steps of the method of any one of claims 1 to 7.

9. An electronic device, comprising: comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the method of any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, the computer program, when executed by the processor, implements the steps of the method of any one of claims 1 to 7.

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