Voltage drop violation repairing method, related device and storage medium

Abstract

The invention provides a voltage drop violation repairing method, a related device and a storage medium. The method comprises the steps of obtaining a voltage drop violation distribution area in a chip, setting one or more decoupling units in the voltage drop violation distribution area after circuit module placement and power supply / ground network routing in the chip are completed in an automatic layout and wiring stage designed at the rear end of the chip, performing voltage drop analysis on the chip, and determining the voltage drop violation distribution area according to the voltage drop analysis result. According to the method, the voltage drop violation unit in the chip is determined according to the voltage drop violation unit in the chip, the voltage drop violation restoration strategy is adopted to restore the voltage drop violation unit in the chip, the probability of voltage drop violation of the circuit unit in the chip is reduced, the voltage drop violation restoration pressure and difficulty are reduced, and then the chip design efficiency is improved.

Description

Technical Field

[0001] This disclosure belongs to the field of integrated circuit design technology, specifically relating to a voltage drop violation repair method, related device and storage medium. Background Technology

[0002] Before integrated circuit design data is delivered to chip manufacturers for production, a series of analyses and verifications are usually required to ensure that the design data meets delivery standards. This series of analyses and verifications is collectively called signoff, which helps relevant technical personnel to correct any deficiencies in the design data before tape-out, thereby saving costs.

[0003] In the back-end design process of a chip, after performing Automatic Placement & Routing (APR), that is, after the front-end design is transformed into a true schematic and layout, IR-Drop analysis (i.e., post-simulation) is performed on the schematic and layout. If IR-Drop violations exist, they are corrected through continuous iteration of the Engineer Changing Order (ECO) process. Since the chip design process is essentially complete after the front-end design is transformed into a true schematic and layout, the available strategies for correcting IR-Drop violations are limited. For example, adding power and ground (PG) lines to reduce local PG resistance requires complex Design Rules Checking (DRC) rules and sufficient routing resources. Another example is reducing the size of the IR-Drop violation cell, which requires sufficient timing margin. Yet another example is moving the IR-Drop violation cell, which also requires sufficient timing margin and may cause routing problems. Obviously, after performing automatic placement and routing and then performing voltage drop violation repair, some IR-Drop violation cells may not be repaired, causing the chip to fail to meet the expected functional requirements. In extreme cases, there is even a risk that the chip may be irreparable and the power network structure may need to be redesigned, which greatly reduces the chip design efficiency. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a voltage drop violation repair method, related device and storage medium, which aims to use one or more decoupling units set in the voltage drop violation distribution area during the automatic placement and routing stage of chip back-end design to quickly filter high-frequency current, reduce the probability of voltage drop violations in circuit units in the chip, reduce the pressure and difficulty of voltage drop violation repair, and thus improve chip design efficiency.

[0005] According to a first aspect of this disclosure, a method for repairing voltage drop violations is provided, comprising:

[0006] Obtain the voltage drop violation distribution area in the chip;

[0007] In the automatic placement and routing stage of the chip back-end design, after the placement of circuit modules and power / ground network wiring in the chip are completed, one or more decoupling units are set in the voltage drop violation distribution area.

[0008] Voltage drop analysis is performed on the chip to identify voltage drop violation units within the chip;

[0009] A voltage drop violation repair strategy is adopted to repair the voltage drop violation unit in the chip.

[0010] Optionally, the step of obtaining the voltage drop violation distribution region in the chip includes:

[0011] During the chip front-end design phase, the functions of the circuit modules in the chip are obtained;

[0012] Based on the function of the circuit modules in the chip, identify the first circuit module in the chip that may cause a voltage drop violation.

[0013] In the automatic placement and routing stage of chip back-end design, after the circuit modules in the chip are laid out and the units are placed, the first circuit module is marked.

[0014] The area where the first circuit module that was marked is located is determined as the voltage drop violation distribution area.

[0015] Optionally, the step of obtaining the voltage drop violation distribution region in the chip includes:

[0016] The automatic placement and routing stage of the chip back-end design is executed in advance. After the automatic placement and routing stage of the chip back-end design is completed, the circuit modules in the chip are simulated for signal value changes.

[0017] Based on simulation results, a second circuit module in the chip that may experience voltage drop violations was identified.

[0018] The area where the second circuit module is located is defined as the voltage drop violation distribution area.

[0019] Optionally, in the automatic placement and routing stage of the chip back-end design, after completing the placement of circuit modules and power / ground network wiring in the chip, one or more decoupling units are set in the voltage drop violation distribution area, including:

[0020] In the automatic placement and routing stage of chip back-end design, after the circuit modules in the chip are placed and the units are arranged, the power / ground network is wired.

[0021] One or more decoupling units are provided in the voltage drop violation distribution area.

[0022] Optionally, in the automatic placement and routing stage of the chip back-end design, after completing the placement of circuit modules and power / ground network wiring in the chip, one or more decoupling units are set in the voltage drop violation distribution area, including:

[0023] The automatic placement and routing stage of the chip back-end design is executed again to perform placement and unit placement operations on the circuit modules in the chip and to perform wire bonding operations on the power / ground network.

[0024] One or more decoupling units are provided in the voltage drop violation distribution area.

[0025] Optionally, the provision of one or more decoupling units in the voltage drop violation distribution region includes:

[0026] Obtain the type of the decoupling unit;

[0027] Obtain the regional coordinates of the voltage drop violation distribution area;

[0028] The placement spacing between the decoupling units in the voltage drop violation distribution area is determined based on the area size of the circuit module and the placement density of the circuit units included in the circuit module.

[0029] The decoupling unit is placed in the voltage drop violation distribution area according to the type, the area coordinates, and the placement spacing.

[0030] Optionally, in the first direction of the chip, the placement spacing between the decoupling units in the voltage drop violation distribution area is equal, and in the second direction of the chip, the placement spacing between the decoupling units in the voltage drop violation distribution area is equal, with the first direction and the second direction being intersected.

[0031] According to a second aspect of this disclosure, a voltage drop violation repair device is provided, comprising:

[0032] Voltage drop violation distribution area acquisition unit, used to acquire the voltage drop violation distribution area in the chip;

[0033] The decoupling unit setting unit is used to set one or more decoupling units in the voltage drop violation distribution area during the automatic placement and routing stage of the chip back-end design, after the placement of circuit modules and power / ground network wiring in the chip are completed.

[0034] A voltage drop analysis unit is used to perform voltage drop analysis on the chip to identify voltage drop violation units in the chip.

[0035] The violation repair unit is used to repair the voltage drop violation unit in the chip by adopting a voltage drop violation repair strategy.

[0036] According to a third aspect of this disclosure, an electronic device is provided, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the method described above.

[0037] According to a fourth aspect of this disclosure, a storage medium is provided that stores a computer program or instructions, which, when executed by a processor, implement the steps of the method described above.

[0038] This disclosure brings the following beneficial effects:

[0039] The voltage drop violation repair method disclosed herein obtains the voltage drop violation distribution area in the chip. During the automatic placement and routing stage of the chip back-end design, after completing the placement of circuit modules and power / ground network wiring in the chip, one or more decoupling units are set in the voltage drop violation distribution area. After the automatic placement and routing stage of the chip back-end design, voltage drop analysis is performed on the chip to identify the voltage drop violation units in the chip. A voltage drop violation repair strategy is adopted to repair the voltage drop violation units in the chip. In this way, by using one or more decoupling units set in the voltage drop violation distribution area during the automatic placement and routing stage of the chip back-end design to quickly filter high-frequency current, the probability of voltage drop violations occurring in physical units in the chip is reduced, the pressure and difficulty of voltage drop violation repair are reduced, and thus the chip design efficiency is improved.

[0040] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0041] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0042] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings, in which:

[0043] Figure 1This is a schematic flowchart of a voltage drop violation repair method according to an embodiment of the present disclosure;

[0044] Figure 2 This is a schematic diagram of a voltage drop violation distribution area according to an embodiment of the present disclosure;

[0045] Figure 3 This is a schematic diagram of the structure of a chip provided according to an embodiment of the present disclosure;

[0046] Figure 4 Provided according to one embodiment of the present disclosure Figure 3 Enlarged schematic diagram of the module within the dashed box;

[0047] Figure 5 This is a schematic diagram of a voltage drop violation repair device provided according to an embodiment of the present disclosure;

[0048] Figure 6 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present disclosure. Detailed Implementation

[0049] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various portions in the drawings are not drawn to scale.

[0050] The following terms are used in this document:

[0051] Voltage drop (IR-drop) (also known as Power Integrity (PI)): In the back-end design of digital circuits, voltage drop typically refers to the voltage loss caused by the traces from the power mesh and ground mesh to the circuit unit in the chip, affecting the voltage supply to that unit. Each circuit unit in the chip is potentially affected by voltage drop. A high voltage drop slows down the signal propagation to the next circuit unit. When the voltage drop exceeds a certain level, it can lead to insufficient setup time, preventing the chip from achieving the required performance, or it may cause the hold time to fail, resulting in functional failure. To ensure the chip functions properly, we need to provide a uniform and stable power supply to each circuit unit. Therefore, before the chip is delivered for production, voltage drop simulation and verification of each circuit unit are required to ensure that the voltage drop of each circuit unit meets the signoff standard. Voltage drop can be divided into static IR drop and dynamic IR drop. Static IR drop typically refers to the product of constant current and equivalent resistance, calculated given the total power consumption and the equivalent resistance of the power mesh. Dynamic voltage drop typically refers to the voltage drop caused by current fluctuations due to logic transitions in digital circuits; that is, dynamic voltage drop mainly depends on the switching activities of digital logic. IR-Drop analysis is used to identify IR-Drop violation cells in the power network whose voltage drop does not meet the acceptable voltage drop range for chip delivery verification. IR-Drop analysis (i.e., the post-simulation process) includes static IR-Drop analysis and dynamic IR-Drop analysis.

[0052] In the chip manufacturing process, chip design is undoubtedly the most crucial step, primarily comprising front-end design and back-end design. Front-end design is mainly responsible for logic implementation, typically using languages ​​such as Verilog and Very-High-Speed ​​Integrated Circuit Hardware Description (VHDL) for behavioral-level descriptions. Back-end design, on the other hand, is responsible for transforming the front-end design into actual schematics and layouts, tape-out, and mass production. To use an analogy, front-end design is like creating blueprints, providing functional and structural details. Back-end design, then, is like turning those blueprints into a real building.

[0053] It's important to note that the chip design verification process includes pre-functional simulation and post-timing simulation (i.e., IR-Drop analysis). Pre-functional simulation focuses on the Register Transfer Level (RTL), primarily verifying the logical correctness of the designed circuit; this method is fast. Post-timing simulation is based on a gate-level netlist composed of basic gate units, taking into account gate-level circuit delays and interconnection delays between various gates. Post-timing simulation mainly identifies potential timing constraints in the design. Because it incorporates delays in circuit components and paths, it is slower, sometimes taking several hours or even days for a single chip. Compared to pre-simulation, post-simulation often reports numerous timing violations, significantly slowing down the process. Timing violations refer to breaches of setup time, hold time, or other timing constraints, preventing the sampling clock from correctly acquiring data. For example, when using a slower (lower frequency) clock signal to sample a faster (higher frequency) cross-clock domain signal, it is generally required that the faster cross-clock domain signal be held for a longer time in the received clock domain to ensure that it can be correctly sampled by the slower clock signal.

[0054] It's important to note that circuit modules within a chip refer to those that implement specific functions within an integrated circuit. Integrating these circuit modules onto the same chip allows for complex functionalities and improves system performance and reliability. Automatic placement and routing (APR) of these circuit modules is a critical part of chip design, requiring precise routing and optimized circuit structures to ensure proper chip operation and performance. APR can be broadly categorized into four stages: floorplan, placement, clock tree synthesis (CTS), and routing.

[0055] It is easy to understand that ensuring the voltage drop analysis results of a chip meet the approval criteria is a necessary step before mass production. When the voltage drop analysis results do not meet the approval criteria (i.e., voltage drop violations exist in the chip), these violations need to be corrected to ensure the chip functions correctly. However, during the back-end design process, after performing Automatic Placement & Routing (APR), i.e., after transforming the front-end design into a true schematic and layout, the chip design process is essentially complete, leaving limited repair strategies for IR-Drop violation cells. In this embodiment, during the back-end design process, during the Automatic Placement & Routing (APR) stage, the distribution of decoupling units (decaps) in the voltage drop violation distribution area (i.e., the PI risk area) of the chip is adjusted to reduce the probability that the voltage drop analysis results of the circuit units in the chip do not meet the approval criteria.

[0056] Figure 1 A schematic flowchart of a voltage drop violation repair method provided according to an embodiment of this disclosure is shown. (See also...) Figure 1 The voltage drop violation repair method includes steps S110 to S140.

[0057] In step S110, the voltage drop violation distribution area in the chip is obtained.

[0058] In some embodiments, during the chip front-end design phase, the functions of circuit modules in the chip are obtained. Based on the functions of the circuit modules in the chip, a first circuit module in the chip that may cause voltage drop violations is identified. For example, a circuit module in the chip used to implement deep convolution operations can be identified as the first circuit module that may cause voltage drop violations (also called a high-computation circuit module). It is easy to understand that computationally intensive circuit modules are prone to voltage drop violations. As another example, a circuit module whose number of included circuit units exceeds a preset threshold can be identified as the first circuit module that may cause voltage drop violations (also called a high-density circuit module). It should be understood that a chip contains a large number of circuit units, which can include various types of standard cells such as combinational logic, sequential logic, functional units, and special-type units. These various circuit units are the foundation of the back-end design process of integrated circuit chips. Common circuit units can include inverters, AND gates, registers, selectors, full adders, etc. The more circuit units in a circuit module, the more complex the timing paths and power networks of the circuit modules in the chip become, and the more prone they are to voltage drop violations. For example, circuit modules in a chip that undergo large-scale simultaneous switching can be identified as the first circuit module potentially causing voltage drop violations (also known as high-switching circuit modules). It should be understood that for modules with large-scale simultaneous switching in a chip, these modules contain a large number of registers that simultaneously transition from a quiescent state to an active state. This generates extremely large transient currents, resulting in a significant voltage drop from the power network pads to the circuit cells within the module. This leads to large-scale voltage drop violations across the entire module, thus affecting the chip's functionality. In some embodiments, during the automatic placement and routing stage of the chip's back-end design, after the placement and cell arrangement operations of the circuit modules in the chip, the first circuit module is marked. The area where the marked first circuit module is located is defined as the voltage drop violation distribution area.

[0059] Figure 2 This is a schematic diagram of a voltage drop violation distribution area according to an embodiment of the present disclosure. In some embodiments, during the automatic placement and routing stage of chip back-end design, after placement and cell placement operations are performed on the circuit modules in the chip, the layer (hierarchy) where a first circuit module that may cause a voltage drop violation can be located can be determined, and the first circuit module can be highlighted in the floorplan. This highlighted area ( Figure 2 The area highlighted in red (shown in the image) represents the identified voltage drop violation distribution area.

[0060] In some embodiments, the automatic placement and routing stage of the chip back-end design is performed in advance. After the automatic placement and routing stage of the chip back-end design is completed, value change dump (VCD) scenario simulation is performed on the circuit modules in the chip. Based on the simulation results, a second circuit module in the chip that may experience voltage drop violations is identified. The area where the second circuit module is located is determined as the voltage drop violation distribution area. It should be noted that the value change dump (VCD) data scenario simulation refers to the simulation waveform data obtained by the front end simulating the design data of the integrated circuit based on the corresponding real working scenario of the chip, which can represent the real working switching state of the signal values ​​corresponding to all gate cells. As the result data of the front end simulation, it can be generated based on the placement and routing (PR) database.

[0061] In step S120, during the automatic placement and routing stage of the chip back-end design, after the placement of circuit modules and power / ground network wiring in the chip are completed, one or more decoupling units are set in the voltage drop violation distribution area.

[0062] In some embodiments, for the voltage drop violation distribution area determined in the region where the first circuit module marked during the automatic placement and routing stage of the chip back-end design is located, a power / ground network can be wired after the placement and cell placement operations of the circuit modules in the chip are performed. One or more decoupling cells are then provided in this voltage drop violation distribution area.

[0063] In some embodiments, after the automatic placement and routing stage of the chip back-end design is performed in advance, the automatic placement and routing stage of the chip back-end design can be performed again based on the simulation results of the value change dump (VCD) scenario simulation of the circuit modules in the chip, to perform placement and cell placement operations on the circuit modules in the chip, to perform wire bonding operations on the power / ground network, and to set one or more decoupling cells in the voltage drop violation distribution area.

[0064] In some embodiments, during the automatic placement and routing stage of the chip back-end design, the type of decoupling unit and the area coordinates of the voltage drop violation distribution area can be obtained. Based on the area size of the circuit module in the voltage drop violation distribution area and the placement density of the circuit units included in the circuit module, the placement spacing between decoupling units in the voltage drop violation distribution area is determined. The decoupling units are then placed in the voltage drop violation distribution area according to the type, the area coordinates, and the placement spacing. In some embodiments, the placement spacing between decoupling units in the voltage drop violation distribution area is equal in a first direction (e.g., the X-axis direction) of the chip, and equal in a second direction (e.g., the Y-axis direction). The first and second directions are intersecting (e.g., perpendicular).

[0065] In some embodiments, setting decoupling units in the voltage drop violation distribution area can be achieved by executing the following command in an automatic placement and routing tool (e.g., Innovus):

[0066] addwellTap –cell${DECAP(CELL)} –area${DECAP(AREA)} –prefix DECAP –cellInterval$space_x –checkerBoard / / Adds decoupling units evenly at certain spatial intervals within the selected voltage drop violation distribution area (i.e., PI risk area) according to the method of adding circuit units. The variable ${DECAP(CELL)} defines the type of decoupling unit used, ${DECAP(AREA)} defines the area coordinates of the voltage drop violation distribution area, and $space_x defines the placement spacing of the decoupling units along the X-axis of the chip.

[0067] Figure 3 This is a schematic diagram of the structure of a chip provided according to an embodiment of the present disclosure. Figure 3 As shown, the integrated circuit chip 300 includes circuit modules 1 to n (Block n, where n is a natural number greater than 1). The top-level module Top 0 of circuit modules 1 to n is used to establish the signal relationships between different modules. Figure 3 The dashed box 301 represents the defined voltage drop violation distribution area. Figure 4 Provided according to one embodiment of the present disclosure Figure 3 An enlarged view of the module within the dashed box. (See attached image.) Figure 4As shown, circuit module 5 includes multiple circuit units 410 and decoupling units 420. The decoupling units 420 are arranged at equal intervals in the voltage drop violation distribution region in the first direction of the chip (e.g., the X-axis direction), and the decoupling units 420 are arranged at equal intervals in the voltage drop violation distribution region in the second direction of the chip (e.g., the Y-axis direction).

[0068] It should be understood that decoupling units have the characteristic of passing AC and blocking DC. When the transient current flowing through the power network pads in the chip increases, the decoupling unit can offset part of the current during charging and discharging, thereby effectively reducing the voltage drop generated from the power network pads to the circuit units within the module. Simultaneously, the decoupling unit acts as a filter, filtering out some transient current spikes. In this embodiment, by setting one or more decoupling units in the voltage drop violation distribution area, it is possible to quickly drain power from circuit modules in the chip that may experience voltage drop violations, effectively filter high-frequency currents, reduce pull-up behavior during unpacking, and thus reduce the voltage drop by slowing down the rate of change of transient current flowing through the power network pads in the chip.

[0069] It is easy to understand that by using one or more decoupling units set in the voltage drop violation distribution area during the automatic placement and routing stage of the chip back-end design, high-frequency currents are quickly filtered, reducing the probability of voltage drop violations occurring in the circuit units of the chip, reducing the pressure and difficulty of voltage drop violation repair, and thus improving chip design efficiency.

[0070] The key takeaway is that for voltage drop violation repair, the earlier the strategy optimization is performed in the early stages of chip design, the fewer changes are required to execute the repair operation. For APR, even a single line of work during the placement phase can significantly reduce voltage drop violations and greatly alleviate the pressure on the sign-off process in the later stages of chip design.

[0071] The concept behind capacity is that, in some cases, many modules in a chip are not at risk of voltage drop violations. Therefore, setting decoupling units only in areas where voltage drop violations are distributed can avoid wasting chip area.

[0072] In step S130, voltage drop analysis is performed on the chip to identify voltage drop violation units in the chip.

[0073] In some embodiments, a voltage drop violation analysis tool (e.g., Redhawk) is used to perform voltage drop violation analysis on the modules in the chip to obtain the circuit units (i.e., voltage drop violation units) in the modules where voltage drop violations occur.

[0074] In step S140, a voltage drop violation repair strategy is adopted to repair the voltage drop violation unit in the chip.

[0075] In some embodiments, for voltage drop violations occurring in circuit modules within a chip, the following voltage drop violation repair strategies are employed to repair the voltage drop violation units in the chip: increasing the density of metal windings on the top metal layer of the power network and / or widening the width of the metal windings; replacing all circuit units in the chip with decoupling units; and replacing the circuit units in the module that experience voltage drop violations with circuit units with lower drive capabilities. It is understood that each voltage drop violation repair strategy has its own advantages and disadvantages, and when repairing voltage drop violations caused by specific reasons, the optimal strategy can be strategically selected based on the principle of minimizing modifications to the existing chip design.

[0076] Figure 5 A schematic diagram of a voltage drop violation repair device according to an embodiment of the present disclosure is shown. Figure 5 As shown, the voltage drop violation repair device 500 includes a voltage drop violation distribution area acquisition unit 510, a decoupling unit setting unit 520, a voltage drop analysis unit 530, and a violation repair unit 540.

[0077] The voltage drop violation distribution area acquisition unit 510 is used to acquire the voltage drop violation distribution area in the chip.

[0078] The decoupling unit setting unit 520 is used to set one or more decoupling units in the voltage drop violation distribution area during the automatic placement and routing stage of the chip back-end design, after the placement of circuit modules and power / ground network wiring in the chip are completed.

[0079] The voltage drop analysis unit 530 is used to perform voltage drop analysis on the chip to identify voltage drop violation units in the chip.

[0080] The violation repair unit 540 is used to repair the voltage drop violation unit in the chip by adopting a voltage drop violation repair strategy.

[0081] Since the specific process for repairing voltage drop violations has been detailed above, it will not be repeated here.

[0082] This disclosure also provides an electronic device, such as... Figure 6 As shown, it includes a memory 620, a processor 610, and a program stored in the memory 620 and executable on the processor 610. When the program is executed by the processor 610, it can implement the various processes of each embodiment of the voltage drop violation repair method described above and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0083] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. Therefore, this disclosure also provides a storage medium storing a computer program or instructions that, when executed by a processor, can implement the various processes in the embodiments of the voltage drop violation repair methods described above.

[0084] Since the instructions stored in the storage medium can execute the steps in the voltage drop violation repair method provided in the embodiments of this disclosure, the beneficial effects achievable by the voltage drop violation repair method provided in the embodiments of this disclosure can be realized, as detailed in the preceding embodiments, and will not be repeated here. The specific implementation of each of the above operations can be found in the preceding embodiments, and will not be repeated here.

[0085] In summary, according to the embodiments of this disclosure, the voltage drop violation distribution area in the chip is obtained. During the automatic placement and routing stage of the chip back-end design, after the placement of circuit modules and power / ground network wiring are completed, one or more decoupling units are set in the voltage drop violation distribution area. After the automatic placement and routing stage, voltage drop analysis is performed on the chip to identify the voltage drop violation units in the chip. A voltage drop violation repair strategy is adopted to repair the voltage drop violation units in the chip. In this way, by using one or more decoupling units set in the voltage drop violation distribution area during the automatic placement and routing stage of the chip back-end design to quickly filter high-frequency current, the probability of voltage drop violations occurring in physical units in the chip is reduced, the pressure and difficulty of voltage drop violation repair are reduced, and the chip design efficiency is improved.

[0086] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of this disclosure.

Claims

1. A method for repairing voltage drop violations, comprising: Obtain the voltage drop violation distribution area in the chip; In the automatic placement and routing stage of the chip back-end design, after the placement of circuit modules and power / ground network wiring in the chip are completed, one or more decoupling units are set in the voltage drop violation distribution area. Voltage drop analysis is performed on the chip to identify voltage drop violation units within the chip; A voltage drop violation repair strategy is adopted to repair the voltage drop violation unit in the chip.

2. The voltage drop violation repair method according to claim 1, wherein, The method of obtaining the voltage drop violation distribution area in the chip includes: During the chip front-end design phase, the functions of the circuit modules in the chip are obtained; Based on the function of the circuit modules in the chip, identify the first circuit module in the chip that may cause a voltage drop violation. In the automatic placement and routing stage of chip back-end design, after the circuit modules in the chip are laid out and the units are placed, the first circuit module is marked. The area where the first circuit module that was marked is located is determined as the voltage drop violation distribution area.

3. The voltage drop violation repair method according to claim 1, wherein, The method of obtaining the voltage drop violation distribution area in the chip includes: The automatic placement and routing stage of the chip back-end design is executed in advance. After the automatic placement and routing stage of the chip back-end design is completed, the circuit modules in the chip are simulated for signal value changes. Based on simulation results, a second circuit module in the chip that may experience voltage drop violations was identified. The area where the second circuit module is located is defined as the voltage drop violation distribution area.

4. The voltage drop violation repair method according to claim 2, wherein, In the automated placement and routing stage of the chip back-end design, after completing the placement of circuit modules and power / ground network wiring in the chip, one or more decoupling units are set in the voltage drop violation distribution area, including: In the automatic placement and routing stage of chip back-end design, after the circuit modules in the chip are placed and the units are arranged, the power / ground network is wired. One or more decoupling units are provided in the voltage drop violation distribution area.

5. The voltage drop violation repair method according to claim 3, wherein, In the automated placement and routing stage of the chip back-end design, after completing the placement of circuit modules and power / ground network wiring in the chip, one or more decoupling units are set in the voltage drop violation distribution area, including: The automatic placement and routing stage of the chip back-end design is executed again to perform placement and unit placement operations on the circuit modules in the chip and to perform wire bonding operations on the power / ground network. One or more decoupling units are provided in the voltage drop violation distribution area.

6. The voltage drop violation repair method according to claim 4 or 5, wherein, The provision of one or more decoupling units in the voltage drop violation distribution area includes: Obtain the type of the decoupling unit; Obtain the regional coordinates of the voltage drop violation distribution area; The placement spacing between the decoupling units in the voltage drop violation distribution area is determined based on the area size of the circuit module and the placement density of the circuit units included in the circuit module. The decoupling unit is placed in the voltage drop violation distribution area according to the type, the area coordinates, and the placement spacing.

7. The voltage drop violation repair method according to claim 6, wherein, In the first direction of the chip, the placement spacing between the decoupling units in the voltage drop violation distribution area is equal, and in the second direction of the chip, the placement spacing between the decoupling units in the voltage drop violation distribution area is equal, with the first direction and the second direction being intersected.

8. A voltage drop violation repair device, comprising: Voltage drop violation distribution area acquisition unit, used to acquire the voltage drop violation distribution area in the chip; The decoupling unit setting unit is used to set one or more decoupling units in the voltage drop violation distribution area during the automatic placement and routing stage of the chip back-end design, after the placement of circuit modules and power / ground network wiring in the chip are completed. A voltage drop analysis unit is used to perform voltage drop analysis on the chip to identify voltage drop violation units in the chip. The violation repair unit is used to repair the voltage drop violation unit in the chip by adopting a voltage drop violation repair strategy.

9. An electronic device, comprising: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the method as described in any one of claims 1 to 7.

10. A storage medium storing a computer program or instructions that, when executed by a processor, implement the steps of the method as described in any one of claims 1 to 7.

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