Power management chip circuit of OLED screen

Abstract

The invention provides a power supply management chip circuit of an OLED screen, and the circuit comprises a two-phase interdigital charge pump which is connected with the input of a positive power supply voltage ELVDD and the input of a negative power supply voltage ELVSS of the OLED screen, and is used for obtaining a first voltage based on the positive voltage ELVDD and the negative voltage ELVSS, and the first voltage is greater than the positive voltage ELVDD; and the voltage stabilizer is connected with the output end of the two-phase interdigital charge pump and is used for stabilizing the first voltage. The ELVDD and the ELVSS are converted into high voltage output through the two-phase interdigital charge pump, so that the output voltage is increased along with the increase of the power supply voltage, a fixed voltage difference is kept between the output voltage and the power supply voltage, the output voltage does not change along with the change of the load current, and it is guaranteed that the system has very high efficiency within the full-load range.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of OLED, in particular to a power management chip circuit of an OLED screen. BACKGROUND

[0002] With the continuous development of display technology, display devices are increasingly widely used, and people's requirements for display devices are also increasingly high. Organic light-emitting diode (OLED) is a new generation of screen evolved from LCD screen (liquid crystal screen), and compared with traditional LCD screen, OLED screen has the characteristic of not needing backlight illumination, has a wider color gamut, and can realize screen-off display, so it has been more widely welcomed.

[0003] On a type of terminal (such as Android) mainboard, three power supplies are needed to drive the OLED screen, which are positive voltage AVDD (+5.6V) and ELVDD (+4.6V) and negative voltage ELVSS (-4V). AVDD is used to power the internal analog circuit of the screen, and the voltage of the power module is changed through the ASWIRE pin. ELVDD and ELVSS power the screen display pixel circuit, and the ELVDD voltage is fixed and cannot be adjusted, and the ELVSS voltage can be changed through the ESWIRE pin communication protocol. On another type of terminal (such as Apple) mainboard, two power supplies are needed to drive the OLED screen, which are positive voltage AVDD (+5.6V) and PVDD (8V).

[0004] Because the number and voltage of power supplies needed by OLED screens used by different terminals are different, OLED screens customized for one type of terminal cannot be directly used on another type of terminal, such as the driving chip on the traditional Android mainboard, which can only provide ELVDD of about 4.6V at most, and cannot meet the demand of 8V voltage required by Apple OLED screen. SUMMARY

[0005] Therefore, the embodiments of the present application expect to provide a power management chip circuit of an OLED screen, which can serve as a bridge connecting OLED screens of terminals requiring high voltage and terminals requiring low voltage, and can provide OLEDs suitable for high voltage requirements.

[0006] A power management chip circuit of an OLED screen, comprising:

[0007] A two-phase interdigital charge pump connected to the input of the positive power voltage ELVDD and the input of the negative power voltage ELVSS of the OLED screen, for obtaining a first voltage based on the positive voltage ELVDD and the negative voltage ELVSS, the first voltage being greater than the positive voltage ELVDD;

[0008] A voltage regulator is connected to the output of the two-phase interdigitated charge pump and is used to stabilize the first voltage.

[0009] In some embodiments, the power management chip circuit further includes: an adaptive reference voltage generation module ARG, used to convert the first voltage into a reference voltage, wherein the difference between the reference voltage and the first voltage is a fixed value, and the voltage difference between the reference voltage and the positive power supply voltage ELVDD and the negative power supply voltage ELVSS is a fixed value.

[0010] In some embodiments, the adaptive reference voltage generation module (ARG) includes a bandgap circuit and a voltage divider network.

[0011] In some embodiments, the two-phase interdigitated charge pump, the adaptive reference voltage generation module (ARG), and the voltage regulator are integrated on a single chip.

[0012] In some embodiments, at least one external capacitor C1 is also included, one end of which is connected to the output terminal of the two-phase interdigitated charge pump, and the other end is grounded.

[0013] In some embodiments, the two-phase interdigitated charge pump includes a first charge pump and a second charge pump, the output terminal of the first charge pump is connected to the output terminal of the second charge pump, and the output terminals of the first charge pump and the second charge pump are connected to the off-chip capacitor C1.

[0014] In some embodiments, the first charge pump includes a first switching circuit that connects a first switch S1 and a second switch S2 in series, and a second switching circuit that connects a third switch S3 and a fourth switch S4 in series. The positive power supply voltage ELVDD is connected to the first switching circuit, and the negative power supply voltage ELVSS is connected to the second switching circuit. The first charge pump also includes a first flying capacitor C3, one end of which is connected to the first switching circuit, and the other end of which is connected to the second switching circuit.

[0015] In some embodiments, the second charge pump includes a third switching circuit that connects a fifth switch S5 and a sixth switch S6 in series, and a fourth switching circuit that connects a seventh switch S7 and an eighth switch S8 in series. The positive power supply voltage ELVDD is connected to the third switching circuit, and the negative power supply voltage ELVSS is connected to the fourth switching circuit. The second charge pump also includes a second flying capacitor C4, one end of which is connected to the third switching circuit, and the other end of which is connected to the fourth switching circuit.

[0016] In some embodiments, the two-phase interdigitated charge pump includes a first operating state; in the first operating state, the first switch S1 and the third switch S3 are open, the positive power supply voltage ELVDD and the negative power supply voltage ELVSS are connected across the first flying capacitor C3, the first flying capacitor C3 is charged, the fifth switch S5 and the seventh switch S7 are open, and the second flying capacitor C4 is connected to the output terminal of the two-phase interdigitated charge pump.

[0017] In some embodiments, the two-phase interdigitated charge pump further includes a second operating state; in the second operating state, the sixth switch S6 and the eighth switch S8 are turned on, the positive power supply voltage ELVDD and the negative power supply voltage ELVSS are connected across the two ends of the second flying capacitor C4, the first flying capacitor C4 is charged, the second switch S2 and the fourth switch S4 are turned on, and the second flying capacitor C3 is connected to the output terminal of the two-phase interdigitated charge pump.

[0018] The power management chip circuit for the OLED screen provided in this application uses a two-phase interdigitated charge pump to convert ELVDD and ELVSS into a high-voltage output so that the output voltage increases with the increase of the power supply voltage, maintains a fixed voltage difference with the power supply voltage, and does not change with the load current, so as to ensure that the system has high efficiency across the entire load range. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the power management chip circuit of an OLED screen in one embodiment of this application;

[0020] Figure 2 for Figure 1 The diagram shows the structure of the ARG and LDO.

[0021] Figure 3 This is a schematic diagram of a two-phase interdigitated charge pump.

[0022] Figure 4 This is a schematic diagram of the first operating state of a two-phase interdigitated charge pump.

[0023] Figure 5 This is the second operating state of a schematic diagram of a two-phase interdigitated charge pump. Detailed Implementation

[0024] The embodiments of this application will be described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate this application, but should not be used to limit the scope of this application.

[0025] It should be noted that in the embodiments of this application, the orientations or positional relationships such as "upper" and "lower" are based on the orientations or positional relationships shown in the accompanying drawings. It should be understood that these orientational terms are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0027] In the embodiments of this application, unless otherwise expressly specified and limited, the first feature "on" the second feature may be in direct contact with the first feature and the second feature, or indirect contact between the first feature and the second feature through an intermediate medium.

[0028] In the description of this specification, references to terms such as "some embodiments," "exemplary," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine the different embodiments or examples described in this application, as well as the features of those different embodiments or examples.

[0029] In one embodiment, such as Figure 1 As shown, a power management chip circuit for an OLED screen is provided, comprising:

[0030] A two-phase interdigital charge pump 101 is connected to the input of the positive power supply voltage ELVDD and the input of the negative power supply voltage ELVSS of the OLED screen, and is used to obtain a first voltage based on the positive voltage ELVDD and the negative voltage ELVSS, wherein the first voltage is greater than the positive voltage ELVDD; a voltage regulator is connected to the output terminal of the two-phase interdigital charge pump 101 and is used to stabilize the first voltage.

[0031] In some embodiments, the regulator is a low-dropout linear regulator (LDO) connected in series at the lower end of the two-phase interdigital charge pump. The LDO is connected in series after the interdigital charge pump to stabilize the output voltage Vsc of the two-phase interdigital charge pump 101, i.e., the first voltage, at a fixed value.

[0032] In some embodiments, such as Figure 2 As shown, the LDO consists of an error amplifier (EA), a regulating transistor, and voltage divider resistors, stabilizing the output voltage through a negative feedback loop. Thus, even under different load conditions, while the output voltage Vsc of the two-phase interdigitated charge pump 101 varies with the load current, the output voltage Vout of the series-connected low-dropout linear regulator (LDO) remains constant, ensuring stable screen brightness. Furthermore, the LDO's inherent power supply rejection ratio (PSR) further suppresses voltage ripple from Vsc to the output voltage.

[0033] In some embodiments, such as Figure 1 As shown, it also includes: an adaptive reference voltage generation module ARG 102, used to convert the first voltage into a reference voltage, wherein the difference between the reference voltage and the first voltage is a fixed value, and the voltage difference between the reference voltage and the positive power supply voltage ELVDD and the negative power supply voltage ELVSS is a fixed value.

[0034] Because the brightness of an OLED screen needs to change during display, the output voltage also needs to change with the input voltage. The current common method is to fix ELVDD and change the value of ELVSS (from -1.4V to -4.4V) via the SWIRE protocol. Simple boost converters, because the input voltage is ELVDD, cannot adjust the voltage themselves and require an additional one-swire digital channel to transmit information to the boost converter, changing the output voltage value by changing the reference voltage. This embodiment provides a reference voltage generation method that follows the changes in ELVSS through a two-phase interdigitated charge pump 101 and the adaptive reference voltage generation module ARG 102. This saves the resources of this digital channel and also reduces the design of the digital-to-analog interface circuit, offering applicability and simplicity.

[0035] Figure 2 This describes the internal structure of the adaptive reference voltage generation module ARG 102 and the interface internal structure of the low dropout linear regulator LDO.

[0036] In some embodiments, the adaptive reference voltage generation module ARG 102 includes a bandgap circuit and a voltage divider network. For example... Figure 2As shown, the leftmost circuit is the bandgap circuit, powered by a VINP power supply, outputting a temperature-independent reference voltage of approximately 1.2V. This voltage is used to obtain the reference voltage for the first EA through a resistor divider network, with the formula V1 = α1 * 1.2. Due to the clamping effect of EA, the voltage V1 across R4 is equal to the voltage across R5, therefore the current through R5 is... The current mirror is used to copy the module 1:1 to the right; the reference voltage EA below the module is also V1. Clamping ensures the voltage at the top of R10 is V1. Note... have to The upper left corner of the module contains a voltage divider network consisting of ELVDD and resistors R7 and R8. The voltage V2 across R8 is V2 = α2 * ELVDD. Due to the clamping effect of EA, the voltage V1 across R9 is equal to the voltage across R8, therefore the current through R9 is... The current mirror copies the data 1:1 to the right; the two currents I1 and I2 on the right are added at Vref, and I4 is subtracted simultaneously, resulting in... Given that resistors R6 = R9 and R6 = α3 * R5, then the voltage across R6 is... Cdp at Vref is an on-chip integrated capacitor used to filter power supply ripple conducted from ELVDD. Let... The LDO output voltage is then Vout = α4 * α3 * |ELVSS| + α4 * α2 * ELVDD - α4 * α3 * α1 * 1.2. From the above definition, we know that α1 and α2 < 1, α4 > 1. Setting α2 = α3 and α4 * α3 = 1, we have α4 * α2 = 1, and therefore Vout = |ELVSS| + ELVDD - α1 * 1.2. The difference between the input voltage and the output voltage is α1 * 1.2, which is a set constant value.

[0037] When ELVSS changes, VOUT also changes accordingly, realizing the function of the output voltage following the input voltage change. When ELVDD and ELVSS are at a certain constant value, the system efficiency is a constant value that does not change with the load current, and its value is... Higher efficiency can be achieved by choosing a smaller α1. Assuming α1 = 0.9, ELVDD = 4.6V, ELVSS = -4V, the calculated overall system efficiency is 87.5%.

[0038] In some embodiments, the two-phase interdigitated charge pump 101, the adaptive reference voltage generation module ARG 102, and the voltage regulator are integrated on a single chip 10.

[0039] In some embodiments, such as Figure 1 As shown, the power management chip of the OLED screen also includes at least one external capacitor C1, one end of which is connected to the output terminal of the two-phase interdigitated charge pump 101, and the other end is grounded.

[0040] In some embodiments, such as Figure 3 As shown, the two-phase interdigitated charge pump 101 includes a first charge pump and a second charge pump. The output terminal of the first charge pump is connected to the output terminal of the second charge pump, and the output terminals of the first charge pump and the second charge pump are connected to the external capacitor C1.

[0041] In some embodiments, the first charge pump includes a first switching circuit that connects a first switch S1 and a second switch S2 in series, and a second switching circuit that connects a third switch S3 and a fourth switch S4 in series. The positive power supply voltage ELVDD is connected to the first switching circuit, and the negative power supply voltage ELVSS is connected to the second switching circuit. The first charge pump also includes a first flying capacitor C3, one end of which is connected to the first switching circuit, and the other end of which is connected to the second switching circuit.

[0042] In some embodiments, the second charge pump includes a third switching circuit that connects a fifth switch S5 and a sixth switch S6 in series, and a fourth switching circuit that connects a seventh switch S7 and an eighth switch S8 in series. The positive power supply voltage ELVDD is connected to the third switching circuit, and the negative power supply voltage ELVSS is connected to the fourth switching circuit. The second charge pump also includes a second flying capacitor C4, one end of which is connected to the third switching circuit, and the other end of which is connected to the fourth switching circuit.

[0043] An interdigitated charge pump is a switching power supply circuit consisting of switches and capacitors, typically used in integrated circuits requiring voltage boost / buck conversion. The switches here refer to metal-oxide-semiconductor transistor (MOSFET) switches integrated on a silicon chip, constructed from MOSFETs operating in the linear region. Compared to traditional off-chip switches, they are smaller and have lower on-resistance (Rdson). The capacitors include flying capacitors (Cfly) for charge transfer and voltage-regulating capacitors (Cload) for output filtering. Figure 3In the diagram, C1 and C2 are voltage-stabilizing capacitors, and C3 and C4 are flying capacitors. For a charge pump, it can be modeled as an ideal transformer with an output resistor. Its output resistance is related to the on-resistance of the switch and the value of the flying capacitor. As the on-resistance of the switch decreases, the switching frequency increases, and the capacitance of the flying capacitor increases, the equivalent output resistance of the charge pump decreases, resulting in higher efficiency. It should be noted that although the interdigitated charge pump of the present invention consists of two identical units and uses two flying capacitors, its area and cost are exactly the same as those of a simple single-boost charge pump without interdigitation. That is, the sum of the areas of all switches in the present invention is equal to the sum of the areas of the switches in a single-boost charge pump without interdigitation. This means that the on-resistance of a single switch in the present invention is twice that of a single switch in a single-boost charge pump without interdigitation. The sum of the capacitance values ​​of the two flying capacitors in the present invention is equal to the capacitance value of the flying capacitor in a single-boost charge pump without interdigitation. In other words, the capacitance value of a single flying capacitor in the present invention is equal to half the capacitance value of the flying capacitor in a single-boost charge pump without interdigitation.

[0044] In some embodiments, such as Figure 4 As shown, the two-phase interdigitated charge pump 101 includes a first operating state; in the first operating state, the first switch S1 and the third switch S3 are open, the positive power supply voltage ELVDD and the negative power supply voltage ELVSS are connected to the two ends of the first flying capacitor C3, the first flying capacitor C3 is charged, the fifth switch S5 and the seventh switch S7 are open, and the second flying capacitor C4 is connected to the output terminal of the two-phase interdigitated charge pump 101.

[0045] Specifically, in the first phase, S1 and S3 are turned on, and ELVDD and ELVSS are connected to the positive and negative terminals of C3 to charge C3; when S5 and S7 are turned on, C4 is connected to the output terminal to provide charge to the output terminal.

[0046] In some embodiments, such as Figure 5As shown, the two-phase interdigitated charge pump 101 also includes a second operating state. In the second operating state, the sixth switch S6 and the eighth switch S8 are open, the positive power supply voltage ELVDD and the negative power supply voltage ELVSS are connected across the second flying capacitor C4, the first flying capacitor C4 is charged, the second switch S2 and the fourth switch S4 are open, and the second flying capacitor C3 is connected to the output terminal of the two-phase interdigitated charge pump 101. Specifically, in the second phase, S2 and S4 are open, C3 is connected to the output terminal, providing charge to the output terminal. S6 and S8 are open, ELVDD and ELVSS are connected across the positive and negative terminals of C4, charging C4. Through the alternating operation of C3 and C4 in the two phases, charge is continuously transported from the input to the output by the flying capacitor. Since both ELVDD and ELVSS voltages are used simultaneously, the value of the output voltage VOUT is ELVDD-ELVSS, i.e., 4.6V-(-4)=8.6V. Due to the interdigitated design, the output current is converted from discontinuous to continuous, significantly reducing output voltage ripple without increasing area or cost, making it more suitable for the requirements of high-quality OLED screens. An LDO is connected in series after the interdigitated charge pump to stabilize the output voltage at a fixed value. The LDO consists of an error amplifier (EA), a regulating transistor, and voltage divider resistors, stabilizing the output voltage through a negative feedback loop. Thus, even under different load conditions, although the output voltage Vsc of the two-phase interdigitated charge pump 101 varies with the load current, the output voltage remains constant, ensuring stable screen brightness. Simultaneously, the LDO's power supply rejection ratio (PSR) further suppresses voltage ripple from the output voltage Vsc of the two-phase interdigitated charge pump 101 to the output voltage.

[0047] This application provides a low-cost, high-efficiency, and high-quality interface solution for scenarios where Android motherboards cannot directly drive Apple OLED screens. This solution includes the design of the power management chip and the selection of peripheral components. The adaptive reference voltage generation module in the design is universal and can be widely used in various power management modules to provide a reference voltage that differs from the power supply voltage by a fixed value. This application fully utilizes the current-providing capabilities of ELVDD and ELVSS voltages, enabling the output voltage to provide a large current at 8V, thus solving the problem of insufficient current-providing capability in boost solutions. It eliminates the need for a large external inductor, requiring only capacitors, significantly reducing system cost and making the system smaller and more compact, meeting integration requirements.

[0048] The above description is merely a preferred embodiment of this application and is not intended to limit the application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A power management chip circuit for an OLED screen, characterized in that, include: A two-phase interdigitated charge pump is connected to the input of the positive power supply voltage ELVDD and the input of the negative power supply voltage ELVSS of the OLED screen, and is used to obtain a first voltage based on the positive voltage ELVDD and the negative voltage ELVSS, wherein the first voltage is greater than the positive voltage ELVDD; A voltage regulator is connected to the output of the two-phase interdigitated charge pump and is used to stabilize the first voltage.

2. The power management chip circuit according to claim 1, characterized in that, Also includes: An adaptive reference voltage generation module (ARG) is used to convert the first voltage into a reference voltage. The difference between the reference voltage and the first voltage is a fixed value, and the voltage difference between the reference voltage and the positive power supply voltage ELVDD and the negative power supply voltage ELVSS is a fixed value.

3. The power management chip circuit according to claim 2, characterized in that, The adaptive reference voltage generation module (ARG) includes a bandgap circuit and a voltage divider network.

4. The power management chip circuit according to claim 2 or 3, characterized in that, The two-phase interdigitated charge pump, the adaptive reference voltage generation module (ARG), and the voltage regulator are integrated on a single chip.

5. The power management chip circuit according to claim 1, characterized in that, It also includes at least one external capacitor C1, one end of which is connected to the output terminal of the two-phase interdigitated charge pump, and the other end is grounded.

6. The power management chip circuit according to claim 5, characterized in that, The two-phase interdigitated charge pump includes a first charge pump and a second charge pump. The output terminal of the first charge pump is connected to the output terminal of the second charge pump, and the output terminals of the first charge pump and the second charge pump are connected to the external capacitor C1.

7. The power management chip circuit according to claim 6, characterized in that, The first charge pump includes a first switching circuit that connects a first switch S1 and a second switch S2 in series, and a second switching circuit that connects a third switch S3 and a fourth switch S4 in series. The positive power supply voltage ELVDD is connected to the first switching circuit, and the negative power supply voltage ELVSS is connected to the second switching circuit. The first charge pump also includes a first flying capacitor C3, one end of which is connected to the first switching circuit and the other end of which is connected to the second switching circuit.

8. The power management chip circuit according to claim 7, characterized in that, The second charge pump includes a third switch circuit that connects the fifth switch S5 and the sixth switch S6 in series, and a fourth switch circuit that connects the seventh switch S7 and the eighth switch S8 in series. The positive power supply voltage ELVDD is connected to the third switch circuit, and the negative power supply voltage ELVSS is connected to the fourth switch circuit. The second charge pump also includes a second flying capacitor C4, one end of which is connected to the third switching circuit and the other end of which is connected to the fourth switching circuit.

9. The power management chip circuit according to claim 8, characterized in that, The two-phase interdigitated charge pump includes a first operating state; In the first operating state, the first switch S1 and the third switch S3 are open, the positive power supply voltage ELVDD and the negative power supply voltage ELVSS are connected to the two ends of the first flying capacitor C3, the first flying capacitor C3 is charged, the fifth switch S5 and the seventh switch S7 are open, and the second flying capacitor C4 is connected to the output end of the two-phase interdigitated charge pump.

10. The power management chip circuit according to claim 9, characterized in that, The two-phase interdigitated charge pump also includes a second operating state; In the second operating state, the sixth switch S6 and the eighth switch S8 are open, the positive power supply voltage ELVDD and the negative power supply voltage ELVSS are connected across the two ends of the second flying capacitor C4, the first flying capacitor C4 is charged, the second switch S2 and the fourth switch S4 are open, and the second flying capacitor C3 is connected to the output end of the two-phase interdigitated charge pump.

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