Signal recovery system and storage device
By using frequency division and signal recovery operations in a double data rate synchronous dynamic random access memory, the problem of reduced skew margin between the clock signal and the data strobe signal is solved, thus improving the accuracy of data write operations.
Patent Information
- Application Number
- CN202410614614.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-17
- Publication Date
- 2025-11-18
AI Technical Summary
In double data rate synchronous dynamic random access memory, the reduced skew margin between the clock signal and the data strobe signal due to processing, voltage, and temperature variations affects the accuracy of data write operations.
By using frequency division and signal recovery operations, the clock signal and data strobe signal are divided and recovered using the frequency divider and signal recovery circuit in the signal recovery system, resulting in a recovered clock signal and data strobe signal to indicate that the rising edge of the data strobe signal is at a specific level of the clock signal.
This effectively avoids the impact of processing, voltage, and temperature changes on the delay circuit, improving the accuracy of data writing operations.
Smart Images
Figure CN120977346A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to double data rate (DDR) synchronous dynamic random access memory (SDRAM), and in particular to a signal recovery system capable of performing write leveling operation by signal recovery operation and frequency division operation, and related memory device. BACKGROUND
[0002] With the development of double data rate synchronous dynamic random access memory, a plurality of frequency division operations are usually performed on a clock signal and a data strobe (DQS) signal with high speed frequency to generate a plurality of divided clock signals and a plurality of divided data strobe signals for data write operation. For LPDDR4, during the write leveling operation, the double data rate synchronous dynamic random access memory receives the clock signal and the data strobe signal from the memory controller, and generates and returns the data (DQ) signal to the memory controller according to the clock signal and the data strobe signal, to indicate whether the rising edge of the data strobe signal is at the high level or the low level of the clock signal. The memory controller can then determine whether to delay the data strobe signal according to the data signal to successfully perform the data write operation. For the existing memory device including the memory controller and the double data rate synchronous dynamic random access memory, the clock signal and the data strobe signal can be used to perform the write leveling operation by a plurality of delay circuits (such as a plurality of inverters) that imitate the delay of the normal data write path. However, some problems may occur, for example, when the process, voltage, and temperature (PVT) change and the LPDDR4 standard only allows the tDQSS to have a tolerance value of 1±0.25tck (clock period time; that is, the clock period time tck is 0.46 nanoseconds (ns) at the current fastest clock speed), there may be a difference between the delay of the plurality of delay circuits and the delay of the normal data write path, which causes some errors in subsequent data write operations. Therefore, there is an urgent need for a novel signal recovery system and related memory device capable of performing write leveling operation by a recovered clock signal and a recovered data strobe signal obtained by signal recovery operation on the divided clock signal and the divided data strobe signal. SUMMARY
[0003] Therefore, one of the purposes of the present application is to provide a signal recovery system and a related storage device, which can perform a write equalization operation by a frequency division operation and a signal recovery operation to solve the above problems.
[0004] According to an embodiment of the present application, a signal recovery system is provided. The signal recovery system can include a plurality of frequency dividers, a plurality of signal recovery circuits, and a data signal generation circuit. The plurality of frequency dividers are configured to perform a frequency division operation on a clock signal and a data strobe signal, respectively, to generate a set of divided clock signals and a set of divided data strobe signals. The plurality of signal recovery circuits are configured to perform a signal recovery operation on the set of divided clock signals and the set of divided data strobe signals, respectively, to generate a recovered clock signal and a recovered data strobe signal. The data signal generation circuit is configured to generate a data signal based on the recovered clock signal and the recovered data strobe signal to indicate that a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.
[0005] According to an embodiment of the present application, a storage device is provided. The storage device can include a memory controller, a memory, a plurality of signal recovery circuits, and a data signal generation circuit. The memory can include a plurality of frequency dividers configured to receive a clock signal and a data strobe signal from the memory controller and perform a frequency division operation on the clock signal and the data strobe signal, respectively, to generate a set of divided clock signals and a set of divided data strobe signals. The plurality of signal recovery circuits are configured to perform a signal recovery operation on the set of divided clock signals and the set of divided data strobe signals, respectively, to generate a recovered clock signal and a recovered data strobe signal. The data signal generation circuit is configured to generate a data signal based on the recovered clock signal and the recovered data strobe signal and transmit the data signal to the memory controller to indicate that a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.
[0006] One of the advantages of the present application is that, compared with the case of using a clock signal and a data strobe signal to perform a write equalization operation by a plurality of delay circuits (e.g., a plurality of inverters) that imitate the delay of a normal data write path, the signal recovery system of the present application performs a write equalization operation by a frequency division operation and a signal recovery operation on the divided signals in a double data rate synchronous dynamic random access memory, which can avoid the signal delay problem (e.g., the problem of reducing the skew margin between the data strobe signal and the clock signal during a data write operation) caused by the process, voltage, and temperature variations of the delay circuits, so that the accuracy of the data write operation can be greatly improved. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figure 1 A schematic diagram of a memory device according to an embodiment of the present application.
[0008] Figure 2 A timing chart of signals associated with a signal recovery circuit according to an embodiment of the present application.
[0009] Figure 3 A schematic diagram of a first portion of a signal recovery circuit according to an embodiment of the present application.
[0010] Figure 4 A schematic diagram of a second portion of a signal recovery circuit according to an embodiment of the present application.
[0011] Figure 5 A schematic diagram of a third portion of a signal recovery circuit according to an embodiment of the present application.
[0012] Figure 6 A schematic diagram of a fourth portion of a signal recovery circuit according to an embodiment of the present application.
[0013]
Symbol Explanation
[0014] 100: memory device
[0015] 102: memory controller
[0016] 103: signal recovery system
[0017] 104: memory
[0018] 106, 108, 300: signal recovery circuit
[0019] 110: data signal generation circuit
[0020] 112, 114: frequency divider
[0021] DQ: data signal
[0022] XCLK: clock signal
[0023] XDQS: data strobe signal
[0024] CK[0] ~ CK[3]: divided clock signal
[0025] DQS[0] ~ DQS[3]: divided data strobe signal
[0026] RCLK: recovered clock signal
[0027] RDQS: recovered data strobe signal
[0028] T: period
[0029] t0, t1, t2, t3, t4: Time points
[0030] 301, 303, 401, 403: Logic combination circuits
[0031] 300, 302, 304, 305, 306, 308, 310, 312, 318, 320, 322, 324, 325, 326, 328, 330, 400, 402, 404, 405, 406, 408, 410, 412, 418, 420, 422, 424, 425, 426, 428, 430, 608, 610, 612: Inverters
[0032] 314, 332, 414, 432, 614, 616: NAND gate circuits
[0033] 316, 334, 416, 434, 600, 602, 604, 606: Transmission gate circuits
[0034] C1, C2, C3, C4, C5, C6: Control signals
[0035] RCK[0], RCK[1], RCK[2], RCK[3]: Recover signal
[0036] VC, VSS: Voltage signals
[0037] 500, 502: NOR gate circuits
[0038] 601, 603: Signal transmission circuits
[0039] 618, 620: n-type transistors
[0040] GND: Ground voltage signal Detailed Implementation
[0041] Figure 1 This is a schematic diagram of a storage device 100 according to an embodiment of the present invention. Figure 1As shown, the memory device 100 can include a memory controller 102, a memory (e.g., a double data rate (DDR) synchronous dynamic random access memory (SDRAM)) 104, a plurality of signal recovery circuits 106 and 108, and a data signal generation circuit 110, wherein the memory 104 can include a plurality of frequency dividers 112 and 114; and the frequency dividers 112 and 114, the signal recovery circuits 106 and 108, and the data generation circuit 110 can be regarded as a signal recovery system 103. In response to the memory 104 being in a write leveling mode, the memory controller 102 can transmit a clock signal XCLK and a data strobe (DQS) signal XDQS to the memory 104 (especially, the frequency dividers 112 and 114 of the memory 104). The frequency divider 112 can be used to divide the clock signal XCLK to generate a set of divided clock signals CK[0]-CK[M]. The frequency divider 114 can be used to divide the data strobe signal XDQS to generate a set of divided data strobe signals DQS[0]-DQS[N].
[0042] In this embodiment, the frequency divider 112 can divide the clock signal XCLK by a divisor of "2" to generate the set of divided clock signals CK[0]-CK[3] (i.e., M=3) having different phases, wherein the frequency of each of the set of divided clock signals CK[0]-CK[3] is half of the frequency of the clock signal XCLK. The frequency divider 114 can divide the data strobe signal XDQS by a divisor of "2" to generate the set of divided data strobe signals DQS[0]-DQS[3] (i.e., N=3) having different phases, wherein the frequency of each of the set of divided data strobe signals DQS[0]-DQS[3] is half of the frequency of the data strobe signal XDQS. This is for illustration only, and the present application is not limited thereto. In some embodiments, the frequency divider 112 can divide the clock signal XCLK by other divisors (e.g., "4") to generate the set of divided clock signals, and the frequency divider 114 can divide the data strobe signal XDQS by other divisors (e.g., "4") to generate the set of divided data strobe signals.
[0043] The signal recovery circuit 106 can be configured to perform a signal recovery operation on the set of divided clock signals CK[0]-CK[3] to generate a recovered clock signal RCLK, where the duty cycle of the recovered clock signal RCLK is similar to or equal to the duty cycle of the clock signal XCLK. The signal recovery circuit 108 can be configured to perform a signal recovery operation on the set of divided data strobe signals DQS[0]-DQS[3] to generate a recovered data strobe signal RDQS, where the duty cycle of the recovered data strobe signal RDQS is similar to or equal to the duty cycle of the data strobe signal XDQS. The data signal generation circuit 110 can be configured to generate and transmit a data signal DQ to the memory controller 102 based on the recovered clock signal RCLK and the recovered data strobe signal RDQS to indicate whether a rising edge of the data strobe signal XDQS is located at a high level (e.g., logic value "1") or a low level (e.g., logic value "0") of the clock signal XCLK. The memory controller 102 can determine whether to delay the data strobe signal XDQS based on the data signal DQ to successfully perform a data write operation.
[0044] For the signal recovery operation of each of the signal recovery circuits 106 and 108, since the signal recovery operation of the signal recovery circuit 106 on the divided clock signals CK[0]-CK[3] is similar to the signal recovery operation of the signal recovery circuit 108 on the divided data strobe signals DQS[0]-DQS[3], the following content only illustrates the signal recovery operation of the signal recovery circuit 106, and one skilled in the art can analogize the signal recovery operation of the signal recovery circuit 108 based on the following content. Figure 2 FIG. 6 is a timing diagram of the related signals of the signal recovery circuit 106 according to an embodiment of the present application. As shown in FIG. 6, the divided clock signals CK[0]-CK[3] are generated based on the clock signal XCLK, and the divided data strobe signals DQS[0]-DQS[3] are generated based on the data strobe signal XDQS. The signal recovery circuit 106 can be configured to perform a signal recovery operation on the set of divided clock signals CK[0]-CK[3] to generate a recovered clock signal RCLK, where the duty cycle of the recovered clock signal RCLK is similar to or equal to the duty cycle of the clock signal XCLK. The signal recovery circuit 108 can be configured to perform a signal recovery operation on the set of divided data strobe signals DQS[0]-DQS[3] to generate a recovered data strobe signal RDQS, where the duty cycle of the recovered data strobe signal RDQS is similar to or equal to the duty cycle of the data strobe signal XDQS. The data signal generation circuit 110 can be configured to generate and transmit a data signal DQ to the memory controller 102 based on the recovered clock signal RCLK and the recovered data strobe signal RDQS to indicate whether a rising edge of the data strobe signal XDQS is located at a high level (e.g., logic value "1") or a low level (e.g., logic value "0") of the clock signal XCLK. The memory controller 102 can determine whether to delay the data strobe signal XDQS based on the data signal DQ to successfully perform a data write operation. Figure 2As shown, the clock signal XCLK is a square wave signal having a period "T" (e.g., a time period from time point tO to time point t2), and each of the divided clock signals CK[0]-CK[3] is a square wave signal having a period "2T" (e.g., a time period from time point tO to time point t4), in which at time point tO, the divided clock signal CK[0] is generated according to a first rising edge of the clock signal XCLK (e.g., at time point tO, a first rising edge of the divided clock signal CK[0] is aligned with the first rising edge of the clock signal XCLK); at time point t-i, the divided clock signal CK[1] is generated according to a first falling edge of the clock signal XCLK (e.g., at time point t-i, a first rising edge of the divided clock signal CK[1] is aligned with the first falling edge of the clock signal XCLK); at time point t2, the divided clock signal CK[2] is generated according to a second rising edge of the clock signal XCLK (e.g., at time point t2, a first rising edge of the divided clock signal CK[2] is aligned with the second rising edge of the clock signal XCLK); and at time point t3, the divided clock signal CK[3] is generated according to a second falling edge of the clock signal XCLK (e.g., at time point t3, a first rising edge of the divided clock signal CK[3] is aligned with the second falling edge of the clock signal XCLK).
[0045] The signal recovery circuit 106 can generate a plurality of recovery signals RCK[0]-RCK[3] according to a plurality of rising edges of the divided clock signals CK[0]-CK[3], and generate a recovered clock signal RCLK according to the recovery signals RCK[0]-RCK[3], in which each of the recovery signals RCK[0]-RCK[3] is generated according to rising edges of two of the divided clock signals CK[0]-CK[3]. For example, the recovery signal RCK[0] is generated according to rising edges of the divided clock signals CK[0] and CK[1], the recovery signal RCK[1] is generated according to rising edges of the divided clock signals CK[1] and CK[2], the recovery signal RCK[2] is generated according to rising edges of the divided clock signals CK[2] and CK[3], and the recovery signal RCK[3] is generated according to rising edges of the divided clock signals CK[0] and CK[3]. In detail, the recovery signal RCK[0] can toggle from a low level (e.g., a logic value "0") to a high level (e.g., a logic value "1"; marked as "R_RCK[0]" in Figure 2 Figure 2 The recovery signal RCK[0] can switch from low to high (marked as "R_RCK[0]") in response to a rising edge of the divided clock signal CK[0] from low to high (marked as "F_RCK[0]") in response to a rising edge of the divided clock signal CK[l] from high to low (marked as "F_RCK[l]").
[0046] The recovery signal RCK[l] can switch from low to high (marked as "R_RCK[l]") in response to a rising edge of the divided clock signal CK[l] from low to high (marked as "F_RCK[l]"). Figure 2 The recovery signal RCK[l] can switch from low to high (marked as "R_RCK[l]") in response to a rising edge of the divided clock signal CK[l] from low to high (marked as "F_RCK[l]"). Figure 2 The recovery signal RCK[l] can switch from low to high (marked as "R_RCK[l]") in response to a rising edge of the divided clock signal CK[l] from low to high (marked as "F_RCK[l]").
[0047] The recovery signal RCK[2] can switch from low to high (marked as "R_RCK[2]") in response to a rising edge of the divided clock signal CK[2] from low to high (marked as "F_RCK[2]"). Figure 2 The recovery signal RCK[2] can switch from low to high (marked as "R_RCK[2]") in response to a rising edge of the divided clock signal CK[2] from low to high (marked as "F_RCK[2]"). Figure 2 The recovery signal RCK[2] can switch from low to high (marked as "R_RCK[2]") in response to a rising edge of the divided clock signal CK[2] from low to high (marked as "F_RCK[2]").
[0048] The recovery signal RCK[3] can switch from low to high (marked as "R_RCK[3]") in response to a rising edge of the divided clock signal CK[3] from low to high (marked as "F_RCK[3]"). Figure 2 The recovery signal RCK[3] can switch from low to high (marked as "R_RCK[3]") in response to a rising edge of the divided clock signal CK[3] from low to high (marked as "F_RCK[3]").Figure 2 The recovery signal RCK[3] is at high level only when the divided clock signal CK[3] is at high level and the divided clock signal CK[0] is at low level. In other cases (i.e., both of the divided clock signals CK[3] and CK[0] are at low level, the divided clock signal CK[3] is at low level and the divided clock signal CK[0] is at high level, and both of the divided clock signals CK[3] and CK[0] are at high level), the recovery signal RCK[3] is at low level.
[0049] Please refer to Figure 3 and Figure 4 . Figure 3 Fig. 1 is a schematic diagram of a signal recovery circuit 100 according to an embodiment of the present application. Figure 4 Fig. 2 is a schematic diagram of a first part of the signal recovery circuit 100 according to an embodiment of the present application. Figure 1 The signal recovery circuit 106 shown in Fig. 1 can be implemented by the signal recovery circuit 300. As shown in Fig. 2, the signal recovery circuit 300 can include a plurality of logic combination circuits 301, 303, 401 and 403 for generating the recovery signals RCK[0]-RCK[3], respectively. Figure 3 and Figure 4 The signal recovery circuit 300 can include a plurality of logic combination circuits 301, 303, 401 and 403 for generating the recovery signals RCK[0]-RCK[3], respectively.
[0050] The logic combination circuit 301 can be configured to receive the divided clock signals CK[0] and CK[1] for generating the recovery signal RCK[0], and can include a plurality of inverters 300, 302, 304, 305, 306, 308, 310 and 312, a NAND gate circuit 314, and a transmission gate circuit 316. The NAND gate circuit 314 has a first input port for receiving the divided clock signal CK[0] through the inverters 300 and 302, a second input port for receiving an inverted version of the divided clock signal CK[1] through the inverter 304, and an output port. In order to avoid signal conflict, the number of inverters (e.g., the inverters 300 and 302) for transmitting the divided clock signal CK[0] to the NAND gate circuit 314 is greater than the number of inverters (e.g., the inverter 304) for transmitting the divided clock signal CK[1] to the NAND gate circuit 314, which makes the timing of the divided clock signal CK[1] transmitted to the NAND gate circuit 314 earlier than the timing of the divided clock signal CK[0] transmitted to the NAND gate circuit 314.
[0051] An inverted version of the output result of the NAND gate circuit 314 can be generated by inverters 306, 308, and 310 as the recovery signal RCK[0]. For subsequent processing, the output result of the NAND gate circuit 314 can be transmitted by inverter 306, transmission gate circuit 316, and inverter 312 to subsequent circuits as an inverted version of the recovery signal RCK[0] (labeled as Figure 3 in the following ). For example, the inverter 306 has a first end and a second end coupled at the output port of the NAND gate circuit 314. The transmission gate circuit 316 can be a complementary metal-oxide-semiconductor (CMOS) including an n-type metal-oxide-semiconductor field-effect transistor (MOSFET; hereinafter referred to as an n-type transistor) and a p-type metal-oxide-semiconductor field-effect transistor (hereinafter referred to as a p-type transistor), and has an input port and an output port coupled at the second end of the inverter 306, wherein the gate end of the n-type transistor is coupled at a voltage signal Vc having a high level, and the gate end of the p-type transistor is coupled at a voltage signal Vss (e.g., the voltage signal Vss can be a ground voltage signal GND) having a low level, that is, the output result of the inverter 306 is transmitted from the input port of the transmission gate circuit 316 to the output port of the transmission gate circuit 316. The inverter 312 has a first end and a second end coupled at the output port of the transmission gate circuit 316, wherein the inverted version of the recovery signal RCK[0] is output from the second end of the inverter 312. In addition, the inverter 305 can be coupled at the output port of the NAND gate circuit 314, and can be used to generate the inverted version of the output result of the NAND gate circuit 314 as the control signal C1.
[0052] The logic combining circuit 303 can be used to receive the divided clock signals CK[1] and CK[2] for generating the recovered signal RCK[1], and can include a plurality of inverters 318, 320, 322, 324, 325, 326, 328, and 330, a NAND gate circuit 332, and a transmission gate circuit 334. The NAND gate circuit 332 has a first input port for receiving the divided clock signal CK[1] through inverters 318 and 320, a second input port for receiving an inverted version of the divided clock signal CK[2] through inverter 322, and an output port. To avoid signal collision, the number of inverters (e.g., inverters 318 and 320) used to transmit the divided clock signal CK[1] to the NAND gate circuit 332 is greater than the number of inverters (e.g., inverter 322) used to transmit the divided clock signal CK[2] to the NAND gate circuit 332, which makes the timing of the divided clock signal CK[2] transmitted to the NAND gate circuit 332 earlier than the timing of the divided clock signal CK[1] transmitted to the NAND gate circuit 332.
[0053] An inverted version of the output result of the NAND gate circuit 332 can be generated through inverters 324, 326, and 328 as the recovered signal RCK[1]. For subsequent processing, the output result of the NAND gate circuit 332 can be transmitted through inverter 324, the transmission gate circuit 334, and inverter 330 to subsequent circuits as an inverted version of the recovered signal RCK[1] (labeled as RCK[1] in Figure 3 ). For example, inverter 324 has a first end and a second end coupled at the output port of the NAND gate circuit 332. The transmission gate circuit 334 can be a complementary metal-oxide-semiconductor including an n-type transistor and a p-type transistor, and has an input port coupled at the second end of the inverter 324 and an output port, wherein the gate end of the n-type transistor is coupled at the voltage signal VC, and the gate end of the p-type transistor is coupled at the voltage signal VSS (i.e., the output result of the inverter 324 is transmitted from the input port of the transmission gate circuit 334 to the output port of the transmission gate circuit 334). Inverter 330 has a first end and a second end coupled at the output port of the transmission gate circuit 334, wherein the inverted version of the recovered signal RCK[1] is output from the second end of the inverter 330. In addition, inverter 325 can be coupled at the output port of the NAND gate circuit 332, and can be used to generate an inverted version of the output result of the NAND gate circuit 332 as the control signal C2.
[0054] The logic combination circuit 401 can include a plurality of inverters 400, 402, 404, 405, 406, 408, 410 and 412, a NAND gate circuit 414, and a transmission gate circuit 416, wherein an inverted version of the output result of the NAND gate circuit 414 is taken by the inverter 405 as the control signal C4. Since the logic combination circuit 401 is used to generate the recovered signal RCK[2] and an inverted version of the recovered signal RCK[2] (labeled as RCK[2] in Figure 4 ) from the divided clock signals CK[2] and CK[3], the operation of the logic combination circuit 401 is similar to that of the logic combination circuit 301, and similar details are not repeated here.
[0055] The logic combination circuit 403 can include a plurality of inverters 418, 420, 422, 424, 425, 426, 428 and 430, a NAND gate circuit 432, and a transmission gate circuit 434, wherein an inverted version of the output result of the NAND gate circuit 432 is taken by the inverter 425 as the control signal C5. Since the logic combination circuit 403 is used to generate the recovered signal RCK[3] and an inverted version of the recovered signal RCK[3] (labeled as RCK[3] in Figure 4 ) from the divided clock signals CK[3] and CK[0], the operation of the logic combination circuit 403 is similar to that of the logic combination circuit 301, and similar details are not repeated here.
[0056] Figure 5 Fig. 4 is a schematic diagram of a third portion of the signal recovery circuit 300 according to an embodiment of the present application. As shown in Fig. 4, the signal recovery circuit 300 can further include a plurality of NOR gate circuits 500 and 502. The NOR gate circuit 500 has a first input port receiving the control signal C1 from the logic combination circuit 301, a second input port receiving the control signal C2 from the logic combination circuit 303, and an output port, wherein the control signal C3 is generated at the output port of the NOR gate circuit 500 for subsequent processing. The NOR gate circuit 502 has a first input port receiving the control signal C4 from the logic combination circuit 401, a second input port receiving the control signal C5 from the logic combination circuit 403, and an output port, wherein the control signal C6 is generated at the output port of the NOR gate circuit 502 for subsequent processing. Figure 5
[0057] Figure 6 Fig. 5 is a schematic diagram of a fourth portion of the signal recovery circuit 300 according to an embodiment of the present application. As shown in Fig. 5, the signal recovery circuit 300 can further include a plurality of NOR gate circuits 600 and 602. The NOR gate circuit 600 has a first input port receiving the control signal C1 from the logic combination circuit 301, a second input port receiving the control signal C2 from the logic combination circuit 303, and an output port, wherein the control signal C3 is generated at the output port of the NOR gate circuit 600 for subsequent processing. The NOR gate circuit 602 has a first input port receiving the control signal C4 from the logic combination circuit 401, a second input port receiving the control signal C5 from the logic combination circuit 403, and an output port, wherein the control signal C6 is generated at the output port of the NOR gate circuit 602 for subsequent processing. Figure 6 As shown, the signal recovery circuit 300 may further include multiple signal transmission circuits 601 and 603, multiple NAND gate circuits 614 and 616, and an inverter 612. The signal transmission circuit 603 can be used to determine whether to transmit voltage signal VC or voltage signal VSS based on the recovered signals RCK[0] and RCK[1]. Specifically, the signal transmission circuit 603 may include multiple transmission gate circuits 600 and 602, an inverter 608, and an n-type transistor 620, wherein each of the transmission gate circuits 600 and 602 may be a complementary metal-oxide-semiconductor (CMOS) circuit containing an n-type transistor and a p-type transistor. The transmission gate circuit 600 has an input port for receiving the voltage signal VC, a control port for receiving the recovered signal RCK[0] (e.g., the gate of the n-type transistor receiving the recovered signal RCK[0]), and an inverted version of the recovered signal RCK[0] (in Figure 6 The middle mark is The transmission gate circuit 602 has an input port for receiving the voltage signal VSS, a control port for receiving the recovery signal RCK[1] (e.g., the gate of the n-type transistor that receives the recovery signal RCK[1]), and an inverted version of the recovery signal RCK[1] (in the p-type transistor gate terminal) and an output port. Figure 6 The middle mark is The inverter 608 has a first terminal coupled to the output port of transmission gate 600, the output port of transmission gate 602, and the drain terminal of n-type transistor 620, and a second terminal for transmitting the output result of inverter 608, wherein n-type transistor 620 can be used to transmit the output result of inverter 608. Figure 5 The control signal C3 obtained by the NOR gate circuit 500 is used to determine whether to couple the first terminal of the inverter 608 to the ground voltage signal GND (or voltage signal VSS).
[0058] In response to the control signal C3 being at a high level (i.e., the recovery signals RCK[0] and RCK[1] are both at a low level), the n-type transistor 620 determines to couple the first terminal of the inverter 608 to the ground voltage signal GND. In response to the control signal C3 being at a low level, the n-type transistor 620 determines not to couple the first terminal of the inverter 608 to the ground voltage signal GND, and the first terminal of the inverter 608 will receive the voltage signal VC or the voltage signal VSS through the transmission gate circuit 600 or the transmission gate circuit 602 according to the levels of the recovery signals RCK[0] and RCK[1].
[0059] The signal transmission circuit 601 can be used to determine whether to transmit voltage signal VC or voltage signal VSS based on the recovery signals RCK[2] and RCK[3]. Specifically, the signal transmission circuit 601 may include multiple transmission gate circuits 604 and 606, an inverter 610, and an n-type transistor 618. Each of the transmission gate circuits 604 and 606 may be a complementary metal-oxide-semiconductor (CMOS) circuit containing an n-type transistor and a p-type transistor. The transmission gate circuit 604 has an input port for receiving the voltage signal VC, a control port for receiving the recovery signal RCK[2] (e.g., the gate of the n-type transistor receiving the recovery signal RCK[2]), and an inverted version of the recovery signal RCK[2] (in the p-type transistor). Figure 6 The middle mark is The transmission gate circuit 606 has an input port for receiving the voltage signal VSS, a control port for receiving the recovery signal RCK[3] (e.g., the gate of the n-type transistor that receives the recovery signal RCK[3]), and an inverted version of the recovery signal RCK[3] (in the p-type transistor gate terminal) and an output port. Figure 6 The middle mark is The inverter 610 has a first terminal coupled to the output ports of transmission gate 604 and transmission gate 606 and the drain terminal of n-type transistor 618, and a second terminal for transmitting the output result of the inverter 610, wherein the n-type transistor 618 can be determined by... Figure 5 The control signal C6 obtained by the NOR gate circuit 502 shown is used to determine whether to couple the first terminal of the inverter 610 to the ground voltage signal GND (or voltage signal VSS).
[0060] In response to the control signal C6 being at a high level (that is, the recovery signals RCK[2] and RCK[3] are both at a low level), the n-type transistor 618 determines to couple the first terminal of the inverter 610 to the ground voltage signal GND. In response to the control signal C6 being at a low level, the n-type transistor 618 determines not to couple the first terminal of the inverter 610 to the ground voltage signal GND, and the first terminal of the inverter 610 will receive the voltage signal VC or the voltage signal VSS through the transmission gate circuit 604 or the transmission gate circuit 606 according to the level of the recovery signals RCK[2] and RCK[3].
[0061] The NOR gate circuit 614 has a first input port coupled to the second end of the inverter 608 and configured to receive the output result of the signal transmission circuit 603, a second input port coupled to the second end of the inverter 610 and configured to receive the output result of the signal transmission circuit 601, and an output port. The NOR gate circuit 616 has a first input port coupled to the output port of the NOR gate circuit 614 and configured to receive the output result of the NOR gate circuit 614, a second input port configured to receive the voltage signal VC, and an output port. The inverter 612 has a first end coupled to the output port of the NOR gate circuit 616 and a second end, wherein the inverter 612 is configured to generate an inverted version of the output result of the NOR gate circuit 616 at the second end as the recovered clock signal RCLK.
[0062] Accordingly, the signal recovery circuit 106 / 300 can be configured to perform signal recovery operations on the divided clock signals CK[0]-CK[3] to generate the recovered clock signal RCLK. Similarly, the signal recovery circuit 108 can be configured to perform signal recovery operations on the divided data strobe signals DQS[0]-DQS[3] to generate the recovered data strobe signal RDQS by using the same logic circuit configuration of the signal recovery circuit 106 / 300, for example, the logic combination circuit 301 can be modified to receive the divided data strobe signals DQS[0] and DQS[l] for generating the recovered signal RDS[0]; the logic combination circuit 303 can be modified to receive the divided data strobe signals DQS[l] and DQS[2] for generating the recovered signal RDS[l]; the logic combination circuit 401 can be modified to receive the divided data strobe signals DQS[2] and DQS[3] for generating the recovered signal RDS[2]; and the logic combination circuit 403 can be modified to receive the divided data strobe signals DQS[3] and DQS[0] for generating the recovered signal RDS[3]. The control ports of the transmission gate circuits 600, 602, 604, and 606 can be modified to receive the recovered signals RDS[0]-RDS[3], respectively, and the inverter 612 can be configured to generate an inverted version of the output result of the NOR gate circuit 616 as the recovered data strobe signal RDQS. For brevity, similar details regarding the operation of the signal recovery circuit 108 are not repeated in detail herein.
[0063] In summary, compared to the case of utilizing a clock signal and a data strobe signal for write leveling operation by imitating a plurality of delay circuits (e.g. a plurality of inverters) of a normal data write path, the signal recovery system of the present application performs write leveling operation by frequency division operation within a double data rate synchronous dynamic random access memory and signal recovery operation on the frequency divided signal, which can avoid the signal delay problem caused by process, voltage, and temperature (PVT) variation of the delay circuits (e.g. the problem of reducing skew margin between the data strobe signal and the clock signal during data write operation), so as to greatly improve the accuracy of data write operation.
[0064] The above descriptions are only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall fall within the scope of the present application.
Claims
1. A signal recovery system, comprising: Multiple frequency dividers are used to divide the clock signal and the data strobe signal separately to generate a frequency-divided clock signal and a frequency-divided data strobe signal. Multiple signal recovery circuits are used to perform signal recovery operations on the frequency-divided clock signal and the frequency-divided data gating signal respectively, so as to generate the recovered clock signal and the recovered data gating signal. as well as A data signal generation circuit is used to generate a data signal based on the recovered clock signal and the recovered data strobe signal, so as to indicate that the rising edge of the data strobe signal is at a first level or a second level of the clock signal, wherein the first level is higher than the second level.
2. The signal recovery system as described in claim 1, wherein each of the frequency-divided clock signal and the frequency-divided data strobe signal comprises a first frequency-divided signal, a second frequency-divided signal, a third frequency-divided signal, and a fourth frequency-divided signal.
3. The signal recovery system of claim 2, wherein the first frequency-divided signal is generated based on a first rising edge of the corresponding signal before the frequency division operation of each of the frequency-divided clock signal and the frequency-divided data strobe signal; the second frequency-divided signal is generated based on a first falling edge of the corresponding signal; the third frequency-divided signal is generated based on a second rising edge of the corresponding signal; and the fourth frequency-divided signal is generated based on a second falling edge of the corresponding signal.
4. The signal recovery system as claimed in claim 3, wherein for the recovered signal among the recovered clock signal and the recovered data strobe signal, the plurality of signal recovery circuits are used to generate a plurality of recovery signals based on the plurality of frequency-divided signals, and to generate the recovered signal based on the plurality of recovery signals.
5. The signal recovery system of claim 4, wherein the plurality of recovered signals includes a first recovered signal, a second recovered signal, a third recovered signal, and a fourth recovered signal.
6. The signal recovery system of claim 5, wherein the first recovery signal is generated based on a plurality of rising edges of the first frequency-divided signal and the second frequency-divided signal; the second recovery signal is generated based on a plurality of rising edges of the second frequency-divided signal and the third frequency-divided signal; the third recovery signal is generated based on a plurality of rising edges of the third frequency-divided signal and the fourth frequency-divided signal; and the fourth recovery signal is generated based on a plurality of rising edges of the first frequency-divided signal and the fourth frequency-divided signal.
7. The signal recovery system of claim 6, wherein each of the plurality of signal recovery circuits comprises a plurality of logic combination circuits; and each of the plurality of logic combination circuits corresponds to a recovered signal among the plurality of recovered signals, and comprises: A first NAND gate circuit has a first input port for receiving a first corresponding frequency-divided signal via a plurality of first inverters, a second input port for receiving an inverted version of a second corresponding frequency-divided signal via at least one second inverter, and an output port, wherein the recovered signal among the plurality of recovered signals is generated based on a plurality of rising edges of the first corresponding frequency-divided signal and the second corresponding frequency-divided signal, and the inverted version of the output result of one of the first NAND gate circuits is used as the recovered signal among the plurality of recovered signals.
8. The signal recovery system of claim 7, wherein, in response to the rising edge of the first corresponding frequency-divided signal, the recovery signal among the plurality of recovery signals switches from a third level to a fourth level; in response to the rising edge of the second corresponding frequency-divided signal, the recovery signal among the plurality of recovery signals switches from the fourth level to the third level; and the third level is lower than the fourth level.
9. The signal recovery system of claim 7, wherein the number of the plurality of first inverters is greater than the number of the at least one second inverter.
10. The signal recovery system of claim 7, wherein each of the plurality of signal recovery circuits further comprises: A first signal transmission circuit is used to determine whether to transmit a first voltage signal or a second voltage signal based on the first recovery signal and the second recovery signal, wherein the level of the first voltage signal is higher than the level of the second voltage signal; The second signal transmission circuit is used to determine whether to transmit the first voltage signal or the second voltage signal based on the third recovery signal and the fourth recovery signal. The second NAND gate circuit has a first input port for receiving the output result of one of the first signal transmission circuits and a second input port for receiving the output result of one of the second signal transmission circuits. The third NAND gate circuit has a first input port for receiving the output result of one of the second NAND gate circuits and a second input port for receiving the first voltage signal. as well as A third inverter is used to generate an inverted version of the output of one of the third NAND gates as the recovered signal.
11. The signal recovery system of claim 10, wherein the first signal transmission circuit comprises: The first transmission gate circuit has an input port for receiving the first voltage signal, a control port for receiving the first recovery signal, and an output port. The second transmission gate circuit has an input port for receiving the second voltage signal, a control port for receiving the second recovery signal, and an output port. as well as The fourth inverter has a first terminal coupled to the output port of the first transmission gate circuit, the output port of the second transmission gate circuit, and the drain terminal of one of the n-type transistors, and a second terminal for transmitting the output result of one of the fourth inverters, wherein the n-type transistor determines whether to couple the first terminal of the fourth inverter to the second voltage signal according to a control signal.
12. The signal recovery system of claim 11, wherein each of the plurality of signal recovery circuits further comprises: The NOR gate has a first input port for receiving an inverted version of the output of the first NAND gate corresponding to the first recovery signal, and a second input port for receiving an inverted version of the output of the first NAND gate corresponding to the second recovery signal, wherein the output of the NOR gate serves as the control signal.
13. The signal recovery system of claim 10, wherein the second signal transmission circuit comprises: The first transmission gate circuit has an input port for receiving the first voltage signal, a control port for receiving the third recovery signal, and an output port. The second transmission gate circuit has an input port for receiving the second voltage signal, a control port for receiving the fourth recovery signal, and an output port. as well as The fourth inverter has a first terminal coupled to the output port of the first transmission gate circuit, the output port of the second transmission gate circuit, and the drain terminal of one of the n-type transistors, and has a second terminal for transmitting the output result of one of the fourth inverters, wherein the n-type transistor determines whether to couple the first terminal of the fourth inverter to the second voltage signal according to a control signal.
14. The signal recovery system of claim 13, wherein each of the plurality of signal recovery circuits further comprises: The NOR gate has a first input port for receiving an inverted version of the output of the first NAND gate corresponding to the third recovery signal, and a second input port for receiving an inverted version of the output of the first NAND gate corresponding to the fourth recovery signal, wherein the output of the NOR gate serves as the control signal.
15. A storage device comprising: Memory controller; The memory includes: Multiple frequency dividers are used to receive clock signals and data strobe signals from the memory controller, and to divide the clock signals and data strobe signals respectively to generate a frequency-divided clock signal and a frequency-divided data strobe signal. Multiple signal recovery circuits are used to perform signal recovery operations on the frequency-divided clock signal and the frequency-divided data strobe signal respectively, so as to generate a recovered clock signal and a recovered data strobe signal; and A data signal generation circuit is used to generate a data signal based on the recovered clock signal and the recovered data strobe signal, and transmit the data signal to the memory controller to indicate that the rising edge of the data strobe signal is at a first level or a second level of the clock signal, wherein the first level is higher than the second level.