Data storage device and operating method thereof

Abstract

The invention provides a data storage device and an operating method thereof. A data storage device having an improved lifespan according to the present technology may include: a memory device including a plurality of memory cells disposed between a word line and a bit line, and a voltage generator configured to generate an operating voltage and supply the operating voltage to the plurality of memory cells; and a controller configured to control the memory device to divide the plurality of memory cells into a plurality of groups according to a line resistance from the voltage generator to each of the plurality of memory cells, and store data in memory cells included in a selected group among the plurality of groups according to an attribute of the data to be stored.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0063333, filed on May 14, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure generally relate to a data storage device and a method of operating the same, and more specifically, to a data storage device and a method of operating the same with an improved lifespan. Background Technology

[0004] Memory devices can include volatile memory devices and non-volatile memory devices. Data stored in volatile memory devices is lost when power is cut off, while data stored in non-volatile memory devices is retained even when power is cut off. A memory device can have a certain logical state depending on the physical / chemical properties of the materials used to configure the memory cells included in the memory device. Memory cells containing chalcogenide materials can have the following characteristics: lower operating speed than dynamic random access memory (DRAM), but higher capacity (integration density) than DRAM. Furthermore, memory cells containing chalcogenide materials have a smaller capacity (integration density) than NAND flash memory, but a faster operating speed than NAND flash memory. Summary of the Invention

[0005] Embodiments of this disclosure provide a memory device with improved lifespan and a method of operating the same.

[0006] According to embodiments of the present disclosure, a data storage device includes: a memory device including a plurality of memory cells and a voltage generator, the plurality of memory cells being disposed between word lines and bit lines, the voltage generator being configured to generate an operating voltage and provide the operating voltage to the plurality of memory cells; and a controller configured to control the memory device to: divide the plurality of memory cells into a plurality of groups based on line resistance from the voltage generator to each of the plurality of memory cells, and to store data in memory cells included in a selected group of the plurality of groups based on the attributes of the data to be stored.

[0007] According to an embodiment of the present disclosure, the controller includes: a cell attribute information storage device configured to store cell attribute information, the cell attribute information being information about the group to which each of a plurality of memory cells in a plurality of groups belongs.

[0008] According to embodiments of the present disclosure, a memory device includes: a word line controller configured to provide word line voltages, among operating voltages, to word lines; and a bit line controller configured to provide bit line voltages, among operating voltages, to bit lines.

[0009] According to an embodiment of the disclosure, as the path length increases, a value of the line resistance to reach each of the plurality of memory cells increases, and the path length is determined as a sum of a length of a metal wire from a voltage generator of the memory device to the word line controller and the bit line controller, a length of a word line connected from the word line controller to each of the plurality of memory cells, and a length of a bit line connected from the bit line controller to each of the plurality of memory cells.

[0010] According to an embodiment of the disclosure, the controller further includes an address allocator configured to allocate an address of a memory cell selected to store data according to the cell attribute information and an attribute of the data, and an operation processor configured to provide a command instructing to store the data in the selected memory cell to the memory device.

[0011] According to an embodiment of the disclosure, the plurality of groups include a first group, a second group, and a third group according to the line resistance.

[0012] According to an embodiment of the disclosure, the line resistance of the memory cell belonging to the second group is greater than the line resistance of the memory cell belonging to the first group and less than the line resistance of the memory cell belonging to the third group.

[0013] According to an embodiment of the disclosure, the first group includes memory cells among the plurality of memory cells whose line resistance belongs to a first range, the second group includes memory cells among the plurality of memory cells whose line resistance belongs to a second range greater than the first range, and the third group includes memory cells among the plurality of memory cells whose line resistance belongs to a third range greater than the second range.

[0014] According to an embodiment of the disclosure, when the attribute of the data is cold data having a relatively less access frequency, the address allocator allocates an address of a memory cell belonging to the first group for the data.

[0015] According to an embodiment of the disclosure, when the attribute of the data is hot data having a relatively more access frequency, the address allocator allocates an address of a memory cell belonging to the second group or the third group for the data.

[0016] According to an embodiment of the disclosure, when the attribute of the data is firmware data of the memory device, the address allocator allocates an address of a memory cell belonging to the first group for the data.

[0017] According to an embodiment of the disclosure, when the attribute of the data is user data, the address allocator allocates an address of a memory cell belonging to the second group or the third group for the data.

[0018] According to an embodiment of the disclosure, the plurality of memory cells include amorphous chalcogenide-based material.

[0019] According to an embodiment of the disclosure, a data storage device includes a memory device including a plurality of groups each including a plurality of memory cells, and a controller configured to control the memory device to store wear level information determined according to a number of times an access operation is performed on each of the plurality of groups, a type of the access operation, and an attribute of each of the plurality of groups, and to perform a wear leveling operation that moves data stored in the memory cells belonging to a group selected among the plurality of groups based on the wear level information to memory cells belonging to other groups.

[0020] According to an embodiment of the disclosure, the controller includes a wear level manager configured to update wear level information of a group including a memory cell on which an access operation is performed after the memory device performs the access operation, and a wear level information storage configured to store the wear level information.

[0021] According to an embodiment of the disclosure, the wear level information includes wear level information corresponding to each of the plurality of groups.

[0022] According to an embodiment of the disclosure, the wear level information includes bitmap data indicating whether wear level information corresponding to each of the plurality of groups exceeds a reference value.

[0023] According to an embodiment of the disclosure, the wear level manager moves data stored in a group having wear level information exceeding a reference value among the plurality of groups to other groups based on the bitmap data.

[0024] According to an embodiment of the disclosure, the wear level manager exchanges data stored in a group having wear level information exceeding a reference value among the plurality of groups with data stored in a group having wear level information less than or equal to the reference value based on the bitmap data.

[0025] According to an embodiment of the disclosure, the wear level information storage stores information about access type weights including a first access type weight corresponding to a write operation and a second access type weight corresponding to a read operation.

[0026] According to an embodiment of the disclosure, the memory device includes a voltage generator configured to generate an operation voltage and to supply the operation voltage to the plurality of memory cells, a word line controller configured to supply a word line voltage among the operation voltage to a word line, and a bit line controller configured to supply a bit line voltage among the operation voltage to a bit line, and wherein the plurality of groups are determined according to a line resistance from the voltage generator to each of the plurality of memory cells.

[0027] According to an embodiment of the disclosure, as the path length increases, a value of a line resistance to reach each of the plurality of memory cells increases, and the path length is determined as a sum of a length of a metal wire from the voltage generator to the word line controller and the bit line controller, a length of a word line connected from the word line controller to each of the plurality of memory cells, and a length of a bit line connected from the bit line controller to each of the plurality of memory cells.

[0028] According to an embodiment of the disclosure, the wear level information storage stores information about a cell attribute weight of each of a plurality of groups determined according to a size of a line resistance.

[0029] According to an embodiment of the disclosure, the information about the cell attribute weight includes a plurality of cell attribute weights that increase as the size of the line resistance decreases.

[0030] According to an embodiment of the disclosure, the wear level manager calculates the wear level information by reflecting the access type weight and the cell attribute weight in the number of times the access operation is performed.

[0031] According to an embodiment of the disclosure, the wear level manager reflects a first access type weight in the number of times the access operation is performed when the access operation is a write operation, and reflects a second access type weight smaller than the first access type weight in the number of times the access operation is performed when the access operation is a read operation.

[0032] According to an embodiment of the disclosure, the wear level manager updates the wear level information by accumulating the calculated wear level information on the previously stored wear level information.

[0033] According to an embodiment of the disclosure, the plurality of memory cells include amorphous chalcogenide-based material.

[0034] According to an embodiment of the disclosure, a data storage device includes a plurality of memory groups each including a plurality of memory cells, and a controller configured to move data in a memory cell included in one of the plurality of memory groups to a memory cell included in another memory group based on wear level information reflecting a type of an operation performed on the plurality of memory cells and a weight corresponding to each of the plurality of memory groups.

[0035] The present technology can provide a memory device having an improved lifespan and an operating method thereof. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a diagram illustrating a data storage device including a memory device according to an embodiment of the disclosure.

[0037] Figure 2 is a diagram illustrating a data storage device including a memory device according to an embodiment of the disclosure.Figure 1 a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0038] Figure 3 is a diagram illustrating voltages applied during a write operation and a read operation of a memory device according to an embodiment of the present disclosure.

[0039] Figure 4 is a diagram illustrating properties of a memory cell according to an embodiment of the present disclosure.

[0040] Figure 5 is a diagram illustrating a reference for determining a group to which a memory cell belongs according to a path length according to an embodiment of the present disclosure.

[0041] Figure 6 is a diagram illustrating a group to which a memory cell belongs according to a size of a line resistance according to an embodiment of the present disclosure.

[0042] Figure 7 is a diagram illustrating a memory device according to an embodiment of the present disclosure. Figure 1 a diagram illustrating a controller of the memory device according to an embodiment of the present disclosure.

[0043] Figure 8 is a diagram illustrating cell property information stored in a cell property information storage of the memory device according to an embodiment of the present disclosure. Figure 7

[0044] Figure 9 is a diagram illustrating cell property information stored in a cell property information storage of the memory device according to another embodiment of the present disclosure. Figure 7

[0045] Figure 10 is a flowchart illustrating an operation of a data storage device according to an embodiment of the present disclosure.

[0046] Figure 11 is a diagram illustrating a controller of the memory device according to another embodiment of the present disclosure. Figure 7

[0047] Figure 12 is a diagram illustrating wear level information stored in a wear level information storage of the memory device according to an embodiment of the present disclosure. Figure 11

[0048] is a diagram illustrating wear level information according to another embodiment of the present disclosure. Figure 13

[0049] Figure 14 is a diagram illustrating an access type weight according to an embodiment of the present disclosure.

[0050] Figure 15 is a diagram illustrating a cell property weight according to an embodiment of the present disclosure.​​​​

[0051] Figure 16 is a diagram illustrating a unit attribute weight according to another embodiment of the present disclosure.

[0052] Figure 17 is a diagram illustrating a wear leveling operation according to an embodiment of the present disclosure.

[0053] Figure 18 is a diagram illustrating a wear leveling operation according to another embodiment of the present disclosure.

[0054] Figure 19 is a flowchart illustrating an operation of a data storage device according to another embodiment of the present disclosure.

[0055] Figure 20 is a flowchart illustrating a method of updating wear level information of Figure 19 according to an embodiment of the present disclosure.

[0056] Figure 21 is a diagram illustrating a controller of Figure 1 according to still another embodiment of the present disclosure.

[0057] Figure 22 is a block diagram illustrating a user system applying a data storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] The specific structural or functional descriptions of embodiments according to the concepts disclosed in the present specification are only for describing the embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure can be implemented in various forms, and are not limited to the embodiments described in the present specification.

[0059] Hereinafter, embodiments of the present disclosure are described with reference to the accompanying drawings, in order to describe sufficient details so that those skilled in the art can practice the technical idea of the present disclosure.

[0060] Figure 1 is a diagram illustrating a data storage device including a memory device according to an embodiment of the present disclosure.

[0061] Referring to Figure 1 , the data storage device 50 can include a memory device 100 and a controller 200. The data storage device 50 can be a device that stores data under the control of a host 400 such as a cellular phone, a smart phone, a notebook computer, a desktop computer, a game machine, a smart television, a tablet PC, or an in-vehicle infotainment system. In an embodiment, the data storage device 50 can be a device that receives the control of the host 400 through wired or wireless communication by storing data in a remote location such as a server or a data center.

[0062] The data storage device 50 can be interfaced with the host 400 through various communication methods, and the data storage device 50 can be configured by various devices according to the interface method. For example, the data storage device 50 can be configured by any one of various types of storage devices such as a solid state drive (SSD), an embedded multimedia card (eMMC), a secure digital card in the form of an SD, mini-SD, and micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a PCI express (PCI-e or PCIe) card-type storage device, a compact flash (CF) card, and a smart media card.

[0063] In an embodiment, the data storage device 50 can be manufactured as any one of various types of packages. For example, the data storage device 50 can be manufactured as any one of various package types such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer level package (WFP), and a wafer level stack package (WSP).

[0064] The memory device 100 can store data. The memory device 100 can operate in response to a control of the controller 200. The memory device 100 can include a plurality of memory cells that store data.

[0065] Each memory cell can be configured to store one bit of data or a plurality of bits of data.

[0066] The memory cells can be accessed in units of a predetermined size according to the type of the memory device. The unit of accessing the memory cells can be different for each operation. For example, a write operation that stores data in the memory cells, a read operation that senses data stored in the memory cells, and an erase operation that erases data stored in the memory cells can be accessed in units of different sizes.

[0067] In an embodiment, the memory device 100 can be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change memory (PCM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM).

[0068] In general, memory cells included in the memory device 100 form an array and are configured by memory cells that store data and selectors that select the memory cells.

[0069] In a DRAM, a capacitor is used as a memory cell and a transistor is used as a selector. In the case of a NAND flash device, a transistor is used as a selector for selecting a memory cell of a string unit.

[0070] The memory device 100 according to an embodiment of the disclosure can include a single cell including a chalcogenide-based material and two electrodes. In an embodiment, the chalcogenide-based material of the memory device 100 can be referred to as a dual functional material (DFM). The DFM can have a threshold voltage similar to that of an ovonic threshold switch (OTS) used as a selector in a phase change memory (PCM).

[0071] The DFM is different from the OTS, the threshold voltage of which does not change, and the threshold voltage of the DFM can change during a bidirectional write operation. This change can be used as a memory cell, and thus the DFM can be used as both a memory cell and a selector through a bidirectional write operation. A memory device using the DFM can be a selector-only memory (SOM) device or a self-selecting memory (SSM) device.

[0072] In this specification, an embodiment is described based on the type of the memory device 100 being a phase change memory including a SOM cell, which is a memory cell including a chalcogenide-based material.

[0073] The memory device 100 can be configured to receive a command and an address from the controller 200 and access a region selected by the address in the array of memory cells. The memory device 100 can perform an operation indicated by the command on the region selected by the address. For example, the memory device 100 can perform a write operation (a program operation), a read operation, and an erase operation. During the program operation, the memory device 100 can write data in the region selected by the address. During the read operation, the memory device 100 can read data from the region selected by the address. During the erase operation, the memory device 100 can erase data stored in the region selected by the address.

[0074] The controller 200 can control the overall operation of the data storage device 50.

[0075] When power is supplied to the data storage device 50, the controller 200 can execute firmware (FW). The data storage device 50 can convert a logical address provided by the host 400 to a physical address used by the memory device 100.

[0076] The controller 200 can control the memory device 100 to perform a write operation, a read operation, an erase operation, etc., according to a request of the host 400. During the write operation, the controller 200 can provide a write command, an address, and data to the memory device 100. During the read operation, the controller 200 can provide a read command and an address to the memory device 100. During the erase operation, the controller 200 can provide an erase command and an address to the memory device 100.

[0077] The memory cells included in the memory device 100 can have a cycle endurance characteristic. The cycle endurance characteristic can be a phenomenon in which a failure occurs when a write operation to store data in the memory cells or a read operation to read the stored data is performed at a certain level or higher. A main cause of the cycle endurance characteristic can be a kind of spike current that occurs during a program operation of the memory cells. The spike current can be reduced in occurrence as the line resistance of the memory cells increases. That is, according to the size of the line resistance of each memory cell, the memory cells can show different cycle endurance characteristics, which indicates that the service life of each memory cell can be different from each other.

[0078] When the memory cells are used without considering the cycle endurance characteristic, the service life of the memory device 100 can be determined based on the memory cell having the worst cycle endurance characteristic.

[0079] In general, as the line resistance of the memory cells increases, the cycle endurance characteristic can be relatively good. This is because the frequency of occurrence of the spike current decreases as the line resistance increases. Therefore, it is necessary to consider the cycle endurance characteristic to store data.

[0080] In an embodiment, the controller 200 can allocate an address according to the attribute of data to be stored. The data to be stored in the memory device 100 can be classified into various attributes. For example, the data can be firmware (FW) data of the controller 200. Alternatively, the data can be user data stored in the memory device 100 according to a request of the host 400. The firmware (FW) data can be data that is not corrected and performs only a read operation unless there is a special case. However, the user data can be updated or corrected according to the user's needs, and the frequency of the update or correction can be significantly higher than that of the firmware (FW) data.

[0081] In various embodiments, the data can be classified into hot data or cold data. The hot data can be data that is accessed relatively more than the cold data. Here, the access can refer to a write operation performed due to the need to update or correct the data, or a read operation performed in order to use the data.

[0082] According to an embodiment, the controller 200 can assign an address indicating a location of data to be stored in the memory device 100, considering attributes of the data. That is, data accessed relatively more can be stored in a memory cell having a relatively long lifespan (i.e., a memory cell having a relatively good cycle endurance characteristic), and data accessed relatively less can be stored in a memory cell having a short lifespan (i.e., a memory cell having a relatively poor cycle endurance characteristic).

[0083] In an embodiment, the controller 200 can independently generate commands, addresses, and data, and transfer the commands, addresses, and data to the memory device 100 regardless of a request of the host 400. For example, the controller 200 can control the memory device 100 to perform various background operations to maintain performance of the memory device 100. In an embodiment, the controller 200 can control the memory device to perform a wear leveling operation of transferring data stored in a memory cell having a poor cycle endurance characteristic to a memory cell having a cycle endurance characteristic not poor by exploiting a difference in lifespan of the memory cells having different cycle endurance characteristics.

[0084] The address assignment and wear leveling will be described in more detail with reference to a block diagram of the memory device 100 later described. Figures 4 to 20

[0085] In an embodiment, the controller 200 can include an error correction code (ECC) processor. Alternatively, the ECC processor can be included in the data storage device 50 as a chip or a device separate from the controller 200. The ECC processor can detect and correct errors included in data obtained by a read operation of the memory device 100. In an embodiment, the number of bits that can be corrected by the ECC processor can be limited.

[0086] Figure 2 is a diagram illustrating a memory device 100 according to an embodiment of the disclosure. Figure 1

[0087] Referring to Figure 2 , the memory device 100 can include a memory cell array 110, a voltage generator 120, a word line (WL) controller 130, a bit line (BL) controller 140, an input and output (input / output, IO) controller 150, and an operation controller 160.

[0088] The memory cell array 110 can include memory cells disposed at points where a plurality of word lines WL1 to WLn and a plurality of bit lines BL1 to BLm cross.

[0089] ​​In an embodiment, the memory cell array 110 can include a plurality of memory blocks BLK1 to BLKx. The memory blocks can be units that are structurally or electrically driven together. Each memory cell included in the memory cell array 110 can be connected to one word line and one bit line. In an embodiment, the memory cells can include a chalcogenide-based dual functional material (DFM). The memory cells can store a logic state according to physical / chemical properties or attributes of the DFM.

[0090] In some embodiments, the memory cells can be SOM cells or self-selecting memory (SSM) cells.

[0091] The memory cells can be in one of a set state or a reset state. The set state and the reset state can have opposite polarities.

[0092] In an embodiment, the set state can represent a logic "0" and the reset state can represent a logic "1". Alternatively, the set state can represent a logic "1" and the reset state can represent a logic "0" in reverse.

[0093] The logic state of the memory cells can be detected through a read operation. The logic state of the memory cells can be based on a polarity of a voltage applied to the DFM configuring the memory cells. In an embodiment, the logic state of the memory cells can be based at least in part on a direction of a current applied to the memory cells or a polarity of a voltage applied during a write operation.

[0094] In this specification, for ease of description, the set state is defined as a logic "1" state storing data "1" and the reset state is defined as a logic "0" state storing data "0".

[0095] In an embodiment, a threshold voltage of the memory cells in the set state can be relatively higher than a threshold voltage of the memory cells in the reset state.

[0096] The voltage generator 120 can generate voltages required for operations of the memory device 100. The voltage generator 120 can generate voltages in response to a control of the operation controller 160 and provide the voltages to the word line controller 130 and the bit line controller 140. The voltage generator 120 can receive a power supply voltage from the outside and generate required voltages by distributing or pumping the power supply voltage. In an embodiment, the voltage generator 120 can further include a pumping circuit that pumps a voltage in response to a clock signal.

[0097] The word line controller 130 can provide word line voltages to the memory cells through a plurality of word lines WL1 to WLn connected to the memory cells included in the memory cell array 110, respectively.

[0098] The bit line controller 140 can provide a bit line voltage to the memory cells included in the memory cell array 110 through a plurality of bit lines BL1 to BLm connected to the memory cells, respectively.

[0099] In an embodiment, the bit line controller 140 can include a sense amplifier (not shown) that senses data stored in the memory cells through the bit lines. In addition, the bit line controller 140 can include a latch that stores the sensed data.

[0100] The input / output controller 150 can communicate data with the controller 200 described with reference to FIG. 1. Figure 1 In particular, the input / output controller 150 can receive a command, an address, or data from the controller 200, and can transfer data stored in the memory cells or internal registers to the controller 200.

[0101] The operation controller 160 can control the word line controller 130 and the bit line controller 140 so that an operation on the memory cell array can be performed. Under the control of the operation controller 160, each of the word line controller 130 and the bit line controller 140 can provide a voltage to the memory cell array.

[0102] Since the memory cells included in the memory cell array 110 have a two-dimensional or three-dimensional arrangement structure, the memory cells can have different line resistances, respectively. The line resistance of each memory cell with respect to the voltage generated by the voltage generator 120 is related to a path length corresponding to each memory cell. In particular, the path length can be the sum of the length of a metal line from the voltage generator 120 to the word line controller 130 and the bit line controller 140, the length of a word line from the word line controller 130 to each memory cell, and the length of a bit line from the bit line controller 140 to each memory cell. Since the path lengths of each memory cell are different from each other, the line resistances of each memory cell can be different. In general, as the line resistance increases, the frequency at which a sharp current occurs when the memory cell is turned on significantly decreases. Therefore, with respect to a cycle endurance characteristic, the service life of the memory cells can be different from each other due to the difference in the line resistance due to the difference in the path length.

[0103] Figure 3 is a graph showing voltages applied during a write operation and a read operation of a memory device according to an embodiment of the disclosure.

[0104] Referring to Figure 3A) shows voltages applied to a word line and a bit line connected to a memory cell during a write operation for writing a set state. B) shows voltages applied to a word line and a bit line connected to a memory cell during a write operation for writing a reset state. C) shows voltages applied to a word line and a bit line connected to a memory cell during a read operation for sensing a write state of the memory cell, i.e., for reading data stored in the memory cell.

[0105] To write a set state to the memory cell (i.e., to write data "1"), with reference to Figure 2 The operation controller 160 described above can control each of the bit line controller 140 and the word line controller 130 so that a positive voltage is applied to the bit line and a negative voltage is applied to the word line for a period of tl to t2. At this time, the potential between the bit line and the word line can be a write voltage Vwrite. The write voltage Vwrite can have a voltage level at which the memory cell can be turned on.

[0106] To write a reset state to the memory cell (i.e., to write data "0"), with reference to Figure 2 The operation controller 160 described above can control each of the bit line controller 140 and the word line controller 130 so that a negative voltage is applied to the bit line and a positive voltage is applied to the word line for a period of t3 to t4. At this time, the potential between the bit line and the word line can be a write voltage Vwrite. The write voltage Vwrite can have a voltage level at which the memory cell can be turned on.

[0107] In an embodiment, the voltage applied to the word line and the bit line to write a set state to the memory cell and the voltage applied to the word line and the bit line to write a reset state to the memory cell can have the same magnitude and opposite polarity.

[0108] During a read operation, with reference to Figure 2 The operation controller 160 described above can apply the same voltage regardless of the logic state of the memory cell. In particular, the operation controller 160 can control each of the bit line controller 140 and the word line controller 130 so that a negative voltage is applied to the word line and a positive voltage is applied to the bit line for a period of t5 to t6. The voltage level of a read voltage Vread for the voltage applied during the read operation can be lower than the voltage level of the write voltage Vwrite. Table 1 below shows the polarity of the read voltage Vread applied according to the read operation and the sensing result according to the logic state of the memory cell.

[0109] Table 1

[0110]

[0111] Upon application of a read voltage, a sense amplifier included in the bit line controller 140 can sense a state of the memory cell. When the memory cell is in a set state, as a result of performing a read operation, a sensed result of the memory cell can be sensed as an on-cell. The memory cell as an on-cell can indicate that the memory cell is turned on according to the read voltage, and can be classified as a logic '1' state. When the memory cell is in a reset state, as a result of performing a read operation, a sensed result of the memory cell can be sensed as an off-cell. The memory cell as an off-cell can indicate that the memory cell is turned off according to the read voltage, and can be classified as a logic '0' state.

[0112] Figure 4 is a diagram illustrating a property of a memory cell according to an embodiment of the disclosure.

[0113] Figure 5 is a diagram illustrating a reference for determining a group to which a memory cell belongs according to a path length according to an embodiment of the disclosure.

[0114] Referring to Figure 4 and Figure 5 , the memory cell can be formed in an array form disposed at a point where a word line and a bit line cross. As described with reference to Figure 2 , since the memory cell included in the memory cell array 110 has a two-dimensional or three-dimensional arrangement structure, the memory cell can have different path lengths, respectively. In an example shown in Figure 2 , the path length of the memory cell can be a sum of a length of a metal line from the voltage generator 120 to the word line controller 130 and the bit line controller 140, a length from the word line controller 130 to a word line of each memory cell, and a length from the bit line controller 140 to a bit line of each memory cell.

[0115] In an embodiment, the memory cell can be classified into a plurality of groups or a plurality of regions according to the path length. For example, the memory cell having a path length shorter than D1 is generally close to the word line controller 130 and the bit line controller 140, and thus can be determined as a near group. The memory cell having a path length greater than or equal to D1 and shorter than D2 can be determined as a middle group. The memory cell having a path length greater than or equal to D2 can be determined as a far group.

[0116] In Figure 4In this case, the first region can be determined as a near group. The second region, the fourth region, and the fifth region can be determined as a middle group. The third region and the sixth to ninth regions can be determined as a far group. Since the cycle endurance characteristics of the memory cells belonging to the near group can be worse than those of the memory cells belonging to the middle group or the far group, the lifespan of the memory cells belonging to the near group can be shorter than that of the memory cells belonging to the middle group or the far group. The lifespan of the memory cells belonging to the middle group can be longer than that of the memory cells belonging to the near group, but can be relatively shorter than that of the memory cells belonging to the far group. The lifespan of the memory cells belonging to the far group can be longer than that of the memory cells included in the middle group and the near group.

[0117] In another embodiment of the disclosure, the memory cells can be classified into a plurality of groups according to the size of the wire resistance. That is, the memory cells can be classified into a first group, a second group, and a third group.

[0118] As the path length of the memory cells decreases, the size of the wire resistance can decrease. Conversely, as the path length of the memory cells increases, the size of the wire resistance can increase. When the wire resistance is small, the occurrence frequency of the spike current can relatively increase. When the wire resistance is large, the occurrence frequency of the spike current can relatively decrease. Accordingly, when the size of the wire resistance is small, the cycle endurance characteristics can be relatively poor.

[0119] Accordingly, the size of the wire resistance of the memory cells belonging to the first group can be smaller than that of the memory cells belonging to the second group. The size of the wire resistance of the memory cells belonging to the second group can be smaller than that of the memory cells belonging to the third group.

[0120] Since the cycle endurance characteristics of the memory cells belonging to the first group are worse than those of the memory cells belonging to the second group or the third group, the lifespan of the memory cells belonging to the first group can be shorter than that of the memory cells belonging to the second group or the third group. The lifespan of the memory cells belonging to the second group can be longer than that of the memory cells belonging to the first group, but can be relatively shorter than that of the memory cells belonging to the third group. The lifespan of the memory cells belonging to the third group can be longer than that of the memory cells included in the second group and the first group.

[0121] Figure 6 FIG. 1 is a diagram illustrating groups to which memory cells belong according to the size of wire resistance according to an embodiment of the disclosure.

[0122] Referring to Figure 6 The memory cells can be classified into a plurality of groups or a plurality of regions according to the size of the wire resistance (LR).

[0123] Here, the wire resistance can refer to a resistance of a wire from a referenceFigure 2 The resistance of the path of the described voltage generator 120 to each memory cell.

[0124] Memory cells having a wire resistance less than R1 can be determined as a first group, memory cells having a wire resistance greater than or equal to R1 and less than R2 can be determined as a second group. Memory cells having a wire resistance greater than or equal to R2 can be determined as a third group.

[0125] Figure 7 is a diagram illustrating a controller 200 according to an embodiment of the disclosure. Figure 1 of the controller 200.

[0126] Referring to Figure 7 , the controller 200 can include an operation processor 210, an address allocator 220, a data attribute determiner 230, and a cell attribute information storage 240.

[0127] The operation processor 210 can control the overall operation of the controller 200. The operation processor 210 can receive an address allocated from the address allocator 220. The operation processor 210 can generate a command indicating an operation to be performed by the memory device 100, and provide the generated command and address to the memory device 100.

[0128] In an embodiment, when the operation to be performed by the memory device 100 is a write operation, the operation processor 210 can provide the memory device 100 with a command, an address, and data. When the operation to be performed by the memory device 100 is a read operation, the operation processor 210 can provide the memory device 100 with a command and an address.

[0129] The address allocator 220 can allocate an address of a memory cell to be accessed in the memory device 100. In particular, during a write operation, the address allocator 220 can allocate an address indicating an address of a memory cell of data to be stored, and provide the allocated address to the operation processor 210. During a read operation, the address allocator 220 can provide the operation processor 210 with an address indicating an address of a memory cell on which a read operation is to be performed.

[0130] The data attribute determiner 230 can determine an attribute of data to be stored, and provide the determined attribute of data to the address allocator 220. In particular, data to be stored in the memory device 100 can be data provided from a host, or can be data read from the memory device 100. The data attribute determiner 230 can determine and allocate an attribute of data to be stored based on various criteria. In an embodiment, the attribute of data to be stored can be one of hot data or cold data. Hot data can be data that is accessed more frequently than cold data. Here, access can refer to updating, changing, storing data, or reading stored data.

[0131] In various embodiments, the attribute of the data can be one of firmware data or user data. The firmware data can be data that is not frequently updated or changed. In contrast, the user data can be data that performs a write operation or a read operation more frequently than the firmware data by updating or changing the data according to the user's needs through the host.

[0132] The cell attribute information storage 240 can store information about attributes of the memory cells included in the memory device 100. The cell attribute information storage 240 can include information about the group to which the memory cells belong. In an embodiment, the group to which the memory cells belong can be one of a near group, a middle group, or a far group.

[0133] In various embodiments, the group to which the memory cells belong can be one of a first group, a second group, or a third group, which are divided according to a line resistance size of each memory cell.

[0134] The address allocator 220 can allocate an address based on the attribute of the data provided from the data attribute determiner 230 and the cell attribute information stored in the cell attribute information storage. For example, when the attribute of the data to be stored is cold data, an address of a memory cell belonging to a near group (or a first group) having a relatively poor cycle endurance characteristic can be allocated. In contrast, when the attribute of the data to be stored is hot data, an address of a memory cell belonging to a middle group (or a second group) or a far group (or a third group) having a relatively good cycle endurance characteristic can be allocated.

[0135] In an embodiment, when the data to be stored is firmware data, the address allocator 220 can allocate an address of a memory cell belonging to a near group (a first group). In contrast, when the data to be stored is user data, an address of a memory cell belonging to a middle group (a second group) or a far group (a third group) can be allocated.

[0136] According to an embodiment, the controller 200 can allocate an address considering the attribute of the data to be stored and the service life of the memory cells included in the memory device 100. Thereby, the controller 200 can control the memory device 100 so that the memory device 100 is used for as long as possible.

[0137] Figure 8 is a diagram illustrating cell attribute information stored in the cell attribute information storage 240 of the memory device 100 according to an embodiment of the disclosure. Figure 7

[0138] Referring to Figure 8 , the cell attribute information can include a physical address of the memory cell, a path length, and information about the group to which the memory cell belongs.

[0139] ​For example, the memory cells corresponding to physical addresses PA0-PA9 from the zeroth to the ninth physical address can have a first path length PL1, and the value of the first path length PL1 can be less than the reference. Figure 5 The description of D1. In this case, the attributes of the memory cells corresponding to the zeroth physical address to the ninth physical address PA0-PA9 can be near group.

[0140] The memory cells corresponding to the tenth to nineteenth physical addresses PA10-PA19 can have a second path length PL2, and the value of the second path length PL2 can be greater than or equal to the reference. Figure 5 The description is D1 and less than D2. In this case, the attributes of the memory cells corresponding to the tenth physical address to the nineteenth physical address PA10-PA19 can be the middle group.

[0141] The memory cells corresponding to physical addresses 20 to 29 (PA20-PA29) can have a third path length PL3, which can be greater than or equal to the reference path length PL3. Figure 5 Described as D2. In this case, the attributes of the memory cells corresponding to the twentieth physical address to the twenty-ninth physical address PA20-PA29 can be far group.

[0142] exist Figure 8 In this example, the physical addresses of each memory cell are divided into 10, but this is only for ease of description and does not limit the implementation. In various embodiments, cell attribute information of the physical addresses of 10 or fewer or 10 or more memory cells can be managed.

[0143] Figure 9 This illustrates storage according to another embodiment of the present disclosure. Figure 7 A diagram illustrating the unit attribute information in the unit attribute information storage device.

[0144] Reference Figure 9 Cell attribute information can include the physical address of the memory cell, line resistance, and information about the group to which the memory cell belongs. Figure 9 In this context, LR1 can be less than LR2, and LR2 can be less than LR3.

[0145] For example, the memory cells corresponding to physical addresses PA0-PA9 from the zeroth to the ninth physical address can have a first line resistor LR1, and the value of the first line resistor LR1 can be less than a reference value. Figure 6 R1 is described. In this case, the attributes of the memory cells corresponding to the zeroth physical address to the ninth physical address PA0-PA9 can be the first group.

[0146] The memory cells corresponding to the tenth to nineteenth physical addresses PA10-PA19 can have a second line resistance LR2, the value of which can be greater than or equal to the reference value R1 and less than R2. In this case, the attributes of the memory cells corresponding to the tenth to nineteenth physical addresses PA10-PA19 can be the second group. Figure 6 The memory cells corresponding to the twentieth to twenty-ninth physical addresses PA20-PA29 can have a third line resistance LR3, the value of which can be greater than or equal to the reference value R2. In this case, the attributes of the memory cells corresponding to the twentieth to twenty-ninth physical addresses PA20-PA29 can be the third group.

[0147] The memory cells corresponding to the twentieth to twenty-ninth physical addresses PA20-PA29 can have a third line resistance LR3, the value of which can be greater than or equal to the reference value R2. In this case, the attributes of the memory cells corresponding to the twentieth to twenty-ninth physical addresses PA20-PA29 can be the third group. Figure 6 The memory cells corresponding to the twentieth to twenty-ninth physical addresses PA20-PA29 can have a third line resistance LR3, the value of which can be greater than or equal to the reference value R2. In this case, the attributes of the memory cells corresponding to the twentieth to twenty-ninth physical addresses PA20-PA29 can be the third group.

[0148] In Figure 9 , the physical addresses of the memory cells are each divided into 10, but this is only for convenience of description and does not limit the embodiments. In various embodiments, attribute information of units of the physical addresses of 10 or less or 10 or more memory cells can be managed.

[0149] Figure 10 is a flowchart illustrating an operation of a data storage device according to an embodiment of the disclosure.

[0150] Referring to Figure 10 , in S801, a write operation of storing data in the data storage device is performed.

[0151] In S803, the data storage device can determine whether the attribute of the data to be stored is hot data. When it is determined that the attribute of the data to be stored is hot data (S803, Yes), the operation proceeds to S805. When it is determined that the attribute of the data to be stored is cold data (S803, No), the operation proceeds to S807.

[0152] In S805, the data storage device can allocate an address of a memory cell belonging to the middle group (second group) or the far group (third group) to store the hot data.

[0153] In S807, the data storage device can allocate an address of a memory cell belonging to the near group (first group) to store the cold data.

[0154] In S809, the data storage device can store the data at the allocated address.

[0155] As described above, since the memory cells included in the memory device have different cycle endurance characteristics due to the difference in path length, each memory cell can have a different lifespan that can withstand repeated read operations and write operations. By dividing the memory cells into the near group, the middle group, and the far group according to the path length, or dividing the memory cells into the first group, the second group, and the third group according to the magnitude of the line resistance, and managing the addresses by considering the attributes of the data to be stored, the lifespan of the memory device 100 can be maximized.

[0156] However, even in this case, when a specific area is repeatedly accessed according to the workload, there can be a limitation in maximizing the lifespan of the memory device. For example, even when hot data is stored in a memory cell belonging to the far group (or the third group), when intensive access occurs only to the memory cells of a specific area, as a result, the lifespan of the memory device follows the lifespan of the area in which the cycle endurance failure occurs the fastest.

[0157] According to an embodiment of Figures 11 to 20 described later, the data storage device can maximize the lifespan of the memory device by dividing the memory cells into a plurality of groups and performing a wear leveling operation that manages the wear level of each group similarly increased.

[0158] Figure 11 is a diagram illustrating a controller 200 of a data storage device according to another embodiment of the disclosure. Figure 7

[0159] Referring to Figure 11 , in addition to the operation processor 210, the address allocator 220, the data attribute determiner 230, and the cell attribute information storage 240, the controller 200 can further include a wear level manager 250 and a wear level information storage 260.

[0160] Since the operations of the operation processor 210, the address allocator 220, the data attribute determiner 230, and the cell attribute information storage 240 are substantially the same as those of the embodiment of Figure 7 , only the parts different from the embodiment of Figure 7 will be described below.

[0161] The operation processor 210 can process an access operation to the memory device 100. Here, the access operation can include a write operation to store data in the memory device 100 and a read operation to read data from the memory device 100.

[0162] When the operation processor 210 processes the access operation, the operation processor 210 can provide the wear level manager 250 with information about the address of the memory cell on which the access operation is performed and the type of the access operation. ​

[0163] The wear level manager 250 can manage a wear level of the memory device 100. In particular, the wear level manager 250 can store wear level information of memory cells included in the memory device 100. Each time an access operation to the memory device 100 is performed, the wear level manager 250 can accumulate to update the wear level information.

[0164] In an embodiment, the wear level manager 250 can generate the wear level information with respect to a number of times the access operation is performed by first reflecting an access type weight and second reflecting a cell attribute weight. The access type weight is a weight according to a type of the access operation. The cell attribute weight is a weight according to an attribute of a memory cell in which the access operation is performed. A method of generating the wear level information by the wear level manager 250 is mathematically expressed as Equation 1 below.

[0165] Equation 1

[0166] Waste level information (WLi) = Access Count (AC) × Access Type Weight (AW) × Cell Attribute Weight (CAW)

[0167] According to Equation 1, the wear level information can be a value obtained by multiplying the access count AC by the access type weight AW and then by the cell attribute weight CAW. The access count AC is a number of times the access operation is performed. The access type weight AW is a weight according to a type of the access operation. The cell attribute weight CAW is a weight according to a cell attribute of the memory cell.

[0168] In particular, a stress level of a write operation and a read operation of the SOM cell can be different. For example, a stress level of a case where the read operation is performed can be about 10% compared to a stress level of a case where the write operation is performed. That is, according to a type of the access operation, the stress level can be different, such as a stress level of a case where the write operation is performed once is similar to a stress level of a case where the read operation is performed 8 to 9 times. Therefore, in order to manage the wear level of the SOM memory device, it is necessary to reflect a weight according to a type of the access operation, rather than simply counting a number of times the access operation is performed.

[0169] As described with reference to Figure 4 Since the memory cells can have different cycle endurance characteristics due to a difference in the path length, each of the memory cells can have a different lifespan that can withstand repeated read operations and write operations. Therefore, even in a case of managing the wear level, it is necessary to divide the memory cells into a plurality of groups according to the path length and to reflect the cell attribute weight according to the attribute of the path length of the memory cell.

[0170] In this embodiment, precise management of loss levels can be achieved by reflecting weights based on the type of access operation and cell attribute weights based on the path length or line resistance of the memory cell targeted by the access operation, rather than simply managing the number of access operations.

[0171] The loss level information storage device 260 can store loss level information generated by the loss level manager 250. The loss level manager 250 can generate loss level information each time an access operation is performed. The loss level manager 250 can update the loss level information using a value obtained by adding the generated loss level information to existing loss level information previously stored in the loss level information storage device 260.

[0172] In this embodiment, loss level information can be managed in the form of bitmap data, which indicates whether the loss level exceeds a reference value. Storing and managing loss level information for all memory cells could require a large amount of storage capacity. However, when loss level information is calculated and stored in bitmap form to determine whether the loss level exceeds a reference value, the amount of data to be stored can be reduced.

[0173] In this embodiment, when loss level information exceeding a reference value is generated, the loss level manager 250 can perform a loss leveling operation. Specifically, when loss level information exceeding a reference value is generated, the loss level manager 250 can control the memory device 100 to perform the loss leveling operation via the operating processor 210.

[0174] In various embodiments, the loss level manager 250 can periodically monitor loss level information. That is, to prevent performance degradation due to loss leveling operations, the decision to perform a loss leveling operation can be determined by checking the loss level information for each preset time period, rather than performing the operation every time loss level information exceeding a reference value is generated. Specific methods for performing loss leveling operations will be described later. Figure 17 and Figure 18 A more detailed description.

[0175] Figure 12 This illustrates the storage according to embodiments of the present disclosure. Figure 11 A diagram showing the loss level information stored in the loss level information storage device 260.

[0176] Reference Figure 12 This allows for the management of wear level information for each physical address group of memory cells. For example, the wear level information for physical addresses zero to nine (PA0 to PA9) could be a first wear level WLi1, and the wear level information for physical addresses ten to nineteen (PA10 to PA19) could be a second wear level WLi2. Similarly, refer to...Figure 11 The described wear level manager 250 can store the wear level information of the memory cells included in the memory device in a wear level information storage 260.

[0177] In an embodiment, the wear level information storage 260 can be implemented as a volatile memory device. For example, the wear level information storage 260 can be implemented as a DRAM or an SRAM. In various embodiments, the wear level information storage 260 can also be implemented as a non-volatile memory device.

[0178] In Figure 12 In various embodiments, the physical addresses of 10 or less or 10 or more memory cells can be managed with respect to the wear level information.

[0179] Figure 13 FIG. 4 is a diagram illustrating wear level information according to another embodiment of the disclosure.

[0180] Referring to Figure 13 , the wear level information can be in the form of bitmap data. In particular, the wear level information can be managed in the form of bitmap data indicating whether the calculated wear level information exceeds a reference value.

[0181] In various embodiments, when the wear level information is managed with the bitmap data, the wear level information can be converted based on normalized data by adjusting the range of the data.

[0182] In Figure 13 , the wear level information is illustrated in the form of bits expressed in the number of x columns and y rows. One bit can indicate whether the wear level information of a plurality of memory cells exceeds a reference value. For example, one bit can correspond to memory cells accessed at the same time when one write operation or read operation is performed.

[0183] The memory cell 11 in which the bitmap data is stored as "1" can indicate that the wear level information exceeds the reference value. The memory cell 12 in which the bitmap data is stored as "0" can indicate that the wear level information is less than or equal to the reference value. In various embodiments, the memory cell in which the bitmap data is stored as "0" can be a memory cell included in an empty area in which no data is stored.

[0184] When the wear level information of all memory cells is individually stored and managed, a large amount of storage capacity can be required. However, when the wear level information is calculated and then whether the wear level information exceeds the reference value is stored in the form of bitmap, the amount of data to be stored can be reduced.

[0185] Figure 14is a diagram illustrating access type weights according to an embodiment of the disclosure.

[0186] Referring to Figure 14 , the access types can include a first access type weight AW1 corresponding to a write operation and a second access type weight AW2 corresponding to a read operation.

[0187] The values of the first access type weight AW1 and the second access type weight AW2 can be determined through experiments performed in a manufacturing step or a test step of the memory device.

[0188] In general, the value of the first access type weight AW1 can be greater than the value of the second access type weight AW2. For example, the first access type weight AW1 can be 1 and the second access type weight AW2 can be 0.11. This case indicates that the degree of wearout and wear of the memory cell can be greater in the case where the read operation is performed 10 times than in the case where the write operation is performed once.

[0189] In Figure 14 , only the first access type weight AW1 corresponding to the write operation and the second access type weight AW2 corresponding to the read operation are illustrated. However, in addition to the write operation and the read operation, the access type weights can include more access type weights for each operation performed.

[0190] The access type weights can be stored in the wear level information storage 260 described with reference to Figure 11 .

[0191] Figure 15 is a diagram illustrating cell attribute weights according to an embodiment of the disclosure.

[0192] Referring to Figure 15 , the plurality of memory cells included in the memory device can be divided into a near group, a middle group, and a far group according to path lengths. Alternatively, in various embodiments, the plurality of memory cells can be divided into a first group, a second group, and a third group according to the size of line resistance. Since the path length of the memory cell belonging to the near group is shorter than the path length of the memory cell belonging to the middle group, a cycle endurance failure can occur more easily. Since the path length of the memory cell belonging to the middle group is shorter than the path length of the memory cell belonging to the far group, a cycle endurance failure can occur more easily. Accordingly, the number of cycles allowed can be different according to which group the memory cell belongs to.

[0193] Accordingly, even if the same access operation is performed, the remaining useful life of the memory cell belonging to the near group can still be greatly reduced. To take this into account, referring to Figure 11The described wear-level manager 250 can reflect different weights depending on which group the target memory cell performing the access operation belongs to (according to the cell attribute of the target memory cell).

[0194] For example, the cell attribute weight for memory cells belonging to the near group can be a first cell attribute weight CAW1. The cell attribute weight for memory cells belonging to the middle group can be a second cell attribute weight CAW2. The cell attribute weight for memory cells belonging to the far group can be a third cell attribute weight CAW3.

[0195] Since the longer the path length of a memory cell, the relatively better the cycle endurance characteristics, the second cell attribute weight CAW2 can be less than the first cell attribute weight CAW1, and the third cell attribute weight CAW3 can be less than the second cell attribute weight CAW2. For example, the first cell attribute weight CAW1 can be 1, the second cell attribute weight CAW2 can be 0.5, and the third cell attribute weight CAW3 can be 0.1.

[0196] In various embodiments, since the line resistance of memory cells belonging to the first group is less than the line resistance of memory cells belonging to the second group, cycle endurance failures can be more likely to occur. Since the line resistance of memory cells belonging to the second group is less than the line resistance of memory cells belonging to the third group, cycle endurance failures can be more likely to occur. Thus, depending on which group a memory cell belongs to, the number of cycles allowed can be different.

[0197] Thus, even if the same access operation is performed, the remaining useful life of memory cells belonging to the first group can still be greatly reduced. To account for this, reference is made to Figure 11 The described wear-level manager 250 can reflect different weights depending on which group the target memory cell performing the access operation belongs to (according to the cell attribute of the target memory cell).

[0198] For example, the cell attribute weight for memory cells belonging to the first group can be a first cell attribute weight CAW1. The cell attribute weight for memory cells belonging to the second group can be a second cell attribute weight CAW2. The cell attribute weight for memory cells belonging to the third group can be a third cell attribute weight CAW3.

[0199] Since the longer the path length of a memory cell, the relatively better the cycle endurance characteristics, the second cell attribute weight CAW2 can be less than the first cell attribute weight CAW1, and the third cell attribute weight CAW3 can be less than the second cell attribute weight CAW2. For example, the first cell attribute weight CAW1 can be 1, the second cell attribute weight CAW2 can be 0.5, and the third cell attribute weight CAW3 can be 0.1.

[0200] Figure 16 is a diagram illustrating cell attribute weights according to another embodiment of the disclosure.

[0201] Referring to Figure 16 , unlike the embodiment of Figure 15 , the memory cell groups can be divided into a zeroth group G0 to a fifteenth group G15. The cell attribute weights corresponding to the zeroth group G0 to the fifteenth group G15, respectively, can be a zeroth cell attribute weight CAW0 to a fifteenth cell attribute weight CAW15.

[0202] The path length of the memory cell belonging to the zeroth group G0 can be the shortest, and the path length of the memory cell belonging to the fifteenth group G15 can be the longest. The path length can gradually become longer from the zeroth group G0 to the fifteenth group G15.

[0203] The size of the line resistance of the memory cell belonging to the zeroth group G0 can be the smallest, and the size of the line resistance of the memory cell belonging to the fifteenth group G15 can be the largest. The size of the line resistance can increase from the zeroth group G0 to the fifteenth group G15.

[0204] The value of the zeroth cell attribute weight CAW0 can be the largest, and the value of the fifteenth cell attribute weight CAW15 can be the smallest. The size can gradually decrease from the zeroth cell attribute weight CAW0 to the fifteenth cell attribute weight CAW15.

[0205] In the case where the cell attribute weights according to the embodiment of Figure 16 are applied, the wear level information can be more accurately calculated than in the case where the cell attribute weights according to the embodiment of Figure 15 are applied.

[0206] Figure 17 is a diagram illustrating a wear leveling operation according to an embodiment of the disclosure.

[0207] In Figure 17 , the memory device includes memory cells divided into first to ninth groups (a total of nine groups) GROUP1 to GROUP9. Referring to Figure 17 , the wear leveling operation can be performed in the order of T1 to T3.

[0208] At the T1 period, first data is stored in the first group, second data is stored in the second group, and third data is stored in the third group. The fourth to ninth groups of memory cells can not store data. At the T1 period, the wear level information of all groups in the form of 1-bit bitmap data can be "0" according to the wear level information, and groups whose wear level information exceeds a reference value can not be generated.

[0209] At the T2 period, the wear level information of the first group becomes "1" according to the wear level information in the form of the 1-bit bitmap data per group. This can indicate that the wear level information of the first group exceeds the reference value. In this case, the data storage device can perform a wear leveling operation so that the memory cells belonging to another group store the data stored in the first group. At this time, the group whose wear level information is "0" can be the second group to the ninth group. Since the data is stored in the second group and the third group, the data storage device can move the data to the memory cells belonging to one of the fourth group to the ninth group which are empty of data.

[0210] At the T3 period, when the first data is moved to the memory cells belonging to the fourth group, the data storage device can reset the wear level information of the first group to "0". Figure 17

[0211] At the T3 period, when the first data is moved to the memory cells belonging to the fourth group, the data storage device can reset the wear level information of the first group to "0".

[0212] Figure 18 is a diagram illustrating a wear leveling operation according to another embodiment of the disclosure.

[0213] At the T4 period, according to the wear level information in the form of the 1-bit bitmap data per group at the T4 period, the wear level information of all groups can be "0", and no group whose wear level information exceeds the reference value is generated. Figure 18 Figure 17 In the embodiment, unlike the embodiment of Figure 18 , the memory device includes memory cells divided into the first group to the ninth group (a total of nine groups) GROUP1 to GROUP9, and the first data to the ninth data DATA1 to DATA9 are respectively stored in the first group to the ninth group GROUP1 to GROUP9. Referring to , the wear leveling operation can be performed in the order from T4 to T6.

[0214] At the T4 period, according to the wear level information in the form of the 1-bit bitmap data per group at the T4 period, the wear level information of all groups can be "0", and no group whose wear level information exceeds the reference value is generated.

[0215] At the T5 period, the wear level information of the first group becomes "1" according to the wear level information in the form of the 1-bit bitmap data per group. This can indicate that the wear level information of the first group exceeds the reference value. In this case, the data storage device can perform a wear leveling operation so that the memory cells belonging to another group store the data stored in the first group. In determining a target group to which the first data stored in the first group is to be moved, since there is no group empty of data, the data storage device can select one of the groups whose wear level information is "0". For example, the data storage device can perform a wear leveling operation of changing (swapping) the fourth data stored in the memory cells belonging to the fourth group and the first data stored in the memory cells belonging to the first group.

[0216] ​At the T6 period, the first data can be stored in the memory cell belonging to the fourth group, and the fourth data can be stored in the memory cell belonging to the first group. Thereafter, the data storage device can reset the wear level information of the 1st group to "0".

[0217] Figure 17 and Figure 18 The wear leveling operation describes a case where the wear leveling is performed when the wear level information exceeds the reference value. However, in various embodiments, the wear leveling operation can be performed at a preset period.

[0218] Figure 19 is a flowchart illustrating an operation of a data storage device according to another embodiment of the disclosure.

[0219] Referring to Figure 19 , at S1701, the data storage device can perform an access operation.

[0220] At S1703, the data storage device can update the wear level information about the performed access operation. The specific method of updating the wear level information is described in more detail with reference to Figure 18 .

[0221] At S1705, the data storage device can determine whether the wear level information exceeding the reference value is generated. When it is determined that the wear level information exceeding the reference value is generated (S1705, Yes), the operation proceeds to S1707, and otherwise, the operation ends.

[0222] At S1707, the data storage device can perform a wear leveling operation so that data stored in a group corresponding to the wear level information exceeding the reference value is stored in a memory cell belonging to another group.

[0223] Figure 20 is a flowchart illustrating a method of updating the wear level information of Figure 19 according to an embodiment of the disclosure.

[0224] Referring to Figure 20 , at S1801, the data storage device can determine whether the performed access operation is a write operation. As a result of the determination, when the performed access operation is the write operation (S1801, Yes), the method proceeds to S1803. When it is determined that the performed access operation is the read operation (S1801, No), the method proceeds to S1805.

[0225] At S1803, the data storage device can reflect the access type weight corresponding to the write operation as 1, which is the number of times of performing the access operation.

[0226] The data storage device can reflect the access type weight corresponding to the read operation as 1, which is the number of times of performing the access operation, at S1805. The value of the access type weight corresponding to the read operation can be less than the value of the access type weight corresponding to the write operation.

[0227] The data storage device can reflect the cell attribute weight at S1807. In particular, the data storage device can reflect the weight according to the attribute of the memory cell in which the access operation is performed.

[0228] The data storage device can store (update) the generated wear level information in the wear level information storage device at S1809.

[0229] Figure 21 is a diagram illustrating a controller of Figure 1 according to another embodiment of the disclosure.

[0230] Referring to Figure 21 , the memory controller 800 can include a processor 810, a RAM 820, an error correction circuit 830, a host interface 840, a ROM 850, and a memory interface 860. The memory controller 800 can be the controller 200 described with reference to Figure 1 .

[0231] The processor 810 can control the overall operation of the memory controller 800. The RAM 820 can be used as a buffer memory, a cache memory, an operation memory, etc. of the memory controller 800. The operation processor 210, the address allocator 220, the data attribute determiner 230, and the wear level manager 250 described with reference to Figure 7 and Figure 11 may be stored in the ROM 850 or the RAM 820 in the form of software executed by the processor 810. In addition, the cell attribute information storage device 230 and the wear level information storage device 260 can be included in the RAM 820.

[0232] The ROM 850 can store various information required for the memory controller 800 to be executed in the form of firmware.

[0233] The memory controller 800 can communicate with an external device (e.g., the host 400, an application processor, etc.) through the host interface 840.

[0234] The memory controller 800 can communicate with the memory device 100 through the memory interface 860. The memory controller 800 can transmit a command CMD, an address ADDR, a control signal CTRL, etc. to the memory device 100 through the memory interface 860, and can receive data DATA.

[0235] Figure 22is a block diagram illustrating a user system to which a data storage apparatus according to an embodiment of the disclosure is applied.

[0236] Referring to Figure 22 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0237] The application processor 4100 can drive components included in the user system 4000, an operating system (OS), a user program, etc. For example, the application processor 4100 can include a controller, an interface, a graphic engine, etc. that control components included in the user system 4000. The application processor 4100 can be provided as a system on chip (SoC).

[0238] The memory module 4200 can operate as a main memory, an operation memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 can include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PCM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 can be packaged based on package on package (POP) and provided as one semiconductor package.

[0239] The network module 4300 can communicate with an external device. For example, the network module 4300 can support wireless communication such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 can be included in the application processor 4100.

[0240] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transfer data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 can be implemented with a non-volatile semiconductor memory element such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash, NOR flash, and three-dimensional NAND flash. In an embodiment, the storage module 4400 can be a solid state drive (SSD). Figure 1The described data storage device 50. Optionally, in various embodiments, the storage module 4400 can be provided as a removable storage device (removable drive) such as a memory card and an external drive of the user system 4000.

[0241] For example, the storage module 4400 can include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices can operate identically to the memory device 100 described with reference to Figure 1 The storage module 4400 can operate identically to the data storage device 50 described with reference to Figure 1 The storage module 4400 can operate identically to the data storage device 50 described with reference to

[0242] The user interface 4500 can include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 can include a user input interface such as a keypad, a key, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezo element. The user interface 4500 can include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a display.

[0243] The inventive concept has been disclosed in connection with some embodiments described above. It will be appreciated by persons skilled in the art that various modifications, additions and substitutions can be made thereto without departing from the scope and spirit of the disclosure. Therefore, the embodiments disclosed in the specification should not be taken as limiting, but are made as illustrative only. The scope of the inventive concept is not limited by the above description but is only limited by the claims attached hereto, and all modifications and alterations equivalent to those described are to be understood within the scope of the inventive concept. Furthermore, the embodiments can be combined into additional embodiments.

Claims

1. A data storage device, comprising: A memory device includes a plurality of memory cells and a voltage generator, the plurality of memory cells being disposed between word lines and bit lines, the voltage generator generating an operating voltage and providing the operating voltage to the plurality of memory cells; as well as The controller controls the memory device: The plurality of memory cells are divided into multiple groups based on the line resistance from the voltage generator to each of the plurality of memory cells, and Based on the attributes of the data to be stored, the data is stored in a memory unit included in a selected group among the plurality of groups.

2. The data storage device according to claim 1, wherein, The controller includes: A unit attribute information storage device stores unit attribute information, which is information about the group to which each of the plurality of memory units belongs.

3. The data storage device according to claim 2, wherein, The memory device includes: Word line controller, providing the word line voltage, one of the operating voltages, to the word line; and The bit line controller provides the bit line voltage, one of the operating voltages, to the bit line.

4. The data storage device according to claim 3, wherein, As the path length increases, the value of the line resistance reaching each of the plurality of memory cells increases, and The path length is determined as the sum of the length of the metal line from the voltage generator of the memory device to the word line controller and the bit line controller, the length of the word line from the word line controller to each of the plurality of memory cells, and the length of the bit line from the bit line controller to each of the plurality of memory cells.

5. The data storage device according to claim 2, wherein, The controller further includes: An address allocator, based on the cell attribute information and the attributes of the data, allocates an address to the memory cell selected for storing the data; and The processor operates by providing a command to the memory device instructing the data to be stored in a selected memory cell.

6. The data storage device according to claim 5, wherein, Based on the line resistance, the plurality of groups includes a first group, a second group, and a third group.

7. The data storage device according to claim 6, wherein, The line resistance of memory cells belonging to the second group is greater than that of memory cells belonging to the first group and less than that of memory cells belonging to the third group.

8. The data storage device according to claim 6, wherein, The first group includes memory cells whose line resistance falls within a first range among the plurality of memory cells. The second group includes memory cells among the plurality of memory cells whose line resistance falls within a second range, where the second range is larger than the first range, and The third group includes memory cells among the plurality of memory cells whose line resistance belongs to a third range, and the third range is greater than the second range.

9. The data storage device according to claim 7, wherein, When the data is cold data with relatively low access frequency, the address allocator assigns an address to the data belonging to the memory cell of the first group.

10. The data storage device according to claim 7, wherein, When the data is hot data with a relatively high access frequency, the address allocator assigns an address to the data belonging to the memory cell of the second group or the third group.

11. The data storage device according to claim 7, wherein, When the attribute of the data is firmware data of the memory device, the address allocator assigns an address to the data belonging to a memory cell of the first group.

12. The data storage device according to claim 7, wherein, When the attribute of the data is user data, the address allocator assigns an address to the data belonging to a memory cell in the second group or the third group.

13. The data storage device according to claim 1, wherein, The plurality of memory cells comprise amorphous chalcogenide-based materials.

14. A data storage device, comprising: A memory device comprising multiple groups, each group comprising multiple memory cells; as well as The controller controls the memory device: The system stores loss level information determined based on the number of access operations performed on each of the plurality of groups, the type of the access operations, and the attributes of each of the plurality of groups. A loss leveling operation is performed to move data stored in memory cells belonging to a group selected based on the loss level information from the plurality of groups to memory cells belonging to other groups.

15. The data storage device according to claim 14, wherein, The controller includes: A loss level manager updates the loss level information of a group including the memory cells that performed the access operation after an access operation is performed on the memory device; and A loss level information storage device for storing the loss level information.

16. The data storage device according to claim 15, wherein, The loss level information includes loss level information corresponding to each of the plurality of groups.

17. The data storage device according to claim 15, wherein, The loss level information includes bitmap data indicating whether the loss level information corresponding to each of the plurality of groups exceeds a reference value.

18. The data storage device according to claim 17, wherein, The loss level manager moves data from the group containing loss level information exceeding the reference value, which is stored in the plurality of groups, to other groups based on the bitmap data.

19. The data storage device according to claim 17, wherein, The loss level manager, based on the bitmap data, exchanges data from groups containing loss level information exceeding the reference value with data from groups containing loss level information less than or equal to the reference value.

20. The data storage device according to claim 15, wherein, The loss level information storage device stores information about access type weights, including a first access type weight corresponding to a write operation and a second access type weight corresponding to a read operation.

21. The data storage device according to claim 20, wherein, The memory device includes: A voltage generator generates an operating voltage and provides the operating voltage to the plurality of memory cells; The word line controller provides the word line voltage, one of the operating voltages, to the word line; and The bit line controller provides the bit line voltage, which is part of the operating voltage, to the bit line, and The plurality of groups are determined based on the line resistance from the voltage generator to each of the plurality of memory cells.

22. The data storage device according to claim 21, wherein, As the path length increases, the value of the line resistance reaching each of the plurality of memory cells increases, and The path length is determined as the sum of the length of the metal lines from the voltage generator to the word line controller and the bit line controller, the length of the word lines from the word line controller to each of the plurality of memory cells, and the length of the bit lines from the bit line controller to each of the plurality of memory cells.

23. The data storage device according to claim 22, wherein, The loss level information storage device stores information about the cell attribute weights of each of the plurality of groups, determined based on the magnitude of the line resistance.

24. The data storage device according to claim 23, wherein, Information regarding the unit attribute weights includes multiple unit attribute weights that increase as the line resistance decreases.

25. The data storage device according to claim 23, wherein, The loss level manager calculates the loss level information by reflecting the access type weight and the cell attribute weight in the number of times the access operation is performed.

26. The data storage device according to claim 23, wherein, The loss level manager reflects the first access type weight in the number of times the access operation is performed when the access operation is a write operation, and reflects the second access type weight in the number of times the access operation is performed when the access operation is a read operation, wherein the second access type weight is less than the first access type weight.

27. The data storage device according to claim 23, wherein, The loss level manager updates the loss level information by adding calculated loss level information to previously stored loss level information.

28. The data storage device according to claim 14, wherein, The plurality of memory cells comprise amorphous chalcogenide-based materials.

29. A data storage device, comprising: Multiple memory groups, each memory group comprising multiple memory cells; as well as The controller moves data stored in memory cells within one of the multiple memory groups to memory cells within other memory groups, based on loss level information reflecting the type of operation performed on the multiple memory cells and the weight corresponding to each of the multiple memory groups.

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