Memory device performing link ECC operation and method of operating same

Abstract

The invention relates to a memory device performing a link ECC operation and an operating method thereof. A memory device includes: a syndrome calculator configured to generate an error position signal based on first data and an error correction code; an error corrector configured to generate second data by correcting an error in the first data according to the error position signal; and a data masking (DM) calculation circuit configured to generate a DM signal according to a logical high bit of the first data, and to calculate the error position based on the error position signal, the logic level of the DM signal is changed according to at least one of the increase signal and the decrease signal by activating the increase signal when an error bit is detected in a logic low bit of the first data, and activating the decrease signal when the error bit is detected in a logic high bit of the first data.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0064465, filed on May 17, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to semiconductor design techniques, and more specifically, to a memory system including a memory device that supports link error correction code (ECC) operation, data masking (DM) operation, and data bus inversion (DBI) operation. Background Technology

[0004] In the early stages of the semiconductor memory industry, memory chips manufactured using semiconductor manufacturing processes produced defect-free memory cells. However, as memory device capacity increased, manufacturing memory devices without defective memory cells became difficult. Currently, it is virtually impossible to manufacture a memory device without any defective memory cells. To address this issue, repair methods are being used, such as replacing defective memory cells with redundant ones, or error correction methods using on-chip error correction circuits to correct errors in the memory device.

[0005] As the communication speed of the channel between the memory controller and the memory device is increasing, so is the interest in the accuracy of signal transmission. Therefore, a method for correcting errors that may occur in channel transmission has been proposed. This method employs link error correction circuitry in the memory controller and memory device at both ends of the channel, transmits data along with error correction codes at the data transmitting end, and uses the received error correction codes at the data receiving end to correct errors in the received data. Summary of the Invention

[0006] Embodiments of this disclosure relate to a memory device and a method of operating the same that support link error correction code (ECC) operation, data masking (DM) operation, and data bus inversion (DBI) operation.

[0007] According to embodiments of the present disclosure, a memory device includes: a corrector calculator configured to generate an error location signal based on first data and an error correction code; an error corrector configured to generate second data by correcting errors in the first data according to the error location signal; and a data masking (DM) calculation circuit configured to generate a DM signal based on the logic high bits of the first data, and to change the logic level of the DM signal based on at least one of the increase signal and decrease signal by activating an increase signal when an error bit is detected in the logic low bits of the first data and activating a decrease signal when an error bit is detected in the logic high bits of the first data.

[0008] According to embodiments of the present disclosure, a memory device includes: a correction calculator configured to generate a first error location signal and a second error location signal based on first data and an error correction code, the first data including m burst data input via data pads over m burst lengths, where m is a positive integer; an error corrector configured to generate second data by correcting errors in the first data according to the first error location signal and the second error location signal; and a plurality of data masking (DM) calculators configured to generate DM signals corresponding to the m burst data, each DM calculator being configured to: generate an amplification signal and a decrementation signal by detecting whether an error has occurred in the corresponding burst data according to the first error location signal and the second error location signal; and generate the corresponding DM signal according to at least one of the amplification signal and the decrementation signal.

[0009] According to an embodiment of the present disclosure, a method of operating a memory device includes: generating an error location signal based on first data and an error correction code; generating second data by correcting errors in the first data according to the error location signal; generating a data masking (DM) signal based on the logic high bits of the first data; and changing the logic level of the DM signal according to at least one of the increment signal and decrement signal by activating an increment signal when an error bit is detected in the logic low bits of the first data and activating a decrement signal when an error bit is detected in the logic high bits of the first data; and writing the second data into a memory core by selectively masking the second data according to the DM signal.

[0010] According to embodiments of this disclosure, the memory device can minimize write latency by performing error correction operations and DM calculation operations in parallel during link ECC operations. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a storage system according to an embodiment of the present disclosure.

[0012] Figure 2 This is a detailed configuration diagram of a memory device according to an embodiment of the present disclosure.

[0013] Figure 3 It is used to describe Figure 2 A diagram showing the configuration of the input / output signals.

[0014] Figure 4 It is shown Figure 2 Detailed configuration diagram of the write error correction circuit and DM calculation circuit.

[0015] Figure 5 It is shown Figure 4 Detailed configuration diagram of the calibrator calculator.

[0016] Figure 6A and Figure 6B It is shown Figure 4 The circuit diagram and waveform diagram of the error corrector.

[0017] Figure 7 This is a detailed block diagram illustrating any DM calculator according to embodiments of the present disclosure.

[0018] Figure 8 It is used for explanation Figure 7 The table showing the operation of the DM calculator.

[0019] Figure 9 It is shown Figure 7 The circuit diagram of the first logic determinant.

[0020] Figure 10 It is shown Figure 7 The circuit diagram of the second logic determinant.

[0021] Figure 11 It is shown Figure 7 The circuit diagram of the first change detector.

[0022] Figure 12 It is shown Figure 7 The circuit diagram of the second change detector.

[0023] Figure 13 It is shown Figure 7 The circuit diagram of the masking signal generation circuit.

[0024] Figure 14A and Figure 14B It is used for explanation Figure 7 The waveform diagram of the operation of the DM calculator.

[0025] Figure 15 This is a detailed block diagram illustrating a DM calculator according to another embodiment of the present disclosure.

[0026] Figure 16 It is shown Figure 15 The circuit diagram of the first change detector.

[0027] Figure 17 It is shown Figure 15 The circuit diagram of the second change detector.

[0028] Figure 18 It is shown Figure 15 The circuit diagram of the masking signal generation circuit.

[0029] Figure 19A and Figure 19B It is used to describe Figure 15 The waveform diagram of the operation of the DM calculator. Detailed Implementation

[0030] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the embodiments of the present disclosure may take different forms and should not be construed as limited to those described herein. Rather, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the disclosure to those skilled in the art. Throughout this disclosure, the same reference numerals denote the same parts in the various figures and embodiments of the present disclosure.

[0031] It is understood that when an element is referred to as "coupled" or "connected" to another element, this may mean that the two elements are directly coupled, or that they are electrically connected to each other through another circuit inserted between them. It should also be understood that the terms "comprising," "including," "having," etc., as used in this specification, specify the presence of said features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In this disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0032] Figure 1 This is a block diagram illustrating a storage system 10 according to an embodiment of the present disclosure.

[0033] Reference Figure 1 The storage system 10 can store or retrieve stored data in response to a request REQ provided by the host. The storage system 10 can be used as a primary or secondary storage device for the host. The storage system 10 can be used as a device that stores data under the control of the host, such as mobile phones, smartphones, MP3 players, laptops, desktop computers, game consoles, televisions, tablets, and in-vehicle infotainment systems.

[0034] The storage system 10 may include a first semiconductor device 100 and a second semiconductor device 200 as electronic components communicating with each other. The first semiconductor device 100 may be a master device, and the second semiconductor device 200 may be a slave device operating under the control of the first semiconductor device 200.

[0035] The first semiconductor device 100 may be a host device such as a processor or controller, and may include a central processing unit (CPU), a graphics processing unit (GPU), a multimedia processor (MMP), a digital signal processor, and a memory controller. Furthermore, the first semiconductor device 100 may be implemented as a system-on-a-chip (SoC) by combining processor chips (e.g., application processors (APs)) with multiple functions.

[0036] The second semiconductor device 200 may be a memory device and may include volatile memory and / or non-volatile memory. Volatile memory may include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and low-power double data rate (LPDDR) DRAM. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically erasable programmable ROM (EEPROM), electrically programmable ROM (EPROM), flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0037] The first semiconductor device 100 can control the overall operation of the second semiconductor device 200 and control the data exchange between the host and the second semiconductor device 200. The first semiconductor device 100 can send command and address (command / address) signals C / A to the second semiconductor device 200 via channel CH, and can also send and receive data DQ with the second semiconductor device 200 via channel CH. For example, the first semiconductor device 100 can provide a command / address signal C / A indicating a read operation to the second semiconductor device 200 according to the host's request REQ. The first semiconductor device 100 can provide data DQ and a command / address signal C / A indicating a write operation to the second semiconductor device 200 according to the host's request REQ. The first semiconductor device 100 can receive data DQ read from the second semiconductor device 200 and provide the read data DQ to the host. Although in Figure 1 In this diagram, the command / address signal C / A and the data DQ are shown as signals transmitted through a pad and a line, but the command / address signal C / A and the digital DQ can each be composed of signals transmitted through multiple pads and lines.

[0038] The first semiconductor device 100 may include a link ECC engine 110. During a write operation, the first semiconductor device 100 can generate an error correction code PAR using the data DQ and provide the error correction code PAR along with the data DQ to the second semiconductor device 200. During a read operation, the first semiconductor device 100 can receive the error correction code PAR along with the data DQ and correct errors in the data DQ using the error correction code PAR. Although Figure 1 Not shown, but in addition to the link ECC engine 110, the first semiconductor device 100 may also include an additional system ECC engine.

[0039] The second semiconductor device 200 may include a link ECC engine 210 and an on-chip ECC engine 250. During a write operation, the link ECC engine 210 can receive an error correction code PAR and data DQ from the first semiconductor device 100, use the error correction code PAR to correct errors in the data DQ, and provide the error-corrected data to the on-chip ECC engine 250. During a write operation, the on-chip ECC engine 250 can use the error-corrected data to generate an internal error correction code and store the error-corrected data and the internal error correction code in a memory region (hereinafter referred to as a memory core). During a read operation, the on-chip ECC engine 250 can receive data and the internal error correction code from the memory core and generate error-corrected data by correcting errors in the data using the internal error correction code. During a read operation, the link ECC engine 210 can use the error-corrected data sent from the on-chip ECC engine 250 to generate the error correction code PAR and output the data DQ (i.e., the error-corrected data) and the error correction code PAR to the first semiconductor device 100.

[0040] As described above, the first semiconductor device 100 and the second semiconductor device 200 can perform link ECC operation to first correct temporary errors on the channel used for transmitting and receiving data DQ between them by transmitting and receiving data DQ together with error correction code PAR via channel CH. In this way, the accuracy of data transmission on the communication link (i.e., channel CH) between the first semiconductor device 100 and the second semiconductor device 200 can be guaranteed.

[0041] First semiconductor device 100 and second semiconductor device 200 can transmit and receive information signal DMI via channel CH. During a write operation, first semiconductor device 110 can provide information signal DMI to instruct a data bus inversion (DBI) operation and / or a data masking (DM) operation on data DQ. When information signal DMI is set to a first logic level (e.g., logic high), second semiconductor device 200 can perform a DBI operation on the inverted bits of data DQ. Furthermore, second semiconductor device 200 can generate a data masking (DM) signal by counting the number of logic high bits of data DQ to determine whether to perform a DM operation. According to one embodiment, second semiconductor device 200 can generate the DM signal only when information signal DMI is at a second logic level (e.g., logic low).

[0042] In conventional technology, after performing a link ECC operation during a write operation, the second semiconductor device 200 can generate a DM signal by counting the number of logic high bits of the error-corrected data according to the information signal DMI. Here and below, the term "logic high bit" refers to a bit with a logic high level, and the term "logic low bit" refers to a bit with a logic low level. Therefore, the write latency caused by performing the error correction operation and DM calculation operation sequentially (or serially) is extended.

[0043] In the following, according to embodiments of the present disclosure, a method for reducing write latency by performing error correction operations and DM calculation operations simultaneously (or in parallel) will be discussed.

[0044] In the following, a detailed configuration of the second semiconductor device 200 according to an embodiment of the present disclosure will be described with reference to the accompanying drawings. The case where the second semiconductor device 200 is a memory device will be described as an example. In this disclosure, descriptions of command / address signals input to the memory device 200 will be omitted.

[0045] Figure 2 This is a detailed configuration diagram of a memory device 200 according to an embodiment of the present disclosure.

[0046] Reference Figure 2 The memory device 200 may include a memory core 201, a write circuit 202, a read circuit 203, a link ECC engine 210, a DM calculation circuit 220, a DBI control circuit 230, an on-chip ECC engine 250, first to third input circuits 271, 273 and 275, and first to third output circuits 272, 274 and 276.

[0047] The first input circuit 271 can receive data DQ input through data pad P1 as write data D_WT<0:127>. The first output circuit 272 can output read data D_RD<0:127> sent from DBI control circuit 230 as data DQ through data pad P1. The first input circuit 271 can parallelize data DQ into write data D_WT<0:127>. The first output circuit 272 can serialize read data D_RD<0:127> into data DQ. The first input circuit 271 may include multiple receivers corresponding to data pad P1. The first output circuit 272 may include multiple transmitters corresponding to data pad P1.

[0048] The second input circuit 273 can receive the error correction code PAR input through the parity pad P2 as the write error correction code P_WT<0:8>. The second output circuit 274 can output the read error correction code P_RD<0:8> sent from the link ECC engine 210 as the error correction code PAR through the parity pad P2.

[0049] The third input circuit 275 can receive the write DBI signal DBI_WT<0:15> from the information pad P3. The third output circuit 276 can output the read DBI signal DBI_RD<0:15> from the DBI control circuit 230 as the information signal DMI through the information pad P3.

[0050] The link ECC engine 210 may include a write error correction circuit 211 and a read error correction circuit 212. During a write operation, the write error correction circuit 211 may generate a corrector SYN based on the write data D_WT<0:127> and the write error correction code P_WT<0:8>. The corrector SYN may include information about the bits in the 128 bits of the write data D_WT<0:127> where errors are located. Furthermore, the write error correction circuit 211 may correct errors in the write data D_WT<0:127> based on the corrector SYN to generate corrected data D_WTE<0:127>. During a read operation, the read error correction circuit 212 may generate a read error correction code P_RD<0:8> using the read data D_RD<0:127> sent from the DBI control circuit 230.

[0051] The DM calculation circuit 220 can generate a data masking (DM) signal DM_BL<0:15> based on the written data D_WT<0:127> and the SYN counter. The DM calculation circuit 220 can generate the DM signal DM_BL<0:15> by counting the number of logic high bits of the written data D_WT<0:127>, and simultaneously change the DM signal DM_BL<0:15> according to the SYN counter.

[0052] The DBI control circuit 230 may include a write inverting circuit 231, a read inverting circuit 232, and a DBI calculation circuit 233. During a write operation, the write inverting circuit 231 can generate write data D1<0:127> by selectively inverting bits of the error-corrected data D_WTE<0:127> according to the write DBI signal DBI_WT<0:15>. The DBI calculation circuit 233 can generate a read DBI signal DBI_RD<0:15> by using error-corrected data D2<0:127> provided from the on-chip ECC engine 250. During a read operation, the read inverting circuit 232 can generate read data D_RD<0:127> by selectively inverting bits of the error-corrected data D2<0:127> according to the read DBI signal DBI_RD<0:15>.

[0053] During a write operation, the on-chip ECC engine 250 can use the write data D1<0:127> to generate an internal error correction code INT_P<0:7>, and send the write data D1<0:127> and the internal error correction code INT_P<0:7> to the write circuit 202. During a read operation, the on-chip ECC engine 250 can use the internal error correction code INT_P'<0:7> sent from the read circuit 203 to correct errors in the data D1'<0:127> provided by the read circuit 203, thereby generating corrected data D2<0:127>.

[0054] The link ECC engine 210 and the on-chip ECC engine 250 can perform error correction operations using different ECC methods or the same ECC method. For example, the link ECC engine 210 uses a single error correction double error detection (SECDED) code, which is based on Hamming codes or cyclic redundancy check (CRC) codes to correct one erroneous bit in the data and detect two erroneous bits. In contrast, the on-chip ECC engine 250 can use a single error correction (SEC) code (which is based on Hamming codes to correct one erroneous bit in the data) or a SECDED code. Figure 2 The diagram illustrates that the internal error correction code INT_P<0:7> or INT_P'<0:7> used by the on-chip ECC engine 250 consists of fewer bits (e.g., 8 bits) than the error correction code P_WT<0:8> or P_RD<0:8> used by the link ECC engine 210. However, embodiments of this disclosure are not limited thereto. According to the specification, the internal error correction code INT_P<0:7> and the error correction code P_WT<0:8> can be set to the same number of bits or different bits.

[0055] During a write operation, the write circuit 202 can write write data D1<0:127> and internal error correction code INT_P<0:7> to the memory core 201. The write circuit 202 can perform a DM operation according to the DM signal DM_BL<0:15> to mask some bits of the write data D1<0:127> and the internal error correction code INT_P<0:7>.

[0056] During a read operation, the read circuit 203 can read data D1'<0:127> and internal error correction code INT_P'<0:7> from the memory core 201.

[0057] In memory devices, the number of data bits input and output in a single operation can be determined based on the burst length. For example, refer to... Figure 3 When the burst length is set to 16 (i.e., BL16), the 128-bit data DQ can be input and output through eight data pads P1, and each burst length can input and output 8 bits of data. In the following text, the data input and output for each burst length will be defined as burst data DQ_BL#<0:7>, where the reference number # can be determined based on the set burst length. For reference, see [reference]. Figure 3 For a burst length of BL16, the 16-bit information signal DMI can be serially input and output through the information pad P3.

[0058] Figure 4 It is shown Figure 2 Detailed configuration diagram of the write error correction circuit 211 and the DM calculation circuit 220. Figure 4 In the example shown, the written data D_WT<0:127> consists of the first to the sixteenth burst data DQ_BL0<0:7> to DQ_BL15<0:7>.

[0059] Reference Figure 4 The error correction circuit 211 may include a corrector calculator 211A and an error corrector 211B.

[0060] The corrector calculator 211A can use the first to sixteenth burst data DQ_BL0<0:7> to DQ_BL15<0:7> to generate preliminary error correction codes (e.g., Figure 5The error correction code (E_P<0:8>) is compared with the written error correction code (P_WT<0:8>) to generate a corrector SYN. ​​The corrector SYN may include a first error location signal S_BL<0:15> and a second error location signal S_DQ<0:7>. The first error location signal S_BL<0:15> may include information about the burst length of the erroneous data within the 16 burst lengths. The second error location signal S_DQ<0:7> may include information about the data pad in data pad P1 where the erroneous data was input. That is, any bit of the burst data containing the error in the first to sixteenth bursts DQ_BL0<0:7> to DQ_BL15<0:7> can be specified by the first error location signal S_BL<0:15> and the second error location signal S_DQ<0:7>. (Refer to...) Figure 5 Describe the detailed configuration of the calibrator calculator 211A.

[0061] Error corrector 211B can generate first to sixteenth error-corrected burst data DQD_BL0<0:7> to DQD_BL15<0:7> by correcting errors in the first to sixteenth burst data DQ_BL0<0:7> to DQ_BL15<0:7> according to the first error position signal S_BL<0:15> and the second error position signal S_DQ<0:7>. The first to sixteenth error-corrected burst data DQD_BL0<0:7> to DQD_BL15<0:7> can constitute the error-corrected data D_WTE<0:127>. (See reference...) Figure 6A and Figure 6B Describe the detailed configuration of the error corrector 211B.

[0062] The DM calculation circuit 220 may include first to sixteenth DM calculators 220_0 to 220_15 corresponding to the first to sixteenth burst data DQ_BL0<0:7> to DQ_BL15<0:7>, to generate first to sixteenth DM signals DM_BL0 to DM_BL15 corresponding to each burst length. Each of the DM calculators 220_0 to 220_15 can generate the corresponding DM signal by counting the number of logic high bits of the corresponding burst data. Each of the DM calculators 220_0 to 220_15 can generate an increase signal and / or decrease signal by detecting whether an error has occurred in the corresponding burst data according to the first error position signal S_BL<0:15> and the second error position signal S_DQ<0:7>, and change the corresponding DM signal according to the increase signal and / or decrease signal. The first to sixteenth DM signals DM_BL0 to DM_BL15 can constitute the DM signal DM_BL<0:15>. (Refer to...) Figures 7 to 1 9. Describe the detailed configuration of the DM computing circuit 220.

[0063] Figure 5 It is shown Figure 4 Detailed configuration diagram of the calibrator calculator 211A.

[0064] Reference Figure 5 The calibrator calculator 211A may include a code calculation circuit 310 and an error location detection circuit 320.

[0065] The code calculation circuit 310 can use the first to sixteenth burst data DQ_BL0<0:7> to DQ_BL15<0:7> to generate the preliminary error correction code E_P<0:8>. For example, the code calculation circuit 310 can use a parity check matrix, also known as the H matrix, to generate the preliminary error correction code E_P<0:8>. However, embodiments of this disclosure are not limited thereto; the code calculation circuit 310 can generate the preliminary error correction code E_P<0:8> by applying known BCH codes, Hamming codes, RS codes, etc., or by applying another type of parity check code.

[0066] The error location detection circuit 320 can compare the preliminary error correction code E_P<0:8> with the written error correction code P_WT<0:8>> for each bit to generate a first error location signal S_BL<0:15> indicating the burst length where an error exists, and a second error location signal S_DQ<0:7> indicating the data pad where an error exists.

[0067] Figure 6A and Figure 6B It is shown Figure 4 The circuit diagram and waveform diagram of the error corrector 211B.

[0068] Reference Figure 6A The error corrector 211B may include first to 128 error correction units 400_0 to 400_127 corresponding to each bit of the written data D_WT<0:127>.

[0069] Each of the first to 128 error correction units 400_0 to 400_127 can receive the bit S_BL of the first error location signal S_BL<0:15> corresponding to its burst length. <y>And the bits S_DQ of the second error location signal S_DQ<0:7> corresponding to its data pad <x>In the following text, bit S_BL <y>The first error position bit S_BL <y>Bit S_DQ <x>The second error position bit S_DQ <x>Each of the first to the 128th error correction units 400_0 to 400_127 may include an inverting control unit 410, a delay unit 420, and an inverting unit 430.

[0070] The inverting control section 410 can be based on the first error position bit S_BL <y>Second error position bit S_DQ <x>The first inverting control signal INV and the second inverting control signal INVB are generated. For example, the inverting control section 410 can control the first error position bit S_BL. <y>Second error position bit S_DQ <x>The second inverting control signal INVB is generated by performing a logical AND-NOT operation, and the first inverting control signal INV is generated by inverting the second inverting signal INVB. When both the first error position bit S_BL<y> and the second error position bit S_DQ<x> become logic high, the inverting control section 410 can generate the first inverting control signal INV as logic high.

[0071] Delay unit 420 can be controlled by changing the input bit DQ_BLy <x>The delayed signal DD is generated after a predetermined delay time.

[0072] The inverting section 430 can generate the output bit DQD_BLy by selectively inverting the delayed signal DD according to the first inverting control signal INV and the second inverting control signal INVB. <x>Output bits: DQD_BLy <x>These bits can be used to construct error-corrected burst data. For example, when the first inverting control signal INV goes high, the inverting section 430 can invert the delayed signal DD, outputting the inverted delayed signal as the output bit DQD_BLy. <x>When the second inverting control signal INVB goes high, the inverting section 430 can output a delayed signal DD as the output bit DQD_BLy. <x>.

[0073] Reference Figure 6B When both the first error location bit S_BL<y> and the second error location bit S_DQ<x> become logic high, the first inverting control signal INV becomes logic high. The inverting section 430 can invert the delayed signal DD to output the inverted delayed signal as the output bit DQD_BLy. <x>On the other hand, when the first error bit is S_BL <x>Second error position bit S_DQ <y>When one of the signals goes low, the second inverting control signal INVB goes high. The inverting section 430 can output a delayed signal DD as the output bit DQD_BLy without inverting the signal. <x>.

[0074] With the above configuration, one of the first to 128 error correction units 400_0 to 400_127 can be selected by the first error position signal S_BL<0:15> and the second error position signal S_DQ<0:7>. The selected error correction unit can invert (i.e., correct) the input bit DQ_BLy. <x>Output bit DQD_BLy <x>.

[0075] Figure 7 is a detailed block diagram illustrating the first DM calculator 220_0 according to an embodiment of the disclosure. Figure 8 is a table for describing the operation of the DM calculator 220_0 of Figure 7 . Each of the second through sixteenth DM calculators 220_1 through 220_15 can have substantially the same configuration as the first DM calculator 220_0.

[0076] Referring to Figure 7 , the first DM calculator 220_0 can include a logic determination circuit 510, an error variation detection circuit 530, and a masking signal generation circuit 550. The first DM calculator 220_0 can further include an inverting logic 560 for generating inverted data DQ_BLB0<2:7> by inverting the first burst data DQ_BL0<2:7>.

[0077] The logic determination circuit 510 can generate first through sixth high bit signals S1A, S2A, S3A, S1B, S2B, and S3B indicating the number of logic high bits of the first burst data DQ_BL0<0:7>, respectively. The logic determination circuit 510 can divide the remaining six bits DQ_BL0<2:7> of the first burst data DQ_BL0<0:7> except for the least significant bits DQ_BL0<0:1> into low bits DQ_BL0<2:4> and high bits DQ_BL0<5:7> to generate the first through sixth high bit signals S1A, S2A, S3A, S1B, S2B, and S3B by counting the number of high bits of the low bits DQ_BL0<2:4> and the high bits DQ_BL0<5:7>, respectively.

[0078] More specifically, the logic determination circuit 510 can include a first logic determiner 512 and a second logic determiner 514. The first logic determiner 512 can generate first through third high bit signals S1A, S2A, and S3A indicating the number of logic high bits of the low bits DQ_BL0<2:4>. The first logic determiner 512 can activate one of the first through third high bit signals S1A, S2A, and S3A when there is one or more logic high bits in the low bits DQ_BL0<2:4>. The second logic determiner 514 can generate fourth through sixth high bit signals S1B, S2B, and S3B indicating the number of logic high bits of the high bits DQ_BL0<5:7>. For example, the second logic determiner 514 can activate one of the fourth through sixth high bit signals S1B, S2B, and S3B when there is one or more logic high bits in the high bits DQ_BL0<5:7>.

[0079] The error change detection circuit 530 can be activated according to the first error position signal S_BL<0:15>, and generates an increasing signal INC or a decreasing signal DECB by detecting whether there is an error bit in the first burst data DQ_BL0<2:7> according to the second error position signal S_DQ<2:7>. The error change detection circuit 530 can generate an increasing signal INC or a decreasing signal DECB according to the corresponding bit of the first error position signal S_BL<0:15> (i.e., the first bit S_BL). <0> The bit is activated, and this bit corresponds to the first burst data DQ_BL0<2:7>. In embodiments of this disclosure, the error change detection circuit 530 can activate the increase signal INC when an error bit exists in the logic low bit of the first burst data DQ_BL0<2:7>, and activate the decrease signal DECB when an error bit exists in the logic high bit of the first burst data DQ_BL0<2:7>.

[0080] More specifically, the error change detection circuit 530 may include a first change detector 532 and a second change detector 534.

[0081] The first change detector 532 can determine the first bit S_BL of the first error position signal S_BL<0:15>. <0> The increment signal INC is activated when the corresponding bits of the inverted data DQ_BLB0<2:7> and the second error position signal S_DQ<2:7> are both logic high bits. For example, when the first bit of the first error position signal S_BL<0:15> is S_BL... <0> It is the logic high bit and the bit of inverted data DQ_BLB0<2:7>. <3> The bits S_DQ of the second error position signal S_DQ<2:7> <3> When it becomes a logic high bit, the first change detector 532 can activate the amplification signal INC.

[0082] The second change detector 534 can determine the first bit S_BL of the first error position signal S_BL<0:15>. <0> The decrement signal DECB is activated when the corresponding bits of the first burst data DQ_BL0<2:7> and the second error position signal S_DQ<2:7> are both logic high bits. For example, when the first bit of the first error position signal S_BL<0:15> is S_BL... <0> It is the high-order logical bit and the bit DQ_BL0 when the first burst of data DQ_BL0<2:7> <3> The bits S_DQ of the second error position signal S_DQ<2:7> <3> When the signal changes to a logic high bit, the second change detector 534 can activate the decrease signal DECB. In this embodiment, the increase signal INC can be activated to a logic high level, while the decrease signal DECB can be activated to a logic low level.

[0083] The masking signal generation circuit 550 can generate a first DM signal DM_BL0 based on the first to sixth high-bit signals S1A, S2A, S3A, S1B, S2B and S3B, and change the logic level of the first DM signal DM_BL0 according to the increase signal INC and the decrease signal DECB.

[0084] In embodiments of this disclosure, when the number of logic high bits of the first burst data DQ_BL0<2:7> is greater than or equal to a reference value, the masking signal generation circuit 550 can activate the first DM signal DM_BL0. Furthermore, when the number of logic high bits is equal to the reference value or a boundary value, the masking signal generation circuit 550 can change the logic level of the first DM signal DM_BL0 according to the increment signal INC and the decrement signal DECB. Both the reference value and the boundary value are positive integers, and the boundary value can be set to a number that is one less than the reference value.

[0085] exist Figure 8 In this circuit, the reference value is set to 5, and the boundary value is set to 4. When the third high-order bit signal S3A and the sixth high-order bit signal S3B are activated, or when the third high-order bit signal S3A and the fifth high-order bit signal S2B are activated, or when the second high-order bit signal S2A and the sixth high-order bit signal S3B are activated, the masking signal generation circuit 550 can determine that the number of logic high-order bits is greater than or equal to the reference value 5, thereby activating the first DM signal DM_BL0. When the third high-order bit signal S3A and the fifth high-order bit signal S2B are activated, or when the second high-order bit signal S2A and the sixth high-order bit signal S3B are activated, the masking signal generation circuit 550 can determine that the number of logic high-order bits is equal to the reference value 5 (marked with dots), thereby changing the logic level of the first DM signal DM_BL0 according to the decrement signal DECB. When the first high-order bit signal S1A and the sixth high-order bit signal S3B are activated, when the second high-order bit signal S2A and the fifth high-order bit signal S2B are activated, or when the third high-order bit signal S3A and the fourth high-order bit signal S1B are activated, the masking signal generation circuit 550 can determine that the number of logic high-order bits is equal to the boundary value 4 (marked with a slash), and thus change the logic level of the first DM signal DM_BL0 according to the increment signal INC.

[0086] Figure 9 It is shown Figure 7 The circuit diagram of the first logic determinant 512.

[0087] Reference Figure 9 The first logic determiner 512 may include a first XOR gate X11 and a second XOR gate X12, first to seventh NAND gates ND11 to ND17, and first to fifth inverters INV11 to INV15.

[0088] The first XOR gate X11 and the second XOR gate X12 can generate a first deterministic signal LA1 by performing a logical XOR operation on the low-order bits DQ_BL0<2:4>. The first inverter INV11 can generate a second deterministic signal LA2 by inverting the first deterministic signal LA1. With the above configuration, when there are an even number of logic low bits in the low-order bits DQ_BL0<2:4>, the first deterministic signal LA1 can be activated to a logic high level, and when there are an even number of logic high bits in the low-order bits DQ_BL0<2:4>, the second deterministic signal LA2 can be activated to a logic high level.

[0089] The first NAND gate ND11 can be used to check the low-order DQ_BL0. <2> and low-order DQ_BL0 <3> Performs a logical NAND operation. The second NAND gate ND12 can perform a logical NAND operation on the lower-order DQ_BL0. <3> and low-order DQ_BL0 <4> Performs a logical NAND operation. The third NAND gate ND13 can perform a logical NAND operation on the lower-order bit DQ_BL0. <2> and low-order DQ_BL0 <4> Perform a logical NAND operation. The fourth NAND gate ND14 can perform a logical NAND operation on the outputs of the first to third NAND gates ND11 to ND13 to generate the third determination signal MA1. The second inverter INV12 can invert the third determination signal MA1 to generate the fourth determination signal MA2. With the above configuration, when at least two of the low-order bits DQ_BL0<2:4> are logic high bits, the third determination signal MA1 can be activated to a logic high level, and when at least two of the low-order bits DQ_BL0<2:4> are logic low bits, the fourth determination signal MA2 can be activated to a logic high level.

[0090] The fifth NAND gate ND15 and the third inverter INV13 can generate the first high-order bit signal S1A by performing a logical AND operation on the first determination signal LA1 and the fourth determination signal MA2. Therefore, when there is a logic high bit in the low-order bits DQ_BL0<2:4>, the first high-order bit signal S1A can be activated to a logic high level.

[0091] The sixth NAND gate ND16 and the fourth inverter INV14 can generate the second high-order bit signal S2A by performing a logical AND operation on the second deterministic signal LA2 and the third deterministic signal MA1. Therefore, when there are two high-order bits in the low-order bits DQ_BL0<2:4>, the second high-order bit signal S2A can be activated to a logic high level.

[0092] The seventh NAND gate ND17 and the fifth inverter INV15 can generate the third high-order bit signal S3A by performing a logical AND operation on the first deterministic signal LA1 and the third deterministic signal MA1. Therefore, when there are three logic high-order bits in the low-order bits DQ_BL0<2:4>, the third high-order bit signal S3A can be activated to a logic high level.

[0093] Figure 10 It is shown Figure 7 The circuit diagram of the second logic determinant 514.

[0094] Reference Figure 10 The second logic determiner 514 may include a first XOR gate X21 and a second XOR gate X22, first to seventh NAND gates ND21 to ND27, and first to fifth inverters INV21 to INV25. Since the second logic determiner 514 has essentially the same configuration as the first logic determiner 512, its detailed description will be omitted.

[0095] With the above configuration, when there is one logic high bit in the high-order DQ_BL0<5:7>, the second logic determiner 514 can activate the fourth high-order bit signal S1B to a logic high level; when there are two logic high bits in the high-order DQ_BL0<5:7>, the second logic determiner 514 can activate the fifth high-order bit signal S2B to a logic high level; and when there are three logic high bits in the high-order DQ_BL0<5:7>, the second logic determiner 514 can activate the sixth high-order bit signal S3B to a logic high level.

[0096] Figure 11 It is shown Figure 7 The circuit diagram of the first change detector 532.

[0097] Reference Figure 11 The first change detector 532 may include first to fifth NAND gates ND31 to ND35, NOR gate NR3 and inverter INV3.

[0098] The first to third NAND gates ND31 to ND33 can control the corresponding bits of the inverted data DQ_BLB0<2:7>, the corresponding bits of the second error position signal S_DQ<2:7>, and the first bit S_BL of the first error position signal S_BL<0:15>. <0> Perform logical AND and NOT operations to generate the incremented detection bits INCB<2:7>. When the first bit S_BL... <0> When it becomes a logic high bit, if the corresponding bit of the inverted data DQ_BLB0<2:7> and the corresponding bit of the second error position signal S_DQ<2:7> are both logic high bits, each of the first to third NAND gates ND31 to ND33 can output the corresponding increased detection bit as a logic low bit.

[0099] The fourth NAND gate ND34 performs a logical NAND operation on the increment detection bits INCB<2:4>. The fifth NAND gate ND35 performs a logical NAND operation on the increment detection bits INCB<5:7>. The NOR gate NR3 and the inverter INV3 generate the increment signal INC by performing a logical OR operation on the outputs of the fourth NAND gate ND34 and the fifth NAND gate ND35. That is, when one of the increment detection bits INCB<2:7> becomes a logic low bit, the increment signal INC can be activated to a logic high level.

[0100] With the above configuration, the first change detector 532 can determine the first bit S_BL of the first error position signal S_BL<0:15>. <0> When activated, and when the logic high bit of the inverted data DQ_BLB0<2:7> (i.e. the logic low bit of the first burst data DQ_BL0<2:7>) is detected as an error bit, the output is activated as an increased logic high signal INC.

[0101] Figure 12 It is shown Figure 7 The circuit diagram of the second change detector 534.

[0102] Reference Figure 12 The second change detector 534 may include first to fifth NAND gates ND41 to ND45 and NOR gate NR4.

[0103] The first to third NAND gates ND41 to ND43 can control the corresponding bits of the first burst data DQ_BL0<2:7>, the corresponding bits of the second error position signal S_DQ<2:7>, and the first bit S_BL of the first error position signal S_BL<0:15>. <0> Perform logical AND and NOT operations to generate the reduced detection bits DECB<2:7>. When the first bit S_BL... <0> When it becomes a logic high bit, if the corresponding bit of the first burst data DQ_BL0<2:7> and the corresponding bit of the second error position signal S_DQ<2:7> are both logic high bits, each of the first NAND gate ND41 to the third NAND gate ND43 can output the corresponding reduced detection bit as a logic low bit.

[0104] The fourth NAND gate ND44 performs a logical NAND operation on the decrement detection bits DECB<2:4>. The fifth NAND gate ND45 performs a logical NAND operation on the decrement detection bits DECB<5:7>. The NOR gate NR4 generates the decrement signal DECB by performing a logical NOR operation on the outputs of the fourth NAND gate ND44 and the fifth NAND gate ND45. That is, when one of the decrement detection bits DECB<2:7> becomes a logic low bit, the decrement signal DECB can be activated to a logic low level.

[0105] With the above configuration, the second change detector 534 can determine the first bit S_BL of the first error position signal S_BL<0:15>. <0> When activated, and when the logic high bit of the first burst data DQ_BL0<2:7> is detected as an error bit, the output is activated as a decreasing signal DECB with a logic low level.

[0106] Figure 13 It is shown Figure 7 The circuit diagram of the masking signal generation circuit 550.

[0107] Reference Figure 13 The masking signal generation circuit 550 may include a first signal generator 551, a second signal generator 552, and a signal combiner 553.

[0108] When the increment signal INC is activated, the first signal generator 551 can generate the first preliminary signal DM_PRE1, which is activated to a logic high level, by detecting that the number of logic high bits of the first burst data DQ_BL0<2:7> is equal to the boundary value based on the first to sixth high bit signals S1A, S2A, S3A, S1B, S2B and S3B.

[0109] More specifically, the first signal generator 551 may include a first NAND gate ND51 through a fourth NAND gate ND54. The first NAND gate ND51 performs a logical NAND operation on the increment signal INC, the third high-order bit signal S3A, and the fourth high-order bit signal S1B. The second NAND gate ND52 performs a logical NAND operation on the increment signal INC, the first high-order bit signal S1A, and the sixth high-order bit signal S3B. The third NAND gate ND53 performs a logical NAND operation on the increment signal INC, the second high-order bit signal S2A, and the fifth high-order bit signal S2B. The fourth NAND gate ND54 performs a logical NAND operation on the outputs of the first NAND gate ND51 through the third NAND gate ND53.

[0110] The second signal generator 552 can generate a second preliminary signal DM_PRE2 that is activated to a logic high level by detecting that the number of logic high bits of the first burst data DQ_BL0<2:7> is greater than or equal to a reference value based on the first to sixth high bit signals S1A, S2A, S3A, S1B, S2B and S3B. When the decrement signal DECB is activated to a logic low level when the number of logic high bits is equal to the reference value, the second preliminary signal DM_PRE2 is deactivated to a logic low level.

[0111] More specifically, the second signal generator 552 may include a fifth NAND gate ND55 through an eighth NAND gate ND58. The fifth NAND gate ND55 performs a logical NAND operation on the decrement signal DECB, the third high-order bit signal S3A, and the fifth high-order bit signal S2B. The sixth NAND gate ND56 performs a logical NAND operation on the decrement signal DECB, the second high-order bit signal S2A, and the sixth high-order bit signal S3B. The seventh NAND gate ND57 performs a logical NAND operation on the third high-order bit signal S3A and the sixth high-order bit signal S3B. The eighth NAND gate ND58 performs a logical NAND operation on the outputs of the fifth NAND gate ND55 through the seventh NAND gate ND57.

[0112] Signal combiner 553 can generate a first DM signal DM_BL0 based on a first preliminary signal DM_PRE1 and a second preliminary signal DM_PRE2. For example, signal combiner 553 may include a NOR gate NR5 and an inverter INV5 to perform a logical OR operation on the first preliminary signal DM_PRE1 and the second preliminary signal DM_PRE2. That is, signal combiner 553 can generate a first DM signal DM_BL0, which is activated to a logic high level when one of the first preliminary signal DM_PRE1 and the second preliminary signal DM_PRE2 is activated.

[0113] The following text will describe the reference. Figures 7 to 13 The operation of the first DM calculator 220_0 is described.

[0114] Figure 14A and Figure 14B It is used to describe Figure 7 The waveform diagram of the operation of the first DM calculator 220_0.

[0115] Reference Figure 14A This shows the case where some bits of the first burst data DQ_BL0<2:7>, DQ_BL0<2,3,4,5> are logic high bits and the remaining bits DQ_BL0<6,7> are logic low bits.

[0116] At time t0, the logic determination circuit 510 can detect the logic high bits of the first burst data DQ_BL0<2:7> to activate the third high bit signal S3A and the fourth high bit signal S1B. Therefore, since the number of logic high bits of the first burst data DQ_BL0<2:7> is equal to the boundary value 4 (the boundary value 4 is less than the reference value 5), the masking signal generation circuit 550 can deactivate the first DM signal DM_BL0 to a logic low level.

[0117] At time t1, the first burst data DQ_BL0<0:7> bit DQ_BL0 <6> The bit was detected as an error. Therefore, the first bit S_BL of the first error location signal S_BL<0:15> is... <0> The bits S_DQ of the second error position signal S_DQ<0:7> <6> It becomes a logical high bit. In this case, due to the bits of the first burst data DQ_BL0<0:7>, DQ_BL0 <6> It is the low logic bit, therefore the error change detection circuit 530 can increase the detection bit INCB. <6> The output is a logic low level, thereby activating the amplification signal INC to a logic high level. Therefore, the masking signal generation circuit 550 can activate the first DM signal DM_BL0 to a logic high level.

[0118] Reference Figure 14B This shows some bits of the first burst data DQ_BL0<2:7>, where DQ_BL0<2, 3, 4, 5, 6> are logic high bits, while only bits DQ_BL0... <7> This refers to the case of the low-order bits.

[0119] At time t0, the logic determination circuit 510 can detect the logic high bits of the first burst data DQ_BL0<2:7> to activate the third high bit signal S3A and the fifth high bit signal S2B. Since the number of logic high bits of the first burst data DQ_BL0<2:7> is equal to the reference value 5, the masking signal generation circuit 550 can activate the DM signal DM_BL0 to a logic high level.

[0120] At time t1, the first burst data DQ_BL0<0:7> bit DQ_BL0 <6> The bit was detected as an error. Therefore, the first bit S_BL of the first error location signal S_BL<0:15> is... <0> The bits S_DQ of the second error position signal S_DQ<0:7> <6> It becomes a logical high bit. In this case, due to the bits of the first burst data DQ_BL0<0:7>, DQ_BL0 <6> It is the high-order logic bit, therefore the error change detection circuit 530 can reduce the detection bit DECB. <6> The output is a logic low level, thereby activating the decrement signal DECB to a logic low level. Therefore, the masking signal generation circuit 550 can deactivate the first DM signal DM_BL0 to a logic low level.

[0121] In the following, a detailed configuration of the first DM calculator 220_0 according to another embodiment of the present disclosure will be described.

[0122] Figure 15 This is a detailed block diagram illustrating a first DM calculator 220_0 according to another embodiment of the present disclosure.

[0123] Reference Figure 15 The first DM calculator 220_0 may include a logic determination circuit 610, an error change detection circuit 630, and a masking signal generation circuit 650. The first DM calculator 220_0 may also include an inverting logic 660 for generating inverted data DQ_BLB0<2:7> by inverting the first burst data DQ_BL0<2:7>.

[0124] The logic determination circuit 610 can generate first to third high-bit signals S1A, S2A, and S3A (indicating the number of logic high bits of the low-order DQ_BL0<2:4> of the first burst data DQ_BL0<2:7>), and generate fourth to sixth high-bit signals S1B, S2B, and S3B (indicating the number of logic high bits of the high-order DQ_BL0<5:7> of the first burst data DQ_BL0<2:7>). The logic determination circuit 610 may include a first logic determiner 612 and a second logic determiner 614. Because the logic determination circuit 610 has... Figure 7 The logic determination circuit 510 has a basically the same configuration, so its detailed description will be omitted.

[0125] The error change detection circuit 630 can detect the error based on the first bit S_BL of the first error position signal S_BL<0:15>. <0> The error change detection circuit 630 is activated and generates an increasing signal INC or a decreasing signal DEC by detecting the presence of erroneous bits in the first burst data DQ_BL0<2:7> based on the second error position signal S_DQ<2:7>. In embodiments of this disclosure, the error change detection circuit 630 can activate the increasing signal INC or the decreasing signal DEC by checking whether the number of logic high bits in the first burst data DQ_BL0<2:7> is equal to a reference value or a boundary value. In this embodiment, the increasing signal INC and the decreasing signal DEC can be activated as logic high.

[0126] More specifically, the error change detection circuit 630 may include a first change detector 632 and a second change detector 634.

[0127] The first change detector 632 can determine the first bit S_BL of the first error position signal S_BL<0:15>. <0> Activated, and the initial amplification signal is activated when the corresponding bits of the inverted data DQ_BLB0<2:7> and the second error position signal S_DQ<2:7> are both logic high bits. Figure 16 The first change detector 632 can activate the first detection signal DET1 by detecting that the number of logic high bits of the first burst data DQ_BL0<2:7> equals the boundary value based on the first to sixth high bit signals S1A, S2A, S3A, S1B, S2B, and S3B. The initial increase signal INCB and the first detection signal DET1 can be signals that are activated to a logic low level. When both the initial increase signal INCB and the first detection signal DET1 are activated, the first change detector 632 can generate an increase signal INC that is activated to a logic high level.

[0128] The second change detector 634 can determine the first bit S_BL of the first error position signal S_BL<0:15>. <0> Activated, and when the corresponding bits of the first burst data DQ_BL0<2:7> and the second error position signal S_DQ<2:7> are both logic high bits, the initial decrease signal is activated (e.g., Figure 17 The second change detector 634 can activate the second detection signal DET2 by detecting that the number of logic high bits of the first burst data DQ_BL0<2:7> equals a reference value based on the first to sixth high bit signals S1A, S2A, S3A, S1B, S2B, and S3B. The initial decrease signal DECB and the second detection signal DET2 can be signals activated as logic low. When both the initial decrease signal DECB and the second detection signal DEC2 are activated, the second change detector 634 can generate a decrease signal DEC activated as logic high.

[0129] The masking signal generation circuit 650 can generate a first DM signal DM_BL0 based on a portion of the first to sixth high-bit signals S1A, S2A, S3A, S1B, S2B, and S3B, and change the logic level of the DM signal DM_BL0 according to the increment signal INC and the decrement signal DEC. Figure 15 In the diagram, reference numeral S5AB is a signal generated by performing a logical NAND operation on the third high-bit signal S3A and the fifth high-bit signal S2B, and will be defined hereinafter as the seventh high-bit signal S5AB. Similarly, reference numeral S5BB is a signal generated by performing a logical NAND operation on the second high-bit signal S2A and the sixth high-bit signal S3B, and will be defined hereinafter as the eighth high-bit signal S5BB. Figure 15 The diagram illustrates that the seventh high-bit signal S5AB and the eighth high-bit signal S5BB generated from the second change detector 634 are provided to the masking signal generation circuit 650, but embodiments of this disclosure are not limited thereto. According to an embodiment, the masking signal generation circuit 650 may receive the first to sixth high-bit signals S1A, S2A, S3A, S1B, S2B, and S3B to generate the seventh high-bit signal S5AB and the eighth high-bit signal S5BB.

[0130] Figure 16 It is shown Figure 15 The circuit diagram of the first change detector 632.

[0131] Reference Figure 16 The first change detector 632 may include first NAND gates ND61 to ninth NAND gates ND69, first NOR gate NR61 and second NOR gate NR62, and inverter INV6.

[0132] The first NAND gate ND61 to the third NAND gate ND63 can control the corresponding bits of the inverted data DQ_BLB0<2:7>, the corresponding bits of the second error position signal S_DQ<2:7>, and the first bit S_BL of the first error position signal S_BL<0:15>. <0> A logical NAND operation is performed to generate the increment detection bits INCB<2:7>. The fourth NAND gate ND64 performs a logical NAND operation on the increment detection bits INCB<2:4>. The fifth NAND gate ND65 performs a logical NAND operation on the increment detection bits INCB<5:7>. The NOR gate NR61 generates the initial increment signal INCB by performing a logical NOR operation on the outputs of the fourth NAND gate ND64 and the fifth NAND gate ND65. As a result, the initial increment signal INCB can be activated to a logic low level when one of the increment detection bits INCB<2:7> becomes a logic low bit.

[0133] The sixth NAND gate ND66 performs a logical NAND operation on the third high-order bit signal S3A and the fourth high-order bit signal S1B. The seventh NAND gate ND67 performs a logical NAND operation on the first high-order bit signal S1A and the sixth high-order bit signal S3B. The eighth NAND gate ND68 performs a logical NAND operation on the second high-order bit signal S2A and the fifth high-order bit signal S2B. The ninth NAND gate ND69 and the inverter INV6 perform a logical AND operation on the outputs of the sixth NAND gate ND66 through the eighth NAND gate ND68 to output the first detection signal DET1. As a result, when the number of logic high-order bits of the first burst data DQ_BL0<2:7> is a boundary value, the first detection signal DET1 can be activated to a logic low level.

[0134] The second NOR gate NR62 can output the amplified signal INC by performing a logical NOR operation on the initial amplified signal INCB and the first detection signal DET1.

[0135] With the above configuration, the first change detector 632 can determine the first bit S_BL of the first error position signal S_BL<0:15>. <0> When activated, and when the number of logic high bits of the first burst data DQ_BL0<2:7> is equal to the boundary value, and a logic high bit of the inverted data DQ_BLB0<2:7> (i.e., the logic low bit of the first burst data DQ_BL0<2:7>) is detected as an error bit, the output is activated as an increased signal INC at a logic high level.

[0136] Figure 17 It is shown Figure 15 The circuit diagram of the second change detector 634.

[0137] Reference Figure 17 The second change detector 634 may include a first NAND gate ND71 to a seventh NAND gate ND77, an AND gate AD7, a first NOR gate NR71, and a second NOR gate NR72.

[0138] NAND gates ND71 to ND73 can control the corresponding bits of the first burst data DQ_BL0<2:7>, the corresponding bits of the second error position signal S_DQ<2:7>, and the first bit S_BL of the first error position signal S_BL<0:15>. <0> A logical NAND operation is performed to generate the decrease detection bits DECB<2:7>. The fourth NAND gate ND74 performs a logical NAND operation on the decrease detection bits DECB<2:4>. The fifth NAND gate ND75 performs a logical NAND operation on the decrease detection bits DECB<5:7>. The first NOR gate NR71 generates the initial decrease signal DECB by performing a logical NOR operation on the outputs of the fourth NAND gate ND74 and the fifth NAND gate ND75. As a result, the initial decrease signal DECB can be activated to a logic low level when one of the decrease detection bits DECB<2:7> becomes a logic low bit.

[0139] The sixth NAND gate ND76 can output the seventh high-bit signal S5AB by performing a logical NAND operation on the third high-bit signal S3A and the fifth high-bit signal S2B. The seventh NAND gate ND77 can output the eighth high-bit signal S5BB by performing a logical NAND operation on the second high-bit signal S2A and the sixth high-bit signal S3B. When the number of logic high bits of the first burst data DQ_BL0<2:7> is equal to the reference value of 5, the seventh high-bit signal S5AB and the eighth high-bit signal S5BB can be provided to the masking signal generation circuit 650 as signals activated to a logic low level. The AND gate AD7 can generate the second detection signal DET2 by performing a logical AND operation on the outputs of the sixth NAND gate ND76 and the seventh NAND gate ND77. As a result, when the number of logic high bits of the first burst data DQ_BL0<2:7> is equal to the reference value, the second detection signal DET2 can be activated to a logic low level.

[0140] The second NOR gate NR72 can output a reduced signal DEC by performing a logical NOR operation on the initial reduced signal DECB and the second detection signal DET2.

[0141] With the above configuration, the second change detector 634 can determine the first bit S_BL of the first error position signal S_BL<0:15>. <0> When activated, and when the number of logic high bits of the first burst data DQ_BL0<2:7> is equal to the reference value, and a logic high bit of the first burst data DQ_BL0<2:7> is detected as an error bit, the output is activated as a decreasing signal DEC at a logic high level.

[0142] Figure 18 It is shown Figure 15 The circuit diagram of the masking signal generation circuit 650.

[0143] Reference Figure 18 The masking signal generation circuit 650 may include an output control unit 651, a signal generation unit 652, and a signal output unit 653.

[0144] The output control unit 651 can generate a transmission control signal OE and an inverted transmission control signal OEB based on the increasing signal INC or the decreasing signal DEC. For example, the output control unit 651 may include a first NOR gate NR81 and a first inverter INV81. The first NOR gate NR81 can output the inverted transmission control signal OEB by performing a logical NOR operation on the increasing signal INC and the decreasing signal DEC. The first inverter INV81 can output the transmission control signal OE by inverting the inverted transmission control signal OEB. With the above configuration, when the increasing signal INC or the decreasing signal DEC is activated, the output control unit 651 can generate a logic high-level transmission control signal OE and a logic low-level inverted transmission control signal OEB.

[0145] The signal generation unit 652 can generate a preliminary DM signal PRE_DM based on the high-order bits S3A, S3B, S5AB, and S5BB. For example, the signal generation unit 652 may include a first NAND gate ND81 and a second NAND gate ND82. The first NAND gate ND81 can perform a logical NAND operation on the third high-order bit signal S3A and the sixth high-order bit signal S3B. The second NAND gate ND82 can perform a logical NAND operation on the seventh high-order bit signal S5AB, the eighth high-order bit signal S5B, and the output of the first NAND gate ND81 to output the preliminary DM signal PRE_DM. With the above configuration, when the number of logical high-order bits of the first burst data DQ_BL0<2:7> is greater than or equal to a reference value, the signal generation unit 652 can activate the preliminary DM signal PRE_DM to a logical high level.

[0146] The signal output unit 653 can output the first DM signal DM_BL0 by selectively inverting the preliminary DM signal PRE_DM according to the transmission control signal OE and the inverting transmission control signal OEB. For example, the signal output unit 653 may include a second inverter INV82, a third inverter INV83, and a transmitter T8. The second inverter INV82 can be activated according to the inverting transmission control signal OEB, and invert the preliminary DM signal PRE_DM and output it to the first node ND1. The transmitter T8 can be activated according to the transmission control signal OE, and can send the preliminary DM signal PRE_DM to the first node ND1 without inverting it. The third inverter INV83 can output the first DM signal DM_BL0 by inverting the signal at the first node ND1. With the above configuration, when the transmission control signal OE becomes a logic high level, the signal output unit 653 can output the first DM signal DM_BL0 by inverting the preliminary DM signal PRE_DM, and when the inverted transmission control signal OEB becomes a logic high level, the signal output unit 653 can output the preliminary DM signal PRE_DM as the first DM signal DMD_BL0.

[0147] The following text will describe the reference. Figures 15 to 18 The operation of the first DM calculator 220_0 is described.

[0148] Figure 19A and Figure 19B It is used to describe Figure 15 The waveform diagram of the operation of the first DM calculator 220_0.

[0149] Reference Figure 19A This shows the case where some bits of the first burst data DQ_BL0<2:7>, DQ_BL0<2,3,4,5> are logic high bits while the remaining bits, DQ_BL0<6,7>, are logic low bits.

[0150] At time t0, the logic determination circuit 610 can detect the logic high bits of the first burst data DQ_BL0<2:7> to activate the third high bit signal S3A and the fourth high bit signal S1B. Therefore, since the number of logic high bits of the first burst data DQ_BL0<2:7> is equal to the boundary value 4, which is smaller than the reference value 5, the masking signal generation circuit 650 can deactivate the preliminary DM signal PRE_DM to a logic low level. In this case, the increment signal INC and the decrement signal DEC are both deactivated, so the masking signal generation circuit 650 can output the preliminary DM signal PRE_DM as the first DM signal DM_BL0.

[0151] At time t1, the first burst data DQ_BL0<0:7> bit DQ_BL0 <6> The bit was detected as an error. Therefore, the first bit S_BL of the first error location signal S_BL<0:15> is... <0> The bits S_DQ of the second error position signal S_DQ<0:7> <6> It becomes a logical high bit. In this case, since the number of logical high bits in the first burst data DQ_BL0<2:7> is the boundary value of 4, bit DQ_BL0 <6> It is the low logic bit, therefore the error change detection circuit 630 can increase the detection bit INCB. <6> The output is logic low, thereby activating the amplified signal INC to logic high. Therefore, the masking signal generation circuit 650 can activate the first DM signal DM_BL0 to logic high by inverting the preliminary DM signal PRE_DM.

[0152] Reference Figure 19B This shows some bits of the first burst data DQ_BL0<2:7>, where DQ_BL0<2, 3, 4, 5, 6> are logic high bits, while only bits DQ_BL0... <7> This refers to the case of the low-order logical bit.

[0153] At time t0, the logic determination circuit 610 can detect the logic high bits of the first burst data DQ_BL0<2:7> to activate the third high bit signal S3A and the fifth high bit signal S2B. Since the number of logic high bits of the first burst data DQ_BL0<2:7> is equal to the reference value 5, the masking signal generation circuit 650 can activate the preliminary DM signal PRE_DM to a logic high level. In this case, the increment signal INC and the decrement signal DEC are deactivated, and the masking signal generation circuit 650 can output the preliminary DM signal PRE_DM as the first DM signal DM_BL0.

[0154] At time t1, the first burst data DQ_BL0<0:7> bit DQ_BL0 <6> The bit was detected as an error. Therefore, the first bit S_BL of the first error location signal S_BL<0:15> is... <0> The bits S_DQ of the second error position signal S_DQ<0:7> <6> It becomes a logical high bit. In this case, since the number of logical high bits of the first burst data DQ_BL0<2:7> is the reference value of 5, the bits of the first burst data DQ_BL0<0:7> DQ_BL0 <6> Since it is a logic high bit, the error change detection circuit 630 can activate the decrease signal DEC to a logic high level. Therefore, the masking signal generation circuit 650 can deactivate the first DM signal DM_BL0 to a logic low level by inverting the preliminary DM signal PRE_DM.

[0155] As described above, according to embodiments of the present disclosure, the memory device can minimize write latency by executing error correction operations and DM calculation operations performed during link ECC operations in parallel.

[0156] Various embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is only for describing embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. Those skilled in the art will understand that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein. These embodiments can be combined to form additional embodiments.

[0157] It should be noted that although the technical spirit of this disclosure has been described in conjunction with embodiments thereof, this is for illustrative purposes only and should not be construed as limiting. Those skilled in the art will understand that various modifications can be made without departing from the technical spirit of this disclosure and the appended claims.

[0158] For example, the logic gates and transistors provided as examples in the above embodiments can be implemented in different positions and types according to the polarity of the input signal.< / x> < / x> < / x> < / y> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / y> < / x> < / y> < / x> < / x> < / y> < / y> < / x> < / y>

Claims

1. A memory device, comprising: The correction calculator generates an error location signal based on the first data and the error correction code; An error corrector that generates second data by correcting errors in the first data based on the error location signal; and A DM calculation circuit, wherein: a DM signal is generated based on the logic high bit of the first data; and based on the error position signal, the logic level of the DM signal is changed according to at least one of the increase signal and the decrease signal by activating an increase signal when an error bit is detected in the logic low bit of the first data and activating a decrease signal when the error bit is detected in the logic high bit of the first data, DM representing data masking.

2. The memory device according to claim 1, wherein, The DM calculation circuit: When the number of logical high bits of the first data is greater than or equal to the reference value, the DM signal is activated; when the decrease signal is activated when the number of logical high bits is equal to the reference value, the DM signal is deactivated. And when the amplification signal is activated when the number of the logic high bits is equal to the boundary value, the DM signal is activated.

3. The memory device according to claim 2, wherein, The boundary value is set to a number that is less than the reference value.

4. The memory device according to claim 1, further comprising: The DBI control circuit generates third data by selectively inverting the second data according to the DBI signal, where DBI stands for Data Bus Inversion; and The write circuit writes the third data into the memory core by masking the third data according to the DM signal.

5. The memory device according to claim 4, further comprising: Multiple input / output circuits, Specifically, it receives the first data, the error correction code, and the DBI signal from an external device, and outputs the first data, the error correction code, and the DBI signal to an external device.

6. A memory device, comprising: A correction calculator that generates a first error location signal and a second error location signal based on first data and an error correction code, wherein the first data includes m burst data input via data pads over a period of m burst lengths, where m is a positive integer; An error corrector that generates second data by correcting errors in the first data based on the first error location signal and the second error location signal; and Multiple DM calculators generate DM signals corresponding to the m burst data. Each DM calculator generates an increase signal and a decrease signal by detecting whether an error has occurred in the corresponding burst data based on the first error location signal and the second error location signal; and generates a corresponding DM signal based on at least one of the increase signal and the decrease signal, where DM stands for data masking.

7. The memory device according to claim 6, in, The first error location signal indicates the burst length in which the error bits of the first data were input out of the m burst lengths, and The second error location signal indicates the data pad in which the error bit was input.

8. The memory device according to claim 6, wherein, Each DM calculator: Based on the activation of the first error position signal, and According to the second error location signal, when an error bit is detected in the logical low bit of the corresponding burst data, the increase signal is activated, and when the error bit is detected in the logical high bit of the corresponding burst data, the decrease signal is activated.

9. The memory device according to claim 6, wherein, Each DM calculator: When the number of logical high bits of the corresponding burst data is greater than or equal to the reference value, the corresponding DM signal is activated; when the decrease signal is activated when the number of logical high bits is equal to the reference value, the corresponding DM signal is deactivated. And when the amplification signal is activated when the number of logic high bits is equal to the boundary value, the corresponding DM signal is activated.

10. The memory device according to claim 6, wherein, The corrector calculator includes: The code calculation circuit, which: uses the first data to generate a first preliminary error correction code; and An error location detection circuit, wherein: for each bit, the first preliminary error correction code is compared with the error correction code to generate a first error location signal and a second error location signal, and Wherein, the first error position signal indicates the burst length in which the error bit of the first data was input in the m burst lengths, and the second error position signal indicates the data pad in the data pad in which the error bit was input.

11. The memory device according to claim 6, wherein, Each DM calculator includes: A logic determination circuit that generates a high-bit signal representing the number of logic high-bits of the corresponding burst data. An error change detection circuit, activated based on the first error position signal, generates the increasing signal or the decreasing signal by detecting the presence of error bits in the corresponding burst data based on the second error position signal; and A masking signal generation circuit, which: generates the corresponding DM signal based on the high-bit signal; and changes the logic level of the corresponding DM signal according to at least one of the increasing signal and the decreasing signal.

12. The memory device according to claim 11, wherein, The logic determination circuit includes: A first logic determiner, which: generates a high-bit signal indicating the number of logic high-bits in the low-order bits of the corresponding burst data; and The second logic determiner generates the high-bit signal indicating the number of logical high-bits in the high-order bits of the corresponding burst data.

13. The memory device according to claim 11, wherein, The error change detection circuit includes: A first change detector, activated based on the first error location signal, activates the amplification signal when the second error location signal and the corresponding bit of the inverted data of the corresponding burst data are both logic high bits; and The second change detector is activated based on the first error position signal. The second change detector activates the decreasing signal when the corresponding burst data and the corresponding bit of the second error position signal are both logic high bits.

14. The memory device according to claim 11, wherein, The masking signal generation circuit includes: A first signal generator, which, when the amplification signal is activated, generates a first preliminary signal by detecting, based on the high-bit signal, the number of logical high bits of the corresponding burst data being equal to a boundary value; A second signal generator, comprising: generating a second preliminary signal by detecting a condition where the number of logical high bits is greater than or equal to a reference value based on the high-bit signal; and deactivating the second preliminary signal when the decreasing signal is activated in the state where the number of logical high bits is equal to the reference value; and A signal combiner that generates the corresponding DM signal based on the first preliminary signal and the second preliminary signal.

15. The memory device according to claim 6, wherein, Each DM calculator includes: A logic determination circuit that generates a high-bit signal representing the number of logic high-bits of the corresponding burst data. An error change detection circuit, activated based on the first error position signal, wherein the error change detection circuit: based on the high-bit signal, when the number of logical high bits of the corresponding burst data equals a reference value or a boundary value, generates the increasing signal or the decreasing signal by detecting whether there are error bits in the corresponding burst data according to the second error position signal; and A masking signal generation circuit, which: generates the corresponding DM signal based on the high-bit signal; and changes the logic level of the corresponding DM signal according to at least one of the increasing signal and the decreasing signal.

16. The memory device according to claim 15, wherein, The error change detection circuit includes: A first change detector, activated based on the first error location signal, activates the amplification signal when the number of logic high bits equals the boundary value, and the corresponding bits of the second error location signal and the inverted data of the corresponding burst data are both logic high bits; and The second change detector is activated based on the first error position signal. The second change detector activates the decrease signal when the number of logic high bits is equal to the reference value, and the corresponding bits of the corresponding burst data and the second error position signal are both logic high bits.

17. The memory device according to claim 15, wherein, The masking signal generation circuit includes: An output control unit that activates a transmission control signal based on the increasing signal or the decreasing signal; A signal generation unit, comprising: generating a preliminary DM signal by detecting a condition where the number of logical high bits is greater than or equal to a reference value based on the high-bit signal; and The signal output unit outputs the corresponding DM signal by selectively inverting the initial DM signal according to the transmission control signal.

18. A method of operating a memory device, the method comprising: The error location signal is generated based on the first data and the error correction code; The second data is generated by correcting the errors in the first data based on the error location signal; A DM signal is generated based on the high-order bits of the first data, and based on the error position signal, the logic level of the DM signal is changed according to at least one of the increasing signal and the decreasing signal by activating an increasing signal when the error bit is detected in the low-order bits of the first data and activating a decreasing signal when the error bit is detected in the high-order bits of the first data, where DM represents data masking. and The second data is written into the memory core by selectively masking the second data according to the DM signal.

19. The operating method according to claim 18, wherein, The generation of the DM signal is performed simultaneously with the correction of errors in the first data.

20. The operating method according to claim 18, wherein, Changing the logic level of the DM signal includes: The DM signal is activated when the number of logical high bits of the first data is greater than or equal to the reference value; and When the decrease signal is activated when the number of logic high bits is equal to the reference value, the DM signal is deactivated; and when the increase signal is activated when the number of logic high bits is equal to the boundary value, the DM signal is activated.

21. The operating method according to claim 20, wherein, The boundary value is set to a number that is less than the reference value.

22. The operating method according to claim 18, further comprising: Receive the first data and the error correction code from an external device.

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