Method of forming package structure and package structure

Abstract

The method includes forming an interconnect structure and an interposer. The interconnect structure includes a first plurality of redistribution lines and a wafer seal ring surrounding the first plurality of redistribution lines. The interposer includes a second plurality of redistribution lines and a plurality of die seal rings surrounding the second plurality of redistribution lines. The method includes bonding a first plurality of package components to an interposer, and bonding a second plurality of package components to an interconnect structure. The first plurality of package components are electrically connected to the second plurality of package components through the interposer and the interconnect structure. The embodiment of the invention also relates to a method for forming the packaging structure and the packaging structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to methods for forming packaging structures and packaging structures themselves. Background Technology

[0002] Interconnect dies are used in electrical interconnect device dies and packages. Interconnect dies can be embedded in on-chip packages on a substrate. The wafer in the package is typically an interposer.

[0003] As computing power demands increase, intermediary layers are becoming increasingly larger. This creates problems because larger intermediary layers have narrower coverage windows. Issues such as cold connections are more likely to occur. Summary of the Invention

[0004] Embodiments of this disclosure provide a method for forming an encapsulation structure, comprising:

[0005] An interconnect structure is formed, the interconnect structure comprising: a first plurality of redistribution lines; and a wafer sealing ring surrounding the first plurality of redistribution lines;

[0006] An intermediary layer is formed, the intermediary layer comprising: a second plurality of redistribution lines; and a plurality of core sealing rings surrounding the second plurality of redistribution lines;

[0007] Joining the first plurality of encapsulation components to the intermediary layer; and

[0008] A second plurality of packaged components are attached to the interconnect structure, wherein the first plurality of packaged components are electrically connected to the second plurality of packaged components through the interposer and the interconnect structure.

[0009] Another embodiment of this disclosure provides a packaging structure, including:

[0010] The intermediate layer includes: a first plurality of redistribution lines; and a plurality of die sealing rings, each die sealing ring surrounding a portion of the first plurality of redistribution lines;

[0011] An interconnect structure is located above the interposer layer, wherein the interposer layer and the interconnect structure are included in a package, and the interconnect structure includes: a second plurality of redistribution lines; and a wafer sealing ring adjacent to the outer periphery of the package, wherein, in a top view of the package structure, the wafer sealing ring surrounds at least some of the plurality of die sealing rings; and

[0012] Multiple packaged components are located above the interconnect structure and electrically coupled to the interposer and the interconnect structure.

[0013] Another embodiment of this disclosure provides a packaging structure, including:

[0014] An interposer layer includes: a first plurality of dielectric layers; a plurality of die sealing rings located in the first plurality of dielectric layers, wherein the plurality of die sealing rings are electrically grounded or electrically floated; and a first plurality of redistribution lines located in the first plurality of dielectric layers, wherein, in a top view of the package structure, the first plurality of redistribution lines form a plurality of groups, the plurality of groups being physically separated from each other by the plurality of die sealing rings.

[0015] An interconnect structure located above the interposer layer and comprising: a second plurality of dielectric layers; a wafer sealing ring located in the second plurality of dielectric layers, wherein the wafer sealing ring is electrically grounded or electrically floating; and a second plurality of redistribution lines located in the second plurality of dielectric layers, wherein the second plurality of redistribution lines interconnect two of the plurality of groups;

[0016] Multiple packaged components are located below the interposer and electrically coupled to the interposer and the interconnect structure; and

[0017] The bridge connector core is located above the interposer and the interconnect structure and is electrically coupled to the interposer and the interconnect structure. Attached Figure Description

[0018] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the individual components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be increased or decreased in any way.

[0019] Figures 1 to 6 A cross-sectional view of an intermediate stage in the formation of a package according to some embodiments is shown.

[0020] Figure 7 A package according to some embodiments is shown.

[0021] Figures 8 to 15 A cross-sectional view of an intermediate stage in the formation of a package according to some embodiments is shown.

[0022] Figure 16 , Figure 17 and Figure 18 Some packages according to some embodiments are shown.

[0023] Figure 19 and Figure 20 A top view of some packages according to some embodiments is shown.

[0024] Figure 21 A process flow for forming a package is shown according to some embodiments. Detailed Implementation

[0025] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the discussed embodiments and / or configurations.

[0026] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0027] A package comprising an interconnect structure and an interposer, a corresponding sealing ring, and a method for forming the same are provided. According to some embodiments, a wafer sealing ring is formed in the interconnect structure, and a die sealing ring (or multiple die sealing rings) is formed in the interposer. A package assembly including a device die can be incorporated into the package and interconnected via the interconnect structure and the interposer. By forming the wafer sealing ring and the die sealing ring, package warpage can be reduced.

[0028] The embodiments discussed herein are intended to provide examples to enable making or using the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0029] Figures 1 to 6 A cross-sectional view is shown of an intermediate stage in the formation of a package including a wafer sealing ring and a die sealing ring according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in… Figure 21 The process flow shown is as follows.

[0030] refer to Figure 1A carrier 20 is provided, and a release film 22 is coated on the carrier 20. The carrier 20 is formed of a transparent material and can be a glass carrier, a ceramic carrier, an organic carrier, etc. The release film 22 is in physical contact with the top surface of the carrier 20. The release film 22 can be formed of a photothermal conversion (LTHC) coating material. The release film 22 can be applied to the carrier 20 by coating.

[0031] According to some embodiments, the LTHC coating material is capable of decomposing under the heat of light / radiation (such as a laser beam) and releasing the carrier 20 from the structure placed and formed thereon. According to some embodiments, a buffer dielectric layer (not shown) may be formed above the release film 22. The buffer dielectric layer may include polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. According to alternative embodiments, no buffer layer is formed.

[0032] Further reference Figure 1 Interconnect structure 24 is formed above carrier 20 (and above buffer layer, when formed). The corresponding process is shown as follows. Figure 21 Process 202 in the process flow 200 shown. Then, as... Figure 2 As shown, an interposer layer 34 is formed above the interconnect structure 24. The corresponding process is shown as follows. Figure 21 Process 204 in the process flow 200 shown. Throughout the description, the interconnect structure 24 and the intermediate layer 34 are optionally referred to as the redistribution structure.

[0033] According to some embodiments, interconnect structure 24 can be used for global lateral connections, such as interconnections of packaged components above interposer 34 and / or interconnections of packaged components below interconnect structure 24. On the other hand, interposer 34 can be used for local interconnections, such as interconnections of connections between components in a packaged assembly, and / or connections between packaged components below interconnect structure 24 and packaged components above interposer 34.

[0034] According to some embodiments, interconnect structure 24 and interposer 34 include dielectric layer 26 and dielectric layer 36, respectively. The boundaries between adjacent dielectric layers 26 (and / or between adjacent dielectric layers 36) are not shown, and the boundaries may (or may not) be distinguishable.

[0035] According to some embodiments, dielectric layer 26 is formed of a photosensitive polymer such as PBO, polyimide, BCB, etc., wherein each dielectric layer 26 is formed of a homogeneous dielectric material. According to alternative embodiments, dielectric layer 26 is formed of a non-photosensitive material, such as molding compound, molded underfill, silicon oxide, silicon nitride, etc. The formation of each dielectric layer 26 may include dispensing the respective dielectric layer in a flowable form, and then curing the dielectric layer. Optionally, the dielectric layer 26 can be formed by a deposition process.

[0036] According to some embodiments, dielectric layer 36 is formed of a material selected from the same group of candidate materials as dielectric layer 26, and may include PBO, polyimide, BCB, molding compound, molded underfill, etc. According to alternative embodiments, dielectric layer 36 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0037] RDL 28 is formed in dielectric layer 26, and RDL 38 is formed in dielectric layer 36. RDL 28 and 38 interconnect packaged components (such as device dies) as a system for electrical and signal interconnection. According to some embodiments, RDL 28 is thicker and / or wider than RDL 38 (when viewed from top) and can be used for long-distance circuitry, while RDL 38 can be used for short-distance circuitry.

[0038] As an example, the exemplary fabrication process of dielectric layer 26 and RDL 28 is discussed below. First, as... Figure 1 As shown, a first dielectric layer (the bottom dielectric layer below the bottom surface of one of the bottom dielectric layers 26) is deposited above the carrier 20 (or above the buffer layer, if formed). The dielectric layer 26 is then patterned to form an opening that exposes the underlying buffer layer or release film 22. The patterning process can be performed using a photolithography process, which includes exposing the dielectric layer 26 and developing the dielectric layer 26.

[0039] Next, a metal seed layer (not shown) is deposited, for example, via a physical vapor deposition (PVD) process. The metal seed layer may include a titanium layer and a copper layer above the titanium layer. Alternatively, the metal seed layer may be a copper layer. Then, a plating mask (not shown) (which may include photoresist) is formed on a patterned dielectric layer 26, and the plating mask is also patterned. A plating process is then performed to deposit a metal material (such as copper, aluminum, aluminum-copper, etc.) in the openings in the plating mask. The plating mask is then removed, and the underlying metal seed layer is subsequently etched, leaving RDL 28.

[0040] like Figure 1 As shown, an RDL layer 28 (including multiple RDLs 28 at the same level) is formed, including line portions located above the bottom dielectric layer 26 and via portions located in the bottom dielectric layer 26. This process can be repeated to form multiple dielectric layers 26 and corresponding RDLs 28. Therefore, distinguishable interfaces can be formed between adjacent dielectric layers 26, wherein the distinguishable interfaces can be at the same level as the metal lines connecting to the corresponding underlying vias.

[0041] According to an optional embodiment, dielectric layer 26 and RDL 28 are formed using an alternating process, wherein line portions are formed before the corresponding via portions are formed. In an example formation process, a metal seed layer is deposited, followed by the formation and patterning of a first plating mask (not shown), which may be photoresist. A first plating process is then performed to plating the line portions of RDL 28. The first plating mask is then removed. Next, a second plating mask (not shown), which may also be photoresist, is formed without etching the metal seed layer. A second plating process is then performed to plating the via portions of RDL 28.

[0042] The second plating mask is then removed, followed by etching of the underlying metal seed layer not covered by the line portions of RDL 28. This forms an RDL 28 layer and vias on top. Next, another dielectric layer 26, such as molding compound, PBO, or polyimide, is applied and cured. A planarization process is then performed so that the top surface of the via portions of RDL 28 is flush with the top surface of the dielectric layer 26.

[0043] This process can be repeated to form multiple dielectric layers 26 and corresponding RDLs 28. Therefore, distinguishable interfaces can be formed between adjacent dielectric layers 26. These distinguishable interfaces can be at the same layer level as the line portions contacting the corresponding underlying vias, and can be distinguishable due to the planarization process.

[0044] In the same process used to form RDL 28, a wafer sealing ring 30 is formed. The wafer sealing ring 30 is so named because it is formed near the outer periphery of the resulting reconstructed wafer or package, such as... Figure 19 and Figure 20 As shown, it does not extend into the internal regions of the reconstructed wafer. According to some embodiments, the wafer sealing ring 30 is formed layer by layer in the same process used to form RDL 28.

[0045] Intermediate layer 34 is formed over interconnect structure 24 and includes dielectric layer 36 and RDL 38. According to some embodiments, dielectric layer 36 and RDL 38 are formed by the same group of candidate methods as dielectric layer 26 and RDL 28.

[0046] According to some embodiments, dielectric layer 26 is thicker than dielectric layer 36. For example, the thickness of each dielectric layer 26 may be in the range of about 10 μm to about 40 μm, while the thickness of each dielectric layer 36 may be in the range of about 1 μm to about 10 μm.

[0047] According to some embodiments, a die sealing ring 40 is formed in the same process used to form RDL 38. The die sealing ring 40 is so named because multiple sealing rings can be formed, each corresponding to one of the device dies to be bonded in subsequent processes. For example, as... Figure 4 As shown, each die sealing ring 40 may surround the area directly beneath one of the packaging components 44 (which may include the device die).

[0048] Figure 3 The formation of the top electrical connector 42 (also known as under-bump metal (UBM)) is shown. The corresponding process is shown as follows. Figure 21 Process 206 in the illustrated process flow 200. According to some embodiments, the formation process may include etching the top dielectric layer 38 to expose metal pads in the top RDL 36, depositing a metal seed layer, forming a patterned plating mask, and performing a plating process. The plating mask is then removed, followed by etching of the metal seed layer. The plating mask may be formed from a photosensitive material such as photoresist. Patterning of the plating mask may be achieved through an exposure process and a subsequent development process.

[0049] Electrical connector 42 may include a metal pillar and may or may not include a solder layer. If a solder layer is formed, the solder layer may also be plated onto the metal pillar and then reflowed.

[0050] Figure 4 The bonding of package assembly 44 is shown, which is bonded to the underlying interposer layer 34 via electrical connector 42. The corresponding process is shown as follows. Figure 21 Process 208 in the illustrated process flow 200. According to some embodiments, bonding can be performed via solder region 45, the height of which may be less than about 100 μm or less than about 50 μm. Optionally, bonding may include metal-to-metal direct bonding or hybrid bonding, wherein hybrid bonding includes metal-to-metal direct bonding between metal components and fusion bonding between dielectric layers.

[0051] Package assembly 44 may include logic dies (such as computing dies), memory dies (such as dynamic random access memory (DRAM) dies or static random access memory (SRAM) dies), packages (including packaged device dies), input / output (I / O) dies, digital dies, analog dies, and die stacks such as high-bandwidth memory (HBM) blocks. Package assembly 44 may also include passive device dies, such as independent passive device (IPD) dies.

[0052] After bonding the package assembly 44, underfill 46 can be dispensed into the gap between the package assembly 44 and the underlying interposer 34. The corresponding process is shown as follows. Figure 21Process 210 in the process flow 200 shown. Then, molding compound 48 is dispensed to seal the encapsulation assembly 44 therein. The corresponding process is shown as follows. Figure 21 Process 212 in the illustrated process flow 200. The underfill 46 and molding compound 48 are individually and collectively referred to as sealants. According to some embodiments, the underfill 46 and molding compound 48 may comprise a base material (such as epoxy, polymer, and / or resin) and filler particles located within the respective base material. The filler particles may include silica, alumina, boron nitride, etc.

[0053] A planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, is performed to expose the top surface of the package assembly 44. The exposed surface of the package assembly 44 can be the silicon substrate of the corresponding device die. The resulting structure above the release film 22 is called the reconstructed wafer 90.

[0054] In subsequent processes, the reconstructed wafer 90 is decoupled from the carrier 20. The corresponding process is shown as follows. Figure 21 Process 214 in the process flow 200 shown. For example, debonding can be performed by projecting a light beam (such as a laser beam) onto the release film 22, and the beam passes through the transparent carrier 20. As a result, the release film 22 decomposes, and the reconstructed wafer 90 is released from the carrier 20. Figure 5 The resulting reconstructed wafer 90 is shown, which is relative to... Figure 4 The structure shown is flipped upside down.

[0055] Figure 5 The connection between the device die 54 and the interconnect structure 24 is further illustrated. According to some embodiments, the device die 54 may include a packaging assembly 64 for interconnecting the above-ground components. Figure 6 The local silicon interconnect (LSI) die (also known as a bridge die) is shown as follows. Figure 21 Process 216 in the process flow 200 shown. According to some embodiments, device die 54 may also include an integrated voltage regulator (IVR). Throughout the description, device die 54 may be referred to as an LSI die, and device die 54 may also include other types of device dies.

[0056] Through-holes 56 may be formed in the LSI die 54 to connect the interconnect structure 24 to a subsequently bonded package assembly. A sealant 60 is formed to seal the LSI die 54 therein. Through-holes 58 may also be formed by redistribution lines 26 and penetrate the sealant 60. The sealant 60 may include molding compound, underfill, etc.

[0057] Figure 6 The joining of the packaging assembly 64 to form the package 100 is further illustrated. The corresponding process is shown as follows: Figure 21Process 218 in the illustrated process flow 200. According to some embodiments, package assembly 64 includes a device die 64A and a connector 64B. According to some embodiments, device die 64A may include an integrated IVR, power module, IPD, etc. Connector 64B may include a socket for connecting package 100 to a package assembly external to package 100.

[0058] According to some embodiments, package 100 includes a reconstructed wafer and is a wafer-level package used in wafer form, rather than being cut into multiple identical smaller packages. When in use (powered on), package 100 may include rounded edges when viewed from the top. Optionally, package 100 may be edge-trimmed to remove portions or all of the rounded edges that do not include circuitry, device dies, metal wires, etc. The resulting package 100 may include alternating rounded and straight edges, or include straight edges but not rounded edges.

[0059] In the resulting wafer-level package, the wafer sealing ring 30 is formed to include multiple portions, each portion being adjacent to a corresponding edge of the package 100. For example, Figure 19 and Figure 20 A top view of a package 100 according to some embodiments is shown. According to... Figure 19 and Figure 20 In some embodiments shown, package 100 may have a rectangular top-view shape including four edges, and / or may include rounded edges. Wafer sealing ring 30 includes four edge portions, each adjacent to one of the four edges of package 100. In the top view, there may be no other conductive components, package assemblies (such as device dies), etc., outside wafer sealing ring 30.

[0060] Return to reference Figure 6 (also Figure 19 and Figure 20 As shown in the diagram, the RDL 36 can be divided into multiple groups, each group being surrounded by a die sealing ring 40. The multiple groups of RDL 36 are physically separated from each other and therefore do not have the functionality of the interconnect package assembly 44, nor the functionality of the interconnect package assembly 64.

[0061] For example, Figure 19 Multiple discrete die sealing rings 40 spaced apart from each other are shown. The RDL 36 surrounded by the die sealing rings 40 can be electrically connected to individual package assemblies within the package assembly 44, but is not used for interconnecting package assemblies 44. In other words, the RDL 36 does not cross or penetrate (in...) Figure 6In the transverse direction, a first die sealing ring 40 is connected to an RDL 36 surrounded by a second sealing ring 40. Conversely, each RDL 36 is confined to an area surrounded by a single die sealing ring 40.

[0062] Return to reference Figure 6 RDL 26 can span across and overlap with die seal ring 40 to electrically interconnect RDL 36 surrounded by different die seal rings 40. Therefore, interconnect structure 24 functions to interconnect different package assemblies 44. Furthermore, interconnect structure 24 can also function to interconnect different package assemblies 64. For example, when power is connected to package 100 via one of connectors 64B, power can be conducted through interconnect structure 24 to one of package assemblies 64A (which may be an IVR), and the output of package assembly 64A can be redistributed by interconnect structure 24 and supplied to more than one package assembly 44.

[0063] If possible Figure 19 and Figure 20 This allows the wafer sealing ring 30 and die sealing ring 40 to have the same reinforcing ring function to reduce warpage of the package 100. The width W1 of the die sealing ring 40 ( Figure 19 and Figure 20 The width W1 of the die sealing ring 40 can be in the range of approximately 1 μm to 100 μm, and can be in the range of approximately 10 μm to approximately 20 μm. The width W1 of the die sealing ring 40 can be adjusted according to the available space and type of the package assembly 44. The width W2 of the wafer sealing ring 30 can be in the range of approximately 1 μm to approximately 100 μm, and can be in the range of approximately 10 μm to approximately 50 μm. According to some embodiments, the width W2 of the wafer sealing ring 30 can be greater than or equal to the width W1 of the die sealing ring 40.

[0064] Further reference Figure 19 and Figure 20 The wafer sealing ring 30 forms a full ring, which is close to the outer contour of the plurality of die sealing rings 40. The wafer sealing ring 30 may not have any metal components located within and connected to the full ring. Although Figure 19 The wafer sealing ring 30 is shown to surround and be larger than the plurality of die sealing rings 40, such that the wafer sealing ring 30 can be easily distinguished from the plurality of die sealing rings 40, but the wafer sealing ring 30 can overlap with the outer plurality of die sealing rings 40 (in Figure 6 (in the cross-sectional view).

[0065] In some embodiments, the wafer sealing ring 30 is electrically grounded. In alternative embodiments, the wafer sealing ring 30 is electrically floated. The die sealing ring 40 may also be electrically grounded or electrically floated.

[0066] According to some embodiments, such as Figure 6 As shown, the encapsulation components 44 can have the same lateral dimension. According to an alternative embodiment, such as... Figure 7 As shown, the package assembly 44 can have different sizes. According to some embodiments, the die seal ring 40 corresponding to (and surrounding the overlapping area) the larger package assembly 44 can be wider than the die seal ring 40 corresponding to (and surrounding the overlapping area) the smaller package assembly 44 to provide greater support force, thereby compensating for warpage caused by the larger package assembly 44. Furthermore, the width of the die seal ring 40 can be adjusted according to the available space and type of the package assembly 44.

[0067] Figures 8 to 15 The formation of a package 100 according to an alternative embodiment is illustrated. These embodiments are similar to those shown in the foregoing embodiments, except that the interposer 30, which bonds to the different package components 44, is a discrete interposer rather than a wafer-scale interposer. Unless otherwise stated, the materials, structures, and forming processes of the components in these embodiments are substantially the same as those of the same components indicated by the same reference numerals in the foregoing embodiments. Throughout the description, details regarding the materials, structures, and forming processes provided in each embodiment can be applied to any other applicable embodiments.

[0068] refer to Figure 8 The system provides a carrier 120 and a release membrane 122. A buffer layer (not shown) may be present (or may not be present) above the release membrane 122. The material of the buffer layer (if formed) may be selected from PBO, polyimide, BCB, etc.

[0069] Intermediate layer 34 is formed above carrier 120. The formation process, materials, and structure of intermediate layer 34 can be consistent with... Figure 2 As shown and referenced Figure 2 The basic discussion is the same and will not be repeated here. A core sealing ring 40 is formed in the interlayer 34. An electrical connector 42 is formed on the top surface of the interlayer 34.

[0070] refer to Figure 9 The package assembly 44 is bonded to the interposer 34, for example, via solder region 45, metal-to-metal direct bonding, or hybrid bonding (including metal-to-metal direct bonding and fusion bonding). Underfill 46 may be dispensed into the gap between the package assembly 44 and the interposer 34. Molding compound 48 is also dispensed. A planarization process is performed to make the top surface of the package assembly 44 flush with the top surface of the molding compound 48. This forms a reconstructed wafer 70, which includes a structure located above the release film 122.

[0071] Then, for example, by projecting a laser beam onto the release film 122, the reconstructed wafer 70 can be detached from the carrier 120. The reconstructed wafer 70 can then be placed on a dicing tape (not shown). A sawing (splitting) process can then be performed to saw the reconstructed wafer 70 to form a plurality of packages 70'. Figure 10 One of the packages 70' is shown.

[0072] Figure 9 The diagram illustrates a sawing process performed according to some embodiments. Each package 70' may include one or more package components 44 and portions of a wafer-level interposer. The wafer-level interposer portion is also referred to as a die-level interposer. According to some embodiments, the lateral distance S1 between the die sealing ring 40 and the corresponding package component 44 is... Figure 10 The size can range from approximately 20 μm to approximately 64 μm. This configuration can improve yield during segmentation.

[0073] According to some embodiments, the die sealing rings 40 in different packages 70' are physically and electrically connected to each other. For example, in Figure 9 and Figure 10 In some embodiments, region 56 may include an RDL line 36 that connects the die sealing ring 40 on the left side of region 56 to the die sealing ring 40 on the right side of region 56. When viewed from above, the die sealing rings 40 are interconnected and can form a connection with… Figure 20 The same grid pattern is shown. The result is as follows: Figure 10 As shown, after the sawing process, the die sealing ring 40 extends to the edge of the package 70' and is exposed through the sidewall of the dielectric layer 38.

[0074] According to an optional embodiment, the die sealing rings 40 in different reconstructed wafers 70 are physically and electrically separated from each other. For example, in Figure 9 and Figure 10 In some embodiments, region 56 may not include RDL line 36. Therefore, adjacent die sealing rings 40 are separated from each other. When viewed from above, the die sealing rings 40 form a plurality of discrete rings separated from each other, and thus have a... Figure 19 The same pattern is shown. The sawing path (cut) can be spaced apart from the die sealing ring 40, and therefore in the resulting package 70', the die sealing ring 40 is spaced apart from the edge of the package 70' and from the edge of the dielectric layer 38. The die sealing ring 40 is not exposed through the edge of the dielectric layer 38. When Figure 9 and Figure 10 When there is no die sealing ring in region 56, these embodiments can be implemented by those skilled in the art. According to some embodiments, the distance S2 between the edge of the die sealing ring 40 and the edge of the package 70' is... Figure 10It can be in the range of approximately 1 μm to approximately 10 μm.

[0075] If possible Figure 10 As achieved, the die sealing ring 40 forms a full ring (when viewed from the top of the package 70'), which comprises four parts, with the four parts of the die sealing ring 40 located near the edges of the respective packages 70'.

[0076] refer to Figure 11 A carrier 20 and a release membrane 22 are provided. An interconnect structure 24 is formed above the release membrane 22. Details regarding the formation process, materials, and structure of the interconnect structure 24 can be found in [reference needed]. Figure 1 The details are found, and will not be repeated here. Next, the electrical connector 72 is formed as the top component of the interconnect structure 24. The electrical connector 72 may include metal pillars, metal pads, solder areas, etc.

[0077] Next, as Figure 12 As shown, package 70' is bonded to interconnect structure 24. Bonding can be performed via solder region 74. According to an alternative embodiment, bonding can be performed via direct metal-to-metal bonding or hybrid bonding.

[0078] refer to Figure 13 The package 70' is sealed in a sealant 76, which may include a molding compound. This forms a reconstructed wafer 90. According to some embodiments, the package 70' is molded by pass molding. According to some embodiments, the sealant 76 may have a lower hardness than the molding compound, which may form a dielectric layer 38. The lower hardness compared to the molding compound, and therefore the softer sealant 76, helps absorb stress and reduce warpage of the resulting package, thereby improving the reliability of the resulting package.

[0079] Depending on whether the die-sealing ring 40 extends to the edge of the corresponding dielectric layer 38, the sealant 76 can physically contact the edge of the die-sealing ring 40, and / or can be spaced apart from the die-sealing ring 40 by the edge portion of the dielectric layer 38. It should be understood that multiple packages 70' exist, which can be formed individually and therefore can have different structures from each other. Thus, the sealant 76 can physically contact the edge of the die-sealing ring 40 in some packages 70', and be spaced apart from some other die-sealing rings 40 by the edge portion of the corresponding dielectric layer 38 in some other packages 70'. Throughout the description, the structure above the release film 22 is referred to as the reconfigured wafer 90.

[0080] Next, the reconstructed wafer 90 will be detached from the carrier 20. Figure 14 The resulting reconstructed wafer 90 is shown in the figure. Figure 14 It shows Figure 13 An inverted view of the reconstructed wafer 90.

[0081] In subsequent processes, such as Figure 14 As shown, the LSI die 54 is bonded, and a through-hole 58 and sealant 60 are formed. Then, a package assembly 64 is bonded to the underlying LSI die 54, forming a package 100. The package 100 can be used as a wafer or diced into smaller packages, as discussed with reference to the foregoing embodiments. When used as a wafer (powered on), the package 100 may or may not be edge-trimmed. A top view of the package 100 can be seen in... Figure 19 As shown in the figure, package 70' is shown as an example.

[0082] Figure 16 A package 100 according to an alternative embodiment is shown. These embodiments are similar to those described above. Figure 6 The embodiments shown are essentially the same, except that the core sealing rings 40 are interconnected as a single continuous structure. Figure 20 A top view of the corresponding interconnected die seal rings 40 is schematically shown. According to some embodiments, the interconnected die seal rings 40 may form a grid.

[0083] Figure 17 A package 100 according to yet another alternative embodiment is shown. These embodiments are similar to those described below. Figure 6 The embodiments shown are essentially the same, except that some external die sealing rings 40 near the edge of the package 100 are connected to the wafer sealing ring 30. According to these embodiments, as shown, the die sealing rings 40 can be spaced apart from each other. Alternatively, as... Figure 16 and Figure 20 As shown, the core sealing rings 40 can be connected together.

[0084] Figure 18 A package 100 according to yet another alternative embodiment is shown. These embodiments are similar to those described above. Figure 6 The illustrated embodiment is substantially the same, except that a separate sealing ring 140 is formed in the interposer 34. The sealing ring 140 surrounds all die sealing rings 40 and is spaced apart from all die sealing rings 40. The wafer sealing ring 30 is connected to the sealing ring 140 to form a continuous sealing ring extending into the interposer 34 and the interconnect structure 24. This embodiment can also be considered as the wafer sealing ring 30 including an extension portion extending into the interposer 34.

[0085] In the embodiments shown above, some processes and components are discussed according to some embodiments of this disclosure to form a three-dimensional (3D) package. Other components and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3DIC using probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to improve yield and reduce costs.

[0086] The embodiments disclosed herein have several advantageous features. By forming die sealing rings and wafer sealing rings in the interposer and interconnect structure of the package, warpage of the resulting package can be reduced. This improves the reliability of the package.

[0087] According to some embodiments, a method includes: forming an interconnect structure including: a first plurality of redistribution lines; and a wafer sealing ring surrounding the first plurality of redistribution lines; forming an interposer layer including: a second plurality of redistribution lines; and a plurality of die sealing rings surrounding the second plurality of redistribution lines; bonding a first plurality of package components to the interposer layer; and bonding a second plurality of package components to the interconnect structure, wherein the first plurality of package components are electrically connected to the second plurality of package components through the interposer layer and the interconnect structure.

[0088] In one embodiment, an interconnect structure is formed over a carrier, and an interposer is formed over the interconnect structure and the carrier. In another embodiment, the method further includes: after forming the interconnect structure and the interposer, bonding a first plurality of package components to the interposer; and disengaging the carrier from the bonding. In yet another embodiment, the method further includes, after bonding the first plurality of package components to the interposer, sawing the interposer into a plurality of discrete packages, wherein each discrete package includes a discrete portion of the interposer; one of a die-sealing ring; and one of the first plurality of package components, wherein one of the die-sealing rings includes a first portion adjacent to the outer periphery of the discrete package.

[0089] In one embodiment, the method further includes bonding a discrete package to an interconnect structure to form a package, wherein a wafer sealing ring includes a second portion adjacent to the outer periphery of the package. In one embodiment, in a top view of the interconnect structure, the wafer sealing ring surrounds at least some of a plurality of die sealing rings therein. In one embodiment, the plurality of die sealing rings are physically separated from each other. In one embodiment, the plurality of die sealing rings are physically interconnected.

[0090] In an embodiment, in a top view of the interposer, the second plurality of redistribution lines form a plurality of groups, each group being surrounded by one of a plurality of die-sealing rings. In an embodiment, in a top view of the interposer, each of the plurality of groups is confined to a region surrounded by one of the plurality of die-sealing rings, and in the top view, the second plurality of redistribution lines cross the plurality of die-sealing rings to interconnect the plurality of groups. In an embodiment, none of the second plurality of redistribution lines includes portions extending into two of the plurality of die-sealing rings.

[0091] According to some embodiments, a structure includes: an interposer including a first plurality of redistribution lines; and a plurality of die sealing rings, each die sealing ring surrounding a portion of the first plurality of redistribution lines; an interconnect structure located above the interposer, wherein the interposer and the interconnect structure are included in a package, and the interconnect structure includes: a second plurality of redistribution lines; and a wafer sealing ring adjacent to the outer periphery of the package, wherein, in a top view of the structure, the wafer sealing ring surrounds at least some of the plurality of die sealing rings; and a plurality of package assemblies located above the interconnect structure and electrically coupled to the interposer and the interconnect structure.

[0092] In one embodiment, the wafer sealing ring and the plurality of die sealing rings are electrically grounded. In another embodiment, the wafer sealing ring is physically spaced apart from the plurality of die sealing rings. In another embodiment, the plurality of die sealing rings are spaced apart from each other. In another embodiment, the plurality of die sealing rings are interconnected. In another embodiment, all portions of a first plurality of redistribution lines surrounded by the plurality of die sealing rings are physically separated from each other by the plurality of die sealing rings, and one of a second plurality of redistribution lines crosses two of the plurality of die sealing rings. In another embodiment, the wafer sealing ring comprises a full ring and has no conductive components located within the full ring and physically connected to the full ring.

[0093] According to some embodiments, a structure includes: an interposer comprising: a first plurality of dielectric layers; a plurality of die sealing rings located in the first plurality of dielectric layers, wherein the plurality of die sealing rings are electrically grounded or electrically floated; and a first plurality of redistribution lines located in the first plurality of dielectric layers, wherein, in a top view of the structure, the first plurality of redistribution lines form a plurality of groups, the plurality of groups being physically separated from each other by the plurality of die sealing rings; an interconnect structure located above the interposer and including: a second plurality of dielectric layers; a wafer sealing ring located in the second plurality of dielectric layers, wherein the wafer sealing ring is electrically grounded or electrically floated; and a second plurality of redistribution lines located in the second plurality of dielectric layers, wherein the second plurality of redistribution lines interconnect two of the plurality of groups; a plurality of package components located below the interposer and electrically coupled to the interposer and the interconnect structure; and a bridging die located above the interposer and the interconnect structure and electrically coupled to the interposer and the interconnect structure.

[0094] In one embodiment, an interposer, an interconnect structure, and multiple packaging components are included in a package, and a wafer sealing ring is located near the outer peripheral region of the package, wherein, in a top view of the structure, some of the multiple die sealing rings are surrounded by the wafer sealing ring.

[0095] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming an encapsulation structure, comprising: Forming an interconnect structure, the interconnect structure comprising: The first multiple redistribution lines; and A wafer sealing ring surrounds the first plurality of redistribution lines; An intermediary layer is formed, the intermediary layer comprising: The second multiple redistribution line; and Multiple core sealing rings surround the second multiple redistribution line; Joining the first plurality of encapsulation components to the intermediary layer; and A second plurality of packaged components are attached to the interconnect structure, wherein the first plurality of packaged components are electrically connected to the second plurality of packaged components through the interposer and the interconnect structure.

2. The method according to claim 1, wherein, The interconnect structure is formed over the carrier, and the interposer layer is formed over the interconnect structure and the carrier.

3. The method according to claim 2, wherein, The method further includes, after forming the interconnect structure and the intermediary layer: Joining the first plurality of encapsulation components to the intermediary layer; and This causes the carrier to disengage from the bonding.

4. The method according to claim 1, wherein, The method further includes, after bonding the first plurality of encapsulation components to the interposer layer, sawing the interposer layer into a plurality of discrete encapsulations, wherein the discrete encapsulations include: The discrete portion of the intermediary layer; One of the core sealing rings; and One of the first plurality of packaging components, wherein the die sealing ring includes a first portion adjacent to the outer periphery of the discrete package.

5. The method of claim 4, further comprising bonding the discrete package to the interconnect structure to form a package, wherein, The wafer sealing ring includes a second portion near the outer periphery of the package.

6. The method according to claim 1, wherein, In a top view of the interconnect structure, the wafer sealing ring surrounds at least some of the plurality of die sealing rings therein.

7. The method according to claim 1, wherein, The multiple core sealing rings are physically separated from each other.

8. A packaging structure, comprising: The intermediary layer includes: The first multiple redistribution lines; and Multiple core sealing rings, each core sealing ring surrounding a portion of the first plurality of redistribution lines; An interconnect structure is located above the interposer layer, wherein the interposer layer and the interconnect structure are included in a package, and the interconnect structure includes: The second multiple redistribution line; and A wafer sealing ring, located near the outer periphery of the package, wherein, in a top view of the package structure, the wafer sealing ring surrounds at least some of the plurality of die sealing rings; and Multiple packaged components are located above the interconnect structure and electrically coupled to the interposer and the interconnect structure.

9. A packaging structure, comprising: The intermediary layer includes: The first multiple dielectric layers; Multiple die sealing rings are located within the first plurality of dielectric layers, wherein the plurality of die sealing rings are electrically grounded or electrically floating; and The first plurality of redistribution lines are located in the first plurality of dielectric layers, wherein, in a top view of the package structure, the first plurality of redistribution lines form a plurality of groups, the plurality of groups being physically separated from each other by the plurality of die sealing rings; An interconnect structure, located above the intermediary layer, includes: The second multiple dielectric layers; A wafer sealing ring, located in the second plurality of dielectric layers, wherein the wafer sealing ring is electrically grounded or electrically floating; and The second plurality of redistribution lines are located in the second plurality of dielectric layers, wherein the second plurality of redistribution lines interconnect two groups of the plurality of groups; Multiple packaged components are located below the interposer and electrically coupled to the interposer and the interconnect structure; and The bridge connector core is located above the interposer and the interconnect structure and is electrically coupled to the interposer and the interconnect structure.

10. The packaging structure according to claim 9, wherein, The interposer, the interconnect structure, and the plurality of packaging components are included in a package, and the wafer sealing ring is located near the outer peripheral region of the package, wherein, in the top view of the package structure, some of the plurality of die sealing rings are surrounded by the wafer sealing ring.

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