Semiconductor chip metal through hole open circuit risk assessment method and detection method

Abstract

The invention discloses a semiconductor chip metal through hole open circuit risk assessment method and a detection method. The semiconductor chip metal through hole open circuit risk assessment method comprises the following steps: measuring a semiconductor chip to obtain measurement data of each metal through hole to be measured; forming an isolation factor and an intrinsic factor of each metal through hole to be measured according to the measurement data of each metal through hole to be measured; according to a priority rule, the isolated factors and / or the intrinsic factors between the metal through holes to be detected are compared to form a risk sorting result of disconnection of the metal through holes to be detected, and in the priority rule, the comparison order of the isolated factors is prior to that of the intrinsic factors. According to the scheme of the embodiment of the invention, the to-be-detected metal through holes can be sorted according to the risk probability of occurrence of the open circuit defect, so that targeted detection is carried out according to a certain priority sequence during subsequent defect detection, and the detection precision and efficiency are considered.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the technical field of semiconductor inspection. More particularly, the present disclosure relates to a semiconductor chip metal via open risk assessment method and a semiconductor chip metal via open detection method. BACKGROUND

[0002] With the development of integrated circuit technology, the integration of semiconductor chips is continuously improved, and more devices can be integrated at smaller geometrical sizes. In a semiconductor chip, the conductor part of the multi-layer wiring is composed of parallel metal layers (Metal) and metal vias (Via) connecting each layer. With the improvement of the integration of semiconductor chips and the miniaturization of semiconductor chips, the size of the metal via is further reduced to tens of nanometers or less, and the size of the metal via faces the limit of miniaturization, thereby increasing the probability of occurrence of the metal via open problem and further causing chip electrical problems, such as semiconductor functional failure, ultimately resulting in semiconductor chip yield loss. Therefore, it is crucial to inspect the open defects of the metal via for semiconductor chips.

[0003] The existing metal via open defect detection scheme usually uses automatic defect detection tools, such as E-beam electron beam detection equipment, to detect abnormal areas different from the reference on the wafer surface by optical or electron beam technology online, and to mark and classify defects by combining image processing and big data analysis. Alternatively, the open defect detection is completed by the electrical monitoring method of the existing RcV (Resistance, Capacitance, and Via Test Structures) test pattern.

[0004] However, regardless of which of the above detection methods is used, full-scale detection of semiconductor chips will consume a large amount of time and be inefficient. If random sampling detection is performed on several positions of the semiconductor chip, a large error will be generated due to the randomness of the sample, affecting the reliability of the detection result.

[0005] Therefore, there is an urgent need to provide a semiconductor chip metal via open risk assessment scheme to sort the metal vias to be detected according to the risk probability of occurrence of open defects, so as to perform targeted detection according to a certain priority order in subsequent defect detection, taking into account the accuracy and efficiency of the detection. SUMMARY

[0006] To at least solve one or more of the above-mentioned technical problems, the present disclosure proposes a semiconductor chip metal via open risk assessment scheme in various aspects.

[0007] In a first aspect, the present disclosure provides a semiconductor chip metal via open risk assessment method, comprising: performing metrology on a semiconductor chip to obtain metrology data of each to-be-tested metal via; forming an isolation factor and an intrinsic factor of each to-be-tested metal via according to the metrology data of each to-be-tested metal via, wherein the isolation factor is used to describe the surrounding geometric characteristics of the wiring pattern at the location of the to-be-tested metal via, and the intrinsic factor is used to describe the geometric characteristics of the wiring pattern itself at the location of the to-be-tested metal via; comparing the isolation factors and / or intrinsic factors between each to-be-tested metal via according to a priority rule to form a risk ranking result of the open of each to-be-tested metal via, wherein in the priority rule, the comparison order of the isolation factors is prior to that of the intrinsic factors.

[0008] In some embodiments, the isolation factor comprises a first parameter factor, a second parameter factor, and a third parameter factor; the intrinsic factor comprises a fourth parameter factor and a fifth parameter factor; wherein the first parameter factor is used to reflect the virtual metal distribution of the lower metal layer of the metal via, the second parameter factor is used to reflect the virtual metal distribution of the upper metal layer of the metal via, the third parameter factor is used to reflect the surrounding geometric characteristics of the metal via, the fourth parameter factor is used to reflect the minimum enclosing distance between the metal via and its adjacent lower metal layer, and the fifth parameter factor is used to reflect the relative size between the metal via and its adjacent upper metal layer.

[0009] In some embodiments, in the comparison order reflected by the priority rule, the priority of the first parameter factor, the second parameter factor, the third parameter factor, the fourth parameter factor, and the fifth parameter factor decreases in turn.

[0010] In some embodiments, the semiconductor chip comprises a golf club-shaped metal-via combination structure, the metal via is a via structure therein, and is used to connect the metal layer structure in the golf club-shaped metal-via combination structure and its adjacent metal layer structure, the metal layer structure in the golf club-shaped metal-via combination structure comprises a metal short side and a metal long side.

[0011] In some embodiments, wherein forming the isolation factor and intrinsic factor of each metal via under test according to the measurement data of each metal via under test comprises: dividing the cross-sectional area of the metal via by the area of each metal layer located under the metal via to obtain a plurality of area ratios; taking the mean value of the plurality of area ratios as a first parameter factor; taking the minimum distance from the metal via to a specified location of the metal layer adjacent to the metal via as a second parameter factor, wherein the line width of the specified location is greater than or equal to a line width threshold; determining the lateral minimum distance and the longitudinal minimum distance from the metal via to each specified metal layer; calculating the distance ratio of each lateral minimum distance to its corresponding longitudinal minimum distance; taking the maximum value of all distance ratios as a third parameter factor; taking the lateral minimum distance from the metal via to the metal layer adjacent to the metal via as a fourth parameter factor; and dividing the cross-sectional area of the metal via by the length of the long side of the metal layer structure located above the metal via in the golf club-shaped metal-via combination structure in which the metal via is located to obtain a fifth parameter factor.

[0012] In some embodiments, the size of the first parameter factor is negatively correlated with the risk of metal via open circuit, the size of the second parameter factor is positively correlated with the risk of metal via open circuit, the size of the third parameter factor is positively correlated with the risk of metal via open circuit, the size of the fourth parameter factor is positively correlated with the risk of metal via open circuit, and the size of the fifth parameter factor is positively correlated with the risk of metal via open circuit.

[0013] In some embodiments, wherein the risk ranking operation comprises: if the first parameter factor of the metal via under test is equal to 1, the metal via under test is a first-type metal via, otherwise the metal via under test is a second-type metal via, and in the risk ranking result, the risk of the first-type metal via is lower than that of the second-type metal via; performing a risk ranking operation on the second-type metal via according to the first parameter factor, the second parameter factor, the third parameter factor, and the fourth parameter factor; and in response to a preset condition, performing a risk ranking operation again on the second-type metal via according to the first parameter factor, the second parameter factor, the third parameter factor, the fourth parameter factor, and the fifth parameter factor.

[0014] In some embodiments, wherein the risk ranking operation comprises: for any two second-type metal vias, calculating the multiple ratio of the same parameter factor of the two second-type metal vias to obtain a plurality of multiple ratios; determining the maximum multiple ratio among the plurality of multiple ratios; if the parameter factor corresponding to the maximum multiple ratio is the first parameter factor, it is determined that the risk of the second-type metal via with the larger first parameter factor is lower than that of the second-type metal via with the smaller first parameter factor; and if the parameter factor corresponding to the maximum multiple ratio is other than the first parameter factor, it is determined that the risk of the second-type metal via with the smaller parameter factor corresponding to the maximum multiple ratio is lower than that of the second-type metal via with the larger parameter factor corresponding to the maximum multiple ratio.

[0015] In some embodiments, before the operation of risk ranking the second type of via according to the first parameter factor, the second parameter factor, the third parameter factor and the fourth parameter factor, further comprising: screening a third type of via and a fourth type of via from the second type of via according to the isolation factor, wherein the risk of open circuit of the third type of via is lower than that of the fourth type of via in the risk ranking result; the operation of risk ranking the second type of via according to the first parameter factor, the second parameter factor, the third parameter factor and the fourth parameter factor comprises: the operation of risk ranking the third type of via according to the first parameter factor, the second parameter factor, the third parameter factor and the fourth parameter factor; the operation of risk ranking the second type of via again according to the first parameter factor, the second parameter factor, the third parameter factor, the fourth parameter factor and the fifth parameter factor comprises: the operation of risk ranking the fourth type of via according to the first parameter factor, the second parameter factor, the third parameter factor, the fourth parameter factor and the fifth parameter factor.

[0016] In some embodiments, the specified metal layer is each metal layer in the semiconductor chip, or the specified metal layer is a suspicious metal layer in the semiconductor chip screened by the design rule detection method.

[0017] In some embodiments, the number of the to-be-tested metal vias is multiple, and the wiring pattern in the region where the to-be-tested metal vias are located does not contain virtual metal.

[0018] In some embodiments, the to-be-tested metal via is a suspicious metal via in the semiconductor chip screened by the design rule detection.

[0019] In the second aspect, the disclosure provides a semiconductor chip metal via open circuit detection method comprising: performing the semiconductor chip metal via open circuit risk assessment method of any one of the first aspect to obtain a risk ranking result; and performing open circuit detection on part or all of the to-be-tested metal vias according to the order of risk from high to low in the risk ranking result to obtain a detection result.

[0020] The unexpected effect of the present application is that, through the semiconductor chip metal via open circuit risk assessment method provided above, the disclosure embodiments can obtain the isolation factor and the intrinsic factor of the to-be-tested metal via based on the measurement results of the semiconductor chip, analyze the key physical size factors of the metal via related wiring pattern by comparing the isolation factor and the intrinsic factor between the to-be-tested metal vias, and determine the quality risk. Since the isolation factor reflects the surrounding geometric characteristics of the wiring pattern related to the to-be-tested metal via, which involves the load effect risk, and the intrinsic factor reflects the geometric characteristics of the wiring pattern related to the to-be-tested metal via itself, which involves the stress distribution after film deposition, polishing effect, lithography accuracy and etching rate, therefore, by introducing the priority rule, the isolation factor is compared preferentially, the key physical size factors with higher risk correlation degree can be preferentially analyzed, the risk ranking result can be quickly and accurately generated, and then the detection order or detection position can be guided in subsequent defect detection, the time consumption of detection is reduced, and the detection accuracy is improved. BRIEF DESCRIPTION OF DRAWINGS

[0021] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will be more apparent from the following detailed description read in conjunction with the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example, and wherein like reference numerals refer to like elements throughout. In the drawings: Figure 1 A schematic diagram of three golf club-shaped metal-via combination structures is shown; Figure 2 An exemplary flowchart of a semiconductor chip metal via open circuit risk assessment method according to some embodiments of the present disclosure is shown; Figure 3 A schematic diagram of an interconnection structure of a semiconductor chip is shown; Figure 4 An exemplary flowchart of a method for calculating the isolation factor and the intrinsic factor according to some embodiments of the present disclosure is shown; Figure 5 A schematic diagram of the lateral distance from Via3 to M3 according to some embodiments of the present disclosure is shown; Figure 6 An exemplary flowchart of a risk ranking method according to some embodiments of the present disclosure is shown; Figure 7 An exemplary flowchart of a risk ranking method according to some other embodiments of the present disclosure is shown; Figure 8 An exemplary flowchart of a semiconductor chip metal via open circuit detection method according to some embodiments of the present disclosure is shown; Figure 9 An exemplary structural block diagram of an electronic device according to embodiments of the present disclosure is shown. Detailed Implementation

[0022] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0023] It should be understood that the terms “comprising” and “including” used in this disclosure and claims indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0024] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0025] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0026] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0027] Exemplary application scenarios As the integration and miniaturization of semiconductor chips increase, the size of vias is further reduced to tens of nanometers or smaller. The size of vias is facing the miniaturization limit, increasing the risk of open circuit defects, which in turn leads to electrical problems in the chip and ultimately causes a loss in semiconductor chip yield. Therefore, inspecting for open circuit defects in vias is crucial for semiconductor chips, especially for high-risk weak wiring patterns that frequently cause open circuit problems in vias, such as the golf club (x+1)M combine xV pattern.

[0028] Figure 1 Schematic diagrams of three golf club-shaped metal-through-hole combination structures are shown, such as Figure 1 As shown, the golf club-shaped metal-through-hole combination structure consists of a metal layer structure and a through-hole structure. The metal layer structure 11 includes a short metal side and a long metal side. The through-hole structure is a metal through-hole used to connect the metal layer structure and adjacent metal layer structures. It may include an upper metal through-hole 121 connected to the upper metal layer of the metal layer structure and a lower metal through-hole 122 connected to the lower metal layer of the metal layer structure.

[0029] Golf club-shaped metal-via combination structures are high-risk locations for open circuits in metal vias, and it is difficult to quickly and accurately detect defect locations using optical or electron beam technology and / or electrical monitoring methods based on RCV test patterns. Firstly, a full scan of the semiconductor chip would take a lot of time, which does not meet the requirements of mass production scenarios. Secondly, randomly sampling and testing several locations on the semiconductor chip would introduce large errors, easily leading to missed detections of high-risk locations, thus affecting the reliability of the test results.

[0030] Exemplary application scheme In view of this, the present disclosure provides a semiconductor chip metal via open circuit risk assessment scheme, which measures and forms the isolation factor and intrinsic factor of each metal via to be tested and compares them according to priority rules, which can provide guidance for subsequent short circuit detection and improve detection accuracy and efficiency.

[0031] Figure 2 An exemplary flowchart of a semiconductor chip metal via open circuit risk assessment method 200 according to some embodiments of this disclosure is shown, such as... Figure 2 As shown, in step S201, the semiconductor chip is measured to obtain measurement data for each metal via to be measured; In step S202, the isolation factor and intrinsic factor of each metal via to be tested are formed based on the measurement data of each via.

[0032] In step S203, the isolation factors and / or intrinsic factors among the metal vias to be tested are compared according to the priority rules to form a risk ranking result for the open circuit of each metal via to be tested.

[0033] The interconnect structure of a semiconductor chip includes multiple metal layers and multiple vias connecting these metal layers. Taking a semiconductor chip with five metal layers as an example, each pair of adjacent metal layers is connected by a via, and each layer can have one or more vias.

[0034] For ease of understanding, Figure 3This diagram illustrates the interconnect structure of a semiconductor chip. It is assumed that the upper metal layer is the fourth metal layer M4 in the entire interconnect structure (i.e.,...). Figure 3 (34) The lower metal layer is the third metal layer M3 in the entire interconnect structure (i.e. Figure 3 In section 33), the metal through-hole connecting M4 and M3 can be called the third metal through-hole Via3 (i.e. Figure 3 (35 in the text). In the entire interconnect structure, there can be multiple Via3s distributed in multiple locations between M4 and M3. Since the location of each Via3 is different, the surrounding geometry of the wiring pattern at its location and the geometry of the Via3 itself also differ, so the risk of open circuits in each Via3 is not the same.

[0035] It should be noted that for semiconductor chips, an open circuit in any layer of metal vias can lead to electrical problems in the semiconductor device. Therefore, when performing open circuit defect detection on metal vias of semiconductor chips, each layer of metal vias needs to be tested for open circuits. To improve the accuracy and efficiency of the detection, this embodiment of the application performs an operation before testing each layer of metal vias for open circuits. Figure 2 The method shown performs a risk assessment on several metal vias located on the same layer to obtain a risk ranking result, which can effectively indicate the detection sequence or detection location for open circuit detection.

[0036] In other words, the semiconductor chip metal via open circuit risk assessment method shown in this embodiment is for several metal vias on the same layer, for example, Via3 located at several different test points.

[0037] In some embodiments, since the golf club-shaped metal-via combination structure is a high-risk location for open circuit problems in metal vias, the semiconductor chip used for open circuit risk assessment using the method described in this application includes a golf club-shaped metal-via combination structure. The metal via is a via structure used to connect the metal layer structure and its adjacent metal layer structure within the golf club-shaped metal-via combination structure. The metal layer structure in the golf club-shaped metal-via combination structure includes a short metal side and a long metal side. The metal via to be tested selected by the method described in this application is the via structure in the golf club-shaped metal-via combination structure.

[0038] In some embodiments, since analog sensitive circuits that do not use dummy metal are prone to via-hole breakage, when selecting the vias to be tested, several test points can be selected from areas that do not contain dummy metal to identify multiple vias to be tested. In other words, there are multiple vias to be tested, and the wiring pattern in the area where the vias to be tested are located does not contain dummy metal.

[0039] Dummy metal refers to a special structure in semiconductor chips used to fill unused areas of the chip. The filler is usually made of the same material as the chip, but it is not used to implement any circuitry or logic functions. The main purpose of dummy metal is to adjust the physical structure of the chip to meet the requirements of the design rules.

[0040] Furthermore, after determining the area where the metal via to be tested is located based on the virtual metal, design rules can be used to filter out suspicious metal vias through Design Rule Check (DRC), which will then be used as the final metal vias to be tested for open circuit risk assessment. For example, design rule check can be performed on Via3 within areas of the wiring pattern that do not contain virtual metal; Via3 that does not meet the design rules are the metal vias to be tested.

[0041] In other embodiments, the metal via to be tested can also be a suspected metal via in the semiconductor chip that has been directly screened out by design rules. For example, before performing step S201, all Via3s are subjected to design rule detection, and the Via3s that do not meet the design rules are the metal vias to be tested.

[0042] After identifying the metal vias to be tested, measurement data is obtained through measurement. As an example, the measurement object can be a semiconductor chip design layout, allowing for early detection of open-circuit risks and enabling process and / or design improvements before mass production. As another example, the measurement object can also be a semiconductor chip sample; measuring the actual product yields more accurate measurement data.

[0043] It should be noted that the embodiments of this application do not impose strict limitations on the measurement method. As an example, measurement can be performed using optical technology or electron beam technology, and no further restrictions are imposed here.

[0044] Based on the different data described in the measurement data, the data types can be divided into two categories: isolated factors and intrinsic factors. Isolated factors describe the surrounding geometric features of the wiring pattern at the location of the via under test, including the distribution of the dummy pattern in the upper and lower metal layers, thus reflecting the loading effect risk. Intrinsic factors, on the other hand, describe the geometric features of the wiring pattern itself at the location of the via under test, reflecting the impact of stress distribution, polishing effect, lithography accuracy, and etching rate after thin film deposition. In other words, isolated factors and intrinsic factors provide key physical dimensional factors of the wiring pattern related to metal vias for risk analysis.

[0045] After forming the isolation factor and intrinsic factor of each metal via to be tested, the isolation factor and intrinsic factor of each metal via to be tested can be compared. For example, the isolation factor of the first metal via to be tested can be compared with the isolation factor of the second metal via to be tested, and the intrinsic factor of the first metal via to be tested can be compared with the intrinsic factor of the second metal via to be tested, so as to analyze the relative magnitude of the open circuit risk of the first metal via to be tested and the second metal via to be tested.

[0046] Because isolated factors and intrinsic factors describe different types of features, the key physical size factors they provide also reflect different impacts on semiconductor chip performance. Therefore, considering their correlation with open circuit risk, isolated factors can be compared first to improve comparison efficiency. In other words, in the priority rule, isolated factors are compared before intrinsic factors. For example, the isolated factors of the first and second vias under test are compared first. If the isolated factors show that the open circuit risk of the first via is significantly greater than that of the second, then there is no need to compare the intrinsic factors of the first and second vias. If the relative magnitude of the open circuit risk between the first and second vias cannot be determined based on the isolated factors, then the comparison results of the intrinsic factors can be combined to complete the risk ranking.

[0047] It should be noted that the specific execution steps for comparing the open circuit risk of the metal via under test based on isolated factors will be explained in detail below. Similarly, the specific execution steps for comparing the open circuit risk of the metal via under test based on intrinsic factors will also be explained in detail below.

[0048] In this embodiment, after obtaining the risk ranking result of each metal via to be tested through steps S201 to S203, the location and / or order of subsequent open circuit detection can be determined based on the risk ranking result, thereby reducing the detection time and improving the detection accuracy. For example, after obtaining the risk ranking result of the first metal via to be tested, the second metal via to be tested, the third metal via to be tested, and the fourth metal via to be tested with the open circuit risk increasing sequentially (Via3-1 < Via3-2 < Via3-3 < Via3-4, where Via3-1 represents the first metal via to be tested, and so on), when performing open circuit detection, the test points where the first two metal vias to be tested (Via3-1 and Via3-2) are located can be selected as the detection location, or the test points where the first three (Via3-1, Via3-2, and Via3-3) or all metal vias to be tested are located can be selected as the detection location. The testing order is to first test the test point with the highest risk, Via3-4, and then test the test point with the lowest risk, Via3-1, last.

[0049] The following describes the process for assessing open circuit risk based on isolated factors and / or intrinsic factors. Before assessing the open circuit risk of each metal via to be tested, the isolated factors and intrinsic factors can be further decomposed. The isolated factors include: the first parameter factor α, the second parameter factor β, and the third parameter factor γ; the intrinsic factors include: the fourth parameter factor δ and the fifth parameter factor σ. Among them, the first parameter factor α reflects the virtual metal distribution of the lower metal layer of the via, i.e., the Underlayer dummy; the second parameter factor β reflects the virtual metal distribution of the upper metal layer of the via, i.e., the Upperlayer dummy; the third parameter factor γ reflects the surrounding geometrical characteristics of the via, i.e., the Around geometrical characteristic; the fourth parameter factor δ reflects the minimum enclosure distance between the via and its adjacent lower metal layer, i.e., the Enclosure. For ease of understanding, taking Via3 as an example, the fourth parameter factor δ reflects the lateral distance from the via to the edge of the third metal layer M3 in the portion of the portion of the via Via3 surrounded by the lower metal layer (i.e., the third metal layer M3) after the via Via3 and its lower metal layer (i.e., the third metal layer M3) are projected onto the same plane from a top view; the fifth parameter factor σ reflects the relative size of the via and its adjacent upper metal layer, i.e., the width-length ratio. Specifically, the fifth parameter factor σ represents the ratio of the cross-sectional area of ​​the via to the metal long side of its adjacent upper metal layer.

[0050] Furthermore, in the comparison order reflected by the priority rule, the priorities of the first parameter factor α, the second parameter factor β, the third parameter factor γ, the fourth parameter factor δ, and the fifth parameter factor σ decrease sequentially. In other words, when executing step S203 of the previous embodiment, risk ranking is first performed based on α. ​​If a final risk ranking result is not obtained, risk ranking is then performed by combining α and β. If a final risk ranking result is still not obtained, risk ranking is then performed by combining α, β, and γ. If a final risk ranking result is still not obtained, risk ranking is then performed by combining α, β, γ, and δ. If necessary, the final risk ranking result is obtained by combining all five parameter factors.

[0051] Furthermore, to improve the efficiency of comparison, when combining new parameter factors for risk ranking, multiple new parameter factors can be combined according to priority rules. For example, risk ranking can be performed first based on α. ​​If a final risk ranking result is not obtained, then α, β, and γ can be combined for risk ranking. If a final risk ranking result is still not obtained, then α, β, γ, and δ can be combined for risk ranking. If a final risk ranking result is still not obtained, then all five parameter factors can be combined to obtain the final risk ranking result.

[0052] Based on the isolated factor and intrinsic factor described above, some embodiments of this application provide a method for calculating the isolated factor and intrinsic factor. Figure 4 An exemplary flowchart of a method 400 for calculating isolated factors and intrinsic factors according to some embodiments of this disclosure is shown. It will be understood that the method for calculating isolated factors and intrinsic factors is a specific implementation of step S202 described above, and therefore, the foregoing is in conjunction with... Figure 2 The described features can be applied similarly here.

[0053] like Figure 4 As shown, in step S401, the cross-sectional area of ​​the metal via is divided by the area of ​​each metal layer located below the metal via to obtain several area ratios. In step S402, the average of several area ratios is taken as the first parameter factor; In step S403, the minimum distance from the metal via to a specified position in its adjacent upper metal layer is used as a second parameter factor; wherein the linewidth at the specified position is greater than or equal to the linewidth threshold. In step S404, the minimum lateral distance and minimum longitudinal distance from the metal via to each specified metal layer are determined; In step S405, the distance ratio of each horizontal minimum distance to its corresponding vertical minimum distance is calculated; In step S406, the maximum value among all distance ratios is taken as the third parameter factor; In step S407, the minimum lateral distance from the metal via to its adjacent lower metal layer is taken as the fourth parameter factor. In step S408, the cross-sectional area of ​​the metal through hole is divided by the length of the long side of the metal layer structure above the metal through hole in the golf club-shaped metal-through hole combination structure to obtain the fifth parameter factor.

[0054] It is understood that steps S401 to S402 are the calculation steps of the first parameter factor, step S403 is the calculation step of the second parameter factor, steps S404 to S406 are the calculation steps of the third parameter factor, step S407 is the calculation step of the fourth parameter factor, and step S408 is the calculation step of the fifth parameter factor. In this embodiment, there is no strict restriction on the calculation order of the first to fifth parameter factors, and the calculation steps of the first to fifth parameter factors can be executed in any order or in parallel.

[0055] For ease of understanding, let's take Via3 in an interconnect structure with four metal layers (M1-M4) as an example: The first parameter factor of Via3 is the average of overlap / M2 and overlap / M1, where overlap / M2 is the ratio of the cross-sectional area of ​​Via3 to the area of ​​the second metal layer M2, and overlap / M1 is the ratio of the cross-sectional area of ​​Via3 to the area of ​​the first metal layer M1.

[0056] The second parameter factor of Via3 is the distance from Via3 to the nearest large-linewidth fourth metal layer M4, where the large-linewidth M4 refers to the position in M4 where the linewidth is greater than or equal to the linewidth threshold. The linewidth threshold can be determined from the design rules. For example, according to the design rules, the standard for large linewidth can be determined as a linewidth greater than or equal to 4.5nm, then the linewidth threshold can be determined as 4.5nm.

[0057] When calculating the third parameter factor of Via3, first determine the minimum lateral distance (Minimum Space X) from Via3 to the nearest M4 in the lateral direction and the minimum longitudinal distance (Minimum Space Y) from Via3 to the nearest M4 in the longitudinal direction. Then calculate the distance ratio to M4: Space X / Y = Minimum Space X / Minimum Space Y. Calculate the distance ratios to M1, M2, and M3 using the same method. Finally, take the maximum value among the distance ratios to M1, M2, M3, and M4 as the third parameter factor of Via3. The aforementioned minimum lateral and minimum longitudinal distances refer to the distances from a top-down viewpoint, which is the viewpoint perpendicular to the plane containing any metal layer.

[0058] The fourth parameter factor of Via3 is the lateral distance from Via3 to M3. Figure 5 A schematic diagram showing the lateral distance from Via3 to M3 in some embodiments of this disclosure is shown, such as Figure 5 As shown, the lateral distance refers to the distance in the lateral direction from a top-down perspective, which is the perspective perpendicular to the plane where M3 is located.

[0059] The fifth parameter factor of Via3 is the ratio of the cross-sectional area of ​​Via3 to the length of the long side of M4, where the long side of M4 refers to the length of the long metal side belonging to M4 in the golf club-shaped metal-through hole combination structure in which Via3 is located.

[0060] Furthermore, when calculating the third parameter factor, the metal layer can be specified as each metal layer in the semiconductor chip, or as a suspected metal layer in the semiconductor chip screened out by the design rule detection method. Taking Via3 in an interconnect structure with four metal layers (M1~M4) as an example, if the metal layer is specified as each metal layer in the semiconductor chip, the distance ratios of M1, M2, M3, and M4 can be calculated according to the calculation method provided above, and the maximum value among the distance ratios corresponding to M1, M2, M3, and M4 is taken as the third parameter factor of Via3; if the metal layer is specified as a suspected metal layer in the semiconductor chip screened out by the design rule detection method, such as M1 and M3, only the distance ratios of M1 and M3 can be calculated, and the maximum value among the distance ratios corresponding to M1 and M3 is taken as the third parameter factor of Via3.

[0061] By executing steps S401 to S408, a data table as shown in Table 1 can be generated: Table 1. Data on isolated factors and intrinsic factors

[0062] It should be noted that P1-P5 in Table 1 refer to different test points, and Via3 located at test point P1 can be understood as Via3-1 described above. Additionally, it should be noted that the specific values ​​in Table 1 are only examples in this embodiment.

[0063] Table 1 can be further simplified to Table 2, which shows the parameter factor values ​​for the metal via to be tested. Table 2. Parameter factor values ​​for the metal via under test

[0064] Based on the parameter factor values ​​in Table 2, the risk of the Via3 test sites at the five test points P1-P5 can be ranked. Figure 6An exemplary flowchart of a risk ranking method 600 according to some embodiments of this disclosure is shown. It can be understood that the risk ranking method is a specific implementation of the aforementioned step S203, therefore, the foregoing combined with Figure 2 The described features can be applied similarly here.

[0065] like Figure 6 As shown, in step S601, type I and type II through holes are selected based on the first parameter factor; In step S602, risk sorting is performed on the second type of through hole according to the first parameter factor, the second parameter factor, the third parameter factor and the fourth parameter factor; In step S603, in response to preset conditions, the risk sorting operation of the second type of through holes is performed again according to the first parameter factor, the second parameter factor, the third parameter factor, the fourth parameter factor and the fifth parameter factor.

[0066] In some embodiments, the magnitude of the first parameter factor is negatively correlated with the risk of open circuit in the metal via; that is, the larger the value of the first parameter factor, the lower the risk of open circuit in the metal via under test. Based on this, when executing step S601, it can be determined whether the first parameter factor of the metal via under test is equal to 1. If the first parameter factor of the metal via under test is equal to 1, the metal via under test is a Class I via; otherwise, it is a Class II via. According to the relationship between the magnitude of the first parameter factor and the risk of open circuit in the metal via, in the risk ranking result, the risk of open circuit in Class I vias is lower than that in Class II vias.

[0067] Furthermore, in some embodiments, the probability of a Class I via experiencing an open circuit problem can be considered extremely low, approximately zero. Therefore, when a Class I via includes multiple metal vias to be tested, it is not necessary to sort the Class I vias again, and the location of the Class I vias does not need to be detected during subsequent open circuit detection. In other embodiments, when a Class I via includes multiple metal vias to be tested, the Class I vias can be re-ranked for risk. In this case, the risk ranking operation for Class I vias can be performed in the same manner as the risk ranking operation for Class II vias in step S602.

[0068] As described in the preceding embodiments, in the comparison order reflected by the priority rule, the priorities of the first parameter factor α, the second parameter factor β, the third parameter factor γ, the fourth parameter factor δ, and the fifth parameter factor σ decrease sequentially. When ranking risks, risk ranking is first performed based on α. ​​If a final risk ranking result is not obtained, then α and β are combined for risk ranking. If a final risk ranking result is still not obtained, then α, β, and γ are combined for risk ranking. If a final risk ranking result is still not obtained, then α, β, γ, and δ are combined for risk ranking. If necessary, all five parameter factors are combined to obtain the final risk ranking result. Furthermore, to improve the efficiency of the comparison, when combining new parameter factors for risk ranking, multiple new parameter factors can be combined according to the priority rule for risk ranking.

[0069] Furthermore, the magnitude of the second parameter factor is positively correlated with the risk of open circuit in the metal via, the magnitude of the third parameter factor is positively correlated with the risk of open circuit in the metal via, the magnitude of the fourth parameter factor is positively correlated with the risk of open circuit in the metal via, and the magnitude of the fifth parameter factor is positively correlated with the risk of open circuit in the metal via.

[0070] Therefore, after performing risk ranking operations on the second type of vias based on the first, second, third, and fourth parameter factors, a clear risk ranking result may or may not be formed. If a clear risk ranking result is not formed, step S603 needs to be executed to obtain the final risk ranking result. In some embodiments, the preset condition includes: a clear risk ranking result is not formed.

[0071] exist Figure 6 Building upon the method described, to further improve the efficiency of risk ranking, we can first classify the Class II vias to clarify the magnitude of the open circuit risk among different categories, and then rank the Class II vias within each category. For example, Class III and Class IV vias can be selected from Class II vias. In the risk ranking results, the risk of an open circuit in Class III vias is lower than that in Class IV vias.

[0072] Taking the calculation results of the isolation factor and intrinsic factor shown in Table 2 as an example, in some embodiments, based on the value of α, the metal via at test point P3 can be determined to be a Class I via, and the metal vias at test points P1, P2, P4, and P5 can be determined to be Class II vias. Then, based on the values ​​of α, β, and γ, the metal vias at test points P1, P2, P4, and P5 can be further divided into two categories. Among them, P2 and P5 perform better than P1 and P4 in terms of isolation factor. Therefore, the metal vias at test points P2 and P5 are Class III vias, and the metal vias at test points P1 and P4 are Class IV vias.

[0073] Figure 7 An exemplary flowchart of a risk ranking method 700 according to other embodiments of this disclosure is shown. It can be understood that... Figure 7 The risk ranking method shown is a specific implementation of step S203 mentioned above; therefore, the preceding text combines... Figure 2 The described features can be applied similarly here.

[0074] like Figure 7 As shown, in step S701, type I and type II through holes are selected based on the first parameter factor; In step S702, Class III and Class IV vias are selected from Class II vias based on the isolation factor; In step S703, the risk ranking operation is performed on the three types of through holes according to the first parameter factor, the second parameter factor, the third parameter factor and the fourth parameter factor; In step S704, the four types of vias are re-ranked for risk based on the first parameter factor, the second parameter factor, the third parameter factor, the fourth parameter factor, and the fifth parameter factor.

[0075] In this embodiment, the specific execution method of step S701 is the same as that of step S601 in the previous embodiment, and will not be repeated here.

[0076] As an example, step S702 can employ a median-based statistical method to screen for Class III and Class IV vias. In this median-based method, Class II vias can be sorted in descending order according to a first parameter factor to obtain a first sequence. The Class II vias ranked before the median in the first sequence are then used as the first potential Class III via set. Similarly, Class II vias are sorted in ascending order according to a second parameter factor to obtain a second sequence. The Class II vias ranked before the median in the second sequence are then used as the second potential Class III via set. Furthermore, Class II vias are sorted in ascending order according to a third parameter factor to obtain a third sequence. The Class II vias ranked before the median in the third sequence are then used as the third potential Class III via set. After obtaining three potential three-class via sets—the first potential three-class via set, the second potential three-class via set, and the third potential three-class via set—the two-class vias in the intersection / union of the three sets are identified as three-class vias, and the two-class vias that do not belong to the intersection / union are identified as four-class vias.

[0077] Since the magnitude of the first parameter factor is negatively correlated with the risk of metal via breakage, the first sequence obtained by sorting according to the first parameter factor from largest to smallest actually reflects the risk ranking result sorted by the first parameter factor (risk value from smallest to largest). Similarly, the second sequence actually reflects the risk ranking result sorted by the second parameter factor (risk value from smallest to largest), and the third sequence actually reflects the risk ranking result sorted by the third parameter factor (risk value from smallest to largest). Furthermore, taking the intersection method ensures that the three types of vias selected will rank highly in the risk ranking result from smallest to largest risk value, regardless of which isolated parameter factor is used as the basis.

[0078] As another example, different weights can be configured for the first, second, and third parameter factors. Based on the comparison results between the weights and the parameter factors, such as the difference or multiple ratio of the parameter factors or the data type that can characterize the degree of difference, the performance of each type II via on the isolated factor can be comprehensively analyzed, and the type III via with better performance can be selected, while the rest are type IV vias.

[0079] It should be noted that the screening methods for the three types and four types of through holes provided above are only examples. In practical applications, other screening methods are also applicable to this disclosure.

[0080] The execution process of risk ranking is explained below: First, for any two Class II vias, calculate the multiple ratio of their common parameter factors to obtain several multiple ratios; then, determine the largest multiple ratio among these multiple ratios; if the parameter factor corresponding to the largest multiple ratio is the first parameter factor, then the Class II via with the larger first parameter factor is considered to have a lower risk than the Class II via with the smaller first parameter factor; if the parameter factor corresponding to the largest multiple ratio is a parameter factor other than the first parameter factor, then the Class II via with the smaller parameter factor corresponding to the largest multiple ratio is considered to have a lower risk than the Class II via with the larger parameter factor corresponding to the largest multiple ratio.

[0081] To facilitate understanding, the calculation results of isolated factors and intrinsic factors shown in Table 2 are used as an example to illustrate the risk ranking operation based on the first to fourth parameter factors. For the two test points P2 and P5, the ratio of the first parameter factor to the second parameter factor is approximately 13.42, the ratio of the second parameter factor is approximately 3.98, the ratio of the third parameter factor is approximately 15.46, and the ratio of the fourth parameter factor is approximately 53.75. Therefore, the parameter factor corresponding to the largest ratio is the fourth parameter factor. The risk ranking result is obtained based on the comparison results of the fourth parameter factor. Since the magnitude of the fourth parameter factor is positively correlated with the risk of open circuit in the metal via, the fourth parameter factor of the metal via at test point P5 is smaller than that of P2. Therefore, the risk of open circuit in the metal via at test point P5 is lower than that of P2. That is, in the risk ranking result, P5 < P2.

[0082] Based on the same execution process, the risk ranking results between any two Class II vias can be obtained. Combining these risk ranking results yields the final risk ranking result.

[0083] It should be noted that the multiple ratio reflects the degree of difference between the same parameter factors of the two. Therefore, when calculating the multiple ratio, the larger value of the parameter factor is usually divided by the smaller value of the parameter factor to facilitate comparison of the calculated multiple ratios.

[0084] During the initial risk ranking operation of Class II vias, specifically during step S602, contradictory risk ranking results may occur between two Class II vias. Alternatively, the differences in parameter factors may be too small to support the reliability of the comparison results. In such cases, a second risk ranking operation needs to be performed using new parameter factors, i.e., step S603. Therefore, besides the failure to generate a clear risk ranking result, preset conditions may also include: the maximum multiple ratio being less than the multiple ratio threshold.

[0085] By implementing the semiconductor chip metal via open circuit risk assessment method provided in any of the preceding embodiments, the open circuit risks of several metal vias to be tested can be ranked. In some embodiments, the several metal vias to be tested can be suspected metal vias selected through certain criteria, thereby avoiding the omission of weak patterns of high-incidence open circuit problems. When ranking the risks, isolated factors and intrinsic factors, including several parameter factors, are compared according to certain priority rules. Compared with directly using all factors for risk ranking, the comparison method of introducing priority rules can improve the comparison efficiency.

[0086] The resulting risk ranking results can reflect the probability of metal through-hole open circuit problems occurring at different test points, thereby guiding the setting of open circuit detection at high-risk test points, and / or guiding open circuit detection to be carried out in order from high risk to low risk, thus improving detection efficiency while ensuring detection reliability.

[0087] Based on the semiconductor chip metal via open circuit risk assessment method provided in any of the preceding embodiments, some embodiments disclosed herein also provide a semiconductor chip metal via open circuit detection method, which can perform open circuit detection based on risk ranking results, taking into account both detection accuracy and detection efficiency.

[0088] Figure 8 An exemplary flowchart of a semiconductor chip metal via open circuit detection method 800 according to some embodiments of this disclosure is shown, such as... Figure 8 As shown, in step S801, the semiconductor chip is measured to obtain measurement data for each metal via to be measured. In step S802, the isolation factor and intrinsic factor of each metal via are formed based on the measurement data of each via. In step S803, the isolation factors and / or intrinsic factors among the metal vias to be tested are compared according to the priority rules to form a risk ranking result for the open circuit of each metal via to be tested. In step S804, based on the risk ranking results from high to low, some or all of the metal through holes to be tested are subjected to open circuit detection to obtain the detection results.

[0089] exist Figure 8 In the semiconductor chip metal via open circuit detection method shown, the execution methods of steps S801 to S803 can be referred to the preceding text. Figures 2-7 The described embodiments will not be elaborated further here.

[0090] As an example, after obtaining the risk ranking result, such as P3 < P5 < P2 < P1 < P4, step S804 can only perform open circuit detection on the test metal through holes of the lower-ranked test points, such as P2, P1 and P4, thereby reducing the workload of open circuit detection.

[0091] As another example, open circuit detection can also be performed on all test points of the metal via, such as the five test points P1-P5.

[0092] Whether performing open circuit testing on some or all of the metal vias to be tested, the testing sequence is always from high risk to low risk, that is, the metal vias with the highest open circuit risk are tested first, so as to ensure the reliability of the test results.

[0093] In summary, this disclosure provides a method for assessing the risk of open circuits in metal vias of semiconductor chips. Compared to existing detection methods, this risk assessment method can provide early warnings of key suspicious test points, enabling early alerts of online process and / or design issues. Furthermore, it allows for optimization of the testing process by adjusting the testing location and sequence. Compared to existing methods that involve discovering anomalies during chip testing and then slicing the chip to analyze the cause of failure, this risk assessment method significantly reduces time, greatly improves production efficiency, and saves substantial human and material resources.

[0094] This disclosure also provides a method for detecting open circuits in metal vias of semiconductor chips. It utilizes a risk assessment method for open circuits in metal vias of semiconductor chips to generate a risk ranking result, and then determines the scope and / or order of open circuit detection based on the risk ranking result, thereby achieving focused detection of high-risk locations and balancing detection accuracy and efficiency.

[0095] To implement the methods and steps described above in conjunction with the accompanying drawings at the software and hardware level, the embodiments of this disclosure also provide, as follows: Figure 9 The electronic device shown. Specifically... Figure 9 An exemplary structural block diagram of an electronic device 900 according to an embodiment of this disclosure is shown.

[0096] like Figure 9 As shown, the electronic device 900 disclosed herein may include a processor 910 and a memory 920. Specifically, the memory 920 stores executable program instructions. When the program instructions are executed by the processor 910, the electronic device performs the functions described above. Figures 1-8 The methods and steps described.

[0097] It is understood that, in order to clearly illustrate the scheme disclosed herein and avoid confusion with the prior art, Figure 9 The electronic device 900 only shows the components relevant to the embodiments disclosed herein, omitting those components that may be necessary for implementing the embodiments disclosed herein but fall within the scope of the prior art. Therefore, based on the content of this disclosure, those skilled in the art can clearly understand that the electronic device 900 disclosed herein may also include components related to… Figure 9 The following are common constituent elements with different constituent elements.

[0098] In an exemplary implementation scenario, the processor 910 described above can control the overall operation of the electronic device 900. For example, the processor 910 can control the operation of the electronic device 900 by executing a program stored in the memory 920. In terms of implementation, the processor 910 disclosed herein can be implemented as a central processing unit (CPU), application processor (AP), intelligent processing unit (IPU), etc., provided in the electronic device 900. Furthermore, the processor 910 disclosed herein can also be implemented in any suitable manner. For example, the processor 910 can take the form of, for example, a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers, etc.

[0099] In terms of stored content, memory 920 can be used to store various data and instructions processed in electronic device 900. For example, memory 920 can store processed data and data to be processed in electronic device 900. Memory 920 can store datasets that have been processed or are to be processed by processor 910. In addition, memory 920 can store applications, drivers, etc., to be driven by electronic device 900. For example, memory 920 can store various programs to be executed by processor 910. Memory 920 can be DRAM, but this disclosure is not limited thereto. In terms of type, memory 920 can include at least one of volatile memory or non-volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Volatile memory may include dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), PRAM, MRAM, RRAM, ferroelectric RAM (FeRAM), etc. In embodiments, memory 920 may include at least one of hard disk drive (HDD), solid-state drive (SSD), high-density flash memory (CF), secure digital card (SD), micro-secure digital card (Micro-SD), mini-secure digital card (Mini-SD), extreme digital card (xD), cache, or memory stick.

[0100] In summary, the specific functions implemented by the memory 920 and processor 910 of the electronic device 900 provided in this specification can be explained in comparison with the aforementioned embodiments in this specification, and can achieve the technical effects of the aforementioned embodiments. They will not be repeated here.

[0101] Additionally or optionally, this disclosure may also be implemented as a non-transitory machine-readable storage medium (or computer-readable storage medium, or machine-readable storage medium) storing computer program instructions (or computer program, or computer instruction code) that, when executed by a processor of an electronic device (or electronic device, server, etc.), cause the processor to perform some or all of the steps of the methods described above according to this disclosure.

[0102] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

[0103] The collection and acquisition of various data disclosed herein comply with relevant laws and regulations and are authorized by the data providers. Any organization or individual that needs to obtain external data shall obtain authorization in accordance with the law and ensure data security. It is prohibited to illegally collect, use, process, or transmit unauthorized or unprotected data, or to illegally buy, sell, provide, or disclose unauthorized or unprotected data.

Claims

1. A method for assessing the risk of open circuits in metal vias of semiconductor chips, characterized in that, include: The semiconductor chip is measured to obtain measurement data for each metal via under test; Based on the measurement data of each metal via under test, an isolation factor and an intrinsic factor are formed for each metal via under test. The isolation factor is used to describe the surrounding geometric features of the wiring pattern at the location of the metal via under test, and the intrinsic factor is used to describe the geometric features of the wiring pattern itself at the location of the metal via under test. The isolation factors and / or intrinsic factors among the tested metal vias are compared according to a priority rule to form a risk ranking result for each tested metal via open circuit, wherein, in the priority rule, the comparison order of the isolation factors takes precedence over the intrinsic factors.

2. The method according to claim 1, characterized in that, The isolated factors include: a first parameter factor, a second parameter factor, and a third parameter factor; the intrinsic factors include: a fourth parameter factor and a fifth parameter factor. The first parameter factor reflects the virtual metal distribution of the lower metal layer of the via, the second parameter factor reflects the virtual metal distribution of the upper metal layer of the via, the third parameter factor reflects the surrounding geometric features of the via, the fourth parameter factor reflects the minimum enclosure distance between the via and its adjacent lower metal layer, and the fifth parameter factor reflects the relative size of the via and its adjacent upper metal layer.

3. The method according to claim 2, characterized in that, In the comparison order reflected by the priority rule, the priority of the first parameter factor, the second parameter factor, the third parameter factor, the fourth parameter factor, and the fifth parameter factor decreases in sequence.

4. The method according to claim 2, characterized in that, The semiconductor chip includes a golf club-shaped metal-via combination structure, wherein the metal via is a via structure used to connect the metal layer structure in the golf club-shaped metal-via combination structure and its adjacent metal layer structure. The metal layer structure in the golf club-shaped metal-via combination structure includes a short metal side and a long metal side.

5. The method according to claim 4, characterized in that, The isolation factor and intrinsic factor for each metal via, formed based on the measurement data, include: Divide the cross-sectional area of ​​the metal via by the area of ​​each metal layer below the metal via to obtain several area ratios. The average of the aforementioned area ratios is taken as the first parameter factor. The minimum distance from the metal via to a specified location in its adjacent upper metal layer is used as the second parameter factor, wherein the linewidth at the specified location is greater than or equal to a linewidth threshold. Determine the minimum lateral and minimum longitudinal distances from the metal vias to each specified metal layer; Calculate the ratio of each horizontal minimum distance to its corresponding vertical minimum distance; The maximum value among all distance ratios is taken as the third parameter factor; The minimum lateral distance from the metal via to its adjacent lower metal layer is taken as the fourth parameter factor; The fifth parameter factor is obtained by dividing the cross-sectional area of ​​the metal through-hole by the length of the long side of the metal layer structure above the metal through-hole in the golf club-shaped metal-through-hole combination structure.

6. The method according to any one of claims 2-5, characterized in that, The magnitude of the first parameter factor is negatively correlated with the risk of metal via open circuit; the magnitude of the second parameter factor is positively correlated with the risk of metal via open circuit; the magnitude of the third parameter factor is positively correlated with the risk of metal via open circuit; the magnitude of the fourth parameter factor is positively correlated with the risk of metal via open circuit; and the magnitude of the fifth parameter factor is positively correlated with the risk of metal via open circuit.

7. The method according to any one of claims 3-5, characterized in that, Based on priority rules, the isolation factors and / or intrinsic factors among the tested metal vias are compared to form a risk ranking result for each tested metal via open circuit, including: If the first parameter factor of the metal via under test is equal to 1, then the metal via under test is a Class I via; otherwise, the metal via under test is a Class II via. In the risk ranking result, the risk of open circuit of the Class I via is lower than that of the Class II via. Based on the first parameter factor, the second parameter factor, the third parameter factor, and the fourth parameter factor, a risk ranking operation is performed on the two types of through holes; In response to preset conditions, the risk ranking operation is performed again on the second type of through hole according to the first parameter factor, the second parameter factor, the third parameter factor, the fourth parameter factor and the fifth parameter factor.

8. The method according to claim 7, characterized in that, The risk ranking process includes: For any two Class II through holes, calculate the ratio of the multiples of the same parameter factors for each hole to obtain several multiple ratios; Determine the largest multiple ratio among the stated multiple ratios; If the parameter factor corresponding to the maximum multiple ratio is the first parameter factor, then the risk of the Class II via with the larger first parameter factor is considered to be lower than that of the Class II via with the smaller first parameter factor. If the parameter factor corresponding to the maximum multiplier ratio is a parameter factor other than the first parameter factor, then the risk of the Class II via with the smaller parameter factor corresponding to the maximum multiplier ratio is determined to be less than that of the Class II via with the larger parameter factor corresponding to the maximum multiplier ratio.

9. The method according to claim 7, characterized in that, Before performing risk ranking operations on the two types of vias based on the first parameter factor, the second parameter factor, the third parameter factor, and the fourth parameter factor, the method further includes: selecting three types of vias and four types of vias from the two types of vias based on the isolation factor, wherein in the risk ranking results, the risk of open circuits in the three types of vias is lower than that in the four types of vias. The risk ranking operation for the second type of via based on the first parameter factor, the second parameter factor, the third parameter factor, and the fourth parameter factor includes: performing a risk ranking operation for the third type of via based on the first parameter factor, the second parameter factor, the third parameter factor, and the fourth parameter factor; The risk ranking operation for the two types of vias based on the first parameter factor, the second parameter factor, the third parameter factor, the fourth parameter factor, and the fifth parameter factor includes: performing a risk ranking operation for the four types of vias based on the first parameter factor, the second parameter factor, the third parameter factor, the fourth parameter factor, and the fifth parameter factor.

10. The method according to claim 5, characterized in that, The designated metal layer is each metal layer in the semiconductor chip, or the designated metal layer is a suspected metal layer in the semiconductor chip that has been screened out by a design rule detection method.

11. The method according to claim 1, characterized in that, The number of the metal vias to be tested is multiple, and the wiring pattern in the area where the metal vias to be tested are located does not contain virtual metal.

12. The method according to claim 1 or 11, characterized in that, The metal via to be tested is a suspicious metal via in the semiconductor chip that has been detected and screened out by design rules.

13. A method for detecting open circuits in metal vias of semiconductor chips, characterized in that, include: Perform the semiconductor chip metal via open circuit risk assessment method as described in any one of claims 1-12 to obtain risk ranking results; Based on the risk ranking results from high to low, some or all of the metal vias to be tested are subjected to open circuit detection to obtain the test results.

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