Semiconductor package

Abstract

A semiconductor package includes: a semiconductor chip on a substrate; a first spacer and a second spacer extending in a first horizontal direction on the semiconductor chip and spaced apart from each other in a second horizontal direction; and an encapsulant at least partially covering the substrate, the semiconductor chip, the first spacer, and the second spacer. An upper portion of the encapsulant is located between the first spacer and the second spacer. A first edge portion and a second edge portion of the encapsulant overlap the semiconductor chip in the second horizontal direction and are spaced apart from each other in the second horizontal direction with the semiconductor chip interposed therebetween. An upper surface of the first spacer is coplanar with an upper surface of the upper portion of the encapsulant. A cross-sectional area of the upper portion of the envelope is equal to a sum of cross-sectional areas of the first edge portion and the second edge portion of the envelope.

Description

TECHNICAL FIELD

[0001] The present inventive concepts relate to a semiconductor package including spacers. BACKGROUND

[0002] As the demand for high performance, speed, and / or multi-functionality of semiconductor devices increases, the degree of integration of semiconductor devices also increases. In manufacturing fine-patterning semiconductor devices in response to the trend of high integration of semiconductor devices, it is required to implement a pattern having a fine width or a fine spacing distance. In addition, high integration of semiconductor devices mounted on a semiconductor package is required. SUMMARY

[0003] Example embodiments provide a semiconductor package including spacers disposed on a semiconductor chip.

[0004] According to an example embodiment, a semiconductor package can include a semiconductor chip on a substrate, a first spacer on the semiconductor chip and extending in a first horizontal direction, a second spacer on the semiconductor chip, extending in the first horizontal direction, and spaced apart from the first spacer in a second horizontal direction, wherein the second horizontal direction intersects the first horizontal direction, and an encapsulant at least partially covering the substrate, the semiconductor chip, the first spacer, and the second spacer. The encapsulant can include an upper portion, a first edge portion, and a second edge portion. The upper portion of the encapsulant can be between the first spacer and the second spacer. The first edge portion and the second edge portion of the encapsulant overlap the semiconductor chip in the second horizontal direction and are spaced apart from each other in the second horizontal direction, the semiconductor chip being between the first edge portion and the second edge portion of the encapsulant. An upper surface of the first spacer can be coplanar with an upper surface of the upper portion of the encapsulant. A cross-sectional area of the upper portion of the encapsulant can be substantially equal to a sum of a cross-sectional area of the first edge portion of the encapsulant and a cross-sectional area of the second edge portion of the encapsulant.

[0005] According to example embodiments, a semiconductor package can include a semiconductor chip on a substrate, a plurality of spacers on the semiconductor chip, extending along a first horizontal direction and spaced apart from each other in a second horizontal direction, wherein the second horizontal direction intersects the first horizontal direction, and an encapsulant at least partially covering the substrate, the semiconductor chip, and the plurality of spacers. The encapsulant can include at least one upper portion, a first edge portion, and a second edge portion. The at least one upper portion of the encapsulant can be between the plurality of spacers. The first edge portion and the second edge portion of the encapsulant overlap the semiconductor chip in the second horizontal direction and can be spaced apart from each other in the second horizontal direction, the semiconductor chip being between the first edge portion and the second edge portion of the encapsulant. Upper surfaces of the plurality of spacers can be coplanar with an upper surface of the at least one upper portion of the encapsulant. A cross-sectional area of the at least one upper portion of the encapsulant can be substantially equal to a sum of a cross-sectional area of the first edge portion of the encapsulant and a cross-sectional area of the second edge portion of the encapsulant.

[0006] According to an example embodiment, a semiconductor package can include a substrate including an upper pad and an upper protective layer, wherein the upper pad is exposed by the upper protective layer; a semiconductor chip on the substrate; a bump structure between the substrate and the semiconductor chip and electrically connected to the upper pad; a first spacer on the semiconductor chip and extending in a first horizontal direction; a second spacer on the semiconductor chip, extending in the first horizontal direction, and spaced apart from the first spacer in a second horizontal direction, wherein the second horizontal direction intersects the first horizontal direction; a first adhesive layer between the semiconductor chip and the first spacer; a second adhesive layer between the semiconductor chip and the second spacer; and an encapsulant at least partially covering the substrate, the semiconductor chip, the bump structure, the first spacer, and the second spacer. The encapsulant can include an upper portion, a first edge portion, and a second edge portion. The upper portion of the encapsulant can be between the first spacer and the second spacer. The first edge portion and the second edge portion of the encapsulant overlap the upper protective layer in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction, and can be spaced apart from each other in the second horizontal direction with the semiconductor chip between the first edge portion and the second edge portion of the encapsulant. An upper surface of the first spacer can be coplanar with an upper surface of the upper portion of the encapsulant. A cross-sectional area of the upper portion of the encapsulant can be substantially equal to a sum of a cross-sectional area of the first edge portion of the encapsulant and a cross-sectional area of the second edge portion of the encapsulant. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other aspects, features, and advantages of the present inventive concepts will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a partial top view of a semiconductor package according to an example embodiment; Figure 2A is a vertical cross-sectional view along line I-I' of the semiconductor package shown in Figure 1 Figure 2B shows a magnified view of regions R1 and R2 of the semiconductor package shown in Figure 2A Figures 3-7 is a partial top view of a semiconductor package according to an example embodiment; Figure 8 ​​is a partial top view of a semiconductor package according to an example embodiment; Figure 9 is a vertical cross-sectional view taken along line II-II' of the semiconductor package shown in Figure 8 Figure 10 is a partial top view of a semiconductor package according to an example embodiment; Figure 11 is a partial top view of a semiconductor package according to an example embodiment; Figure 12 is a vertical cross-sectional view taken along line III-III' of the semiconductor package shown in Figure 11 Figure 13 is a partial top view of a semiconductor package according to an example embodiment; Figure 14 is a partial top view of a semiconductor package according to an example embodiment; Figure 15A is a vertical cross-sectional view taken along line IV-IV' of the semiconductor package shown in Figure 14 Figure 15B is a magnified view of portion R3 of the semiconductor package shown in Figure 15A Figure 16 is a partial top view of a semiconductor package according to an example embodiment; Figure 17 is a partial top view of a semiconductor package according to an example embodiment; Figure 18 is a vertical cross-sectional view taken along line V-V' of the semiconductor package shown in Figure 17 Figure 19 is a partial top view of a semiconductor package according to an example embodiment; Figures 20-22 is a diagram of a molding process according to an example embodiment; Figure 23 is a plan view of a molding process according to a comparative example; Figure 24 and Figure 25 is a diagram of a molding process according to an example embodiment. DETAILED DESCRIPTION

[0008] The above and other aspects and features of semiconductor packages according to example embodiments and methods of manufacturing the same will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrated by way of example in which:

[0009] ​​​​​It will be understood that although the terms “first,” “second,” and / or “third” may be used herein to describe various materials, layers, areas, pads, electrodes, patterns, structures, and / or processes, these various materials, layers, areas, pads, electrodes, patterns, structures, and / or processes should not be limited by these terms. These terms are used only to distinguish one material, layer, area, pad, electrode, pattern, structure, or process from another. Therefore, “first,” “second,” and / or “third” may be used selectively or interchangeably in describing each material, layer, area, electrode, pad, pattern, structure, or process.

[0010] When the terms “comprising,” “including,” “containing,” and / or “having” are used herein, they indicate the presence of the stated element but do not exclude the presence of additional elements. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0011] The term “connection” may be used in this document to refer to physical and / or electrical connections.

[0012] A first element described as being "on" a second element may be directly disposed on the second element (e.g., in contact with the second element) or indirectly disposed on the second element (e.g., an intermediate element is located between the first and second elements). When a component or layer is referred to herein as being "directly" on another component or layer, or "directly in contact with" another component or layer, or "directly connected to" another component or layer, there is no intermediate component or layer.

[0013] The terms “around”, “cover”, or “fill” as may be used herein may not require complete surrounding, covering, or filling of the described element or layer, but may, for example, refer to partial surrounding, covering, or filling of the described element or layer, such as having one or more discontinuous portions.

[0014] The first element that “covers” the second element may or may not be in contact with the second element.

[0015] When viewed along a line extending in a particular direction or in a plane perpendicular to that direction, components or layers described as “overlapping” in that particular direction at least partially obscure each other. As used herein, “element A overlaps element B in direction C” (or similar language) means that at least one line extending in direction C intersects both element A and element B. For example, element B may be a layer stacked or superimposed on top of element A (i.e., on top of element A), in which case element B can be described as overlapping element A in the vertical direction. However, it will be appreciated that direction C is not limited to the vertical direction and can be, for example, the horizontal direction or any direction between vertical and horizontal.

[0016] The term "exposed" can be used to describe the relationship between components and / or specific intermediate processes during the fabrication of a complete semiconductor device, but it is not necessarily required to expose a specific region, layer, structure, or other component in the context of a complete device. "Component A is exposed by component B" means that at least a portion of component A is not covered by component B. However, such exposed portions of component A may be covered by a third component.

[0017] For illustrative purposes, specific dimensions of components are described herein as the “width” and “length” of the component. Unless otherwise stated, the use of these terms does not imply that the width of a component is necessarily less than its length.

[0018] Figure 1 This is a partial plan view of a semiconductor package 100 according to an example embodiment. Figure 2A It is along Figure 1 The diagram shows a vertical cross-sectional view of the semiconductor package 100 taken along line I-I'. Figure 2B As shown Figure 2A Enlarged view of regions R1 and R2 of the semiconductor package 100 shown.

[0019] refer to Figure 1 and Figure 2A The semiconductor package 100 defines the X-axis, Y-axis, and Z-axis as shown in the figure. The X-axis, Y-axis, and Z-axis are all perpendicular to each other. The Y-axis can be referred to as the first horizontal axis, the X-axis can be referred to as the second horizontal axis, and the Z-axis can be referred to as the vertical axis.

[0020] refer to Figures 1-2B The semiconductor package 100 according to the example embodiment may include a substrate 110, a semiconductor chip 120, a first spacer 130, a second spacer 132, an encapsulant 140, and an external connection terminal 150. Figure 1 This is a partial view; for illustrative purposes, encapsulation 140 is not shown. Figure 1 As shown in the image.

[0021] Substrate 110 may include an insulating layer 111, an interconnect layer 112, a via 113, a protective layer 114, an upper pad 115, a lower pad 116, a via 117, an upper protective layer 118, and a lower protective layer 119. In an example embodiment, substrate 110 may be a substrate for a semiconductor package, such as a printed circuit board (PCB), an interposer substrate, a ceramic substrate, or a strip interconnect. In an example embodiment, substrate 110 may be a printed circuit board. For example, the insulating layer 111 of substrate 110 may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a photosensitive insulating layer, and more specifically, may include materials such as prepreg, Ajinomoto deposited film (ABF), FR-4, Bismalleimide Triazine (BT), and photoimageable dielectric (PID). The insulating layer 111 may be formed using, for example, a copper-clad laminate (CCL), an unclad copper-clad laminate (UCCL), a glass substrate, or a ceramic substrate. According to some example embodiments, substrate 110 may not include insulating layer 111.

[0022] Interconnect layers 112 may be disposed on the lower and upper surfaces of insulating layer 111. Passages 113 may extend vertically through insulating layer 111. Interconnect layers 112 may be electrically connected to each other via passages 113. Interconnect layers 112 may include metallic materials, including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The lower interconnect layer 112 may include, for example, ground patterns, power patterns, and signal patterns. Signal (S) patterns may provide paths for transmitting / receiving various signals (e.g., data signals, etc.).

[0023] The path 113 is electrically connected to the interconnect layer 112 and may include signal paths, ground paths, and power paths. The path 113 may contain a metallic material, including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The path 113 may be in the form of a filled path where the interior of a via is filled with metallic material, or in the form of a conformal path where metallic material forms along the inner wall of the via. The path 113 may be integrated with the interconnect layer 112, but the example embodiments are not limited thereto.

[0024] The protective layer 114 can be disposed on the lower and upper surfaces of the insulating layer 111 and can cover the interconnect layer 112. The upper pad 115 and the lower pad 116 can be disposed on the upper and lower surfaces of the substrate 110, respectively. The upper pad 115 and the lower pad 116 can be disposed on the protective layer 114. The upper pad 115 and the lower pad 116 can be electrically connected to the corresponding interconnect layer 112 via a path 117. The upper pad 115, the lower pad 116, and the path 117 can contain a metallic material, including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0025] An upper protective layer 118 and a lower protective layer 119 may be disposed on the upper and lower surfaces of the substrate 110, respectively, and may cover the protective layer 114. The upper protective layer 118 may partially cover the protective layer 114. For example, the upper protective layer 118 may not cover the upper pad 115, and the upper pad 115 may be exposed by the upper protective layer 118. In an example embodiment, the side surface of the upper pad 115 may be covered by the upper protective layer 118. The lower protective layer 119 may cover the side surface of the lower pad 116, and the lower surface of the lower pad 116 may be exposed by the lower protective layer 119.

[0026] Protective layer 114, upper protective layer 118, and lower protective layer 119 may include insulating resin and inorganic fillers. For example, protective layer 114, upper protective layer 118, and lower protective layer 119 may include ABF, but are not limited thereto. Protective layer 114, upper protective layer 118, and lower protective layer 119 may include photoimageable dielectric (PID) materials or insulating polymers, such as photosensitive polyimide (PSPI).

[0027] The semiconductor package 100 may further include a bump structure 122 disposed between the substrate 110 and the semiconductor chip 120. The semiconductor chip 120 may be placed on the substrate 110 and electrically connected to the substrate 110 via the bump structure 122. For example, the semiconductor chip 120 may include chip pads 121 connected to the bump structure 122. The chip pads 121 may be disposed on the lower surface of the semiconductor chip 120 and may contact the corresponding bump structure 122. For example, the bump structure 122 may have a flip-chip connection structure having solder balls, conductive bumps, or a grid array such as a pin grid array, ball grid array, or land grid array.

[0028] The bump structure 122 may include a first portion 122a that contacts the chip pad 121 and a second portion 122b that connects the first portion 122a and the upper pad 115. For example, the first portion 122a may be a metal pillar portion, and the second portion 122b may be a solder portion containing a low-melting-point metal, but the inventive concept is not limited thereto. According to some example embodiments, the bump structure 122 may include only the second portion 122b. The low-melting-point metal may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or alloys thereof (e.g., Sn-Ag-Cu).

[0029] Semiconductor chip 120 may be a logic chip or a memory chip. Logic chips may include microprocessors, analog elements, or digital signal processors. Memory chips may include volatile memory chips such as dynamic random access memory (DRAM) or static random access memory (SRAM), or non-volatile memory chips such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM).

[0030] In an example embodiment, at least one spacer 130 or 132 may be disposed on the semiconductor chip 120. In an example embodiment, a first spacer 130 and a second spacer 132 may be disposed on the semiconductor chip 120. The first spacer 130 and the second spacer 132 may extend along the Y direction DY (which may be referred to herein as the first horizontal direction) and may be spaced apart from each other in the X direction DX (which may be referred to herein as the second horizontal direction). The Y direction DY and the X direction DX are perpendicular to the Z direction DZ (which may be referred to herein as the vertical direction). The Y direction DY is parallel to the Y-axis. The X direction DX is parallel to the X-axis. The Z direction DZ is parallel to the Z-axis. At least one side surface of the semiconductor chip 120 may be coplanar with the first spacer 130 and the second spacer 132. For example, the side surface of the semiconductor chip 120 perpendicular to the X direction DX may be coplanar with the first spacer 130 and the second spacer 132, respectively. The side surface of the semiconductor chip 120 perpendicular to the Y direction DY may be coplanar with the first spacer 130 and the second spacer 132, respectively. The length W2 of the first spacer 130 and the second spacer 132 in the Y direction DY ( Figure 1 The length of the first spacer 130 can be substantially equal to the length of the semiconductor chip 120 in the Y direction DY. The first spacer 130 and the second spacer 132 can have the same dimensions.

[0031] In an example embodiment, the semiconductor package 100 may further include a first adhesive layer 131 disposed between the semiconductor chip 120 and the first spacer 130, and a second adhesive layer 133 disposed between the semiconductor chip 120 and the second spacer 132. Figure 2A and Figure 2B The first adhesive layer 131 and the second adhesive layer 133 can respectively attach the first spacer 130 and the second spacer 132 to the semiconductor chip 120. The first adhesive layer 131 and the second adhesive layer 133 can be a die attachment film (DAF). In some embodiments, the first adhesive layer 131 and the second adhesive layer 133 can be omitted, and the first spacer 130 and the second spacer 132 can be in direct contact with the upper surface of the semiconductor chip 120.

[0032] Encapsulation 140 may cover substrate 110, semiconductor chip 120, first spacer 130, and second spacer 132. For example, encapsulation 140 may cover the upper surface of substrate 110, and semiconductor chip 120 may be buried within encapsulation 140 without being exposed. Side surfaces of first spacer 130 and second spacer 132 may be covered by encapsulation 140. The upper surfaces of first spacer 130 and second spacer 132 may not be covered by encapsulation 140 and may be exposed. For example, the upper surfaces of first spacer 130 and second spacer 132 may be coplanar with the upper surface of encapsulation 140.

[0033] Encapsulation 140 may include an upper portion 141, edge portions 142A and 142B, a first lower portion 143, and a second lower portion 144.

[0034] In some embodiments, the encapsulation 140 is a single integrated element. In some embodiments, the encapsulation 140 covers... Figure 1 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 1 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0035] The upper portion 141 of the encapsulant 140 is disposed on the semiconductor chip 120 and at least partially overlaps with the semiconductor chip 120 in the vertical direction DZ (Z direction). Edge portions 142A and 142B of the encapsulant 140 are disposed on corresponding side surfaces 124 of the semiconductor chip 120. Figure 2B On the edge, and at least a portion of each edge portion 142A, 142B overlaps with the semiconductor chip 120 in the X direction DX, such as Figure 2A and Figure 2B As shown. For example, inFigures 1-2B In this embodiment, the upper portion 141 is disposed between the first spacer 130 and the second spacer 132, and is disposed on the semiconductor chip 120. The upper portion 141 can contact the inner surfaces 136 of the first spacer 130 and the second spacer 132, and the upper surface 145 of the upper portion 141 can be coplanar with the upper surfaces 137 of the first spacer 130 and the second spacer 132. The upper portion 141 can contact the upper surface 125 of the semiconductor chip 120. Figure 2B ).

[0036] Edge portions 142A and 142B are disposed on the upper protective layer 118 of the substrate 110 and may be disposed on both sides of the semiconductor chip 120. For example, edge portions 142A and 142B may be spaced apart from each other in the X direction DX, with the semiconductor chip 120 situated between them. Each edge portion 142A and 142B may contact the side surface 124 of the semiconductor chip 120 and may contact the corresponding outer surface 138 of the first spacer 130 or the second spacer 132. The upper surfaces of edge portions 142A and 142B may be coplanar with the upper surfaces 137 of the first spacer 130 and the second spacer 132. The upper portion 141 and edge portions 142A and 142B may extend along the first spacer 130 and the second spacer 132 in the Y direction DY.

[0037] The first lower portion 143 of the encapsulant 140 is disposed between the upper protective layer 118 of the substrate 110 and the semiconductor chip 120. The lower surface of the first lower portion 143 may be coplanar with the lower surfaces of the edge portions 142A and 142B.

[0038] A second lower portion 144 of the encapsulant 140 is disposed between the substrate 110 and the semiconductor chip 120, and covers the bump structure 122. The second lower portion 144 may be disposed at a position corresponding to the center of the semiconductor chip 120, and the lower surface of the second lower portion 144 may be disposed at a height lower than the lower surface of the edge portions 142A, 142B and the first lower portion 143. The second lower portion 144 may contact the side surface of the upper protective layer 118 and the upper surface of the protective layer 114.

[0039] Encapsulant 140 may be an epoxy-containing resin or polyimide. For example, the resin may include bisphenol epoxy resin, polycyclic aromatic epoxy resin, o-cresol phenolic epoxy resin, biphenyl epoxy resin, or naphthyl epoxy resin.

[0040] In an example embodiment, the first spacer 130 and the second spacer 132 may comprise materials with higher thermal conductivity than the encapsulation 140. For example, the first spacer 130 and the second spacer 132 may comprise silicon. The first spacer 130 and the second spacer 132 comprise materials with relatively high thermal conductivity, and because the upper surfaces are exposed by the encapsulation 140, heat generated from the semiconductor chip 120 can be effectively dissipated to the outside.

[0041] In the example embodiment, the width W1 of the first spacer 130 and the second spacer 132 in the X direction DX is ( Figure 1 Each of them can satisfy the following equation 1.

[0042] Equation 1:

[0043] In this case, a is the width of the semiconductor chip 120 in the X direction DX, b is the width of the substrate 110 in the X direction DX, and c ( Figure 2B ) is the thickness of the upper portion 141 of the encapsulation 140 (in the vertical direction DZ), and d ( Figure 2B ) is the thickness of each edge portion 142A, 142B (in the vertical direction DZ) of the encapsulation 140.

[0044] According to Equation 1, the cross-sectional area of ​​the upper portion 141 (in the XZ plane) of the encapsulation 140 can be substantially equal to the sum of the cross-sectional areas of the edge portions 142A and 142B (in the XZ plane) of the encapsulation 140. For example, the first edge portion 142A and the second edge portion 142B can be spaced apart from each other in the X direction DX with the semiconductor chip 120 between them, and the sum of the cross-sectional areas of the first edge portion 142A and the second edge portion 142B can be equal to the cross-sectional area of ​​the upper portion 141 of the encapsulation 140. In this case, the cross-sectional area can refer to the area of ​​the surface perpendicular to the Y direction DY when viewed from the XZ plane.

[0045] External connection terminals 150 may be disposed on the lower surface of substrate 110. External connection terminals 150 may contact lower pads 116 disposed on the lower surface of substrate 110. Ground voltage (Vss) or power supply voltage (Vdd) may be applied to the lower pads 116. External connection terminals 150 may be electrically connected to external devices such as motherboards. External connection terminals 150 may include conductive material and may be spherical, pin-shaped, or lead-shaped. For example, external connection terminals 150 may be solder balls.

[0046] The semiconductor package 100 may further include a passive element 160 disposed beneath the substrate 110 and a connection terminal 162. The passive element 160 may be electrically connected to a corresponding lower pad 116 via the connection terminal 162. The passive element 160 may include, for example, capacitors, inductors, beads, etc., such as multilayer ceramic capacitors (MLCCs) or low-inductance chip capacitors (LICCs). In an example embodiment, the passive element 160 may be a ground-side capacitor (LSC). However, the inventive concept is not limited thereto, and according to some example embodiments, the passive element 160 may be a die-side capacitor (DSC) mounted on the upper surface of the substrate 110, or it may be an embedded capacitor built into the interior of the substrate 110.

[0047] In addition to those discussed below, Figures 3-19 The semiconductor package may have a structure substantially the same as that of semiconductor package 100. Therefore, repeated descriptions of identical or similar elements and relationships are omitted below. Figures 3-8 , Figure 10 , Figure 11 , Figure 13 , Figure 14 , Figure 16 , Figure 17 and Figure 19 All are partial views, and the encapsulation 140 is not shown in these figures for ease of explanation. The arrangement of the encapsulation 140 (including the corresponding upper portion 141 of the encapsulation and the first edge portion 142A and the second edge portion 142B) in each of the semiconductor packages 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i, 100j, 100k, 100l, and 100m will be understood based on the discussion and figures herein.

[0048] Figures 3-7 This is a partial plan view of a semiconductor package according to an example embodiment.

[0049] refer to Figure 3 The semiconductor package 100a may include a first spacer 130a and a second spacer 132a disposed on the semiconductor chip 120. In an example embodiment, the horizontal width of the first spacer 130a and the second spacer 132a in the X direction DX may vary in the Y direction DY. For example, the horizontal width of the first spacer 130a and the second spacer 132a in the X direction may gradually decrease or gradually increase in the Y direction, respectively. The distance between the first spacer 130a and the second spacer 132a in the X direction may be constant. (Reference) Figure 2AThe upper portion 141 of the encapsulation 140 described may extend in the Y direction between the first spacer 130a and the second spacer 132a. The horizontal width of the upper portion 141 of the encapsulation 140 in the X direction may be constant. In some embodiments, the encapsulation 140 of the semiconductor package 100a (in...) Figure 3 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 3 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 3 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0050] refer to Figure 4 The semiconductor package 100b may include a first spacer 130b and a second spacer 132b disposed on the semiconductor chip 120. In an example embodiment, the horizontal width of the first spacer 130b and the second spacer 132b in the X direction may vary in the Y direction. For example, the horizontal width of the first spacer 130b and the second spacer 132b in the X direction may gradually decrease and then increase in the Y direction, or vice versa. (See reference...) Figure 2A The upper portion 141 of the described encapsulation 140 may have a constant horizontal width in the X direction. In some embodiments, the encapsulation 140 of the semiconductor package 100b (in...) Figure 4 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 4 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 4 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0051] refer to Figure 5 The semiconductor package 100c may include a first spacer 130c and a second spacer 132c disposed on the semiconductor chip 120. In an example embodiment, the horizontal width of the first spacer 130c and the second spacer 132c in the X direction DX may vary in the Y direction DY. For example, in a top view, the first spacer 130c and the second spacer 132c may include recessed portions, and the facing side surfaces of the first spacer 130c and the second spacer 132c may have recessed curved surfaces. In some embodiments, the encapsulation 140 of the semiconductor package 100c (in...) Figure 5 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 5The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 5 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0052] refer to Figure 6 The semiconductor package 100d may include a first spacer 130d and a second spacer 132d disposed on the semiconductor chip 120. In an example embodiment, the horizontal width of the first spacer 130d and the second spacer 132d in the X direction DX may vary in the Y direction DY. For example, in a top view, the first spacer 130d and the second spacer 132d may include two or more recessed portions.

[0053] Even in Figure 5 In the embodiments, the width W1 of the first spacer 130c and the second spacer 132c in the X direction DX also satisfies Equation 1, and even when Figure 6 In some embodiments, the width W1 of the first spacer 130d and the second spacer 132d in the X direction also satisfies Equation 1. In some embodiments, the encapsulation 140 of the semiconductor package 100d (in...) Figure 6 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 6 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 6 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0054] refer to Figure 7 The semiconductor package 100e may include a first spacer 130e and a second spacer 132e disposed on the semiconductor chip 120. In an example embodiment, the first spacer 130e and the second spacer 132e may extend along the Y direction DY, and the length W2 of the first spacer 130e and the second spacer 132e in the Y direction may be greater than the length of the semiconductor chip 120 in the Y direction. For example, the length W2 may be substantially equal to the length of the substrate 110 in the Y direction. The side surfaces 139 of the first spacer 130e and the second spacer 132e perpendicular to the Y direction may be coplanar with the side surfaces of the substrate 110 and may be exposed without being covered by the encapsulant 140. Because not only the upper surfaces of the first spacer 130e and the second spacer 132e but also the side surfaces are exposed by the encapsulant 140, the heat generated in the semiconductor chip 120 can be effectively dissipated to the outside. In some embodiments, the encapsulant 140 of the semiconductor package 100e (inFigure 7 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 7 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 7 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0055] Figure 8 This is a partial plan view of a semiconductor package according to an example embodiment. Figure 9 It is along Figure 8 The diagram shows a vertical cross-sectional view of the semiconductor package taken along line II-II'.

[0056] refer to Figure 8 and Figure 9 The semiconductor package 100f may include a first spacer 130f, a second spacer 132f, and a third spacer 134f disposed on the semiconductor chip 120. The first spacer 130f and the second spacer 132f may be coplanar with the side surface of the semiconductor chip 120 perpendicular to the X-direction DX. The third spacer 134f may be disposed between the first spacer 130f and the second spacer 132f. The first spacer 130f, the second spacer 132f, and the third spacer 134f may have the same dimensions. The semiconductor package 100f may also include a third adhesive layer 135 disposed between the third spacer 134f and the semiconductor chip 120.

[0057] The encapsulation 140 may include an upper portion 141f disposed on the semiconductor chip 120. The upper portion 141f may be disposed between a first spacer 130f and a third spacer 134f, and between a second spacer 132f and a third spacer 134f, respectively. In some embodiments, the encapsulation 140 of the semiconductor package 100f ( Figure 8 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 8 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 8 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0058] In the example embodiment, the width W1 of the first spacer 130f, the second spacer 132f, and the third spacer 134f in the X direction DX is ( Figure 8 All of them can satisfy the following equation 2.

[0059] Equation 2:

[0060] In this case, a is the width of the semiconductor chip 120 in the X direction DX, b is the width of the substrate 110 in the X direction DX, c is the thickness of the upper portion 141f of the encapsulation 140 (in the vertical direction DZ), and d is the thickness of the edge portions 142A and 142B of the encapsulation 140 (in the vertical direction DZ).

[0061] According to Equation 2, the cross-sectional area (in the XZ plane) of each upper portion 141f of the encapsulation 140 can be substantially equal to the sum of the cross-sectional areas (in the XZ plane) of the edge portions 142A and 142B of the encapsulation 140. For example, the first edge portion 142A and the second edge portion 142B can be spaced apart from each other in the X direction DX with the semiconductor chip 120 between them, and the sum of the cross-sectional areas (in the XZ plane) of the first edge portion 142A and the second edge portion 142B can be equal to the cross-sectional area (in the XZ plane) of each upper portion 141f of the encapsulation 140. The upper portions 141f can have the same dimensions.

[0062] refer to Figure 10 The semiconductor package 100g may include a first spacer 130g, a second spacer 132g, and a third spacer 134g disposed on the semiconductor chip 120. In an example embodiment, the first spacer 130g, the second spacer 132g, and the third spacer 134g may extend along the Y direction DY, and the length W2 of the first spacer 130g, the second spacer 132g, and the third spacer 134g in the Y direction may be greater than the length of the semiconductor chip 120 in the Y direction. For example, the length W2 may be substantially equal to the length of the substrate 110 in the Y direction. The side surfaces 139 of the first spacer 130g, the second spacer 132g, and the third spacer 134g perpendicular to the Y direction may be coplanar with the corresponding adjacent side surfaces of the substrate 110 and may be exposed without being covered by the encapsulation 140. In some embodiments, the encapsulation 140 of the semiconductor package 100g (in Figure 10 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 10 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 10 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0063] Figure 11 This is a partial plan view of a semiconductor package according to an example embodiment. Figure 12It is along Figure 11 The diagram shows a vertical cross-sectional view of the semiconductor package taken from line III-III'.

[0064] refer to Figure 11 and Figure 12 The semiconductor package 100h may include a first spacer 130 and a second spacer 132 disposed on the semiconductor chip 120, and a first lower spacer 130h and a second lower spacer 132h disposed on the substrate 110. The first lower spacer 130h and the second lower spacer 132h may extend along the substrate 110 in the Y direction DY. The first lower spacer 130h and the second lower spacer 132h may be spaced apart from each other in the X direction DX, with the semiconductor chip 120 positioned between them. In an example embodiment, the length of the first lower spacer 130h and the second lower spacer 132h in the Y direction DY may be greater than the length of the semiconductor chip 120 in the Y direction DY. For example, this length may be equal to the length of the substrate 110 in the Y direction DY. In an example embodiment, the semiconductor package 100h may further include a first lower adhesive layer 131h disposed between the substrate 110 and the first lower spacer 130h, and a second lower adhesive layer 133h disposed between the substrate 110 and the second lower spacer 132h. The cross-sectional area of ​​each edge portion 142A, 142B of the encapsulation 140 can reduce the area of ​​the first lower spacer 130h and the lower adhesive layer 131h. In some embodiments, the encapsulation 140 of the semiconductor package 100h (in Figure 11 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 11 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 11 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0065] refer to Figure 13 The semiconductor package 100i may include a first spacer 130, a second spacer 132, and a first lower spacer 130i and a second lower spacer 132i disposed on the semiconductor chip 120. In an example embodiment, the first lower spacer 130i may be arranged to be spaced apart from each other in the Y direction DY, and the second lower spacer 132i may be arranged to be spaced apart from each other in the Y direction. In some embodiments, the encapsulation 140 of the semiconductor package 100i (in...) Figure 13 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 13The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 13 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0066] Figure 14 This is a partial plan view of a semiconductor package according to an example embodiment. Figure 15A It is along Figure 14 The diagram shows a vertical cross-sectional view of line IV-IV' of the semiconductor package. Figure 15B yes Figure 15A An enlarged view of a portion of the semiconductor package shown.

[0067] refer to Figures 14-15B The semiconductor package 100j may include spacers 130j disposed on the semiconductor chip 120. In an example embodiment, the spacers 130j are not aligned with the side surface of the semiconductor chip 120 perpendicular to the X direction DX and may be offset. For example, the side surface 138 of the spacers 130j may not be coplanar with the corresponding side surface of the semiconductor chip 120 perpendicular to the X direction DX.

[0068] The encapsulation 140 may include an upper portion 141j, an edge portion 142j, a first lower portion 143, and a second lower portion 144. The upper portion 141j of the encapsulation 140 is disposed on the semiconductor chip 120 and at least partially overlaps with the semiconductor chip 120 in the vertical direction (Z direction DZ). The edge portion 142j of the encapsulation 140 is disposed on the side surface 124 of the semiconductor chip 120 and at least partially overlaps with the semiconductor chip 120 in the X direction DX. For example, in Figures 14-15B In one embodiment, the upper portion 141j overlaps with the spacer 130j in the X direction DX and can be disposed on the semiconductor chip 120. The upper portion 141j can contact the side surface 138 of the spacer 130j, and the upper surface 145 of the upper portion 141j can be coplanar with the upper surface 137 of the spacer 130j.

[0069] Edge portions 142j are disposed on the upper protective layer 118 of the substrate 110 and may be disposed on both sides of the semiconductor chip 120. For example, edge portions 142j may be spaced apart from each other in the X direction DX, with the semiconductor chip 120 between them. Edge portions 142j may contact the side surface 124 of the semiconductor chip 120 and may be spaced apart from the spacer 130j. The upper surface 147 of the edge portion 142j ( Figure 15BThe edge portion 142j can contact the lower surface of the upper portion 141j, and the side surface 147B of the edge portion 142j can be coplanar with the side surface 147C of the upper portion 141j. In some embodiments, the encapsulation 140 of the semiconductor package 100j (in...) Figure 14 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 14 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 14 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0070] In the example embodiment, the width W1 of the spacer 130j in the X direction DX is ( Figure 15A It can satisfy the following equation 3.

[0071] Equation 3:

[0072] In this case, a is the width of the semiconductor chip 120 in the X direction DX, b is the width of the substrate 110 in the X direction DX, c is the thickness of the upper portion 141j of the encapsulation 140 (in the vertical direction DZ), and d' is the height (in the vertical direction DZ) from the upper surface of the upper protective layer 118 of the substrate 110 to the upper surface of the upper portion 141j of the encapsulation 140. d' is also equal to the sum of the thicknesses (in the vertical direction DZ) of the upper portion 141j and the edge portion 142j.

[0073] According to Equation 3, the cross-sectional area (in the XZ plane) of each upper portion 141j of the encapsulation 140 can be substantially equal to the cross-sectional area (in the XZ plane) of each edge portion 142j of the encapsulation 140. For example, the first upper portion 141j and the second upper portion 141j can be spaced apart from each other in the X direction DX, and the first edge portion 142j and the second edge portion 142j can be spaced apart from each other in the X direction DX. The first edge portion 142j and the second edge portion 142j can each have the same cross-sectional area (in the XZ plane) as the first upper portion 141j and the second upper portion 141j. In this case, the cross-sectional area can refer to the area of ​​the surface perpendicular to the Y direction when viewed from the XZ plane.

[0074] refer to Figure 16The semiconductor package 100k may include spacers 130k disposed on the semiconductor chip 120. In an example embodiment, the spacers 130k may extend along the Y direction DY, and the length W2 of the spacers 130k in the Y direction may be greater than the length of the semiconductor chip 120 in the Y direction. For example, the length W2 may be substantially equal to the length of the substrate 110 in the Y direction. The side surface of the spacers 130k perpendicular to the Y direction may be coplanar with the side surface of the substrate 110 and may be exposed and not covered by the encapsulation 140. In some embodiments, the encapsulation 140 of the semiconductor package 100k (in Figure 16 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 16 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 16 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0075] Figure 17 This is a partial plan view of a semiconductor package according to an example embodiment. Figure 18 It is along Figure 17 The diagram shows a vertical cross-sectional view of the semiconductor package along line V-V'.

[0076] refer to Figure 17 and Figure 18 The semiconductor package 100l may include a first spacer 130l and a second spacer 132l disposed on the semiconductor chip 120. In an example embodiment, the first spacer 130l and the second spacer 132l are not aligned with the side surface of the semiconductor chip 120 perpendicular to the X direction DX, and may be arranged with an offset.

[0077] The encapsulation 140 may include a first upper portion 141l_1, a second upper portion 141l_2, an edge portion 142l, a first lower portion 143, and a second lower portion 144. The edge portion 142l is disposed on the upper protective layer 118 of the substrate 110 and may be disposed on both sides of the semiconductor chip 120. Figure 17 and Figure 18In some embodiments, the first upper portion 141_l may overlap with the spacer 130 and perpendicularly overlap with the edge portion 142l in the X direction DX, and may be disposed on the semiconductor chip 120. The second upper portion 141l_2 may be disposed between the first spacer 130l and the second spacer 132l in the X direction DX. The upper surfaces of the first upper portion 141l_1 and the second upper portion 141l_2 may be coplanar with the upper surfaces of the first spacer 130l and the second spacer 132l. In some embodiments, the encapsulation 140 of the semiconductor package 100l (in Figure 17 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 17 The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 17 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0078] In the example embodiment, the cross-sectional area (in the XZ plane) of the first upper portion 141l_1 can be substantially equal to the cross-sectional area (in the XZ plane) of the edge portion 142l. Furthermore, the cross-sectional area (in the XZ plane) of the first upper portion 141l_1 can be twice the cross-sectional area (in the XZ plane) of the second upper portion 141l_2. For example, the width of the first upper portion 141l_1 in the X direction DX can be twice the width of the second upper portion 141l_2 in the X direction DX.

[0079] refer to Figure 19 The semiconductor package 100m may include a first spacer 130m and a second spacer 132m disposed on the semiconductor chip 120. In an example embodiment, the first spacer 130m and the second spacer 132m are not aligned with the side surface of the semiconductor chip 120 perpendicular to the X direction DX and may be arranged offset. In an example embodiment, the first spacer 130m and the second spacer 132m may extend along the Y direction DY, and the length W2 of the first spacer 130m and the second spacer 132m in the Y direction may be greater than the length of the semiconductor chip 120 in the Y direction. For example, the length W2 may be substantially equal to the length of the substrate 110 in the Y direction. The side surface 139 of the first spacer 130m and the second spacer 132m perpendicular to the Y direction may be coplanar with the side surface of the substrate 110 and may be exposed and not covered by the encapsulation 140. In some embodiments, the encapsulation 140 of the semiconductor package 100m (in Figure 19 (not shown) is a single integrated element. In some embodiments, the encapsulation 140 covers a single integrated element. Figure 19The top view shows all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 (i.e., in the vertical direction DZ, and in the top view). Figure 19 In the top view, all portions of the upper surface of the upper protective layer 118 and the upper surface of the semiconductor chip 120 overlap.

[0080] Figures 20-22 This is a diagram of the molding process according to an example embodiment. Figure 20 A vertical cross-sectional view of the mold used for molding is shown. Figure 21 This illustrates the supply of molding material onto a substrate. Figure 22 It is along Figure 21 The vertical cross-sectional view of line VI-VI' in the diagram.

[0081] refer to Figure 20 The molding die may include a lower die 10 and an upper die 20. A port 50 for supplying molding material M may be located at the center of the lower die 10. A molding space MS may be defined between the lower die 10 and the upper die 20. The molding space MS may be located on both sides of the port 50 and may extend along the Y direction DY.

[0082] The molding material M can be supplied to the molding space MS through the gate G by the reciprocating motion of the pressure head 30 located in port 50. The molding process can be performed simultaneously in the molding spaces MS located on both sides of port 50. The molding material M can correspond to the encapsulation 140 of the semiconductor package described above.

[0083] The substrate 110 can be placed in the molding space MS, and the semiconductor chip 120 and spacers 130 and 132 can be placed on the substrate 110. Spacers 130 and 132 can correspond to a reference. Figures 1-19 The spacers described. For illustrative purposes, Figures 20-22 The spacers 130 and 132 shown correspond to Figures 1-2B The spacers of the semiconductor package 100. Molding material M supplied through the gate (G) can flow in the Y direction DY and cover the substrate 110, the semiconductor chip 120 and the spacers 130 and 132.

[0084] refer to Figure 21 and Figure 22 An active region Area can be disposed on substrate 110. A semiconductor chip 120 can be disposed in the active region Area. The semiconductor chip 120 can be arranged in the X direction DX and the Y direction DY. A first spacer 130 and a second spacer 132 can be disposed on the semiconductor chip 120 respectively. The first spacer 130 and the second spacer 132 can extend along the Y direction DY.

[0085] The molding material M is disposed within the molding space MS so that it can flow in the Y direction (e.g., in the direction indicated by the arrow). Figure 21 As shown, in the example embodiment, the first spacer 130 and the second spacer 132 may extend in the direction of flow of the molding material M.

[0086] In an example embodiment, the molding process can be performed while the first spacer 130 and the second spacer 132 are in contact with the upper mold 20. In an alternative example embodiment, the molding process can be performed while the first spacer 130 and the second spacer 132 are spaced apart from the upper mold 20. When the molding material M flows continuously from the gate (G) into the molding space MS along the Y direction DY, the smaller the cross-sectional area, the higher the flow rate may be if there is no friction. However, head loss may occur due to friction, and the flow rate of the molding material M may decrease between the substrate 110 and the semiconductor chip 120. For example, with Figure 2A and Figure 2B The flow velocity in the regions corresponding to the first lower portion 143 and the second lower portion 144 of the encapsulation 140 shown may be lower than the flow velocity in the regions corresponding to the upper portion 141 and the edge portion 142. The region corresponding to the edge portion 142 is a region extending along the Y direction DY between the semiconductor chips 120, and the region corresponding to the upper portion 141 is a region that overlaps perpendicularly with the semiconductor chips 120 and extends along the Y direction DY.

[0087] Figure 23 This is a plan view showing the molding process according to the comparative example.

[0088] Further reference Figure 23 In the comparative example, the semiconductor chip 120 may be disposed on the substrate 110, and the spacers may not be disposed on the semiconductor chip 120. Figure 23 As shown, the molding material M can flow relatively quickly between the semiconductor chips 120 to first fill the areas between the semiconductor chips 120 with the molding material M. For example, with Figure 15B The flow rate of the molding material M in the region corresponding to the edge portion 142 shown can be greater than the flow rate of the molding material M in the region corresponding to the upper portion 141 (in the comparative example, with Figure 15B Unlike other encapsulations, this one does not have spacers 130j. Therefore, there is a risk of gaps appearing within the encapsulation 140.

[0089] However, as Figure 22As shown, according to the example embodiment, because the cross-sectional area of ​​the region RS extending along the Y direction between the semiconductor chips 120 and the cross-sectional area of ​​the region RU on the semiconductor chip 120 are substantially the same, the flow rate of the molding material M in the regions RS and RU can be equal or the flow rate difference can be reduced. Therefore, voids in the encapsulation 140 can be prevented or reduced.

[0090] refer to Figure 22 When the width of the semiconductor chip 120 in the X direction DX is a, the width of the semiconductor package manufactured after the molding process in the X direction DX is b, the height of region RU is c, the height of region RS is d, and the width of the first spacer 130 and the second spacer 132 in the X direction is W1; the cross-sectional area of ​​region RU (in the XZ plane) can be And the cross-sectional area of ​​region RS (in the XZ plane) can be When the cross-sectional areas of regions RS and RU are the same, the width W1 can satisfy the above equation 1.

[0091] Therefore, according to the example embodiment, since the width W1 of the first spacer 130 and the second spacer 132 in the X direction satisfies Equation 1, the flow rate difference of the molding material M in the region RS and the region RU can be reduced, and voids can be prevented in the encapsulation 140.

[0092] In an example embodiment, the area difference between region RS and region RU can be less than or equal to 10%. For example, the difference between the area of ​​region RS and the area of ​​region RU can be less than or equal to 10% of the larger of the areas of region RS and region RU. Figures 1-7 In one embodiment, the area difference between the area of ​​the upper portion 141 and the area of ​​the edge portion 142 of the encapsulation 140 may be less than or equal to 10%.

[0093] like Figures 3-6 As shown, when the widths of the first spacer 130 and the second spacer 132 in the X direction change in the Y direction, the flow of the molding material M in the region RU can be controlled. Figures 11-13 As shown, when the first lower spacers 130h and 130i and the second lower spacers 132h and 132i are disposed on the substrate 110, the flow of the molding material M in the region RS can be controlled.

[0094] Figure 24 and Figure 25 This is a diagram illustrating the molding process according to an example embodiment.

[0095] Figure 24 It is used to explain the formation Figure 9A diagram illustrating the molding process of the encapsulation 140 shown. (Refer to...) Figure 24 For example, as referenced in this article Figure 8 and Figure 9 As described, the first spacer 130f, the second spacer 132f, and the third spacer 134f can be disposed on the semiconductor chip 120.

[0096] The region RU on the semiconductor chip 120 can be disposed between the first spacer 130f and the third spacer 134f, and between the second spacer 132f and the third spacer 134f. (Similar to reference...) Figure 22 The description states that when regions RU and RS are substantially the same, the flow rate of the molding material M in regions RS and RU can be equal or the flow rate difference can be reduced.

[0097] When the width of the semiconductor chip 120 in the X direction DX is a, the width of the semiconductor package manufactured after the molding process in the X direction DX is b, the height of region RU is c, the height of region RS is d, and the width of the first spacer 130f, the second spacer 132f, and the third spacer 134f in the X direction DX is W1; the cross-sectional area of ​​region RU (in the XZ plane) can be And the cross-sectional area of ​​region RS (in the XZ plane) can be When the cross-sectional area of ​​region RU is the same, the width W1 can satisfy the above equation 2.

[0098] Summary Figure 2A and Figure 24 In an example embodiment, when n spacers are disposed on each semiconductor chip 120 (where n is an integer greater than 1), the width W1 of the spacers in the X direction, which are regularly spaced and have the same size, can satisfy the following equation 4.

[0099] Equation 4:

[0100] At this time, the two spacers can be coplanar with the side of the semiconductor chip 120 perpendicular to the X direction.

[0101] Figure 25 It is used to explain the formation Figure 15A A diagram illustrating the molding process of the encapsulation 140 shown. (Refer to...) Figure 25 For example, as referenced in this article Figures 14-15BAs described, spacers 130j can be disposed on semiconductor chip 120. Regions RU on semiconductor chip 120 can be disposed between adjacent spacers 130j and can also be disposed on semiconductor chip 120. Regions RS can be disposed below regions RU and disposed between semiconductor chips 120. Similar to the reference... Figure 22 The description states that when regions RU and RS are substantially the same, the flow rate of the molding material M in regions RS and RU can be equal or the flow rate difference can be reduced.

[0102] When the width of semiconductor chip 120 in the X direction DX is a, the width of the semiconductor package manufactured after the molding process in the X direction DX is b, the height of region RU is c, the sum of the heights of region RU and region RS is d', and the width of spacer 130j in the X direction DX is W1; the cross-sectional area of ​​region RU can be And the cross-sectional area of ​​region RS can be The width W1 of the same cross-sectional area of ​​region RU can satisfy the above equation 3.

[0103] As described above, according to the example embodiment, spacers can be disposed on a semiconductor chip. During the molding process of manufacturing a semiconductor package, molding material can flow onto the semiconductor chip to form an encapsulation. The spacers, semiconductor chips, and encapsulation together form an assembly of the semiconductor package. During manufacturing, the spacers can regulate the flow rate of molding material in the region between adjacent semiconductor chips and the flow rate of molding material in the region on the semiconductor chip. During the molding process, the cross-sectional area of ​​the region corresponding to the upper portion of the encapsulation and the cross-sectional area of ​​the region corresponding to the edge portion of the encapsulation can be substantially equal to each other. Therefore, the flow rate in the region between semiconductor chips is substantially equal to the flow rate in the region on the semiconductor chip, thereby preventing or reducing voids within the encapsulation of each semiconductor package. In addition, the upper surface of the spacers is exposed by the encapsulation, and because the spacers comprise a material with a higher thermal conductivity than the encapsulation, the spacers can effectively radiate heat generated from the semiconductor chip to the outside to dissipate heat from the semiconductor package.

[0104] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package, the semiconductor package comprising: A semiconductor chip, wherein the semiconductor chip is located on a substrate; A first spacer, the first spacer being located on the semiconductor chip and extending along a first horizontal direction; A second spacer, located on the semiconductor chip, extending along the first horizontal direction and spaced apart from the first spacer in a second horizontal direction, wherein the second horizontal direction intersects the first horizontal direction; and An encapsulation that at least partially covers the substrate, the semiconductor chip, the first spacer, and the second spacer. in: The encapsulation includes an upper portion, a first edge portion, and a second edge portion. The upper portion of the encapsulation is located between the first spacer and the second spacer. The first and second edge portions of the encapsulation overlap with the semiconductor chip in the second horizontal direction and are spaced apart from each other in the second horizontal direction, with the semiconductor chip situated between the first and second edge portions of the encapsulation. The upper surface of the first spacer is coplanar with the upper surface of the upper portion of the encapsulation, and The cross-sectional area of ​​the upper portion of the encapsulation is substantially equal to the sum of the cross-sectional areas of the first edge portion of the encapsulation and the second edge portion of the encapsulation.

2. The semiconductor package according to claim 1, wherein, Both the first spacer and the second spacer comprise materials with thermal conductivity higher than that of the encapsulation.

3. The semiconductor package according to claim 2, wherein, Both the first spacer and the second spacer comprise silicon.

4. The semiconductor package according to claim 1, wherein, The upper surfaces of the first spacer and the second spacer are exposed by the encapsulating material.

5. The semiconductor package of claim 1, further comprising a first adhesive layer between the semiconductor chip and the first spacer and a second adhesive layer between the semiconductor chip and the second spacer.

6. The semiconductor package according to claim 1, wherein, The length of the first spacer in the first horizontal direction is substantially equal to the length of the semiconductor chip in the first horizontal direction.

7. The semiconductor package according to claim 1, wherein, The upper surfaces of the first edge portion and the second edge portion of the encapsulation are coplanar with the upper surface of the first spacer.

8. The semiconductor package according to claim 1, wherein, The width of the first spacer in the second horizontal direction varies along the first horizontal direction.

9. The semiconductor package according to claim 8, wherein, The width of the upper portion of the encapsulation in the second horizontal direction is constant in the first horizontal direction.

10. The semiconductor package according to claim 1, wherein, The length of the first spacer in the first horizontal direction is greater than the length of the semiconductor chip in the first horizontal direction.

11. The semiconductor package of claim 10, wherein, The length of the first spacer in the first horizontal direction is substantially equal to the length of the substrate in the first horizontal direction.

12. The semiconductor package of claim 10, wherein, The side surface of the first spacer is exposed by the encapsulating material.

13. The semiconductor package according to claim 1, wherein, The upper portion of the encapsulation is the first upper portion of the encapsulation; The semiconductor package further includes a third spacer located between the first spacer and the second spacer. The semiconductor package further includes a second upper portion of the encapsulation. The first upper portion of the encapsulation is disposed between the first spacer and the third spacer, and the second upper portion of the encapsulation is disposed between the second spacer and the third spacer. The cross-sectional area of ​​the first upper portion of the encapsulation and the cross-sectional area of ​​the second upper portion of the encapsulation are each substantially equal to the sum of the cross-sectional areas of the first edge portion and the second edge portion.

14. The semiconductor package of claim 1, further comprising a first lower spacer and a second lower spacer located on the substrate and spaced apart from each other in the second horizontal direction, the semiconductor chip being disposed between the first lower spacer and the second lower spacer.

15. The semiconductor package of claim 1, further comprising a plurality of first lower spacers spaced apart from each other in the first horizontal direction and a plurality of second lower spacers spaced apart from each other in the first horizontal direction.

16. The semiconductor package according to claim 1, wherein, The width of the first spacer in the second horizontal direction is substantially equal to the width of the second spacer in the second horizontal direction, and The width W1 of the first spacer in the second horizontal direction satisfies Equation 1: Equation 1 ， Wherein, a is the width of the semiconductor chip in the second horizontal direction, b is the width of the substrate in the second horizontal direction, c is the thickness of the upper portion of the encapsulation in the vertical direction perpendicular to the first and second horizontal directions, and d is the thickness of the first edge portion of the encapsulation in the vertical direction.

17. A semiconductor package, the semiconductor package comprising: A semiconductor chip, wherein the semiconductor chip is located on a substrate; A plurality of spacers, the plurality of spacers being located on the semiconductor chip, extending along a first horizontal direction and spaced apart from each other in a second horizontal direction, wherein the second horizontal direction intersects the first horizontal direction; and An encapsulation that at least partially covers the substrate, the semiconductor chip, and the plurality of spacers. in: The encapsulation includes at least one upper portion, a first edge portion, and a second edge portion. The at least one upper portion of the encapsulation is located between the plurality of spacers. The first and second edge portions of the encapsulation overlap with the semiconductor chip in the second horizontal direction and are spaced apart from each other in the second horizontal direction, with the semiconductor chip situated between the first and second edge portions of the encapsulation. The upper surfaces of the plurality of spacers are coplanar with the upper surface of the at least one upper portion of the encapsulation, and The cross-sectional area of ​​each of the at least one upper portion of the encapsulation is substantially equal to the sum of the cross-sectional area of ​​the first edge portion of the encapsulation and the cross-sectional area of ​​the second edge portion of the encapsulation.

18. The semiconductor package of claim 17, wherein, The plurality of spacers have the same size and are arranged at regular intervals in the second horizontal direction. The width W1 of each of the plurality of spacers in the second horizontal direction satisfies Equation 2: Equation 2 ， Wherein, a is the width of the semiconductor chip in the second horizontal direction, b is the width of the substrate in the second horizontal direction, c is the thickness of the at least one upper portion of the encapsulation in the vertical direction perpendicular to the first and second horizontal directions, d is the thickness of the first edge portion of the encapsulation in the vertical direction, and n is an integer greater than 1.

19. The semiconductor package of claim 17, wherein, The plurality of spacers includes a first spacer and a second spacer. The first spacer and the second spacer are coplanar with the side surface of the semiconductor chip in the second horizontal direction.

20. A semiconductor package, the semiconductor package comprising: A substrate, the substrate including upper pads and an upper protective layer, wherein the upper pads are exposed by the upper protective layer; A semiconductor chip, wherein the semiconductor chip is located on the substrate; A bump structure is located between the substrate and the semiconductor chip and is electrically connected to the upper pad; A first spacer, the first spacer being located on the semiconductor chip and extending along a first horizontal direction; A second spacer is located on the semiconductor chip, extends along the first horizontal direction, and is spaced apart from the first spacer in a second horizontal direction, wherein the second horizontal direction intersects the first horizontal direction; A first adhesive layer is located between the semiconductor chip and the first spacer; A second adhesive layer, the second adhesive layer being located between the semiconductor chip and the second spacer; and An encapsulation that at least partially covers the substrate, the semiconductor chip, the bump structure, the first spacer, and the second spacer. in: The encapsulation includes an upper portion, a first edge portion, and a second edge portion. The upper portion of the encapsulation is located between the first spacer and the second spacer. The first and second edge portions of the encapsulation overlap with the upper protective layer in a vertical direction perpendicular to the first and second horizontal directions, and are spaced apart from each other in the second horizontal direction, with the semiconductor chip located between the first and second edge portions. The upper surface of the first spacer is coplanar with the upper surface of the upper portion of the encapsulation, and The cross-sectional area of ​​the upper portion of the encapsulation is substantially equal to the sum of the cross-sectional areas of the first edge portion of the encapsulation and the second edge portion of the encapsulation.

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