Power semiconductor device stack, power module and method for producing power semiconductor device stack

Abstract

A power semiconductor device stack, a power module and a method of producing a power semiconductor device stack. A stack (1) comprises: a first power semiconductor device (110) in a first chip (11), where the first power semiconductor device (110) is configured for active operation during which an applied load current is conducted by the first power semiconductor device (110) and a power loss occurs in the first power semiconductor device (110); a second power semiconductor device (120) in the second chip (12), where the second power semiconductor device (120) is configured for passive operation during which the voltage is blocked; and a heat sink interface (13) for dissipating the power loss, wherein the second chip (12) is arranged between the first chip (11) and the heat sink interface (13).

Description

Technical Field

[0001] This specification relates to embodiments of power semiconductor device stacks, embodiments of methods for manufacturing power semiconductor device stacks, and embodiments of power modules. Power semiconductor device stacks can exhibit a specific type of coupling between a first power semiconductor device and a heatsink interface. Background Technology

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving electric motors or electric motors, rely on power semiconductor devices. For example, to name just a few, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes have been used in a variety of applications, including but not limited to switches in power supplies and power converters.

[0003] A power semiconductor device includes a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is conducted via an active region of the power semiconductor device. The active region is surrounded by an edge-terminating region that terminates at the edge of the chip.

[0004] In the case of controllable power semiconductor devices (such as transistors), the load current path can be controlled by means of an insulating electrode (often referred to as the gate electrode). For example, when receiving a corresponding control signal from, for instance, the driver unit and via the device's control terminal, the control electrode can set the power semiconductor device to one of a forward conduction state or a blocking state.

[0005] A common problem associated with power semiconductor devices is the dissipation of heat during their operation, such as during switching and during the on-state. To dissipate heat, a device typically called a heat sink can be thermally coupled to the power semiconductor device.

[0006] Furthermore, more than one power semiconductor switch at different voltages can be used in the application, requiring each of these devices to be electrically isolated when coupled to the same heat sink to prevent short circuits. However, thick electrical isolators that provide the required electrical insulation may have poor thermal conductivity.

[0007] This disclosure relates to the coupling between power semiconductor devices and heat sinks. Summary of the Invention

[0008] The subject matter of the independent claim is presented. Features of the exemplary embodiments are defined in the dependent claims.

[0009] According to an embodiment, the stack includes: a first power semiconductor device in a first chip, wherein the first power semiconductor device is configured for active operation, during which an applied load current is conducted through the first power semiconductor device and a power loss occurs in the first power semiconductor device; a second power semiconductor device in a second chip, wherein the second power semiconductor device is configured for passive operation, during which a voltage is blocked; and a heat sink interface for dissipating the power loss, wherein the second chip is disposed between the first chip and the heat sink interface.

[0010] According to another embodiment, a method of manufacturing a stack includes: providing a first power semiconductor device in a first chip, wherein the first power semiconductor device is configured for active operation, during which an applied load current is conducted through the first power semiconductor device and a power loss occurs in the first power semiconductor device; providing a second power semiconductor device in a second chip, wherein the second power semiconductor device is configured for passive operation, during which a voltage is blocked; providing a heat sink interface for dissipating the power loss; and disposing the second chip between the first chip and the heat sink interface.

[0011] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. Attached Figure Description

[0012] The components in the accompanying drawings are not necessarily to scale; instead, the focus is on illustrating the principles of the invention. Furthermore, similar reference numerals designate corresponding parts in each figure. In the drawings:

[0013] Figures 1 to 5 The schematic and exemplary illustrations depict corresponding vertical cross-sections of stacked segments according to some embodiments;

[0014] Figure 6 and Figure 7 Corresponding circuit diagrams according to some embodiments are illustrated schematically and exemplaryly;

[0015] Figures 8 to 15 The schematic and exemplary illustrations depict corresponding vertical cross-sections of stacked segments according to some embodiments;

[0016] Figures 16 to 18 The illustrations schematically and exemplaryly depict corresponding modules including a stack according to some embodiments; and

[0017] Figure 19 A perspective view of a wafer stack according to one or more embodiments is illustrated schematically and exemplary. Detailed Implementation

[0018] In the following detailed description, reference is made to the accompanying drawings, which form part of the description and illustrate, by way of illustration, specific embodiments in which the invention may be practiced.

[0019] In this regard, directional terms such as “top,” “bottom,” “below,” “front,” “rear,” “backside,” “leader,” “tail,” and “above” can be used with reference to the orientation of the figures described. Because the various parts of the embodiments can be positioned in multiple different orientations, directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the invention. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0020] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation and is not intended to limit the invention. For example, features illustrated or described as one embodiment may be used in other embodiments or in combination with other embodiments to produce yet another embodiment. It is intended that the invention include such modifications and variations. The examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements or manufacturing steps have been designated by the same reference numerals in different drawings.

[0021] As used in this specification, the term "horizontal" is intended to describe an orientation that is substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This can be, for example, the surface of a semiconductor wafer, die, or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below can be horizontal directions, wherein the first lateral direction X and the second lateral direction Y can be perpendicular to each other.

[0022] As used herein, the term "vertical" is intended to describe an orientation that is substantially perpendicular to a horizontal plane, i.e., parallel to the normal direction of the semiconductor wafer / chip / die surface. For example, the extension direction Z mentioned below can be an extension direction perpendicular to both the first lateral direction X and the second lateral direction y. The extension direction Z is also referred to herein as the "first blocking direction Z".

[0023] In this specification, n-doping is referred to as the "first conductivity type," and p-doping is referred to as the "second conductivity type." Alternatively, the reverse doping relationship can be used, such that the first conductivity type can be p-doped, and the second conductivity type can be n-doped.

[0024] In the context of this specification, the terms "ohmic contact," "electrical contact," "ohmic connection," and "electrical connection" are intended to describe a low-ohmic electrical connection or low-ohmic current path between two regions, segments, zones, portions, or components of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode and a portion or component of a semiconductor device, wherein "low ohmic" may mean that the characteristics of the corresponding contact are substantially unaffected by ohmic resistance. Further, in the context of this specification, the term "contact" is intended to describe a direct physical connection between two elements of a respective semiconductor device; for example, the transition between two elements in contact with each other may not include additional intermediate elements, etc.

[0025] Additionally, in the context of this specification, unless otherwise stated, the term "electrically insulated" is used in the context of its generally valid understanding and is therefore intended to describe two or more components positioned separately from each other, and where there is no ohmic connection connecting those components. However, components electrically insulated from each other can still be coupled to each other, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled and / or electrostatically coupled (e.g., in the case of a junction). For example, the two electrodes of a capacitor can be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, for example, by means of an insulation (e.g., a dielectric).

[0026] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used in power converters or power supplies. Therefore, in embodiments, such power semiconductor devices can be configured to carry load currents to be fed to a load and / or supplied by a power source. For example, a power semiconductor device may include one or more active power semiconductor unit cells, such as monolithic integrated diode cells, derivatives of monolithic integrated diode cells, monolithic integrated transistor cells, such as monolithic integrated IGBT or MOSFET cells and / or derivatives thereof. Such diode / transistor cells can be integrated within a single chip. Multiple such cells can constitute a cell field arranged within the active region of the power semiconductor device.

[0027] The term "blocking state" in the context of power semiconductor devices refers to the condition when a power semiconductor is configured to block the flow of load current while an external voltage is applied. More specifically, a power semiconductor device can be configured to block forward load current from flowing through it while a forward bias voltage is applied. In contrast, a power semiconductor device can be configured to conduct forward load current in its "conduction state" while a forward bias voltage is applied. The transition between the blocking and conduction states can be controlled by a control electrode, or more specifically, by the potential of the control electrode. Of course, these electrical characteristics can only be applied within a predetermined operating range of the external voltage and current density within the power semiconductor device. Therefore, the term "forward bias blocking state" can refer to the condition where a power semiconductor device is in a blocking state while a forward bias voltage is applied.

[0028] As used in this specification, the term "power semiconductor device" is intended to describe a power semiconductor device on a single chip that has high voltage blocking and / or high current carrying capacity. In other words, such a power semiconductor device is intended for use with high currents, typically in the ampere range, such as up to tens or hundreds of amperes, and / or high voltages, typically above 15V, more typically 100V and above, such as up to at least 600V or even higher, such as up to at least 1.2kV, or even up to 6kV or higher, depending on the application.

[0029] For example, the term "power semiconductor device" as used in this specification does not refer to logic semiconductor devices used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0030] For example, the power semiconductor devices described below can be corresponding single semiconductor chips, for example, exhibiting a strip cell configuration (or a cell / needle cell configuration), and can be configured to be used as power components in low, medium and / or high voltage applications.

[0031] Figure 1 A vertical cross-section of a stacked segment according to some embodiments is illustrated schematically and exemplary.

[0032] Stack 1 includes a first power semiconductor device 110 in a first chip 11. The first power semiconductor device 110 is configured for active operation, during which applied load current is conducted through the first power semiconductor device 110, and power loss occurs in the first power semiconductor device 110. Stack 1 further includes a second power semiconductor device 120 in a second chip 12, wherein the second power semiconductor device 120 is configured for passive operation, during which voltage is blocked. Stack 13 further includes a heat sink interface 13 for dissipating the power loss. The second chip 12 is disposed between the first chip 11 and the heat sink interface 13.

[0033] According to some embodiments presented herein, a stack of two semiconductor chips is proposed, for example, thermally connected in series, one of which provides electrical insulation and thermal conductivity with respect to the heatsink interface. Electrical isolation can be provided, for example, by a low-cost, high-voltage diode based on silicon, which inherently has the task of isolating any high voltage potential at the bottom of the top switch from the heatsink interface while providing a good thermal connection. Such a diode can have asymmetric or symmetric blocking capabilities.

[0034] Refer again Figure 1 In one embodiment, the second power semiconductor device 120 in the second chip 12 is configured to block the first blocking voltage along a first blocking direction Z from the bottom of the first chip 11 to the heat sink interface 13.

[0035] In an embodiment, the second power semiconductor device 120 in the second chip 12 is further configured to block the second blocking voltage along a second blocking direction opposite to the first blocking direction z.

[0036] In an embodiment, the second power semiconductor device 120 in the second chip 12 is configured to block the first blocking voltage up to a first maximum blocking voltage, and is configured to block the second blocking voltage up to a second maximum blocking voltage, wherein the first maximum blocking voltage is different from the second maximum blocking voltage. For example, the ratio of the first maximum blocking voltage to the second maximum blocking voltage is at least 5 or at least 10. Alternatively, in another example, the ratio of the second maximum blocking voltage to the first maximum blocking voltage is at least 5 or at least 10.

[0037] In the embodiment, the first power semiconductor device 110 in the first chip 11 exhibits a power transistor configuration.

[0038] In this embodiment, the second power semiconductor device 120 in the second chip 12 is based on silicon (Si). Further, the first power semiconductor device 110 in the first chip 11 is based on a wide bandgap material, such as silicon carbide (SiC).

[0039] In the embodiment, the second power semiconductor device 120 in the second chip 12 exhibits a diode configuration having at least one pn junction (see [link]). Figure 9 (See attached figures 126 and 127).

[0040] For example, the second power semiconductor device 120 in the second chip 12 includes a first doped region 121 of a first conductivity type coupled to the first power semiconductor device 110 in the first chip 11. Further, the second power semiconductor device 120 may include a substrate region 122 of a second conductivity type, wherein the substrate region 122 is optionally coupled to the heat sink interface 13 via a second doped region 123 of the first conductivity type or the second conductivity type.

[0041] In an embodiment, the semiconductor body of the second device 120 does not include any additional regions (if a second doped region 123 is provided) where the dopant concentration is higher than that of the first doped region 121, or higher than that of the substrate region 122, or higher than that of the second doped region 123. For example, the second device 120 does not include ohmic contacts on the back side where it is coupled to the heat sink interface 13. Alternatively, the second device 120 may include Schottky contacts on the back side where it is coupled to the heat sink interface 13.

[0042] In this embodiment, the second power semiconductor device 120 in the second chip 12 exhibits a non-punch-through configuration.

[0043] In this embodiment, the first chip 11 and the second chip 12 are completely horizontally overlapped.

[0044] In an embodiment, stack 1 includes one or more other first chips 11 (e.g., see...). Figure 13 Each of these chips is completely horizontally overlapped with the second chip 12.

[0045] In an embodiment, the stack 1 includes a metal-based interface layer 1112 between the first chip 11 and the second chip 12, wherein, for example, see... Figure 2 The metal-based interface layer 1112 includes one or more of the following: one or more layers 1112-1 and 1112-5 based on Ti, TiN and / or Al; one or more layers 1112-2 based on NiSn and / or AuSn; one or more barrier layers 1112-3; one or more layers 1112-4 based on Cu; and / or one or more layers 1112-6 based on Ag.

[0046] In the embodiments (see) Figure 5 The stack 1 further includes a conductive clamp 14 between the first chip 11 and the second chip 12, wherein the clamp 14 includes a protrusion 141 that does not laterally overlap with the first chip 11.

[0047] In an embodiment, the stack 1 further includes a die attachment interface 1213 between the second chip 12 and the heat sink interface 13.

[0048] These and other aspects will be described in more detail below:

[0049] Still referencing Figure 1 The first device 110 is, for example, a wide-bandgap switch. For example, the first device 110 carries the applied load current during active operation. During active operation, which may include a switching process, such as at switching frequencies in the range of 1 kHz to 500 kHz, power losses, such as switching losses and conduction losses, occur within the first device 110. These power losses cause the first device 110 to heat up. Therefore, the first device 110 is coupled to a heatsink interface 13 via a second device 120, which is, for example, a high-voltage Si diode in blocking mode and acts as a) an electrical insulator between the first device 110 and the heatsink interface 13, and b) a thermal conductor to transfer heat from the first device 110 to the heatsink interface 13.

[0050] In this embodiment, the second device 120 does not carry the applied load current or any portion thereof. Instead, the second device 120 serves only as a thermally conductive and electrically insulating coupling to the heat sink interface.

[0051] For example, the first doped region 121 of the second device 120 is an n-type cathode coupled to the back side of the first device 110.

[0052] The heatsink interface 13 can be configured in various ways depending on the application. For example, the heatsink interface 13 includes a lead frame structure and / or a substrate. Further, in embodiments, the heatsink interface 13 is coupled to an active or passive heatsink, such as an air cooler and / or a liquid cooler. This disclosure is not limited to any particular heatsink configuration.

[0053] Figure 2 An exemplary configuration of a metal-based interface layer 1112 that can be provided between a first chip 11 and a second chip 12 is illustrated. For example, the layer 1112 is disposed between the back side of the first device 110 and a first doped region 121 of the second device 120.

[0054] An interface to the back side of the first device 110 can be established using a Ti-based layer (see reference numeral 1112-1). Similarly, the interface to the first doped region 121 of the second device 120 can also be established using a Ti, TiN, and / or Al-based layer (see reference numeral 1112-5). Coupled to layer 1112-1, one or more NiSn and / or AuSn-based layers 1112-2 can be provided, for example, to act as contact layers(s). Optionally, one or more copper Cu-based barrier layers 1112-3 and / or one or more layers 1112-4 can be provided between layers 1112-1 and 1112-5, for example, to increase the lateral conductivity and / or thermal capacity of the metal-based interface layer 1112. In general, the interface to the back side of the first device 110 can be based on any die-attachment technique, such as diffusion bonding, sintering, soft soldering, thermally conductive adhesive, or hybrid sintering. For example, the material used can be any metal, such as Sn, Ni, Au, Ag, Cu, etc. The exact configuration of the metal-based interface layer 1112 can depend on the characteristics of the devices 11 and 12 that are to be coupled to each other.

[0055] The thickness of the layer can be within the following range:

[0056]

[0057] According to an embodiment, contact / attachment to devices 110 and 120 is provided by, for example, diffusion bonding of NiSn, wherein the total thickness of NiSn is greater than the short-range thickness variation of stack 1 (e.g., in the range of 1…3 μm, see layers (one or more) 1112-2). If high lateral conductivity is required at the interface devices 110 and 120, a reinforcement layer (e.g., the Cu layer 1112-4) can be provided, for example, in front of the second device 120. For example, the requirements regarding the barrier layer for the second device 120 (see, for example, Ti, TiN, and / or Al-based layers 1112-5) can be reduced due to a low temperature budget (e.g., less than 400°C for short periods).

[0058] Figure 3 The illustration shows another exemplary configuration of a metal-based interface layer 1112 that can be provided between a first chip 11 and a second chip 12. For example, this layer 1112 is coupled to the back side of the first device 110 and a first doped region 121 of the second device 120. As shown in the figure... Figure 2In the first example, the interface to the back side of the first device 110 (see reference numeral 1112-1) can be established using a Ti-based layer. Similarly, the interface to the first doped region 121 of the second device 120 (see reference numeral 1112-5) can also be established using a Ti, TiN, and / or Al-based layer. Coupled to layer 1112-5, an Ag-based layer 1112-6, such as an Ag sintered layer, can be disposed. For example, when the first device 11 equipped with layer 1112-1 is bonded to the second device 12 equipped with said layers 1112-5 and 1112-6, such an Ag sintered layer can be advantageous with respect to the wafer bonding process. The Ag base layer 1112-6 can be produced by employing, for example, a low-pressure sintering process using Ag nanoparticles or by a conventional Ag sintering process.

[0059] Figure 4 Another embodiment of stack 1 is illustrated. In this embodiment, the first device 110 and the second device 120 are coupled to each other based on a metal-based interface layer 1112, for example, including the Cu layer 1112-4 and Ti, TiN and / or Al-based layers 1112-1, 1112-5, wherein it should be understood that this configuration of the metal-based interface layer 1112 is merely exemplary.

[0060] The second chip 12 includes a second device 120 surrounded by an edge structure 129. Both the second device 120 and the edge structure 129 are disposed on a conductive layer 1213, which can be coupled to a heat sink interface 13.

[0061] The first chip 11 houses the first device 110 and optionally provided vias 117. For example, these edge vias may be provided to electrically contact the back-side terminals of the first device 110 (if present). The first device 110 may, for example, exhibit a vertical configuration in which the applied load current flows in a direction parallel to a first blocking direction Z in the first device 110, i.e., between the first load terminal on the front side and the second load terminal on the back side. The vias 117 may be provided to contact the second load terminal. However, if the first device 110 exhibits a lateral configuration, both the first and second load terminals are arranged on the front side of the first device 110, and therefore it is not necessary to electrically contact the back side from the front side of the first chip 11. If vias 117 are provided, they may be arranged in the edge termination region of the first device 110, for example, near the edges 1-4 of the first chip 11. An insulating layer 119 and a front-side metallization 118 may be provided on the top of the first chip 11, for example, to form the first load terminals of the first device 110.

[0062] Figure 5The figure illustrates another variation coupled between two chips 11 and 12. According to this embodiment, the conductive clamp 14 is arranged between the first chip 11 and the second chip 12, wherein the clamp 14 includes the protrusion 141 that does not laterally overlap with the first chip 11. For example, the clamp 14 is coupled to the back metallization 115 of the first device 110 (e.g., forming the second load terminal on the back side of the first device 110) and the front metallization 128 of the second device 120. Based on the protrusion 141, the back metallization 115 of the first device 110 can be electrically contacted, and the via 117 can be omitted, for example. For example, the clamp 14 is first attached to the front metallization 128 of the second device 120 before the first chip 11 is mounted. The interface between the clamp 14 and the back metallization 115 of the first device or the front metallization 128 of the second device 120 can be implemented by the same or different methods, such as soft soldering, diffusion soldering, sintering, or gluing.

[0063] Figure 6 The illustration shows the application of stack 1 described above. According to... Figure 6 In the example illustrated, four transistors 51, 52, 53, and 54, such as SiC-based MOSFETs Q1 through Q4, form a full-bridge circuit 5 coupled to a DC link and a load. Each of MOSFETs Q1 through Q4 includes a source terminal S, a drain terminal D, and a gate terminal G, and each of MOSFETs Q1 through Q4 forms a corresponding first device 110 as described above. Four diodes 56, 57, 58, and 59 (D1 through D4) are additionally provided. Each of diodes D1 through D4 forms a corresponding second device 120 as described above. Diode D1 is coupled to the drain terminal D of MOSFET Q1, forming a stack 1 as described above. Diode D2 is coupled to the drain terminal D of MOSFET Q2, thereby forming another stack 1 as described above. Diode D3 is coupled to the drain terminal D of MOSFET Q3, thereby forming another stack 1 as described above. Diode D4 is coupled to the drain terminal D of MOSFET Q4, thereby forming yet another stack 1 as described above. Through the corresponding heat sink interface 13, for example via the back side of diodes D1 to D4, diodes D1 to D4 are coupled to protective ground / GND, for example, to the grounded heat sink 130.

[0064] Figure 7 The example shown in the diagram essentially corresponds to the one cited above. Figure 6 Examples. However, according to Figure 7In the example illustrated, each of the four diodes D1 to D4 forming the corresponding second device 120 exhibits the aforementioned bidirectional blocking capability, according to which the first blocking voltage can be blocked along a first blocking direction, and the second blocking voltage can be blocked along a second blocking direction opposite to the first blocking direction. For example, when one of MOSFETs Q2 and Q4 is in body diode operation, the current source characteristics of the load may require its drain potential to be more negative than its source potential. Since the source terminal S of MOSFETs Q2 and Q4 is electrically connected to ground GND (and therefore, the source potential is on ground potential), the drain potential must become negative. In this case, diodes D2 and D4 may see a small voltage drop (e.g., in the case of SiC-based MOSFETs, in the range of 2V to 4V), which would cause a standard Si-based pn diode to enter conduction mode. To avoid this, diodes D3 and D4 are configured with reverse blocking capability. As described above, the asymmetric blocking capability can be sufficient. For example, the first maximum blocking voltage is greater than 1000V, and the second maximum blocking voltage can be in the range of 10V.

[0065] Figure 6 and Figure 7 The circuit arrangement shown is for illustrative purposes only and is not intended to be limiting. Alternatively, an additional half-bridge configuration may exist, consisting of two additional transistors, each with a corresponding diode forming the second device 120. In another alternative embodiment, the circuit arrangement may consist of only one half-bridge (e.g., only two transistors 51, 52, such as MOSFETs Q1 and Q2 and their corresponding diodes D1 and D2, which form the second device 120). In another alternative embodiment, the circuit arrangement may consist of only one transistor 51 or 52, such as MOSFET Q1 or Q2, as a high-side or low-side device with a corresponding diode D1 or D2. The corresponding other transistor may be omitted or may be replaced by a free-wheeling device, such as a bipolar diode or a Schottky barrier diode. In another alternative, the free-wheeling device may be arranged on the corresponding second device 120.

[0066] Figure 8 The illustration shows an exemplary progression of the electric field |E| in the second device 120. As explained above, the primary function of the second device 120 is to act as an electrical insulator (i.e., blocking voltage) and a thermal conductor. This allows for the simple design of the second device 120, such as a simple diode design exhibiting non-punch-through characteristics, as... Figure 8 As illustrated in the figure (where the electric field terminates within substrate region 122). For example, it is not necessarily necessary to provide an additional field-stopping layer for the second device 120.

[0067] Figure 9Another embodiment of the second device 120 is illustrated. According to this embodiment, the second device 120 is a bidirectional blocking diode, wherein the substrate region 122 is based on a low-p-doped material. On the positive side, a first doped region 121 forms a first cathode, which is formed, for example, by donor implantation, and annealing can form a first pn junction 126 (J1). Further, beneath the edge structure 129 (e.g., a passivation layer), a planar high-voltage edge termination (not shown) can be provided in the edge region, for example, including variations of a lateral doped (VLD) structure, a junction termination extension (JTE) structure, one or more field rings and / or one or more field plates. On the back side, an optional second doped region 123 forms a second cathode. Since the corresponding second pn junction 127 (J2) only needs to block a voltage slightly higher than the forward voltage of the body diode, a dedicated edge termination mode can be avoided on the back side of the second device 120.

[0068] In an embodiment, when the same voltage level, lower than the first and second maximum blocking voltages, is applied as the first blocking voltage to the first pn junction 126 and as the second blocking voltage to the second pn junction 127, the first leakage current induced at the first pn junction 126 can be at least 10 times lower than the second leakage current induced at the second pn junction 128.

[0069] Figure 10 and Figure 11 Another embodiment of the second device 120 is illustrated. There, as according to Figure 4 The edge structure 129 extends from the front side to the back side of the second device 120. For example, in this embodiment, the edge structure 129 is based on zinc borate (B-Zn) glass or borosilicate glass. Figure 11 As indicated by the vertical dashed line, the lateral width of the edge structure 129 can influence the cooling effect on the peripheral region of the first device 110. For example, depending on the material of the edge structure 129, its thermal conductivity can be relatively low, implying that the peripheral region of the first chip 11, which laterally overlaps with the edge structure 129 of the second chip 12, is cooled less effectively than the portion of the first chip 11 that laterally overlaps with the substrate region 122. However, typically, during active operation, the central region of the first chip 11 becomes hotter than the peripheral region. Therefore, based on the lateral width dimension of the edge structure 129, such a potential temperature gradient in the first device 110 can be reduced or even avoided. Thus, in an embodiment, the edge structure 129 of the second chip 12 may laterally overlap with the peripheral portion of the active region of the first device 110.

[0070] Figure 12Another embodiment of stack 1 is illustrated. Therefore, the horizontal cross-sectional area of ​​the first chip 11 can be smaller than the horizontal cross-sectional area of ​​the second chip 12. Similar to... Figure 5 A variation of this design allows for simple electrical connection to the second load terminal of the first device 110, whereby the second load terminal is implemented as the back-side metallization 115 if the first device 110 exhibits a vertical configuration. For example, as illustrated, the horizontal cross-sectional area of ​​the metal-based interface layer 1112 (e.g., in this embodiment, composed solely of Cu base layers 1112-4) can also be larger than the horizontal cross-sectional area of ​​the first chip 11, for example, the same as the horizontal cross-sectional area of ​​the second chip 12. According to an embodiment, for electrical contact with the back-side metallization 115 of the first device 110, a portion of the metal-based interface layer 1112 not covered by the first chip 11 can be contacted.

[0071] Figures 13 to 15 The figure illustrates yet another embodiment of stack 1. According to these embodiments, the horizontal cross-sectional area of ​​the first chip 11 is significantly smaller than that of the second chip 1, for example, such that several first chips 11 can be arranged on top of the metal-based interface layer 1112 (e.g., in these embodiments, consisting only of Cu base layers 1112-4 or fixture 14). Depending on the application, the second load terminals of the first device 110 can be implemented as corresponding back-side metallizations 115 that can be short-circuited with each other's metal-based interface layers 1112, see [reference]. Figure 13 Such a configuration can be beneficial for connecting the first devices 110 in parallel with each other.

[0072] To prevent such a short circuit from being established between the second load terminals of the first device 110, an additional insulation structure 124 with a similar configuration to the edge structure 129 can be provided, such as... Figure 14 and Figure 15 As illustrated, this is to electrically isolate the second load terminals of the first device 110 from each other. Such a configuration can be advantageous for connecting the first device 110 in a half-bridge topology. The edge structure can be constructed by... Figure 10 and Figure 11 The vertical edge structure described in [the text] can be formed, but it can also be formed by, as in [the text] Figure 9 The planar edge structure described in the text is formed.

[0073] In addition, such as Figure 15 As illustrated, additional components 15 may be mounted on a portion of the metal-based interface layer 1112 not covered by at least one first chip 11. For example, these additional components may be or include level shifters, logic circuitry, sensors (e.g., temperature sensors), and / or gate drivers.

[0074] This article also presents module 3, including, for example, stack 1 exhibiting one of the above configurations.

[0075] For example, refer to Figure 16 and Figure 17 Module 3 has two first chips 11 mounted on a second chip 12 within a package structure 30, the package structure 30 having a lead frame LF assembly, wherein the LF assembly can be connected to ground GND.

[0076] The drain connector structure 3115 of module 3, for example, via... Figure 16-17 The bonding wires schematically illustrated are electrically connected to the second chip 12, for example, to a (not shown) metal-based interface layer 1112, which can establish electrical connections to both a first doped region 121 of the second device 120 and, for example, a (not shown) back metallization layer 115 of the first device 110.

[0077] The source connector structure 3118 of module 3, for example, via... Figure 16-17 The bonding wires schematically illustrated are electrically connected to the first chip 11, for example, electrically connected to the (not shown) front-side metallization 118 of the first chip 11. Additional connector structures 31 and 32 of module 3 can be electrically connected to other parts of the first chip, such as the gate terminal of the first chip 11 and / or the sensor terminal of the first chip 11. Figure 16 Compared to the embodiments illustrated herein, in accordance with Figure 17 In one embodiment, the encapsulation structure 30 additionally accommodates another component 15 (see [link to encapsulation structure]). Figure 15 The additional component 15 may be, for example, a gate driver unit mounted on the LF component.

[0078] For example, package structure 30 exhibits a surface mount device (SMD) configuration.

[0079] refer to Figure 18 In an embodiment, module 3 further includes a leakage current monitor 2, wherein the leakage current monitor 2 is configured to sense leakage current at the second chip 12. For example, the leakage current monitor 2 is operatively coupled to a first power semiconductor device 110 in the first chip 11 to turn off the first power semiconductor device 110 depending on the leakage current.

[0080] For example, leakage current can be detected by sensing the current at die attachment interface 1213 (e.g., via wire or tie connection 21). For example, an increased leakage current above a threshold can be detected, and a safety shutdown of the first device 110 can be triggered. For example, monitoring leakage current of the heatsink coupled to heatsink interface 13 can be avoided.

[0081] This document also presents a method for manufacturing a stack. For example, the method for manufacturing a stack includes: providing a first power semiconductor device in a first chip, wherein the first power semiconductor device is configured for active operation, during which an applied load current is conducted through the first power semiconductor device and a power loss occurs in the first power semiconductor device; providing a second power semiconductor device in a second chip, wherein the second power semiconductor device is configured for passive operation, during which a voltage is blocked; providing a heat sink interface for dissipating the power loss; and distributing the second chip between the first chip and the heat sink interface.

[0082] The embodiments of the above method correspond to the embodiments of the power semiconductor device 1 described above. Therefore, these embodiments of the method will not be described literally herein, but will be referred to above.

[0083] For example, refer to Figure 19 The coupling of the first chip 11 to the second chip 12 is performed based on a wafer bonding process, according to which a first wafer 11' comprising a plurality of first chips 11 is bonded to a second wafer 12' comprising a plurality of second chips 12. Subsequently, a wafer slicing process can be performed to form a plurality of stacks 1. For example, prior to the wafer bonding process, both the plurality of first chips 11 in the first wafer 11' and the plurality of second chips 12 in the second wafer 12' have been fully processed.

[0084] For example, wafer bonding is accomplished using interface layer 1112', such as diffusion or eutectic bonding, wherein bonding metal is deposited on both the front side of the second wafer 12' and the back side of the first wafer 11'. The bonding is accomplished, for example, by applying homogeneous pressure at typical die attachment temperatures. After bonding, the wafer stack can be sliced ​​using conventional mechanical or laser slicing.

[0085] The above text explains examples of power semiconductor devices and corresponding manufacturing methods.

[0086] For example, these power semiconductor devices are based on silicon (Si). Therefore, single-crystal semiconductor regions or layers, such as the semiconductor body and its regions / zones, such as regions, can be single-crystal Si regions or Si layers. In other embodiments, polycrystalline silicon or amorphous silicon can be used.

[0087] However, it should be understood that these power semiconductor devices can be made from any semiconductor material suitable for manufacturing semiconductor devices, as specifically mentioned above. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge); group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name just a few. The aforementioned semiconductor materials are also referred to as "homogeneous junction semiconductor materials." When two different semiconductor materials are combined, heterojunction semiconductor materials are formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switching applications, Si, SiC, GaAs, and GaN materials are currently the primary materials used.

[0088] For ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the corresponding device other than those depicted in the figures. Furthermore, terms such as “first,” “second,” and the like are also used to describe various elements, sections, segments, etc., and are not intended to be limiting. Throughout the description, similar terms may refer to similar elements.

Claims

1. A stack (1), comprising: - A first power semiconductor device (110) in a first chip (11), wherein the first power semiconductor device (110) is configured for active operation, during which an applied load current is conducted by the first power semiconductor device (110) and a power loss occurs in the first power semiconductor device (110); - A second power semiconductor device (120) in a second chip (12), wherein the second power semiconductor device (120) is configured for passive operation, during which voltage is blocked; - A heat sink interface (13) for dissipating the power loss, wherein the second chip (12) is disposed between the first chip (11) and the heat sink interface (13).

2. The stack (1) according to claim 1, wherein the second power semiconductor device (120) in the second chip (12) is configured to block the first blocking voltage along a first blocking direction (Z) from the bottom of the first chip (11) to the heat sink interface (13).

3. The stack (1) according to claim 2, wherein the second power semiconductor device (120) in the second chip (12) is configured to block the second blocking voltage along a second blocking direction opposite to the first blocking direction (Z).

4. The stack (1) according to claim 3, wherein the second power semiconductor device (120) in the second chip (12) is configured to block the first blocking voltage up to a first maximum blocking voltage and is configured to block the second blocking voltage up to a second maximum blocking voltage, wherein the first maximum blocking voltage is different from the second maximum blocking voltage.

5. The stack (1) according to one or more of the preceding claims, wherein the first power semiconductor device (110) in the first chip (11) exhibits a power transistor configuration.

6. The stack (1) according to one or more of the preceding claims, wherein the second power semiconductor device (120) in the second chip (12) is based on Si, and / or wherein the first power semiconductor device (110) in the first chip (11) is based on a wide bandgap material, such as SiC.

7. The stack (1) according to one or more of the preceding claims, wherein the second power semiconductor device (120) in the second chip (12) exhibits a diode configuration having at least one pn junction (126, 127).

8. The stack (1) according to claim 7, wherein the second power semiconductor device (120) in the second chip (12) includes a first doped region (121) of a first conductivity type and a substrate region (122) of a second conductivity type coupled to the first power semiconductor device (110) in the first chip (11), wherein the substrate region (122) is optionally coupled to a heat sink interface (13) via a second doped region of the first conductivity type or the second conductivity type.

9. The stack (1) according to one or more of the preceding claims, wherein the second power semiconductor device (120) in the second chip (12) exhibits a non-punch-through configuration.

10. The stack (1) according to one or more of the preceding claims, wherein the first chip (11) and the second chip (12) are completely laterally overlapped.

11. The stack (1) according to one or more of the preceding claims further includes one or more other first chips (11), each of which is laterally overlapped with the second chip (12).

12. The stack (1) according to one or more of the preceding claims, further comprising a metal-based interface layer (1112) between the first chip (11) and the second chip (12), wherein optionally, the metal-based interface layer (1112) comprises one or more of the following: - One or more layers (1112-1, 1112-5) based on Ti, TiN and / or Al; - One or more layers based on NiSn and / or AuSn (1112-2); - One or more barrier layers (1112-3); - One or more Cu-based layers (1112-4); - One or more layers based on Ag (1112-6).

13. The stack (1) according to one or more of the preceding claims further includes a conductive clamp (14) between the first chip (11) and the second chip (12), wherein the clamp (14) includes a protrusion (141) that does not laterally overlap with the first chip (11).

14. The stack (1) according to one or more of the preceding claims further includes a die attachment interface (1213) between the second chip (12) and the heat sink interface (13).

15. A module (3) comprising one or more of the stacks (1) described in the preceding claims.

16. The module (3) of claim 15 further includes a leakage current monitor (2), wherein the leakage current monitor (2) is configured to sense leakage current at the second chip (12).

17. The module (3) of claim 16, wherein the leakage current monitor (2) is operatively coupled to a first power semiconductor device (110) in the first chip (11) to turn off the first power semiconductor device (110) depending on the leakage current.

18. A method for producing a stack (1), comprising: - A first power semiconductor device (110) is provided in a first chip (11), wherein the first power semiconductor device (110) is configured for active operation, during which an applied load current is conducted by the first power semiconductor device (110) and a power loss occurs in the first power semiconductor device (110); - A second power semiconductor device (120) in a second chip (12), wherein the second power semiconductor device (120) is configured for passive operation, during which voltage is blocked; - A heat sink interface (13) for dissipating the power loss, wherein the second chip (12) is disposed between the first chip (11) and the heat sink interface (13).

19. The method of claim 18, wherein the method comprises a wafer bonding process step and a subsequent slicing process step.

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