Hybrid bonding structure, manufacturing method thereof, hybrid bonding process and bonding equipment

Abstract

The invention belongs to the technical field of semiconductor manufacturing, and provides a hybrid bonding structure, a manufacturing method thereof, a hybrid bonding process and bonding equipment. A first wafer to be bonded in the hybrid bonding structure comprises a dielectric layer with a filling groove, and a first metal block is arranged in the dielectric layer; the first dielectric layer is provided with an open slot capable of exposing the first metal block, and a first inclined side surface is formed on the first dielectric layer in the open slot; a second wafer to be bonded in the hybrid bonding structure comprises a second metal block arranged on the second dielectric layer in a protruding manner; the second metal block is provided with a second inclined side surface matched with the first inclined side surface; during bonding, the opening groove accommodates the second metal block, and bonding errors caused by factors such as mechanical motion and vibration are avoided through cooperation of the first inclined side face and the second inclined side face, so that lower offset is kept, and the bonding alignment precision is effectively improved. The hybrid bonding process and the bonding equipment provided by the invention are used for executing bonding of the hybrid bonding structure.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor processing and manufacturing, and relates to a hybrid bonding structure, a manufacturing method thereof, a hybrid bonding process and a bonding device. BACKGROUND

[0002] Hybrid bonding generally refers to a process of realizing dielectric bonding between dielectric layers and direct metal connection between metal pads in wafer-to-wafer or die-to-wafer integration, so as to construct a vertical interconnection structure. This technology is widely used in the fields of image sensors, memory stacking, logic chip heterogeneous integration and MEMS device packaging, etc., and can significantly improve the signal transmission rate, reduce parasitic capacitance and power consumption, and realize more compact device layout.

[0003] At present, the existing conventional process often needs to complete the alignment of patterns between wafers in a bonding device before bonding, for example, alignment based on infrared or laser markers, and some advanced devices also introduce electron beam assisted or diffraction optical alignment technology to improve the alignment resolution. After alignment, bonding is performed, and then high-temperature treatment and hybrid bonding are completed.

[0004] However, after actual bonding is completed, it is found through detection that the actual alignment deviation of the metal interconnection structure is often significantly increased, generally reaching more than 200 nm, and in extreme cases, even exceeding 500 nm, which seriously deviates from the design expectation. This significant degradation of post-bonding precision has become a major obstacle to the popularization and application of hybrid bonding technology in sub-micron and below interconnection pitch. SUMMARY

[0005] In view of the problems in the prior art, the purpose of the present application is to provide a hybrid bonding structure, a manufacturing method thereof, a hybrid bonding process and a bonding device, so as to mainly solve the problem of post-bonding precision degradation caused by the superposition of factors such as mechanical movement and vibration in the existing hybrid bonding process.

[0006] To achieve this purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a hybrid bonding structure, which comprises a first to-be-bonded wafer and a second to-be-bonded wafer.

[0008] The first wafer to be bonded comprises a first original wafer, a dielectric layer and a first medium layer which are arranged in sequence on a side to be bonded; a filling groove is arranged in the dielectric layer, and a first metal block in contact with the first original wafer is arranged in the filling groove; an opening groove corresponding to the position of the filling groove is arranged in the first medium layer, and the first metal block is exposed; the first inclined side surface is formed in the first medium layer in the opening groove;

[0009] The second wafer to be bonded comprises a second original wafer and a second medium layer arranged on a side to be bonded; a second metal block protruding from a surface of the second medium layer away from the second original wafer is arranged on the second medium layer;

[0010] The opening groove and the second metal block are configured such that the second metal block has a second inclined side surface matching the first inclined side surface, and when the first medium layer and the second medium layer are in contact during bonding, the opening groove accommodates the second metal block.

[0011] The present application effectively improves the accuracy of bonding alignment by making specific structures on the surface of the wafer to be bonded, i.e. by constructing the first inclined side surface and the second inclined side surface matching each other in the opening groove and the second metal block. During the implementation of bonding, the designed inclined side surface can be fully utilized, so that the alignment position and the bonding position of the two wafers to be bonded are corrected, and errors caused by mechanical movement, vibration and other factors are avoided, thereby maintaining a lower deviation.

[0012] The following is a preferred technical solution of the present application, but not as a limitation of the technical solutions provided by the present application. Through the following technical solution, the technical purpose and beneficial effects of the present application can be better achieved and realized.

[0013] As a preferred technical solution of the present application, the first inclined side surface and the second inclined side surface satisfy at least one of the following conditions:

[0014] (a1) The angle between the first inclined side surface and the thickness direction of the first medium layer is a first inclined angle θ1, 0° < θ1 < 90°; preferably (a2) 25° < θ1 < 65°, and further preferably (a3) 40° < θ1 < 50°.

[0015] (a4) The angle between the second inclined side surface and the thickness direction of the second metal block is a second inclined angle θ2, θ2 = θ1.

[0016] As a preferred technical solution of the present application, the first metal block and the second metal block satisfy at least one of the following conditions:

[0017] (b1) The thickness of the first metal block is equal to the thickness of the dielectric layer.

[0018] (b2) when the first dielectric layer and the second dielectric layer are in contact with each other in the bonding, the opening slot accommodates the second metal block, and an expansion gap is reserved between the second metal block and the first metal block.

[0019] The present application can provide an expansion gap for the thermal expansion of copper during the heat treatment of the bonded wafer, which can effectively ensure the quality of the metal interconnection after the bonding and control the stress of the bonding material.

[0020] (b3) the thickness of the second metal block is less than or equal to the thickness of the first dielectric layer.

[0021] (b4) the thickness of the first metal block is H1, the thickness of the second metal block is H2, and the size of the expansion gap is L, then L=((H1+H2)×α×(T-T0))β, wherein α is the linear thermal expansion coefficient of the metal, unit is 10 -6 / ℃; T is the maximum value of the processing temperature during the bonding; T0 is the initial temperature of the environment before the bonding; and β is an empirical coefficient, β is taken from 0.7 to 1.3.

[0022] (b5) the metal component of the first metal block includes copper and / or gold.

[0023] (b6) the metal component of the second metal block includes copper and / or gold.

[0024] As a preferred technical solution of the present application, the mixed bonding structure further satisfies at least one of the following conditions:

[0025] (c1) the first original wafer and the second original wafer each include at least one of silicon, glass, SiC, SiN or LiTaO3.

[0026] (c2) a first isolation layer is arranged in the filling slot, and the first isolation layer is arranged between the first original wafer and the first metal block.

[0027] (c3) the second wafer to be bonded further includes a second isolation layer, and the second isolation layer is arranged between the second dielectric layer and the second metal block.

[0028] (c4) the first isolation layer includes at least one of Ti, Ta or TaN.

[0029] (c5) the first dielectric layer and the second dielectric layer each include silicon nitride and / or silicon carbon nitride.

[0030] (c6) the dielectric layer includes silicon oxide.

[0031] In a second aspect, the present application provides a method for manufacturing the hybrid bonding structure of the first aspect, the method comprising:

[0032] manufacturing a first to-be-bonded wafer: providing a first original wafer, forming a dielectric layer on a to-be-bonded side of the first original wafer, forming a filling groove in the dielectric layer, then forming a first metal block in the filling groove, forming a first dielectric layer to cover the dielectric layer and the first metal layer, then forming an opening groove in the first dielectric layer corresponding to the position of the filling groove, to obtain the first to-be-bonded wafer;

[0033] manufacturing a second to-be-bonded wafer: providing a second original wafer, forming a second dielectric layer on a to-be-bonded side of the second original wafer, then forming a second metal block on the second dielectric layer, to obtain the second to-be-bonded wafer.

[0034] As a preferred technical solution of the present application, the first to-be-bonded wafer satisfies at least one of the following conditions:

[0035] (d1) the method for forming the dielectric layer comprises thermal oxidation and / or chemical vapor deposition.

[0036] (d2) the method for forming the filling groove comprises etching.

[0037] (d3) the method for forming the first metal block in the filling groove comprises: depositing a first metal layer on the side of the dielectric layer having the filling groove, removing the excess first metal layer to retain the first metal block in the filling groove.

[0038] (d4) the method for forming the first metal block in the filling groove further comprises: before depositing the first metal layer, first depositing a first isolation layer on the side of the dielectric layer having the filling groove, then depositing the first metal layer on the first isolation layer, removing the excess first isolation layer and the first metal layer to retain the first isolation layer and the first metal block in the filling groove.

[0039] (d5) the method for depositing the first isolation layer comprises physical vapor deposition.

[0040] (d6) the method for forming the first dielectric layer comprises chemical vapor deposition.

[0041] (d7) the method for forming the opening groove comprises etching.

[0042] (d8) the metal composition of the first metal layer comprises copper and / or gold.

[0043] As a preferred technical solution of the present application, the method for forming the second metal block comprises any one of the following mode one or mode two:

[0044] In the first mode, a second metal layer and a dielectric auxiliary layer are sequentially deposited on the second dielectric layer, a chamfered groove is etched on the dielectric auxiliary layer, the chamfered groove has the same profile shape as the second metal block; then a third metal layer is deposited on the side of the dielectric auxiliary layer with the chamfered groove to fill the chamfered groove with copper, then the excess third metal layer outside the chamfered groove is removed, then the dielectric auxiliary layer is removed, and then the excess second metal layer is removed, so that the remaining part of the third metal layer in the chamfered groove and the remaining part of the second metal layer below it constitute the second metal block.

[0045] In the second mode, a fourth metal layer is deposited on the second dielectric layer, and the fourth metal layer is etched to form the second metal block.

[0046] As a preferred technical solution of the present application, the second wafer to be bonded satisfies at least one of the following conditions:

[0047] (e1) The method for forming the second dielectric layer includes chemical vapor deposition.

[0048] (e2) In the first mode, the method for depositing the second metal layer, the third metal layer and the fourth metal layer all includes physical vapor deposition.

[0049] (e3) In the first mode, the method for depositing the dielectric auxiliary layer includes chemical vapor deposition.

[0050] (e4) In the first mode, the method for etching the chamfered groove includes etching.

[0051] (e5) In the first mode, the method for depositing the second metal layer includes electroplating.

[0052] (e6) In the first mode, the method for removing the excess third metal layer outside the chamfered groove includes chemical mechanical polishing.

[0053] (e7) In the first mode, the method for removing the dielectric auxiliary layer includes dry etching.

[0054] (e8) In the first mode, the method for removing the second metal layer includes etching.

[0055] (e9) The first mode further includes, before depositing the second metal layer, depositing a second isolation layer on the second dielectric layer, and then depositing the second metal layer on the second isolation layer; when removing the excess second metal layer, the excess second isolation layer is also removed to retain part of the second isolation layer below the second metal block.

[0056] (e10) The second mode also includes, before depositing the fourth metal layer, first depositing a second isolation layer on the second dielectric layer, and then depositing the fourth metal layer on the second isolation layer; when etching the fourth metal layer, etching the excess second isolation layer at the same time to reserve part of the second isolation layer under the fourth metal block.

[0057] (e11) The metal components of the second metal layer, the third metal layer and the fourth metal layer all include copper and / or gold.

[0058] (e12) The material of the dielectric auxiliary layer includes silicon oxide.

[0059] In a third aspect, the application provides a wafer-level hybrid bonding process, which includes:

[0060] providing the hybrid bonding structure of the first aspect, taking one of the first wafer to be bonded or the second wafer to be bonded as an upper wafer, and taking the other wafer to be bonded as a lower wafer:

[0061] pre-aligning the upper wafer and the lower wafer, so that the second metal block in the upper wafer is aligned with the open slot in the lower wafer;

[0062] performing point pressing processing to make the first dielectric layer and the second dielectric layer contact, and in this process, the second inclined side of the second metal block cooperates with the first inclined side of the open slot, so that the second metal block is embedded into the open slot, and the precise alignment of the upper wafer and the lower wafer is realized;

[0063] performing surface pressing processing, and after the surface pressing processing is completed, the first dielectric layer and the second dielectric layer are connected, and at the same time, the first metal block and the second metal block are connected.

[0064] As a preferred technical solution of the application, the wafer-level hybrid bonding process meets at least one of the following conditions:

[0065] (f1) The pressure of the point pressing processing is 1N-10N.

[0066] (f2) The duration of the point pressing processing is 5s-15s.

[0067] (f3) The pressure of the surface pressing processing is 100N-300N.

[0068] (f4) The duration of the surface pressing processing is 1min-10min.

[0069] (f5) After the surface pressing processing is completed, annealing is performed.

[0070] (f6) The temperature of the annealing is 250℃-1000℃.

[0071] (f7) the annealing process comprises a first annealing at 250-500 DEG C for 1-3 hours, and then a second annealing at 500-1000 DEG C for 1-3 hours.

[0072] (f8) the upper wafer is grabbed by vacuum suction of a chuck, and the vacuum suction value is -500 mbar to -300 mbar; after the point pressure treatment is finished, the upper wafer is released in a partitioned manner before the surface pressure treatment is started.

[0073] In a fourth aspect, the present application provides a bonding device for performing the bonding process of the third aspect, the bonding device comprising an upper loading platform and a lower loading platform arranged oppositely and used for fixing the upper wafer and the lower wafer respectively;

[0074] A moving slide is used for carrying the upper loading platform and / or the lower loading platform, and is used for adjusting the relative position between the upper wafer and the lower wafer.

[0075] A force output part is connected to the upper loading platform or the lower loading platform, and is used for performing the point pressure and / or the surface pressure between the upper wafer and the lower wafer.

[0076] Compared with the prior art, the present application has at least the following beneficial effects:

[0077] The present application effectively improves the precision of bonding alignment by making a specific structure on the surface of the wafer to be bonded, i.e. by constructing the first inclined side and the second inclined side which match each other in the opening groove and the second metal block, so that the alignment position and the bonding position of the two wafers to be bonded are corrected, and the error caused by mechanical movement, vibration and other factors is avoided, thereby keeping a lower deviation.

[0078] The present application performs the point pressure in the bonding process, and the point pressure is small, so that the first metal block and the second metal block are matched and adjusted in position under small pressure, and the first metal block and the second metal block are not compacted before being adjusted in position under the direct surface pressure, so that the voids are easily generated at the contact position.

[0079] The present application sets a proper expansion gap, which can be used as a free space for the thermal expansion of copper during the thermal treatment of the bonded wafer, so as to not only ensure the quality of the metal interconnection after bonding, but also effectively control the stress of the bonding material. BRIEF DESCRIPTION OF DRAWINGS

[0080] Figure 1 is a structure diagram of the first wafer to be bonded in the hybrid bonding structure provided by one or more embodiments of the present application.

[0081] Figure 2 isFigure 1 Enlarged view of the dotted circle in the middle red line.

[0082] Figure 3 is a structural schematic diagram of a first to-be-bonded wafer in a hybrid bonding structure provided by one or more embodiments of the present application.

[0083] Figure 4 is Figure 3 Enlarged view of the dotted circle in the middle red line.

[0084] Figures 5 to 9 is a structural schematic diagram of a first to-be-bonded wafer in a hybrid bonding structure provided by one or more embodiments of the present application.

[0085] Figures 10 to 17 is a structural schematic diagram of a first to-be-bonded wafer in a hybrid bonding structure provided by one or more embodiments of the present application.

[0086] Figures 18 to 20 is a structural schematic diagram of a first to-be-bonded wafer in a hybrid bonding structure provided by one or more embodiments of the present application.

[0087] Figure 21 is a structural schematic diagram of a first to-be-bonded wafer in a hybrid bonding structure provided by one or more embodiments of the present application.

[0088] In the above figures: 10-first to-be-bonded wafer, 11-first original wafer, 12-dielectric layer, 13-filling groove, 14-first metal block, 15-first dielectric layer, 16-opening groove, 17-first inclined side, 20-second to-be-bonded wafer, 21-second original wafer, 22-second dielectric layer, 23-second metal layer, 24-dielectric auxiliary layer, 25-chamfered groove, 26-remaining part of the third metal layer in the chamfered groove, 27-second metal block, 28-second inclined side, 29-fourth metal layer. DETAILED DESCRIPTION

[0089] The embodiments of the present application are described in detail below, and the reference to "embodiments" herein means that the specific features, structures or characteristics described in connection with the embodiments can be included in one or more embodiments or implementations of the present application. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. The reference to "implementations" herein also has a similar understanding. If there is no special description, all the implementations and optional implementations of the present application can be combined to form new technical solutions, and all the technical features and optional technical features of the present application can be combined to form new technical solutions.

[0090] In the description of the present application, the open technical features or technical solutions described with the words "containing", "including", "comprising", "having" and the like mean to include the contents indicated by the present application. If there is no other description, other contents besides the indicated contents can be regarded as providing both the closed features or solutions constituted by the indicated contents and the open features or solutions including additional other contents besides the indicated contents.

[0091] In the description of the present application, "X and / or Y" optionally includes any one of the case of X alone, the case of Y alone, the case of X and Y, wherein X, Y are only used for example, which can be any technical feature connected with "and / or" in the present application.

[0092] The range disclosed in the present application is defined in the form of lower limit and upper limit, a given range is defined by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundary of a particular range. The range defined in this way can be inclusive of the end value or not, and can be arbitrarily combined, that is, any lower limit can be combined with any upper limit to form a range.

[0093] In the description of the present application, "a plurality of", "a plurality of kinds" and the like, if not particularly limited, mean greater than or equal to 2 in number. For example, "one or more" means one or more than or equal to two.

[0094] In the description of the present application, the terms "first", "second" are only used for description purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. "First feature" "second feature" optionally includes one or more of the features.

[0095] In the description of the present application, the writing order of each step does not mean strict execution order and constitute any limitation to the implementation process, and the detailed execution order of each step should be determined by its function and possible internal logic.

[0096] In the description of the present application, the orientation or positional relationship indicated by the technical terms "length", "width", "thickness", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", "upper", "lower" and the like can be understood as based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the embodiments of the present application and simplifying the description, and does not indicate or imply that the indicated structure must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation to the embodiments of the present application.

[0097] Embodiments of the present application are described below in detail, examples of one or more embodiments are shown in the accompanying drawings, but there will be cases where unnecessary detailed description is omitted. For example, there are cases where detailed description of matters known to those skilled in the art, repeated description of substantially the same structure are omitted. In addition, the accompanying drawings and the following description are provided to enable those skilled in the art to fully understand the present application, and are not intended to limit the subject matter recited in the claims. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0098] In the hybrid bonding process, although the initial alignment accuracy can be made high, during the application of mechanical pressure, the advancement of the wafer inter-contact front is often uneven, especially in the edge region of large-size wafers, due to uneven pressure distribution, surface curvature difference or local particle contamination, which easily causes relative slip or rotation between wafers, resulting in the deviation of the aligned pattern. However, the prior art lacks a mechanism for regulating the dynamic process of bonding, and cannot correct the deviation in real time during the pressure application process, resulting in the inability to effectively maintain the initial alignment results. At the same time, the quality of the metal interconnection after bonding is also significantly affected by the process. During high-temperature annealing, copper and other metal materials produce residual stress due to the mismatch of the thermal expansion coefficient with the surrounding medium, which can cause metal wire breakage, void formation or interface delamination, affecting the reliability of electrical connection.

[0099] Therefore, how to effectively suppress the dynamic deviation during the bonding process while realizing high-density electrical interconnection, improve the actual alignment accuracy after bonding, and improve the integrity of the metal interconnection and the stress distribution of the bonding interface has become a core problem that needs to be solved in the development of current wafer-level hybrid bonding technology.

[0100] Therefore, in one or more embodiments of the present application, a hybrid bonding structure is provided, which includes a first wafer to be bonded and a second wafer to be bonded;

[0101] As shown in the drawings, Figure 1 The first wafer to be bonded 10 includes a first original wafer 11, and a dielectric layer 12 and a first dielectric layer 15 stacked on the side to be bonded; the dielectric layer 12 is provided with a filling groove 13, and the filling groove 13 is provided with a first metal block 14 in contact with the first original wafer 11; the first dielectric layer 15 is provided with an opening groove 16 corresponding to the position of the filling groove 13, exposing the first metal block 14; in the opening groove 16, a first inclined side surface 17 is formed in the first dielectric layer 15;

[0102] As shown in the drawings, Figure 3As shown, the second wafer to be bonded 20 comprises a second original wafer 21, and a second dielectric layer 22 arranged on the side of the wafer to be bonded; the second dielectric layer 22 is arranged with a protruding second metal block 27 on the side surface away from the second original wafer 21;

[0103] The opening groove 16 and the second metal block 27 are configured as follows: the second metal block 27 has a second inclined side 28 matching the first inclined side 17, and when the first dielectric layer 15 and the second dielectric layer 22 are in contact during bonding, the opening groove 16 accommodates the second metal block 27, as shown. Figure 19

[0104] The present application effectively improves the accuracy of the bonding alignment by making a specific structure on the surface of the wafer to be bonded, that is, by constructing the first inclined side 17 and the second inclined side 28 matching each other in the opening groove 16 and the second metal block 27. Specifically, after point pressing in the bonding process, there will be a certain offset between the upper and lower wafer, and the inclined side can provide friction to the upper wafer, so that the inclined side can support the center of gravity of the upper wafer, and when the surface is pressed, the pressure of the surface pressing will be much greater than the friction between the inclined side and the upper wafer, so that the center of gravity of the upper wafer will move towards the center of the supporting surface to achieve stability. That is, when the bonding is implemented in the point pressing and surface pressing integrated device, the designed inclined side is fully utilized, so that the alignment position and bonding position of the two wafers to be bonded are corrected, avoiding errors caused by mechanical movement, vibration and other factors, thereby keeping a lower offset.

[0105] In some embodiments, the profile shape of the opening groove 16 is a first table body; the top surface of the first table body faces the first metal block 14, and the bottom surface of the first table body forms an opening on the surface of the first dielectric layer 15 away from the dielectric layer 12, thereby exposing the first metal block 14; in the opening groove 16, the side surface of the first table body forms the first inclined side 17 in the first dielectric layer 15. Alternatively, it can be understood that, in a certain cross section parallel to the thickness of the first wafer to be bonded 10, the cross-sectional profile shape of the opening groove 16 is an inverted first trapezoid, the long bottom side of the first trapezoid forms the opening, and the two waists of the first trapezoid form the first inclined side 17. At this time, the bonding surface of the first wafer to be bonded 10 includes the surface of the first dielectric layer 15 exposed outside the opening groove 16, the first inclined side 17 in the opening groove 16, and the surface of the first metal block 14 exposed at the bottom of the opening groove 16.

[0106] ​In some embodiments, the profile of the second metal block 27 is a second mesa; the bottom surface of the second mesa is in contact with the second dielectric layer 22, and the top surface of the second mesa is away from the surface of the second dielectric layer 22; the side surface of the second mesa forms the second inclined side surface 28 of the second metal block 27. Alternatively, it can be understood that, in a certain cross section parallel to the thickness of the wafer, the profile of the cross section of the second metal block 27 is a second upright trapezoid, the long bottom side of the second trapezoid is in contact with the second dielectric layer 22, and the two waists of the second trapezoid form the second inclined side surface 28. At this time, the bonding surface of the second wafer to be bonded 20 includes the surface of the second metal block 27 away from the second dielectric layer 22, the second inclined side surface 28 on the second metal block 27, and the surface of the second dielectric layer 22 exposed outside the second metal block 27.

[0107] In some embodiments, as shown in FIG. 1, the first inclined angle θ1 of the first inclined side surface 17 with respect to the thickness direction of the first dielectric layer 15 is 0°<θ1<90°. Exemplarily, θ1 can be 5°, 10°, 15°, 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, or 85°, further 25°<θ1<65°, and more further 40°<θ1<50°. Figure 2 In some embodiments, as shown in FIG. 1, the second inclined angle θ2 of the second inclined side surface 28 with respect to the thickness direction of the second metal block 27 is θ2=θ1. Thus, it is beneficial for the second inclined side surface 28 to better cooperate with the first inclined side surface 17, so that the second metal block 27 is completely embedded in the opening groove 16.

[0108] Figure 4 In some embodiments, as shown in FIG. 1, the second inclined angle θ2 of the second inclined side surface 28 with respect to the thickness direction of the second metal block 27 is θ2=θ1. Thus, it is beneficial for the second inclined side surface 28 to better cooperate with the first inclined side surface 17, so that the second metal block 27 is completely embedded in the opening groove 16.

[0109] The inclined angle of the first inclined side surface 17 and the friction when the first inclined side surface 17 and the second inclined side surface 28 are in contact are related to the friction of the bevel surface and the gravity of the upper wafer (which can be the second wafer to be bonded 20), and are adjusted according to the actual situation. When 40°<θ1=θ2<50°, it is beneficial to obtain better constraint and correction effect.

[0110] As a further example, when the second wafer to be bonded 20 is the upper wafer (i.e., the upper wafer), the friction F1 that the second metal block 27 receives when the first inclined side surface 17 and the second inclined side surface 28 are in contact, the elastic force F2 that the second metal block 27 receives, and the gravity G of the second wafer to be bonded 20 itself are recorded; if there are n second metal blocks 27 on the second wafer to be bonded 20 (i.e., there are corresponding n first metal blocks 14 on the first wafer to be bonded 10), θ2 (or θ1) satisfies: n×F2×sinθ2+n×F1×cosθ2=G. ​

[0111] In some embodiments, as shown in FIG. 1, the thickness of the first metal block 14 is H1, and the thickness of the dielectric layer 12 is H4, then H1=H4. Since the filling slot 13 is through the dielectric layer 12, the thickness of the first metal block 14 is equal to the thickness of the dielectric layer 12, i.e. the first metal block 14 fills the filling slot 13. Figure 2

[0112] In some embodiments, as shown in FIG. 2, the thickness of the second metal block 27 is H2, and the thickness of the first dielectric layer 15 is H3, then H3+H4≥H1+H2; i.e. when the first dielectric layer 15 and the second dielectric layer 22 are in contact in the bonding, the opening slot 16 accommodates the second metal block 27, and the second metal block 27 and the first metal block 14 have an expansion gap therebetween; or, the size of the expansion gap is L, then H3+H4=H1+H2+L, L>0. Figure 2 Figure 19 In some embodiments, the thickness of the second metal block 27 is less than or equal to the thickness of the first dielectric layer 15, i.e. H2≤H3.

[0113] If the thickness of the second metal block 27 is too small, although it is beneficial to be embedded in the opening slot 16, the gap between the second metal block 27 and the first metal block 14 is too large, which may cause the copper interconnection in the two wafers to be unable to be completely connected after the bonding process, thereby affecting the electrical transmission. If the thickness of the second metal block 27 is too large, which causes the gap between the second metal block 27 and the first metal block 14 to be too small or even no gap and direct contact, when the bonding wafer is subjected to heat treatment after the bonding, the copper thermal expansion will cause extrusion at the copper contact, thereby causing stress in the bonding wafer, which is easy to cause internal cracks in the bonding wafer. Therefore, setting an appropriate expansion gap, i.e. the relationship between the thickness of the first dielectric layer 15, the thickness of the second metal block 27 and other layer thicknesses is reasonable, which can provide a free space for the copper thermal expansion when the bonding wafer is subjected to heat treatment, thereby avoiding the problem of internal cracks caused by excessive stress.

[0114] In some embodiments, L=((H1+H2)×α×(T-T0))β, where α is the linear thermal expansion coefficient of the metal, which is 10 -6 / ℃; T is the maximum value of the processing temperature when the bonding is performed; T0 is the initial environmental temperature before the bonding; and β is an empirical coefficient, and β is taken from 0.7 to 1.3.

[0115] In some embodiments, the metal component of the first metal block 14 includes copper and / or gold.

[0116] In some embodiments, the metal component of the second metal block 27 includes copper and / or gold.

[0117] In some embodiments, the metal component of the second metal block 27 includes copper and / or gold. ​​

[0118] Further, based on the temperature consideration of bonding and subsequent heat treatment, when the metal components are both copper, a is taken as 18.91 x 10 -6 / °C~19.53 x 10 -6 / °C; exemplary, a can be 18.91 x 10 -6 / °C, 19 x 10 -6 / °C, 19.1 x 10 -6 / °C, 19.15 x 10 -6 / °C, 19.2 x 10 -6 / °C, 19.25 x 10 -6 / °C, 19.3 x 10 -6 / °C, 19.35 x 10 -6 / °C, 19.4 x 10 -6 / °C, 19.45 x 10 -6 / °C, 19.5 x 10 -6 / °C or 19.53 x 10 -6 / °C, etc.; β can be 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, 1.05, 1.1, 1.15, 1.2, 1.25 or 1.3, etc. Further, when the metal components of the first metal block 14 and the second metal block 27 are different, L = ((a1H1+ a2H2) x (T - T0))β, a1 is the linear thermal expansion coefficient of the first metal, and a2 is the linear thermal expansion coefficient of the second metal.

[0119] In some embodiments, the first original wafer 11 and the second original wafer 21 each comprises at least one of silicon, glass, SiC, SiN or LiTaO3.

[0120] In some embodiments, the first original wafer 11 and the second original wafer 21 each has a size of any one of 4 inches, 6 inches, 8 inches or 12 inches.

[0121] It can be understood that the first original wafer 11 and the second original wafer 21 should be made clean before further setting the related layer structure, for example, in some embodiments, the surface roughness Ra of the first original wafer 11 and the second original wafer 21 is ≤0.5nm (0.5μm×0.5μm area), the bow value is -40μm~40μm; the total thickness deviation TTV value is ≤25μm. Exemplarily, the Ra can be 0.5nm, 0.4nm, 0.3nm, 0.2nm, 0.1nm or 0.05nm, etc.; the Bow value can be -40μm, -30μm, -20μm, -10μm, 0μm, 10μm, 20μm, 30μm or 40μm, etc.; the TTV value can be 25μm, 22μm, 20μm, 18μm, 15μm, 12μm, 10μm, 8μm or 5μm, etc.

[0122] In some embodiments, the filling groove 13 is provided with a first isolation layer, which is arranged between the first original wafer 11 and the first metal block 14.

[0123] In some embodiments, the second to-be-bonded wafer 20 further comprises a second isolation layer, which is arranged between the second dielectric layer 22 and the second metal block 27.

[0124] Before depositing copper, an isolation layer can be deposited first to facilitate the isolation of the metal such as copper in the metal block (metal layer) from diffusing, because copper is more likely to diffuse into the dielectric layer 12 and other layers, so as to prevent the diffusion from reducing the insulation of the dielectric layer 12. It can be understood that after the isolation layer is formed, the isolation layer and the corresponding metal block (metal layer) should be considered as a whole, so as to facilitate the calculation and setting of the thickness of the layer and the thickness relationship between the layers. For example, when the first isolation layer and the second isolation layer are provided, the thickness of the first metal block 14 is H1, the thickness of the dielectric layer 12 is H4, the thickness of the second metal block 27 is H2, the thickness of the first dielectric layer 15 is H3, the thickness of the first isolation layer is H5, the thickness of the second isolation layer is H6, and the size of the expansion gap is L, then H1+H5=H4, H3≥H2+H6, i.e. H3+H4≥H1+H5+H2+H6, or H3+H4=H1+H5+H2+H6+L.

[0125] In some embodiments, the first isolation layer comprises at least one of Ti, Ta or TaN.

[0126] In some embodiments, the first dielectric layer 15 and the second dielectric layer 22 each comprise silicon nitride and / or silicon carbon nitride.

[0127] In some embodiments, the dielectric layer 12 comprises silicon oxide.

[0128] The silicon nitride / carbon nitride silicon layer can be used as a film layer material for reserving a back interconnection for copper, as a cutoff layer, and can prevent short circuit caused by direct connection between copper and silicon in hybrid bonding.

[0129] In one or more embodiments of the present application, a method for manufacturing the hybrid bonding structure described in the above embodiments is provided, and the method comprises:

[0130] As shown in Figures 5 to 9 and Figure 1 manufacturing the first wafer to be bonded 10: providing a first original wafer 11, forming a dielectric layer 12 on the side to be bonded of the first original wafer 11, forming a filling groove 13 in the dielectric layer 12, then forming a first metal block 14 in the filling groove 13, forming a first dielectric layer 15 to cover the dielectric layer 12 and the first metal block, then forming an opening groove 16 in the first dielectric layer 15 corresponding to the position of the filling groove 13, to obtain the first wafer to be bonded 10;

[0131] As shown in Figures 10 to 17 and Figure 3 manufacturing the second wafer to be bonded 20: providing a second original wafer 21, forming a second dielectric layer 22 on the side to be bonded of the first original wafer 11, then forming a second metal block 27 on the second dielectric layer 22, to obtain the second wafer to be bonded 20.

[0132] In some embodiments, the method for forming the dielectric layer 12 comprises thermal oxidation and / or chemical vapor deposition.

[0133] In some embodiments, the method for forming the filling groove 13 comprises etching.

[0134] Exemplarily, the etching described in the embodiments of the present application can optionally comprise the following steps: applying a suitable etching glue on the dielectric layer 12 (for example), exposing, developing, performing a suitable etching method (for example, dry etching and / or wet etching) in the developed area after forming a etching pattern (for example, forming the filling groove 13 in the dielectric layer 12), and removing the glue. Further, the method for applying the glue comprises at least one of spin coating, nozzle coating or screen printing.

[0135] In some embodiments, the method of forming the first metal block 14 in the fill slot 13 comprises: depositing a first metal layer on the side of the dielectric layer 12 having the fill slot 13, removing the excess first metal layer to leave the first metal block 14 in the fill slot 13. In removing the first metal layer on the surface of the dielectric layer 12, some of the dielectric layer 12 can be removed as well, and the surface of the first metal block 14 left in the fill slot 13 can be treated to improve the smoothness and flatness of the surface for subsequent formation of a metal connection as a bonding surface, and to improve the quality of the bonding.

[0136] In some embodiments, the method of forming the first metal block 14 in the fill slot 13 further comprises: before depositing the first metal layer, depositing a first isolation layer on the side of the dielectric layer 12 having the fill slot 13, and then depositing the first metal layer on the first isolation layer, removing the excess first isolation layer and the first metal layer to leave the first isolation layer and the first metal block 14 in the fill slot 13.

[0137] In some embodiments, the method of depositing the first isolation layer comprises physical vapor deposition.

[0138] In some embodiments, the method of forming the first dielectric layer 15 comprises chemical vapor deposition.

[0139] In some embodiments, the method of forming the opening slot 16 comprises etching.

[0140] In the etching process of the opening slot 16, the formation of the first inclined side 17 and the angle of the first inclined side 17 can be adjusted by etching process parameters. For example, when dry etching (such as plasma assisted etching) is used, the angle of the bevel can be controlled by adjusting the power value of the radio frequency bias power and the type of gas. For wet etching, the angle of the bevel can be controlled by adjusting the revolution speed of the machine and the rotation speed of the wafer.

[0141] In some embodiments, the metal component of the first metal layer comprises copper and / or gold.

[0142] In some embodiments, the method of forming the second metal block 27 comprises any one of the following method one or method two:

[0143] Method one, as Figures 10 to 16 and Figure 3As shown, a second metal layer 23 and a dielectric auxiliary layer 24 are sequentially deposited on the second dielectric layer 22, a chamfered groove 25 is etched on the dielectric auxiliary layer 24, the chamfered groove 25 has the same profile shape as the second metal block 27; then a third metal layer is deposited on the side of the dielectric auxiliary layer 24 with the chamfered groove 25 to fill the chamfered groove 25 with copper, then the excess third metal layer outside the chamfered groove 25 is removed, then the dielectric auxiliary layer 24 is removed, and then the excess second metal layer 23 is removed, so that the remaining part of the third metal layer 26 in the chamfered groove and the remaining part of the second metal layer 23 below it constitute the second metal block 27.

[0144] As shown in mode two, a fourth metal layer 29 is deposited on the second dielectric layer 22, and the fourth metal layer 29 is etched to form the second metal block 27. Figure 10 、 Figure 11 、 Figure 17 and Figure 3 As shown in mode two, a fourth metal layer 29 is deposited on the second dielectric layer 22, and the fourth metal layer 29 is etched to form the second metal block 27.

[0145] In some embodiments, the method of forming the second dielectric layer 22 includes chemical vapor deposition.

[0146] In some embodiments, in mode one, the method of depositing the second metal layer 23, the third metal layer, and the fourth metal layer 29 all includes physical vapor deposition.

[0147] In some embodiments, in mode one, the method of depositing the dielectric auxiliary layer 24 includes chemical vapor deposition.

[0148] In some embodiments, in mode one, the method of etching the chamfered groove 25 includes etching.

[0149] In some embodiments, in mode one, the method of depositing the second metal layer 23 includes electroplating.

[0150] In some embodiments, in mode one, the method of removing the excess third metal layer outside the chamfered groove 25 includes chemical mechanical polishing.

[0151] In some embodiments, in mode one, the method of removing the dielectric auxiliary layer 24 includes dry etching.

[0152] In some embodiments, in mode one, the method of removing the second metal layer 23 includes etching.

[0153] In some embodiments, the first mode further comprises, before depositing the second metal layer 23, first depositing a second isolation layer on the second dielectric layer 22, and then depositing the second metal layer 23 on the second isolation layer; when removing the excess second metal layer 23, the excess second isolation layer is also removed to retain the portion of the second isolation layer under the second metal block 27.

[0154] In some embodiments, the second mode further comprises, before depositing the fourth metal layer 29, first depositing a second isolation layer on the second dielectric layer 22, and then depositing the fourth metal layer 29 on the second isolation layer; when etching the fourth metal layer 29, the excess second isolation layer is also etched to retain the portion of the second isolation layer under the second metal block 27.

[0155] In some embodiments, the metal components of the second metal layer, the third metal layer, and the fourth metal layer all include copper and / or gold.

[0156] In some embodiments, the material of the dielectric auxiliary layer 24 includes silicon oxide.

[0157] In one or more embodiments of the present application, a wafer-level hybrid bonding process is provided, which comprises:

[0158] As shown in FIG. 1, a hybrid bonding structure according to the above embodiments is provided, and one of the first wafer to be bonded 10 or the second wafer to be bonded 20 is taken as the upper wafer, and the other wafer to be bonded is taken as the lower wafer; Figure 18 The upper wafer and the lower wafer are pre-aligned, so that the second metal block 27 is initially aligned with the open groove 16;

[0159] As shown in FIG. 2, a point pressing process is performed to make the first dielectric layer 15 and the second dielectric layer 22 contact and adhere to each other. In this process, the second inclined side surface 28 of the second metal block 27 cooperates with the first inclined side surface 17 of the open groove 16, so that the second metal block 27 is embedded into the open groove 16, and the upper wafer and the lower wafer are precisely aligned;

[0160] Figure 19 As shown in FIG. 3, a surface pressing process is performed. After the surface pressing process is completed, the first dielectric layer 15 and the second dielectric layer 22 are connected, and the first metal block 14 and the second metal block 27 are connected.

[0161] In some embodiments, the pressure of the point pressing process is 1N-10N. For example, it can be 1N, 2N, 3N, 4N, 5N, 6N, 7N, 8N, 9N, or 10N, etc. Figure 20 In some embodiments, the pressure of the surface pressing process is 10N-100N. For example, it can be 10N, 20N, 30N, 40N, 50N, 60N, 70N, 80N, 90N, or 100N, etc.

[0162]

[0163] ​​In some embodiments, the duration of the point pressing treatment is 5s-15s. Exemplarily, it can be 5s, 6s, 7s, 8s, 9s, 10s, 11s, 12s, 13s, 14s, 15s, etc.

[0164] In some embodiments, the pressure of the surface pressing treatment is 100N-300N. Exemplarily, it can be 100N, 130N, 150N, 180N, 200N, 220N, 240N, 260N, 280N, 300N, etc.

[0165] In some embodiments, the duration of the surface pressing treatment is 1min-10min. Exemplarily, it can be 1min, 3min, 5min, 7min, 10min, etc.

[0166] In some embodiments, the surface pressing treatment is followed by annealing.

[0167] In some embodiments, the temperature of the annealing is 250℃-1000℃. Exemplarily, it can be 250℃, 300℃, 350℃, 400℃, 450℃, 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, 800℃, 850℃, 900℃, 950℃, 1000℃, etc.

[0168] In some embodiments, the annealing process comprises first annealing at 250℃-500℃ for 1h-3h, and then second annealing at 500℃-1000℃ for 1h-3h.

[0169] In some embodiments, the upper wafer is grabbed by vacuum suction of a chuck. The vacuum value of the vacuum suction is -500mbar--300mbar. Exemplarily, it can be -500mbar, -480mbar, -460mbar, -440mbar, -420mbar, -400mbar, -380mbar, -360mbar, -340mbar, -320mbar, -300mbar, etc.

[0170] Further, in some embodiments, the upper wafer is released by vacuum suction of the chuck in a partitioned manner after the point pressing treatment and before the surface pressing treatment.

[0171] As a further example, the precision after bonding can be observed according to the infrared camera, using the principle that the infrared light source can penetrate the silicon material, find the nested mark on the wafer, to measure the precision after bonding. For example, a first alignment mark can be provided in the first wafer to be bonded 10, and a second alignment mark can be provided on the second wafer to be bonded 20, after precise bonding is achieved by using the hybrid bonding structure and the hybrid bonding process of the above embodiment, the second alignment mark is nested in the first alignment mark, forming a concentric nested mark, as shown in Figure 21

[0172] In one or more embodiments of the present application, a bonding device is provided for performing the bonding process described in the above embodiments, the bonding device includes an upper loading platform and a lower loading platform arranged oppositely, respectively used to fix the upper wafer and the lower wafer;

[0173] A moving slide is provided for carrying the upper loading platform and / or the lower loading platform, for adjusting the relative position between the upper wafer and the lower wafer;

[0174] A force output part is connected to the upper loading platform or the lower loading platform, for performing point pressure and / or surface pressure between the upper wafer and the lower wafer.

[0175] Embodiment 1

[0176] The present embodiment provides a hybrid bonding structure in the above embodiments, as shown in Figures 1 to 2 and Figures 3 to 4 The hybrid bonding structure includes a first wafer to be bonded 10 and a second wafer to be bonded 20, both of which are 12-inch wafers.

[0177] The first wafer to be bonded 10 includes a first original wafer 11 of silicon, and a dielectric layer 12 with a thickness of 300 nm and a first dielectric layer 15 of silicon nitride with a thickness of 200 nm are laminated on the side to be bonded of the first original wafer 11. The dielectric layer 12 is provided with a filling groove 13, and the filling groove 13 is provided with a first metal block 14 in contact with the first original wafer 11. A first isolation layer of titanium with a thickness of 10 nm is further provided between the first original wafer 11 and the first metal block 14. The first dielectric layer 15 is provided with an opening groove 16 corresponding to the position of the filling groove 13, exposing a first metal block 14 with a diameter of 1 μm. In the opening groove 16, a first inclined side surface 17 is formed in the first dielectric layer 15. The first inclined angle θ1 of the first inclined side surface 17 is 45℃. The first wafer to be bonded 10 is further provided with a first alignment mark. The metal composition of the first metal block 14 is copper. The dielectric layer 12 is silicon oxide;

[0178] ​The second wafer to be bonded 20 comprises a second original wafer 21 of silicon, and a second dielectric layer 22 of silicon carbonitride with a thickness of 200 nm arranged on the side of the wafer to be bonded; a second metal block 27 with a diameter of 1 μm is arranged on the surface of the second dielectric layer 22 away from the second original wafer 21; and a second isolation layer of titanium with a thickness of 10 nm is arranged between the second original wafer 21 and the second metal block 27; the second metal block 27 has a second inclined side 28 matching the first inclined side 17, the second inclined side 28 has a second inclined angle θ2 with the thickness direction of the second metal block 27, and θ2 = θ1; the second wafer to be bonded 20 further comprises a second alignment mark; the metal component of the second metal block 27 is copper;

[0179] The thickness of the first metal block 14 is H1 = 290 nm, the thickness of the dielectric layer is H4 = 300 nm, the thickness of the second metal block 27 is H2 = 188 nm, and the thickness of the first dielectric layer 15 is H3 = 200 nm, as shown in Figure 19 When the first dielectric layer 15 and the second dielectric layer 22 are in contact during bonding, the opening slot 16 accommodates the second metal block 27, and an expansion gap L = 2 nm is reserved between the second metal block 27 and the first metal block 14.

[0180] The embodiment also provides a manufacturing method of the hybrid bonding structure, comprising:

[0181] S10. Providing a first original wafer 11 and a second original wafer 21, before further arranging a related layer structure, the first original wafer 11 and the second original wafer 21 are cleaned by a cleaning process to make the surface clean, the surface roughness Ra is ≤ 0.5 nm (0.5 μm x 0.5 μm area), the bending degree Bow value is -40 μm ~ 40 μm, and the total thickness deviation TTV value is ≤ 5 μm.

[0182] S20. As shown in Figures 5 to 9 Figure 1 As shown in Figure 2 The first wafer to be bonded 10 is manufactured:

[0183] S21. Taking the first original wafer 11, and forming a dielectric layer 12 on the side of the first original wafer 11 to be bonded by thermal oxidation;

[0184] S22. Forming a filling slot 13 in the dielectric layer 12 by etching, specifically, coating glue on the dielectric layer 12 by spin coating, after exposure and development, wet etching is performed in the developed area to form the filling slot 13;

[0185] ​S23. Form a first isolation layer on the side of the dielectric layer 12 with the filling groove 13 by physical vapor deposition, and then form a first metal layer on the first isolation layer by physical vapor deposition, which is a copper layer. Remove the excess first isolation layer and the first metal layer to retain the formed part of the first isolation layer and the first metal block 14 in the filling groove 13;

[0186] S24. Form a first dielectric layer 15 on the dielectric layer 12 and the first metal layer by chemical vapor deposition, and then etch an opening groove 16 in the first dielectric layer 15 corresponding to the position of the filling groove 13 to obtain a first to-be-bonded wafer 10. Then, glue is applied on the first dielectric layer 15 by jet coating, and after exposure and development, dry etching is performed in the developed area. The dry etching is plasma-assisted etching. By controlling the power value of the radio frequency bias power and the etching gas, the first inclined angle of the first inclined side 17 is controlled while the filling groove 13 is formed. The first to-be-bonded wafer 10 is obtained.

[0187] S30. As shown in Figures 10 to 16 In order to Figure 3 With Figure 4 The second to-be-bonded wafer 20 is manufactured as follows:

[0188] S31. Take the second original wafer 21, and form a second dielectric layer 22 on the to-be-bonded side of the first original wafer 11 by chemical vapor deposition.

[0189] S32. Form a second isolation layer on the second dielectric layer 22, and then form a second metal layer 23 on the second isolation layer by electroplating, which is a copper layer. Then, a dielectric auxiliary layer 24 is formed by chemical vapor deposition. The dielectric auxiliary layer 24 is silicon oxide.

[0190] S33. Form a chamfer groove 25 on the dielectric auxiliary layer 24 by etching, that is, glue is applied on the dielectric auxiliary layer 24 by screen printing, and after exposure and development, dry etching is performed in the developed area. The profile shape of the chamfer groove 25 is the same as that of the second metal block 27. That is, the inclined angle of the inclined side in the chamfer groove 25 is controlled by dry etching, so that the second inclined side wall in the second metal block 27 reaches the target second inclined angle.

[0191] S34. Then, a third metal layer is deposited on the side of the dielectric auxiliary layer 24 with the chamfered groove 25, which is a copper layer, to fill the chamfered groove 25 with copper, and then the excess third metal layer outside the chamfered groove 25 is removed, followed by removing the dielectric auxiliary layer 24, and then removing the excess second metal layer 23 and the excess second isolation layer, so that the remaining part of the third metal layer 26 in the chamfered groove and the remaining part of the second metal layer 23 below it constitute the second metal block 27, and the part of the second isolation layer below the second metal block 27 is retained; thus, the second wafer to be bonded 20 is obtained.

[0192] Embodiment 2

[0193] The embodiment provides a hybrid bonding structure in the above-mentioned embodiments, and the difference from the embodiment 1 includes that the first wafer to be bonded 10 and the second wafer to be bonded 20 are both 8-inch wafers; in the first wafer to be bonded 10, the first original wafer 11 is silicon carbide, the first isolation layer is Ta / TaN, the first inclination angle θ1 of the first inclined side surface 17 in the first dielectric layer 15 is 60°, the metal components of the first metal block 14 and the second metal block 27 are both gold, and the manufacturing process of the second wafer to be bonded 20 is different, specifically, in the manufacturing method of the hybrid bonding structure, as shown in steps S30 to S34 are replaced by the following steps: Figure 10 、 Figure 11 、 Figure 17 and Figure 3 and Figure 4 .

[0194] S40. Manufacturing the second wafer to be bonded 20:

[0195] S41. Taking the second original wafer 21, and forming the second dielectric layer 22 on the bonding side of the first original wafer 11 by chemical vapor deposition;

[0196] S42. Depositing the second isolation layer on the second dielectric layer 22, and then forming the fourth metal layer 29 on the second isolation layer by electroplating;

[0197] S43. Etching the fourth metal layer 29 to form the second metal block 27; that is, glue is coated on the fourth metal layer 29 by spin coating, after exposure and development, dry etching and wet etching are performed in the developed area to remove the excess second metal layer 23 and the excess second isolation layer, thereby forming the second metal block 27 and retaining the part of the second isolation layer below the second metal block 27; thus, the second wafer to be bonded 20 is obtained.

[0198] Application Example 1

[0199] The application example provides a hybrid bonding process using the hybrid bonding structure of embodiment 1 or embodiment 2, which is performed using the bonding equipment provided in the foregoing embodiments, as shown in Figures 18 to 20 The hybrid bonding process includes the following steps:

[0200] Step 1) using the hybrid bonding structure of the first aspect, the first to-be-bonded wafer 10 is used as the lower wafer, and the second to-be-bonded wafer 20 is used as the upper wafer, which is grabbed by vacuum suction of the chuck, and the vacuum value of the vacuum suction is -400 mbar; the upper wafer and the lower wafer are pre-aligned, so that the second metal block 27 in the upper wafer is initially aligned with the opening groove 16 in the lower wafer;

[0201] Step 2) point pressure treatment is performed to make the first dielectric layer 15 in the lower wafer and the second dielectric layer 22 in the upper wafer contact and adhere, and in this process, the second inclined side surface 28 of the second metal block 27 in the upper wafer cooperates with the first inclined side surface 17 of the opening groove 16 in the lower wafer, so that the second metal block 27 is embedded into the opening groove 16, and the fine alignment of the upper wafer and the lower wafer is realized; the pressure of the point pressure treatment is set to 2N, the point pressure treatment lasts for 10s, and after the point pressure, the vacuum of the upper chuck is released from the center to the edge in turn;

[0202] Step 3) face pressure treatment is performed, and the face pressure treatment pressure is set to 300N. After the face pressure treatment is completed, the first dielectric layer 15 and the second dielectric layer 22 are connected, and at the same time, the first metal block 14 and the second metal block 27 are connected. After the face pressure treatment for 5min, annealing is further performed, the annealing temperature is set to 300℃, and the annealing lasts for 2h.

[0203] After the precise hybrid bonding is realized, the second alignment mark is nested in the first alignment mark, forming a concentric nested mark, as shown in Figure 21 which shows the high precision of the hybrid bonding process.

[0204] Comparative Example 1

[0205] The comparative example provides a hybrid bonding structure in the foregoing embodiments, which is different from embodiment 1, including that the first inclined angle θ1 of the first inclined side surface 17 in the first to-be-bonded wafer 10 is 0°, that is, no inclination is performed, and the second inclined angle θ2 of the second inclined side surface 28 in the second to-be-bonded wafer 20 is also 0°, that is, no inclination is performed, and other conditions are the same as those of embodiment 1.

[0206] When the first inclined angle θ1 of the first inclined side surface 17 in the first to-be-bonded wafer 10 is 0°, if the roughness of the inclined side surface is sufficient, the first wafer can achieve force balance, but Figure 19The distance between the two copper blocks is the height L, and the inside is air, which cannot be discharged during annealing, and finally cannot form the effect of metal interconnection.

[0207] Comparing application example 1 with comparative example 1, it is found that: in the mixed bonding process of application example 1, the point pressure is first applied, the point pressure is small, and the point pressure is first applied at the center of the wafer, so that the center of the wafer is first contacted with the surface, and then the diffusion is spread like a wave, which can discharge the air between the two bonding surfaces; on the other hand, since the mixed bonding structure in example 1 and example 2 is provided with an inclined side surface, the first metal block and the second metal block can be adjusted in position under the cooperation of the inclined side surface during bonding, so as to improve the bonding accuracy, which is beneficial to avoid that the first metal block and the second metal block are pressed under the condition that the position is not adjusted, and the air gap is easily generated at the contact position; the gap between the first metal block and the second metal block will be blocked after the material thermal expansion, and the trace gas can be removed by micro-reaction during high-temperature annealing, or uniformly remain on the interface, and will not gather to form a large cavity. In comparative example 1, since the inclined side surface is not provided, it is impossible to directly align with high accuracy during bonding due to mechanical vibration and other factors, and the interference between the convex block and the side wall of the groove will not be adjusted in a trace. If the width of the groove is excessively increased at this time, although the convex block can be smoothly inserted, the convex block and the groove side wall will have a gap, which is not conducive to improving the bonding accuracy.

[0208] As can be seen from the above, the present application improves the accuracy of bonding alignment by making a specific structure on the surface of the wafer to be bonded, that is, by constructing the first inclined side surface and the second inclined side surface matched with each other in the opening groove and the second metal block, so as to effectively improve the accuracy of bonding alignment. During the implementation of bonding, the designed inclined side surface can be fully utilized, so that the alignment position and the bonding position of the two wafers to be bonded are corrected, and the error caused by mechanical movement, vibration and other factors is avoided, so that the offset is kept lower. The present application further provides a suitable expansion gap, which can be used as a free space for copper thermal expansion during heat treatment of the bonded wafer, which is beneficial to ensure the quality of metal interconnection after bonding, and can effectively control the stress of the bonded material.

[0209] The above describes the preferred embodiments of the present application, but the present application is not limited to the specific details in the above embodiments, and various simple modifications can be made to the technical solutions of the present application within the technical concept of the present application, which all belong to the protection scope of the present application.

[0210] In addition, it should be noted that each specific technical feature described in the above specific embodiments can be combined in any suitable manner without contradiction, and in order to avoid unnecessary repetition, the present application will not further describe various possible combinations.

[0211] Furthermore, the various embodiments can also be combined, if not in contradiction, as long as they do not deviate from the spirit of the present application, which should be considered as disclosed.

Claims

1. A hybrid bonding structure, characterized in that, The hybrid bonding structure includes a first wafer to be bonded and a second wafer to be bonded; The first wafer to be bonded includes a first raw wafer, and a dielectric layer and a first dielectric layer stacked on the side to be bonded thereon; the dielectric layer has a filling groove, and a first metal block in contact with the first raw wafer is disposed in the filling groove; the first dielectric layer has an opening groove corresponding to the position of the filling groove, exposing the first metal block; a first inclined side surface is formed in the first dielectric layer in the opening groove. The second wafer to be bonded includes a second original wafer and a second dielectric layer disposed on one side of the surface to be bonded. A protruding second metal block is provided on the surface of the second dielectric layer away from the second original wafer; The opening slot and the second metal block are configured such that the second metal block has a second inclined side that matches the first inclined side, and the opening slot accommodates the second metal block when the first dielectric layer and the second dielectric layer are in contact during bonding.

2. The hybrid bonding structure according to claim 1, characterized in that, The first inclined side and the second inclined side satisfy at least one of the following conditions: (a1) The angle between the first inclined side and the thickness direction of the first dielectric layer is the first inclined angle θ1, where 0° < θ1 < 90°; (a2) 25° < θ1 < 65°; (a3) 40° < θ1 < 50°; (a4) The angle between the second inclined side and the thickness direction of the second metal block is the second inclined angle θ2, θ2=θ1.

3. The hybrid bonding structure according to claim 1, characterized in that, The first metal block and the second metal block satisfy at least one of the following conditions: (b1) The thickness of the first metal block is equal to the thickness of the dielectric layer; (b2) When the first dielectric layer and the second dielectric layer are in contact during bonding, the opening groove accommodates the second metal block, and an expansion gap is maintained between the second metal block and the first metal block; (b3) The thickness of the second metal block is less than or equal to the thickness of the first dielectric layer; (b4) The thickness of the first metal block is H1, the thickness of the second metal block is H2, and the size of the expansion gap is L. Then L = ((H1 + H2) × α × (T - T0))β, where α is the linear thermal expansion coefficient of the metal, in units of 10. -6 / ℃; T is the maximum processing temperature during bonding; T0 is the initial ambient temperature before bonding; β is an empirical coefficient, β is taken from 0.7 to 1.3; (b5) The metal composition of the first metal block includes copper and / or gold; (b6) The metal composition of the second metal block includes copper and / or gold.

4. The hybrid bonding structure according to claim 1, characterized in that, The hybrid bonding structure also satisfies at least one of the following conditions: (c1) Both the first original wafer and the second original wafer comprise at least one of silicon, glass, SiC, SiN or LiTaO3; (c2) A first isolation layer is provided in the filling groove, and the first isolation layer is disposed between the first original wafer and the first metal block; (c3) The second wafer to be bonded further includes a second isolation layer, which is disposed between the second dielectric layer and the second metal block; (c4) The first isolation layer includes at least one of Ti, Ta, or TaN; (c5) Both the first dielectric layer and the second dielectric layer comprise silicon nitride and / or silicon carbonitride; (c6) The dielectric layer comprises silicon oxide.

5. A method for manufacturing the hybrid bonding structure according to any one of claims 1-4, characterized in that, The manufacturing method includes: Fabricating a first wafer to be bonded: providing a first raw wafer, forming a dielectric layer on the side of the first raw wafer to be bonded; forming a filling trench in the dielectric layer, and then forming a first metal block in the filling trench; forming a first dielectric layer to cover the dielectric layer and the first metal block, and then forming an opening trench in the first dielectric layer corresponding to the position of the filling trench, to obtain the first wafer to be bonded; Manufacturing a second wafer to be bonded: A first raw wafer is provided, a second dielectric layer is formed on the side of the second raw wafer to be bonded, and then a second metal block is formed on the second dielectric layer to obtain a second wafer to be bonded.

6. The method for manufacturing the hybrid bonding structure according to claim 5, characterized in that, The first wafer to be bonded satisfies at least one of the following conditions: (d1) Methods for forming a dielectric layer include thermal oxidation and / or chemical vapor deposition; (d2) Methods for forming filling grooves include etching; (d3) A method for forming a first metal block in a filling trench includes: depositing a first metal layer on one side of a dielectric layer having the filling trench, removing excess first metal layer to retain the first metal block within the filling trench; (d4) The method of forming a first metal block in a filling tank further includes: before depositing to form a first metal layer, first depositing to form a first isolation layer on the side of the dielectric layer having the filling tank, then depositing to form a first metal layer on the first isolation layer, removing excess first isolation layer and first metal layer, so as to retain a portion of the first isolation layer and the first metal block in the filling tank; (d5) Methods for depositing the first isolation layer include physical vapor deposition; (d6) The method for forming the first dielectric layer includes chemical vapor deposition; (d7) Methods for forming the opening groove include etching; (d8) The metal composition of the first metal layer includes copper and / or gold.

7. The method for manufacturing the hybrid bonding structure according to claim 5, characterized in that, The method for forming the second metal block includes either method one or method two: Method 1: A second metal layer and a dielectric auxiliary layer are sequentially deposited on the second dielectric layer. A chamfered groove is etched on the dielectric auxiliary layer, and the outline shape of the chamfered groove is the same as that of the second metal block. Then, a third metal layer is deposited on the side of the dielectric auxiliary layer with the chamfered groove to fill the chamfered groove with metal. Then, the excess third metal layer outside the chamfered groove is removed, followed by the removal of the dielectric auxiliary layer, and then the excess second metal layer is removed, so that the part of the third metal layer remaining in the chamfered groove and the part of the second metal layer remaining below it constitute the second metal block. Method 2 involves depositing a fourth metal layer on the second dielectric layer, and then etching the fourth metal layer to form the second metal block.

8. The method for manufacturing the hybrid bonding structure according to claim 7, characterized in that, The second wafer to be bonded satisfies at least one of the following conditions: (e1) Methods for forming the second dielectric layer include chemical vapor deposition; (e2) In Method 1, the methods for depositing the second, third, and fourth metal layers all include physical vapor deposition; (e3) In Method 1, the method for depositing the dielectric auxiliary layer includes chemical vapor deposition; (e4) In Method 1, the method of etching to form the chamfer groove includes etching; (e5) In Method 1, the method for depositing the second metal layer includes electroplating; (e6) In Method 1, the method for removing the excess third metal layer other than the chamfer groove includes chemical mechanical polishing; (e7) In Method 1, the method for removing the dielectric auxiliary layer includes dry etching; (e8) In Method 1, the method for removing the second metal layer includes etching; (e9) Method 1 further includes depositing a second isolation layer on the second dielectric layer before depositing the second metal layer, and then depositing the second metal layer on the second isolation layer; when removing the excess second metal layer, the excess second isolation layer is also removed so as to retain a portion of the second isolation layer below the second metal block; (e10) Method 2 further includes depositing a second isolation layer on the second dielectric layer before depositing the fourth metal layer, and then depositing the fourth metal layer on the second isolation layer; when etching the fourth metal layer, the excess second isolation layer is simultaneously etched away to retain a portion of the second isolation layer below the second metal block. (e11) The metal composition of the second metal layer, the third metal layer and the fourth metal layer all include copper and / or gold; (e12) The material of the dielectric auxiliary layer includes silicon oxide.

9. A hybrid bonding process, characterized in that, The hybrid bonding process includes: The hybrid bonding structure according to any one of claims 1-8 is provided, wherein one of the first wafer to be bonded or the second wafer to be bonded is used as the upper wafer, and the other wafer to be bonded is used as the lower wafer; The upper and lower wafers are pre-aligned to align the second metal block with the slot. A point pressing process is performed to bring the first dielectric layer and the second dielectric layer into contact. During this process, the second inclined side of the second metal block cooperates with the first inclined side of the opening slot, so that the second metal block is embedded in the opening slot, thereby achieving precise alignment between the upper wafer and the lower wafer. A surface pressing process is performed. After the surface pressing process is completed, the first dielectric layer and the second dielectric layer are connected, and the first metal block and the second metal block are connected.

10. The hybrid bonding process according to claim 9, characterized in that, The hybrid bonding process satisfies at least one of the following conditions: (f1) The pressure of the point pressure treatment is 1N~10N; (f2) The duration of the point pressure treatment is 5s~15s; (f3) The pressure of the surface pressing treatment is 100N~300N; (f4) The duration of the surface pressing treatment is 1 min to 10 min; (f5) Annealing is performed after the surface pressing process is completed; (f6) The annealing temperature is 250℃~1000℃; (f7) The annealing process includes a first annealing at 250℃~500℃ for 1h~3h, followed by a second annealing at 500℃~1000℃ for 1h~3h. (f8) The upper wafer is gripped by vacuum adsorption using a chuck, with a vacuum value of -500mbar to -300mbar. After the point pressure treatment is completed and before the surface pressure treatment begins, the upper wafer vacuum adsorbed by the chuck is vacuum released in sections.

11. A bonding apparatus for performing the hybrid bonding process of claim 9 or 10, characterized in that, It includes an loading stage and a downloading stage arranged opposite to each other, which are used to fix the upper wafer and the lower wafer respectively; A movable slide is used to carry the loading stage and / or the downloading stage, and to adjust the relative position between the upper wafer and the lower wafer. A force output unit, connected to the upper stage or the lower stage, is used to perform point pressure and / or surface pressure between the upper wafer and the lower wafer.

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