Testing device, wafer and testing method

Abstract

The embodiment of the invention provides a test device, a wafer and a test method, the test device comprises a control circuit, M welding pad groups and N test unit groups, M and N are integers greater than 1, the number of test units included in each test unit group is less than or equal to M, and the total number of the test units is greater than M; and the control circuit is configured to receive a test signal, select one of the N test unit groups based on the test signal, and enable at least part of the M welding pad groups to be connected with the test units in the selected test unit group in a one-to-one correspondence manner.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and more particularly, to a testing device, wafer and testing method. BACKGROUND

[0002] In a semiconductor manufacturing process, it is usually necessary to manufacture a wafer acceptance test (WAT) structure on a scribe line between semiconductor devices on a wafer, so as to perform wafer acceptance test after the completion of integrated circuit manufacturing and before the wafer is shipped. However, with the improvement of the semiconductor manufacturing process, the size of the semiconductor device is reduced, the number of semiconductor devices formed on the same wafer is increased, the area of the scribe line is reduced, and the number of process flows and test units that need to be monitored is also increased. How to quickly find and solve problems in the process flow and test unit and reduce the impact on the yield of the semiconductor device becomes a problem to be solved. SUMMARY

[0003] Therefore, the main purpose of the present disclosure is to provide a testing device, wafer and testing method.

[0004] To achieve the above purpose, the technical solution of the present disclosure is as follows:

[0005] According to a first aspect of the embodiments of the present disclosure, a testing device is provided, comprising: a control circuit, M pad groups and N test unit groups, M and N are both integers greater than 1, the number of test units included in each test unit group is less than or equal to M, and the total number of test units is greater than M; the control circuit is configured to: receive a test signal, select one of the N test unit groups based on the test signal, and make at least part of the M pad groups one-to-one connected with the test units in the selected test unit group.

[0006] In the above scheme, at least one pad group is connected with a plurality of test units located in different test unit groups.

[0007] In the above scheme, the same test unit is connected with at most one pad group.

[0008] In the scheme, the control circuit comprises a first sub-control circuit and a second sub-control circuit; the second sub-control circuit is connected with the first sub-control circuit, the M pad groups and the N test unit groups; the first sub-control circuit is configured to generate a selection signal based on the test signal, the selection signal being used to indicate a selected one of the N test unit groups; the second sub-control circuit is configured to receive the selection signal and turn on the connection between the test units in the selected test unit group and at least part of the pad groups according to the selection signal.

[0009] In the scheme, the first sub-control circuit comprises at least a decoder, the decoder having N outputs; the decoder is configured to receive the test signal and output N-bit selection signals to the second sub-control circuit through the N outputs.

[0010] In the scheme, the first sub-control circuit comprises a decoder and N comparators.

[0011] The outputs of the decoder are connected with the inputs of the N comparators, the outputs of the N comparators corresponding to the N test unit groups one by one; the decoder is configured to receive the test signal and output decoding signals to the inputs of the N comparators; each comparator is configured to receive a reference signal and the decoding signals and output 1-bit sub-selection signals, the N 1-bit sub-selection signals output by the N comparators forming N-bit selection signals; each test unit group corresponds to a unique reference signal.

[0012] In the scheme, the second sub-control circuit comprises N groups of transistors, the N groups of transistors being connected with the N test unit groups one by one; in each group of transistors, the first controlled end of a transistor is connected with a pad group, the second controlled end is connected with the test unit corresponding to the pad group, and the control end is used to receive one bit of the N-bit selection signals.

[0013] In the scheme, the number of terminals to be led out of each test unit is one or more; each pad group comprises the same number of pads as the number of terminals to be led out of each test unit.

[0014] In the scheme, the test unit is a word line or a bit line.

[0015] In the scheme, N equals 2, M equals 4, each test unit group comprises 4 word lines, the second sub-control circuit of the control circuit comprises 2 groups of transistors, the 2 groups of transistors corresponding to the 2 test unit groups one by one, each group of transistors comprising 4 transistors, and each pad group being connected with 2 test units in different test unit groups.

[0016] In the above solution, the plurality of word lines or bit lines included in each of the test unit groups have a spaced relationship.

[0017] In the above solution, at least two of the plurality of word lines or bit lines included in each of the test unit groups have an adjacent relationship.

[0018] According to a second aspect of the embodiments of the present disclosure, a wafer is provided, including: a plurality of semiconductor devices; scribe lanes respectively located between the semiconductor devices to separate the semiconductor devices; and a test device as any of the first aspect located in the scribe lanes.

[0019] According to a third aspect of the embodiments of the present disclosure, a test method is provided, including: receiving a test signal; selecting one of N test unit groups based on the test signal, and connecting at least part of M pad groups to the test units in the selected test unit group one by one; wherein M and N are both integers greater than 1, the number of test units included in each of the test unit groups is less than or equal to M, and the total number of test units is greater than M.

[0020] In the above solution, the test method further includes: testing the test units in the selected test unit group via at least part of the test pad groups by a test probe.

[0021] In the above solution, the test method includes: based on the test signal, generating a selection signal for indicating that one of the N test unit groups is selected; receiving the selection signal, and turning on the connection between the test units in the selected test unit group and at least part of the pad groups according to the selection signal.

[0022] The test device provided by the embodiments of the present disclosure can meet the demand of obtaining the electrical performance of each test unit through the pad group by reasonably grouping a plurality of test units and multiplexing at least part of the pad groups in a limited number of pad groups through a control circuit, so that at least part of the pad groups are connected to the test units in the selected test unit group one by one when one test unit group is selected for testing, thereby facilitating to provide a numerical reference for the design of the semiconductor device and improving the yield of the semiconductor device. At the same time, the number of pad groups does not need to be additionally increased, thereby facilitating to improve the area utilization rate of the wafer. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A block diagram of a test device according to an embodiment of the present disclosure Figure 1 ;

[0024] Figure 2 A block diagram of a test device according to an embodiment of the present disclosureFigure 2 ;

[0025] Figure 3 Block diagram of a test device according to an embodiment of the present disclosure Figure 3 ;

[0026] Figure 4 Block diagram of a test device according to an embodiment of the present disclosure Figure 4 ;

[0027] Figure 5 Block diagram of a test device according to an embodiment of the present disclosure Figure 5 ;

[0028] Figure 6 Block diagram of a test device according to an embodiment of the present disclosure Figure 6 ;

[0029] Figure 7 Circuit structure schematic of a test device according to an embodiment of the present disclosure Figure 1 ;

[0030] Figure 8 Circuit structure schematic of a test device according to an embodiment of the present disclosure Figure 2 ;

[0031] Figure 9 Circuit structure schematic of a first sub-control circuit according to an embodiment of the present disclosure

[0032] Figure 10 Schematic diagram of a test unit group division manner according to an embodiment of the present disclosure

[0033] Figure 11 Schematic diagram of a wafer according to an embodiment of the present disclosure

[0034] Figure 12 Implementation flow schematic diagram of a test method according to an embodiment of the present disclosure DETAILED DESCRIPTION

[0035] The technical solutions of the present disclosure will be further described in detail below in combination with the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] The present disclosure will be described with respect to the following drawings in order to explain the present disclosure more clearly. The advantages and features of the present disclosure will be more apparent from the following description. It is noted that the drawings are very simplified and are not drawn to precise scale, and are used merely to facilitate the description of the embodiments of the present disclosure.

[0037] It should be understood that spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then a dependent element described as "below" or "beneath" or "under" another element or feature would then be oriented "above" and "on" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] In order to enable a more detailed understanding of the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure.

[0040] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0041] With the continuous development of semiconductor devices, the process flow contains many complex process steps, and specific process manufacturing deviations may exist in each step, which eventually leads to a reduction in yield. In order to improve the yield of semiconductor devices, it is common to obtain the data necessary for manufacturing process and design yield improvement through wafer acceptance testing.

[0042] However, as the semiconductor device is more complex, the number of test units corresponding to the semiconductor device in the scribe lane also increases. Considering that the area of the solder pad is large, the number of solder pads arranged in the scribe lane is often less than the number of test units, so the number of solder pads in the scribe lane is difficult to realize effective monitoring of the process flow and test units, so as to quickly find and solve problems in the process flow and test units, thereby affecting the yield of the semiconductor device.

[0043] For example, there are at least the same solder pad in the scribe lane simultaneously connected with multiple test units, such as Figure 1 As shown in FIG. 1, four solder pads are connected with eight test units, wherein the first solder pad 131 is connected with four test units 120, the second solder pad 132 is connected with one test unit 120, the third solder pad 133 is connected with one test unit 120, and the fourth solder pad 134 is connected with two test units 120, so it is impossible to separately obtain the electrical performance of each of the eight test units, for example, it is impossible to separately obtain the electrical performance of each of the four test units 120 connected with the first solder pad 131, which is not conducive to providing numerical reference for the design of the semiconductor device. However, increasing the number of solder pads will increase the occupied area of the scribe lane, which is not conducive to improving the area utilization rate of the wafer. Figure 1

[0044] Based on this, the embodiment of the present disclosure provides a test device, as shown in Figure 2 As shown in FIG. 2, the test device 200 includes a control circuit 210, M solder pad groups 230, and N test unit groups 220, M and N are integers greater than 1, the number of test units included in each test unit group 220 is less than or equal to M, and the total number of test units is greater than M; the control circuit 210 is configured to receive a test signal, select one of the N test unit groups 220 based on the test signal, and make at least part of the M solder pad groups 230 one-to-one connected with the test units in the selected test unit group.

[0045] It should be noted that the number of test units included in each test unit group can be the same or different, provided that the number of test units included in each test unit group is less than or equal to the number of solder pad groups, the number of test units included in each test unit group can be set according to actual needs.

[0046] In some embodiments, at least one solder pad group is connected with multiple test units located in different test unit groups.

[0047] In some embodiments, as Figure 3 ​As shown, the testing device includes four pad groups (a first pad group 231, a second pad group 232, a third pad group 233, and a fourth pad group 234) and two testing unit groups (a first testing unit group 221 and a second testing unit group 222), each of which includes four testing units 240. Each pad group is connected to two testing units located in different testing unit groups. For example, the first pad group 231 is connected to one testing unit located in the first testing unit group 221 and one testing unit located in the second testing unit group 222.

[0048] In some embodiments, when the first testing unit group 221 is the selected testing unit group and the second testing unit group 222 is the unselected testing unit group, the first pad group 231, the second pad group 232, the third pad group 233, and the fourth pad group 234 are connected to the testing units 240 in the selected first testing unit group 221 one-to-one.

[0049] When the second testing unit group 222 is the selected testing unit group and the first testing unit group 221 is the unselected testing unit group, the first pad group 231, the second pad group 232, the third pad group 233, and the fourth pad group 234 are connected to the testing units 240 in the selected second testing unit group 222 one-to-one.

[0050] In other embodiments, as shown, Figure 4 As shown, the testing device includes four pad groups (a first pad group 231, a second pad group 232, a third pad group 233, and a fourth pad group 234) and four testing unit groups (a first testing unit group 221, a second testing unit group 222, a third testing unit group 223, and a fourth testing unit group 224), each of which includes four testing units 240. Some pad groups are connected to multiple testing units located in different testing unit groups, and some pad groups are connected to only one testing unit located in one testing unit group. For example, the first pad group 231 is connected to one testing unit located in the first testing unit group 221 and one testing unit located in the second testing unit group 222. The second pad group 232 is connected to only one testing unit located in the first testing unit group 221. The third pad group 233 is connected to one testing unit located in the first testing unit group 221 and one testing unit located in the second testing unit group 222. The fourth pad group 234 is connected to one testing unit located in the first testing unit group 221, one testing unit located in the third testing unit group 223, and one testing unit located in the fourth testing unit group 224.

[0051] In some embodiments, when the first test unit group 221 is the selected test unit group, the first pad group 231, the second pad group 232, the third pad group 233 and the fourth pad group 234 are connected to the four test units 240 in the selected first test unit group 221 one by one.

[0052] When the second test unit group 222 is the selected test unit group, the first pad group 231 and the third pad group 233 are connected to the two test units 240 in the selected second test unit group 222 one by one.

[0053] When the third test unit group 223 is the selected test unit group, the fourth pad group 234 is connected to the one test unit 240 in the selected third test unit group 223.

[0054] When the fourth test unit group 224 is the selected test unit group, the fourth pad group 234 is connected to the one test unit 240 in the selected fourth test unit group 224.

[0055] In this way, by reasonably grouping the plurality of test units and by the control circuit multiplexing at least part of the pad groups, when a test unit group is selected for testing, at least part of the pad groups are connected to the test units in the selected test unit group one by one, thus meeting the requirement of obtaining the electrical performance of each test unit through the pad group alone, which is conducive to providing numerical reference for the design of semiconductor devices and improving the yield of semiconductor devices. At the same time, without the need to additionally increase the number of pad groups, it is conducive to improving the area utilization rate of the wafer.

[0056] It should be noted that, in order to facilitate the description of the correspondence between the test unit group and the pad group, Figure 3 and Figure 4 are brief diagrams after omitting the control circuit between the test unit group and the pad group in Figure 2 The specific connection relationship between the control circuit and the test unit group and the pad group will be further described in the following.

[0057] In some embodiments, at most one test unit in the same test unit group is connected to the same pad group. Exemplarily, as shown in Figure 3 and Figure 4 Any one pad group will not be connected to multiple test units located in the same test unit group at the same time, so that when a test unit group is selected, the same pad group will not be connected to multiple test units at the same time.

[0058] In some embodiments, the same test unit is connected to at most one pad set. The electrical performance of a test unit can be obtained via a single pad set, thus avoiding connection of the same test unit to multiple pad sets and maximizing the utilization of the pad sets.

[0059] In some embodiments, the number of terminals to be brought out in each test unit is one or more; the number of solder pads included in each pad group is the same as the number of terminals to be brought out in each test unit. In other words, the electrical performance of a test unit can be obtained via a pad group.

[0060] In some embodiments, the test unit is a four-terminal device, such as a field-effect transistor, with the four terminals being the source, drain, gate, and base, and each pad group includes 4 pads.

[0061] In some embodiments, the test unit is a two-terminal device, such as a resistor and / or capacitor, and each pad group includes 2 pads.

[0062] In some embodiments, the test unit is a word line or a bit line, and each pad group includes 1 pad.

[0063] It should be noted that the types and quantities of the test units mentioned above are only examples, and the embodiments disclosed herein are not limited thereto. The types and quantities of test units and the number of solder pads included in each pad group can be reasonably set as needed.

[0064] In some embodiments, such as Figure 5 As shown, the control circuit 210 includes a first sub-control circuit 211 and a second sub-control circuit 212; the second sub-control circuit 212 is connected to the first sub-control circuit 211, M pad groups 230 and N test unit groups 220; the first sub-control circuit 211 is configured to generate a selection signal based on a test signal, the selection signal being used to indicate the selection of one of the N test unit groups 220; the second sub-control circuit 212 is configured to receive the selection signal and, according to the selection signal, connect the test unit in the selected test unit group 220 to at least a portion of the pad groups 230.

[0065] In some embodiments, the first sub-control circuit includes at least a decoder having N output terminals; the decoder is configured to receive a test signal and output an N-bit selection signal to the second sub-control circuit through the N output terminals.

[0066] In some embodiments, an even number of inverters can be connected to the output of the decoder to increase the driving capability of the circuit.

[0067] In some implementations, the decoder has P inputs and N outputs, where P and N are both integers greater than 1, and N = 2^N.P For example, the decoder of the first sub-control circuit is configured to receive a P-bit test signal and output an N-bit selection signal to the second sub-control circuit through N output terminals. For each received test signal, only one of the N output terminals of the decoder is active, while the remaining output terminals are inversely active. The output signal can be active high or active low.

[0068] It should be noted that the choice of decoder is related to the number of test unit groups, and the number of decoder outputs is equal to the number of test unit groups.

[0069] Optionally, the decoder includes, but is not limited to, 2-to-4 decoders, 3-to-8 decoders, and 4-to-16 decoders.

[0070] For example, with Figure 4 Taking the test device shown as an example with 4 test unit groups, the decoder can be a 2-to-4 decoder, that is, the decoder has 2 input terminals (A and B) and 4 output terminals (Y0, Y1, Y2 and Y3). Table 1 is the truth table of the 2-to-4 decoder. According to Table 1, when the decoder receives 2 test signals of 00, the output 4-bit selection signal is 0111; when the decoder receives 2 test signals of 10, the output 4-bit selection signal is 1011; when the decoder receives 2 test signals of 01, the output 4-bit selection signal is 1101; and when the decoder receives 2 test signals of 11, the output 4-bit selection signal is 1110.

[0071] It should be noted that in this embodiment, the active-low level is set. Typically, 2-4 decoders also have an enable input; the decoder can only function properly when the enable input is active (usually active-low). If the enable input is inactive, all outputs will be high, indicating that all four outputs of the decoder are inactive.

[0072] Table 1

[0073]

[0074] In some embodiments, the correspondence between test signals and test unit groups can be preset. For example, a test signal of 00 indicates selection of the first test unit group; a test signal of 10 indicates selection of the second test unit group; a test signal of 01 indicates selection of the third test unit group; and a test signal of 11 indicates selection of the fourth test unit group.

[0075] It should be noted that Table 1 is only an exemplary illustration of the truth table of one decoder. Different decoders may have different enable pins and output valid levels, so the truth table of the specific decoder should be referred to when using it.

[0076] In some embodiments, the second sub-control circuit includes N groups of transistors, the N groups of transistors are connected in one-to-one correspondence with the N groups of test units; the first controlled end of each transistor in each group of transistors is connected with a pad group, the second controlled end is connected with a test unit corresponding to the pad group, and the control end is used for receiving one bit of N-bit selection signals.

[0077] It should be noted that the number of transistors included in each group of transistors can be the same or different, and the number of transistors included in each group of transistors can be set according to the number of test units included in the test unit group corresponding to the group of transistors.

[0078] In some embodiments, taking the case that N is equal to 4 and the test units are word lines or bit lines as an example, as shown in Figure 6 the first sub-control circuit 211 includes a 2-4 decoder, the decoder has 2 input ports A and B and 4 output ports (a first output port Y0, a second output port Y1, a third output port Y2 and a fourth output port Y3), and the second sub-control circuit 212 includes 4 groups of transistors (a first group of transistors 2121, a second group of transistors 2122, a third group of transistors 2123 and a fourth group of transistors 2124), the 4 groups of transistors are connected in one-to-one correspondence with the 4 groups of test units, and exemplarily, the first group of transistors 2121 is connected in correspondence with the first group of test units 221, the second group of transistors 2122 is connected in correspondence with the second group of test units 222, the third group of transistors 2123 is connected in correspondence with the third group of test units 223, and the fourth group of transistors 2124 is connected in correspondence with the fourth group of test units 224.

[0079] Among them, the first group of transistors 2121 includes 4 first transistors, the second group of transistors 2122 includes 2 second transistors, the third group of transistors 2123 includes 1 third transistor, and the fourth group of transistors 2124 includes 1 fourth transistor.

[0080] In some embodiments, the first controlled end of each transistor in each group of transistors is connected with a pad group, the second controlled end is connected with a test unit corresponding to the pad group, and the control end is used for receiving one bit of N-bit selection signals.

[0081] Exemplarily, as shown in Figure 6 the first controlled end of the first transistor in the first group of transistors 2121 is connected with the first pad group 231, the second controlled end of the first transistor in the first group of transistors 2121 is connected with a test unit 240 in the first group of test units 221 corresponding to the first pad group 231, and the control end of the first transistor in the first group of transistors 2121 is used for receiving one bit of 4-bit selection signals output by the fourth output port Y3 of the 2-4 decoder.

[0082] Exemplarily, as shown inFigure 6 As shown in FIG. 7, the first controlled end of the first transistor in the second group of transistors 2122 is connected with the second pad group 232, the second controlled end of the first transistor in the second group of transistors 2122 is connected with the test unit 240 in the second test unit group 222 corresponding to the second pad group 232, and the control end of the first transistor in the second group of transistors 2122 is used to receive one bit of the 4-bit selection signal output by the third output port Y2 of the 2-4 decoder.

[0083] As shown in FIG. 7, the first controlled end of the first transistor in the second group of transistors 2122 is connected with the second pad group 232, the second controlled end of the first transistor in the second group of transistors 2122 is connected with the test unit 240 in the second test unit group 222 corresponding to the second pad group 232, and the control end of the first transistor in the second group of transistors 2122 is used to receive one bit of the 4-bit selection signal output by the third output port Y2 of the 2-4 decoder. Figure 6 As shown in FIG. 7, the first controlled end of the first transistor in the second group of transistors 2122 is connected with the second pad group 232, the second controlled end of the first transistor in the second group of transistors 2122 is connected with the test unit 240 in the second test unit group 222 corresponding to the second pad group 232, and the control end of the first transistor in the second group of transistors 2122 is used to receive one bit of the 4-bit selection signal output by the third output port Y2 of the 2-4 decoder.

[0084] Figure 6 As shown in FIG. 7, the first controlled end of the first transistor in the second group of transistors 2122 is connected with the second pad group 232, the second controlled end of the first transistor in the second group of transistors 2122 is connected with the test unit 240 in the second test unit group 222 corresponding to the second pad group 232, and the control end of the first transistor in the second group of transistors 2122 is used to receive one bit of the 4-bit selection signal output by the third output port Y2 of the 2-4 decoder.

[0085] It should be noted that the first transistor, the second transistor, the third transistor and the fourth transistor are of the same type, for example, the first transistor, the second transistor, the third transistor and the fourth transistor are all PMOS transistors, or the first transistor, the second transistor, the third transistor and the fourth transistor are all NMOS transistors.

[0086] The control end of the transistor in the same group of transistors receives one bit of the N-bit selection signal output by the same output port of the decoder, and only one bit of the N-bit selection signal output by the decoder is at the effective level, and the remaining N-1 bits are all at the ineffective level. Therefore, when one of the plurality of test unit groups is selected, the transistors in the group of transistors corresponding thereto will turn on the connection between the test unit and the pad group in response to one bit of the N-bit selection signal output by the decoder.

[0087] It should be noted that, since the test signal has a preset one-to-one correspondence relationship with the test unit group, the selection signal generated by the test signal through the decoder also has a one-to-one correspondence relationship with the test unit group, so that each group of transistors can turn on the connection between the corresponding test unit group and the pad group based on the selection signal.​

[0088] Figure 7 For Figure 6 The circuit structure schematic diagram of the test device is shown when the first transistor, the second transistor, the third transistor and the fourth transistor in the first group of transistors, the second group of transistors, the third group of transistors and the fourth group of transistors are PMOS transistors, and the test unit is a word line or a bit line. Each pad group includes one pad.

[0089] It can be known from the truth table of the 2-4 decoder shown in Table 1 that when the 2-bit test signal received by the decoder is 00, the 4-bit selection signal output is 0111, each first transistor P1 in the first group of transistors is turned on in response to the valid level "0" output by the fourth output port Y3, and the connection between the test unit 240 in the first test unit group 221 and the pad group is turned on. The second transistor P2 is turned off in response to the invalid level "1" output by the third output port Y2, and the connection between the test unit 240 in the second test unit group 222 and the pad group is turned off. The third transistor P3 and the fourth transistor P4 are similar to the second transistor P2, and details are not described here.

[0090] When other test unit groups are selected, the process of turning on or off the transistors in each group can be understood by referring to the process of selecting the first test unit group described above.

[0091] In some embodiments, N is equal to 2, M is equal to 4, each test unit group includes 4 word lines, the second sub-control circuit of the control circuit includes 2 groups of transistors, the 2 groups of transistors correspond to the 2 test unit groups one by one, each group of transistors includes 4 transistors, and each pad group is connected to 2 test units located in different test unit groups.

[0092] As Figure 8 shown, Figure 8 the correspondence between the 2 test unit groups and the 4 pad groups in the test device is the same as that in Figure 3 . Figure 8 The first sub-control circuit 211 in the test device includes a 1-2 decoder, the decoder has 1 input port A and 2 output ports (a first output port D0 and a second output port D1), and Table 2 is a truth table of the 1-2 decoder. According to Table 2, when the 1-bit test signal received by the decoder is 0, the 2-bit selection signal output is 01, and when the 2-bit test signal received by the decoder is 1, the 2-bit selection signal output is 10.

[0093] Table 2

[0094]

[0095] Figure 8Each test unit group shown includes 4 word lines. The second sub-control circuit of the control circuit includes a first group of transistors 2121 and a second group of transistors 2122. The first group of transistors 2121 includes 4 first transistors P1, and the second group of transistors 2122 includes 4 first transistors P2. The first group of transistors 2121 corresponds to the first test unit group 221, and the second group of transistors 2122 corresponds to the second test unit group 222. The first pad group 231, the second pad group 232, the third pad group 233, and the fourth pad group 234 each include 1 pad.

[0096] Combination Figure 8 As shown in Table 2, when the decoder receives a 1-bit test signal of 0, the output 2-bit selection signal is 01. Each of the first transistors P1 in the first group responds to the valid level "0" output by the second output port D1, connecting the test unit 240 in the first test unit group 221 to the pad group. The second transistor P2 responds to the invalid level "1" output by the first output port D0, disconnecting the test unit 240 in the second test unit group 222 from the pad group.

[0097] In some embodiments, the first sub-control circuit includes a decoder and N comparators; the output of the decoder is connected to the input of the N comparators, and the outputs of the N comparators correspond one-to-one with the N test unit groups; the decoder is configured to receive a test signal and output a decoded signal to the input of the N comparators; each comparator is configured to receive a reference signal and a decoded signal and output a 1-bit sub-select signal, and the N 1-bit sub-select signals output by the N comparators constitute an N-bit selection signal; each test unit group corresponds to a unique reference signal.

[0098] For example, let's take N equal to 2 as an example. Figure 9 As shown, the first sub-control circuit 211 includes a 1-to-2 decoder 2110 and two comparators (first comparator 2111 and second comparator 2112).

[0099] The output of the 1-2 decoder 2110 is connected to the input of two comparators, and the outputs of the two comparators correspond one-to-one with two test unit groups. The 1-2 decoder 2110 is configured to receive a test signal and output a decoded signal to the input of the two comparators. Each comparator is configured to receive a reference signal and a decoded signal and output a 1-bit sub-select signal. The two 1-bit sub-select signals output by the two comparators form a 2-bit select signal. Each test unit group corresponds to a unique reference signal.

[0100] This section combines the truth table of the 1-2 decoder shown in Table 2 and... Figure 8The connection relationship between the first sub-control circuit and the test unit group, the second sub-control circuit and the pad group is explained. Figure 9 When the 1-bit test signal received by the 1-2 decoder 2110 is 0, it indicates that the first test unit group is selected, and the 2-bit decoded signal output by the 1-2 decoder 2110 is 01. The output of the first comparator 2111 is connected to... Figure 8 The first test unit group shown corresponds to the output of the second comparator 2112 and... Figure 8 The second test unit group shown corresponds to this. The first comparator 2111 receives the decoded signal 01 and the reference signal 01 corresponding to the first test unit group, and outputs a comparison result "1" as a 1-bit sub-select signal. The second comparator 2112 receives the decoded signal 01 and the reference signal 10 corresponding to the second test unit group, and outputs a comparison result "0" as a 1-bit sub-select signal. Thus, the first sub-control circuit outputs a 2-bit selection signal 10.

[0101] Figure 9 The output of the first comparator 2111 serves as the second output D1 of the first sub-control circuit, and the output of the second comparator 2112 serves as the second output D0 of the first sub-control circuit. Figure 9 The connection method of each transistor in the first sub-control circuit and the second sub-control circuit can be referred to Figure 8 Understand the connection method of the 1-2 decoder.

[0102] It should be noted that when adopting Figure 9 When the results shown are used as the first sub-control circuit, each transistor needs to be set as an NMOS transistor. In this way, when the first test unit group is selected, the transistor corresponding to the first test unit group turns on in response to the "1" output of the first comparator 211, and the transistor corresponding to the second test unit group turns off in response to the "0" output of the first comparator 211.

[0103] It should be noted that the correspondence between the reference signal and the test unit group can be preset. The Nth comparator is connected to the Nth test unit group, and one input of the Nth comparator is used to receive the reference signal corresponding to the Nth test unit group.

[0104] It should be noted that, Figure 2 to Figure 8 The positions of the test units shown are merely examples of how test unit groups are divided and are not intended to limit the actual positions of the test units in this disclosure.

[0105] In some embodiments, at least two of the multiple word lines or multiple bit lines included in each test unit group are adjacent to each other.

[0106] For example, refer to Figure 10The first test unit group 211 includes four word lines (WL1, WL2, WL3, and WL4), where WL1 and WL2 are adjacent, WL2 and WL3 are adjacent, and WL3 and WL4 are adjacent. The second test unit group 212 includes four word lines (WL5, WL6, WL7, and WL8), where WL5 and WL6 are adjacent, WL6 and WL7 are adjacent, and WL7 and WL8 are adjacent. As semiconductor device dimensions shrink, the spacing between adjacent word lines or adjacent bit lines also decreases. When dividing the test unit groups, it is ensured that at least two of the multiple word lines or multiple bit lines included in each test unit group are adjacent. Obtaining the electrical performance of adjacent word lines or bit lines during testing is beneficial for providing numerical references for semiconductor device design, such as analyzing the impact of spacing changes on electrical performance based on test results.

[0107] In some embodiments, each test unit group includes multiple word lines or bit lines that are spaced apart. For example, [the following is an example of a test unit group]. Figure 10 As shown, WL1, WL3, WL5, and WL7 are divided into the first test unit group, and WL2, WL4, WL6, and WL8 are divided into the second test unit group. This ensures that the distance between the connecting lines between the pad groups and the test units in the test unit groups is similar, and the interference such as resistance introduced by the connecting lines during testing is also similar, which is beneficial for obtaining more accurate electrical performance data for the test units.

[0108] The testing apparatus provided in this disclosure, by rationally grouping multiple test units and reusing at least a portion of the solder pads from a limited number of pad groups through a control circuit, ensures that when a test unit group is selected for testing, at least a portion of the pad groups are connected one-to-one with the test units in the selected test unit group. Therefore, it can meet the requirement of obtaining the electrical performance of each test unit individually through the pad groups, which is beneficial for providing numerical references for semiconductor device design and improving semiconductor device yield. Simultaneously, it eliminates the need to increase the number of pad groups, thus improving wafer area utilization.

[0109] This disclosure also provides a wafer, such as Figure 11 As shown, wafer 300 includes: a plurality of semiconductor devices 310; dicing grooves 320, respectively located between the semiconductor devices 310 to separate the semiconductor devices 310; and a testing apparatus as described in the foregoing embodiments located in the dicing grooves 320.

[0110] It should be noted that the test units in the test device set in the dicing groove 320 correspond to the processes or structures of the semiconductor device 310 that need to be monitored.

[0111] This disclosure also provides a testing method.Figure 12 An implementation flowchart of a test method according to an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the test method includes the following steps: Figure 12

[0112] Step S10: receiving a test signal;

[0113] Step S20: selecting one of N test unit groups based on the test signal, and connecting at least part of M pad groups to the test units in the selected test unit group one by one; wherein M and N are both integers greater than 1, the number of test units included in each test unit group is less than or equal to M, and the total number of test units is greater than M.

[0114] In step S20, selecting one of N test unit groups based on the test signal, and connecting at least part of M pad groups to the test units in the selected test unit group one by one, includes: generating a selection signal based on the test signal, the selection signal being used to indicate the selected one of N test unit groups; receiving the selection signal, and turning on the connection between the test units in the selected test unit group and the at least part of pad groups according to the selection signal.

[0115] Reference is made to Figure 6 and Table 1, the first sub-control circuit 211 includes a 2-4 decoder, the decoder having 2 input ports A and B and 4 output ports (a first output port Y0, a second output port Y1, a third output port Y2, and a fourth output port Y3), and the second sub-control circuit 212 includes 4 groups of transistors (a first group of transistors 2121, a second group of transistors 2122, a third group of transistors 2123, and a fourth group of transistors 2124), the 4 groups of transistors being connected to the 4 test unit groups one by one.

[0116] In some embodiments, the first controlled end of a transistor in each group of transistors is connected to a pad group, the second controlled end is connected to a test unit corresponding to the pad group, and the control end is used to receive one bit of an N-bit selection signal.

[0117] For example, the test method includes generating a 4-bit selection signal 0111 based on a 2-bit test signal 00. The 4-bit selection signal indicates that one of the 4 test unit groups (for example, the first test unit group 221) is selected.

[0118] ​The test method further includes receiving a 4-bit selection signal 0111, and turning on the connection between the test units in the selected test unit group and at least part of the pad groups according to the 4-bit selection signal 0111. For example, a first transistor in the first group of transistors 2121 is turned on according to the first bit "0" in the 4-bit selection signal 0111, a second transistor in the second group of transistors 2122 is turned on according to the second bit "1" in the 4-bit selection signal 0111, a third transistor in the third group of transistors 2123 is turned on according to the third bit "1" in the 4-bit selection signal 0111, and a fourth transistor in the fourth group of transistors 2124 is turned on according to the fourth bit "1" in the 4-bit selection signal 0111.

[0119] The control end of the transistors in the same group of transistors receives one bit in the N-bit selection signal output from the same output port of the decoder, and only one bit in the N-bit selection signal output from the decoder is at a valid level, and the remaining N-1 bits are at an invalid level. Therefore, when one of the multiple test unit groups is selected, the transistors in the corresponding group of transistors connected thereto will turn on the connection between the test units and the pad groups in response to one bit at a valid level in the N-bit selection signal output from the decoder.

[0120] It should be noted that, since the test signal has a preset one-to-one correspondence with the test unit group, the selection signal generated by the decoder also has a one-to-one correspondence with the test unit group, and thus each group of transistors can turn on the connection between the corresponding test unit group and the pad group based on the selection signal.

[0121] In some embodiments, the test method further includes testing the test units in the selected test unit group through the test probe via at least part of the pad groups in the test pad group. Since the test method of the embodiments of the present disclosure can obtain the electrical performance of each test unit individually, it is more conducive to improving the manufacturing process and design yield of the semiconductor device.

[0122] It should be understood that the "one embodiment" or "some embodiments" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that the size of the sequence number of each process in various embodiments of the present disclosure does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above embodiments of the present disclosure is only for description, not representing the advantages and disadvantages of the embodiments.

[0123] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A testing device, characterized in that, include: The system comprises a control circuit, M pad groups, and N test unit groups, where M and N are both integers greater than 1. Each test unit group includes a number of test units less than or equal to M, and the total number of test units is greater than M. The control circuit is configured to: receive a test signal, select one of the N test unit groups based on the test signal, and connect at least a portion of the M pad groups to the selected test unit group in a one-to-one correspondence.

2. The testing apparatus according to claim 1, characterized in that, At least one of the pad groups is connected to multiple test units located in different test unit groups.

3. The testing apparatus according to claim 2, characterized in that, The same test unit can be connected to at most one of the pad sets.

4. The testing apparatus according to claim 2, characterized in that, The control circuit includes a first sub-control circuit and a second sub-control circuit; the second sub-control circuit is connected to the first sub-control circuit, the M pad groups, and the N test unit groups. The first sub-control circuit is configured to generate a selection signal based on the test signal, the selection signal being used to indicate the selection of one of the N test unit groups; The second sub-control circuit is configured to: receive the selection signal, and according to the selection signal, enable the connection between the selected test unit in the test unit group and at least a portion of the pad group.

5. The testing apparatus according to claim 4, characterized in that, The first sub-control circuit includes at least a decoder having N output terminals; the decoder is configured to receive the test signal and output an N-bit selection signal to the second sub-control circuit through the N output terminals.

6. The testing apparatus according to claim 4, characterized in that, The first sub-control circuit includes a decoder and N comparators; The output of the decoder is connected to the input of N comparators, and the outputs of the N comparators correspond one-to-one with the N test unit groups. The decoder is configured to receive the test signal and output a decoded signal to the input of the N comparators. Each comparator is configured to receive a reference signal and the decoded signal and output a 1-bit sub-select signal. The N 1-bit sub-select signals output by the N comparators constitute an N-bit selection signal. Each test unit group corresponds to a unique reference signal.

7. The testing apparatus according to claim 5 or 6, characterized in that, The second sub-control circuit includes N groups of transistors, which are connected one-to-one with the N test unit groups; the first controlled terminal of each transistor group is connected to a pad group, and the second controlled terminal is connected to the test unit corresponding to the pad group. The control terminal is used to receive one bit of the N-bit selection signal.

8. The testing apparatus according to claim 1, characterized in that, The number of terminals to be brought out in each test unit is one or more; the number of solder pads included in each pad group is the same as the number of terminals to be brought out in each test unit.

9. The testing apparatus according to claim 1, characterized in that, The test unit is a word line or a bit line.

10. The testing apparatus according to claim 9, characterized in that, The N equals 2, the M equals 4, and each test unit group includes 4 word lines; The second sub-control circuit of the control circuit includes two sets of transistors, which correspond one-to-one with the two test unit groups. Each set of transistors includes four transistors. Each pad group is connected to two test units located in different test unit groups.

11. The testing apparatus according to claim 9, characterized in that, Each test unit group includes multiple word lines or bit lines that are spaced apart.

12. The testing apparatus according to claim 9, characterized in that, At least two of the multiple word lines or multiple bit lines included in each test unit group are adjacent to each other.

13. A wafer, characterized in that, include: Multiple semiconductor devices; Dicing grooves are located between the semiconductor devices to separate them; as well as The testing apparatus as described in any one of claims 1 to 12 is located in the dicing groove.

14. A testing method, characterized in that, The testing method includes: Receive test signals; Based on the test signal, one of the N test unit groups is selected, and at least a portion of the M pad groups are connected one-to-one with the test units in the selected test unit group; wherein M and N are both integers greater than 1, the number of test units included in each test unit group is less than or equal to M, and the total number of test units is greater than M.

15. The test method according to claim 14, characterized in that, The testing method also includes: The test unit in the selected test unit group is tested by a test probe via at least a portion of the test pads in the test pad group.

16. The test method according to claim 14, characterized in that, The testing method includes: Based on the test signal, a selection signal is generated, which is used to indicate the selection of one of the N test unit groups; Receive the selection signal, and connect the selected test unit in the test unit group to at least a portion of the pad group according to the selection signal.

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