Input buffer for boosting charge pump power supply, analog-to-digital converter module, operation chip and electronic equipment

Abstract

The invention relates to an input buffer powered by a boost charge pump, an analog-to-digital converter module, an operation chip and electronic equipment. The input buffer comprises the boost charge pump, M level converters, N upper bridge transistors and P lower bridge transistors, wherein the N upper bridge transistors are cascaded; the P lower bridge transistors are cascaded; the second end of the first upper bridge transistor is connected to the first end of the boost charge pump, and the second end of the Pth lower bridge transistor is connected to the second end of the boost charge pump; the control end of each upper bridge transistor and the control end of each lower bridge transistor are connected with corresponding level translators, and the level translators are cascaded. According to the embodiment of the invention, the boost charge pump is introduced into the power supply path of the buffer, and the expansion of a power supply voltage rail is realized on the premise that an external power supply rail is not needed, so that the linearity of the buffer is remarkably improved, and the design complexity of a system power supply is effectively reduced.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an input buffer powered by a boost charge pump, an analog-to-digital converter module, a computing chip, and electronic equipment. Background Technology

[0002] Source follower architectures, due to their low output impedance and wide bandwidth, are commonly used in analog front-end circuits such as high-speed, high-precision analog-to-digital converters (ADCs) as input buffers. However, current source followers suffer from nonlinear distortion because the input signal swing causes changes in the source-drain voltage (Vds), which in turn leads to nonlinear changes in the output impedance through channel length modulation, severely degrading signal quality. Related technologies typically suppress this distortion by adding more power management modules (such as LDOs) and introducing new voltage rails. This not only increases the complexity and cost of the system design but also consumes additional chip pin resources, reducing overall integration density. Summary of the Invention

[0003] In view of this, this disclosure proposes an input buffer powered by a boost charge pump, the input buffer comprising: a boost charge pump, M level shifters, N upper-bridge transistors, and P lower-bridge transistors.

[0004] N cascaded upper-bridge transistors, wherein the first terminal of the i-th upper-bridge transistor is connected to the second terminal of the (i+1)-th upper-bridge transistor, 1≤i≤N-1, and i is an integer;

[0005] P lower-bridge transistors are cascaded, wherein the second terminal of the j-th upper-bridge transistor is connected to the first terminal of the (j+1)-th upper-bridge transistor, 1≤j≤P-1, and j is an integer;

[0006] The second terminal of the first upper-bridge transistor is connected to the first terminal of the boost charge pump, and the second terminal of the Pth lower-bridge transistor is connected to the second terminal of the boost charge pump.

[0007] Each upper-bridge transistor and each lower-bridge transistor has a corresponding level converter connected to its control terminal, and the level converters are cascaded together.

[0008] The common node of the level shifter connected to the Nth upper-bridge transistor and the level shifter connected to the first lower-bridge transistor serves as the input terminal of the input buffer, which is used to input the signal to be buffered.

[0009] The common node between the first terminal of the Nth upper-bridge transistor and the first terminal of the first lower-bridge transistor serves as the output terminal of the input buffer, and this output terminal is used to output the buffered signal.

[0010] Where M, N, and P are all positive integers, and M ≥ N + P, the doping types of the upper-bridge transistor and the lower-bridge transistor are different.

[0011] In one possible implementation, the input buffer further includes a constant-pressure switching module, which includes at least one upper-bridge switch and at least one lower-bridge switch, wherein...

[0012] The first terminal of each upper bridge switch is connected to a positive power supply voltage, and the second terminal of the i-th upper bridge switch is connected to the junction point between the first terminal of the i-th upper bridge transistor and the second terminal of the (i+1)-th upper bridge transistor.

[0013] The first terminal of each lower bridge switch is connected to a negative power supply voltage, and the second terminal of the j-th lower bridge switch is connected to the connection point between the second terminal of the j-th upper bridge transistor and the first terminal of the (j+1)-th upper bridge transistor.

[0014] In one possible implementation, each upper-bridge transistor is an NMOS transistor, and each lower-bridge transistor is a PMOS transistor. The input buffer includes a first upper-bridge transistor, a second upper-bridge transistor, a first lower-bridge transistor, a second lower-bridge transistor, a first upper-bridge switch, and a first lower-bridge switch, wherein...

[0015] The source of the first upper-bridge transistor is connected to the drain of the second upper-bridge transistor.

[0016] The drain of the first upper-bridge transistor is connected to the first terminal of the boost charge pump.

[0017] The source of the second upper-bridge transistor is connected to the source of the first lower-bridge transistor.

[0018] The drain of the first lower-bridge transistor is connected to the source of the second lower-bridge transistor.

[0019] The drain of the second lower-bridge transistor is connected to the second terminal of the boost charge pump.

[0020] The first terminal of the first upper bridge switch is connected to a positive power supply voltage.

[0021] The second terminal of the first upper-bridge switch is connected to the source of the first upper-bridge transistor and the drain of the second upper-bridge transistor.

[0022] The first terminal of the first downbridge switch is connected to a negative power supply voltage, and the second terminal of the first downbridge switch is connected to the drain of the first downbridge transistor and the source of the second downbridge transistor.

[0023] In one possible implementation, the boost charge pump includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first capacitor, and a second capacitor, wherein...

[0024] The first terminal of the first switch and the first terminal of the second switch are connected to a positive power supply voltage.

[0025] The second terminal of the first switch is connected to the first terminal of the fourth switch and the second terminal of the first capacitor.

[0026] The second terminal of the second switch and the second terminal of the third switch are connected to the first terminal of the first capacitor.

[0027] The first terminal of the third switch serves as the first terminal of the boost charge pump and is connected to the second terminal of the first upper bridge transistor.

[0028] The second terminal of the fourth switch is connected to the first terminal of the second capacitor and the first terminal of the fifth switch.

[0029] The second terminal of the second capacitor is connected to the first terminal of the seventh switch and the first terminal of the sixth switch.

[0030] The second terminal of the seventh switch serves as the second terminal of the boost charge pump and is connected to the second terminal of the Pth lower-bridge transistor.

[0031] The second terminal of the fifth switch and the second terminal of the sixth switch are connected to a negative power supply voltage.

[0032] In one possible implementation, the input buffer further includes:

[0033] The control module, connected to the control terminals of each switch, is used for:

[0034] During the pre-charging phase, the first switch, the third switch, the fourth switch, the fifth switch, the seventh switch, the first upper bridge switch, and the first lower bridge switch are controlled to be turned on, while the second switch and the sixth switch are controlled to be turned off.

[0035] After maintaining the pre-charging phase for a first duration, the coarse tracking phase begins. During the coarse tracking phase, the first switch, the second switch, the third switch, the fifth switch, and the sixth switch are controlled to be turned off, and the seventh switch is controlled to be turned on. The first upper bridge switch, the first lower bridge switch, and the fourth switch are also controlled to be turned off.

[0036] After the coarse tracking phase is maintained for a second duration, the fine tracking phase begins. In the fine tracking phase, the second switch, the sixth switch, the first upper bridge switch, and the first lower bridge switch are turned on, while the first switch, the third switch, the fifth switch, and the seventh switch are turned off. The fine tracking phase is maintained for a third duration.

[0037] In one possible implementation, the second duration is less than or equal to the third duration, and the third duration is less than the first duration.

[0038] The input buffer operates on a preset duration, which is greater than or equal to the sum of the first duration, the second duration, and the third duration.

[0039] In one possible implementation, the first capacitor and the second capacitor have the same capacitance value.

[0040] According to one aspect of this disclosure, an analog-to-digital converter module is provided, the analog-to-digital converter module including the boost charge pump powered input buffer.

[0041] According to one aspect of this disclosure, a computing chip is provided, the chip including the aforementioned analog-to-digital converter module.

[0042] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned computing chip.

[0043] This embodiment of the invention introduces a boost charge pump into the power supply path of the buffer, thereby expanding the power supply voltage rail without the need for an external power rail. This significantly improves the linearity of the buffer. Compared with related technologies, this embodiment of the invention does not require the introduction of an additional voltage rail, achieving a wider voltage swing on the basis of the original power supply, and effectively reducing the complexity of the system power supply design.

[0044] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0045] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0046] Figure 1 A schematic diagram of an input buffer powered by a boost charge pump according to this disclosure is shown.

[0047] Figure 2a A schematic diagram of an input buffer powered by a boost charge pump according to an embodiment of the present disclosure is shown.

[0048] Figure 2b A control timing diagram of an input buffer powered by a boost charge pump according to an embodiment of the present disclosure is shown. Detailed Implementation

[0049] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0050] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0051] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0052] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0053] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0054] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0055] Please see Figure 1 , Figure 1 A schematic diagram of an input buffer powered by a boost charge pump according to this disclosure is shown.

[0056] like Figure 1 As shown, the input buffer includes: a boost charge pump 10, M level shifters LS, N upper-bridge transistors (Q11, Q12, etc.), and P lower-bridge transistors (Q21, Q12, etc.).

[0057] N cascaded upper-bridge transistors, wherein the first terminal of the i-th upper-bridge transistor is connected to the second terminal of the (i+1)-th upper-bridge transistor, 1≤i≤N-1, and i is an integer;

[0058] P lower-bridge transistors are cascaded, wherein the second terminal of the j-th upper-bridge transistor is connected to the first terminal of the (j+1)-th upper-bridge transistor, 1≤j≤P-1, and j is an integer;

[0059] The second terminal of the first upper bridge transistor is connected to the first terminal of the boost charge pump 10, and the second terminal of the Pth lower bridge transistor is connected to the second terminal of the boost charge pump 10.

[0060] Each upper-bridge transistor and each lower-bridge transistor has a corresponding level converter LS connected to its control terminal, and the level converters LS are cascaded together.

[0061] The common node of the level shifter LS connected to the Nth upper-bridge transistor and the level shifter LS connected to the first lower-bridge transistor serves as the input terminal of the input buffer, which is used to input the signal V to be buffered. IN ;

[0062] The common node of the first terminal of the Nth upper-bridge transistor and the first terminal of the first lower-bridge transistor serves as the output terminal of the input buffer, and the output terminal is used to output the buffered signal V. OUT ,

[0063] Where M, N, and P are all positive integers, and M≥N+P, the doping types of the upper-bridge transistor and the lower-bridge transistor are different (such as N-type doping and P-type doping).

[0064] This embodiment of the invention introduces a boost charge pump 10 into the power supply path of the buffer, thereby expanding the power supply voltage rail without the need for an external power rail. This significantly improves the linearity of the buffer. Compared with related technologies, this embodiment of the invention does not require the introduction of an additional voltage rail, achieving a wider voltage swing on the basis of the original power supply, and effectively reducing the complexity of the system power supply design.

[0065] The present disclosure does not limit the specific implementation of the boost charge pump 10. Those skilled in the art can implement it using relevant technologies according to actual conditions and needs.

[0066] This disclosure does not limit the specific type or number of the upper-bridge transistors and lower-bridge transistors, nor does it limit the specific implementation method or number of the level converters LS. Those skilled in the art can set them according to actual conditions and needs. For example, the number of upper-bridge transistors and lower-bridge transistors can be equal, for example, both are N, and correspondingly, M = 2N, and the number of level converters LS can also be 2N.

[0067] For example, such as Figure 1As shown, the upper bridge transistor may include two, the lower bridge transistor may include two, and correspondingly, the level shifter LS may include four. The upper bridge transistor and the lower bridge transistor may include a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The transistors may be based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.

[0068] For example, such as Figure 1 As shown, the upper bridge transistor can be an NMOS (N-Metal-Oxide-Semiconductor) transistor, and the lower bridge transistor can be a PMOS (P-Metal-Oxide-Semiconductor) transistor.

[0069] For example, a level converter LS can be implemented using a shift register resistor and a shift register capacitor. For instance, one end of the shift register resistor serves as the input terminal of the level converter LS, and the other end of the shift register resistor is connected to one end of the shift register capacitor as the output terminal of the level converter LS. The other end of the shift register capacitor is grounded. Of course, the level converter LS can also be implemented in other ways, and this disclosure does not limit its implementation.

[0070] Please see Figure 2a , Figure 2a A schematic diagram of an input buffer powered by a boost charge pump 10 according to an embodiment of the present disclosure is shown.

[0071] In one possible implementation, such as Figure 2a As shown, the input buffer may further include a constant pressure switch module 20, which may include at least one upper bridge switch (such as S8) and at least one lower bridge switch (such as S9), wherein,

[0072] The first terminal of each upper bridge switch is connected to the positive power supply voltage VDD, and the second terminal of the i-th upper bridge switch is connected to the junction point between the first terminal of the i-th upper bridge transistor and the second terminal of the (i+1)-th upper bridge transistor.

[0073] The first terminal of each lower bridge switch is connected to the negative power supply voltage VSS, and the second terminal of the j-th lower bridge switch is connected to the connection point between the second terminal of the j-th upper bridge transistor and the first terminal of the (j+1)-th upper bridge transistor.

[0074] In this embodiment of the disclosure, the voltage of the connection point of the adjacent upper bridge transistor and the connection point of the adjacent lower bridge transistor can be controlled by the constant pressure switch module 20. The magnitude of the positive power supply voltage VDD (e.g., 0.9V) and the negative power supply voltage VSS (e.g., 0V) can be set according to the actual situation and needs.

[0075] In one possible implementation, such as Figure 2a As shown, each upper-bridge transistor is an NMOS transistor, and each lower-bridge transistor is a PMOS transistor. The input buffer includes a first upper-bridge transistor Q11, a second upper-bridge transistor Q12, a first lower-bridge transistor Q21, a second lower-bridge transistor Q22, a first upper-bridge switch S8, and a first lower-bridge switch S9.

[0076] The source of the first upper-bridge transistor Q11 is connected to the drain of the second upper-bridge transistor Q12.

[0077] The drain of the first upper-bridge transistor Q11 is connected to the first terminal of the boost charge pump 10.

[0078] The source of the second upper-bridge transistor Q12 is connected to the source of the first lower-bridge transistor Q21.

[0079] The drain of the first lower-bridge transistor Q21 is connected to the source of the second lower-bridge transistor Q22.

[0080] The drain of the second lower-bridge transistor Q22 is connected to the second terminal of the boost charge pump 10.

[0081] The first terminal of the first upper bridge switch S8 is connected to the positive power supply voltage VDD.

[0082] The second terminal of the first upper-bridge switch S8 is connected to the source of the first upper-bridge transistor Q11 and the drain of the second upper-bridge transistor Q12.

[0083] The first terminal of the first downbridge switch S9 is connected to the negative power supply voltage VSS, and the second terminal of the first downbridge switch S9 is connected to the drain of the first downbridge transistor Q21 and the source of the second downbridge transistor Q22.

[0084] In the input buffer of this embodiment, the second upper-bridge transistor Q12 and the first lower-bridge transistor Q21 serve as main follower transistors, and the first upper-bridge transistor Q11 and the second lower-bridge transistor Q22 serve as auxiliary follower transistors. By making the gate voltages of the auxiliary follower transistors, the first upper-bridge transistor Q11 and the second lower-bridge transistor Q22, track the input signal, the drain potentials of the main follower transistors (the second upper-bridge transistor Q12 and the first lower-bridge transistor Q21) change synchronously, thereby maintaining the stability of the drain-source voltage of the main follower transistors.

[0085] In one possible implementation, such as Figure 2a As shown, the boost charge pump 10 may include a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, a first capacitor C1, and a second capacitor C2, wherein...

[0086] The first terminal of the first switch S1 and the first terminal of the second switch S2 are connected to a positive power supply voltage VDD.

[0087] The second terminal of the first switch S1 is connected to the first terminal of the fourth switch S4 and the second terminal of the first capacitor C1.

[0088] The second terminal of the second switch S2 and the second terminal of the third switch S3 are connected to the first terminal of the first capacitor C1.

[0089] The first terminal of the third switch S3 serves as the first terminal of the boost charge pump 10 and is connected to the second terminal of the first upper bridge transistor (e.g., ...). Figure 2a As shown, this is the drain of the first upper-bridge transistor Q11.

[0090] The second terminal of the fourth switch S4 is connected to the first terminal of the second capacitor C2 and the first terminal of the fifth switch S5.

[0091] The second terminal of the second capacitor C2 is connected to the first terminal of the seventh switch S7 and the first terminal of the sixth switch S6.

[0092] The second terminal of the seventh switch S7 serves as the second terminal of the boost charge pump 10 and is connected to the second terminal of the Pth lower bridge transistor (e.g., ...). Figure 2a As shown, this is the drain of the second lower-bridge transistor Q22.

[0093] The second terminal of the fifth switch S5 and the second terminal of the sixth switch S6 are connected to the negative power supply voltage VSS.

[0094] The embodiments disclosed herein can generate the high voltage required by the source follower by controlling the conduction state of each switch, thereby effectively simplifying the system power supply architecture.

[0095] Please see Figure 2b , Figure 2b A control timing diagram of an input buffer powered by a boost charge pump 10 according to an embodiment of the present disclosure is shown.

[0096] In one possible implementation, the input buffer may further include:

[0097] The control module (not shown) is connected to the control terminal of each switch, such as... Figure 2a and Figure 2b As shown, it is used for:

[0098] During the pre-charging phase (corresponding to the first duration T1), the first switch S1, the third switch S3, the fourth switch S4, the fifth switch S5, the seventh switch S7, the first upper bridge switch S8, and the first lower bridge switch S9 are controlled to be turned on, while the second switch S2 and the sixth switch S6 are controlled to be turned off.

[0099] After maintaining the pre-charging phase for a first duration T1, the coarse tracking phase (corresponding to the second duration T2) is entered. In the coarse tracking phase, the first switch S1, the second switch S2, the third switch S3, the fifth switch S5, and the sixth switch S6 are controlled to be turned off, and the seventh switch S7 is controlled to be turned on. The first upper bridge switch S8, the first lower bridge switch S9, and the fourth switch S4 are also controlled to be turned off.

[0100] After the coarse tracking phase is maintained for a second duration T2, the fine tracking phase (corresponding to the third duration T3) is entered. In the fine tracking phase, the second switch S2, the sixth switch S6, the first upper bridge switch S8, and the first lower bridge switch S9 are controlled to be turned on, while the first switch S1, the third switch S3, the fifth switch S5, and the seventh switch S7 are controlled to be turned off. The fine tracking phase is maintained for a third duration T3.

[0101] For example, each switch can be defined to be turned on when a high-level control signal is received and turned off when a low-level control signal is received. For example, such as... Figure 2b As shown, the control signals may include a first control signal Φ1, a second control signal Φ2, and a third control signal Φ3, wherein, as... Figure 2b As shown, the first control signal Φ1 can be used to control the switching states of the second switch S2 and the sixth switch S6, the second control signal Φ2 can be used to control the switching states of the fourth switch S4, the first upper bridge switch, and the first lower bridge switch, and the third control signal Φ3 can be used to control the switching states of the first switch S1, the third switch S3, the fifth switch S5, and the seventh switch S7.

[0102] It should be understood that the control module can also be located outside the input buffer. Each switch of the input buffer can receive control signals from the external control module, thereby realizing the control of the conduction state.

[0103] This disclosure does not limit the specific implementation of the control module. The control module can be implemented through a processing component. In one example, the processing component includes, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device that has the function of executing instructions. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Inside the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0104] In one possible implementation, such as Figure 2b As shown, the second duration T2 is less than or equal to the third duration T3, and the third duration T3 is less than the first duration T1.

[0105] The input buffer operates with a preset duration T, where the preset duration T is greater than or equal to the sum of the first duration T1, the second duration T2, and the third duration T3.

[0106] In one possible implementation, the first capacitor C1 and the second capacitor C2 have the same capacitance value.

[0107] For example, such as Figure 2a As shown, during the pre-charging phase, two capacitors are connected in series between VDD (e.g., 0.9V) and VSS (e.g., 0V). The charging process stabilizes the intermediate node voltage at VDD / 2 (e.g., 0.45V), which serves as the floating reference voltage during the subsequent boosting process.

[0108] For example, such as Figure 2a As shown, after the coarse tracking stage, the source follower enters the boost-fine tracking stage. This is achieved by controlling the first switch S1, the third switch S3, the fifth switch S5, and the seventh switch S7 to disconnect, breaking the series connection of the capacitors, and connecting the midpoints of the two capacitors to VDD (e.g., 0.9V) and VSS (e.g., 0V), respectively. Due to the conservation of charge in the floating capacitors, the potential at their other ends is raised to [values ​​to be filled in]. (e.g., 1.35V) and (e.g., -0.45V), thereby extending the voltage rail to provide high-level power supply support for the source follower.

[0109] Compared with traditional input buffer schemes, the embodiments disclosed herein have the following advantages:

[0110] Simplified power management: This disclosure introduces a boost charge pump 10, which obtains the required high voltage by extending the power rail, eliminating the need for an additional high-voltage power rail and its associated power management module (such as an LDO), thus simplifying power management.

[0111] Reduced power consumption: A two-phase sampling strategy is adopted. The first phase performs coarse tracking under normal supply voltage to quickly lock the input signal level, while the second phase performs fine tracking by increasing the supply voltage, thereby improving sampling accuracy and driving capability. This strategy effectively reduces overall power consumption while ensuring the accuracy and speed of the buffer.

[0112] In summary, the input buffer of this disclosure, which uses a boost charge pump 10 for power supply and adopts a two-phase sampling strategy, has the advantages of high linearity, simple power management, and low power consumption. It can effectively support analog signal chain modules such as high-speed, high-precision analog-to-digital converters that have stringent requirements for input buffer performance.

[0113] According to one aspect of this disclosure, an analog-to-digital converter (ADC) module is provided, the ADC module including an input buffer powered by the boost charge pump 10. Of course, the input buffer of this embodiment can also be used in other high-speed, high-precision analog signal chain modules, and this embodiment does not limit its use.

[0114] According to one aspect of this disclosure, a computing chip is provided, the chip including the aforementioned analog-to-digital converter module.

[0115] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned computing chip.

[0116] This disclosure does not limit the specific type of electronic device. Those skilled in the art can configure it according to actual circumstances and needs. For example, the electronic device may include a terminal device, such as a user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks. For example, the server can be a local server or a cloud server.

[0117] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An input buffer powered by a boost charge pump, characterized in that, The input buffer includes: a boost charge pump, M level shifters, N upper-bridge transistors, and P lower-bridge transistors. N cascaded upper-bridge transistors, wherein the first terminal of the i-th upper-bridge transistor is connected to the second terminal of the (i+1)-th upper-bridge transistor, 1≤i≤N-1, and i is an integer; P lower-bridge transistors are cascaded, wherein the second terminal of the j-th upper-bridge transistor is connected to the first terminal of the (j+1)-th upper-bridge transistor, 1≤j≤P-1, and j is an integer; The second terminal of the first upper-bridge transistor is connected to the first terminal of the boost charge pump, and the second terminal of the Pth lower-bridge transistor is connected to the second terminal of the boost charge pump. Each upper-bridge transistor and each lower-bridge transistor has a corresponding level converter connected to its control terminal, and the level converters are cascaded together. The common node of the level shifter connected to the Nth upper bridge transistor and the level shifter connected to the first lower bridge transistor serves as the input terminal of the input buffer, which is used to input the signal to be buffered. The common node between the first terminal of the Nth upper-bridge transistor and the first terminal of the first lower-bridge transistor serves as the output terminal of the input buffer, and this output terminal is used to output the buffered signal. Where M, N, and P are all positive integers, and M ≥ N + P, the doping types of the upper-bridge transistor and the lower-bridge transistor are different.

2. The input buffer according to claim 1, characterized in that, The input buffer further includes a constant-pressure switching module, which comprises at least one upper-bridge switch and at least one lower-bridge switch. The first terminal of each upper bridge switch is connected to a positive power supply voltage, and the second terminal of the i-th upper bridge switch is connected to the junction point between the first terminal of the i-th upper bridge transistor and the second terminal of the (i+1)-th upper bridge transistor. The first terminal of each lower bridge switch is connected to a negative power supply voltage, and the second terminal of the j-th lower bridge switch is connected to the connection point between the second terminal of the j-th upper bridge transistor and the first terminal of the (j+1)-th upper bridge transistor.

3. The input buffer according to claim 2, characterized in that, Each upper-bridge transistor is an NMOS transistor, and each lower-bridge transistor is a PMOS transistor. The input buffer includes a first upper-bridge transistor, a second upper-bridge transistor, a first lower-bridge transistor, a second lower-bridge transistor, a first upper-bridge switch, and a first lower-bridge switch. The source of the first upper-bridge transistor is connected to the drain of the second upper-bridge transistor. The drain of the first upper-bridge transistor is connected to the first terminal of the boost charge pump. The source of the second upper-bridge transistor is connected to the source of the first lower-bridge transistor. The drain of the first lower-bridge transistor is connected to the source of the second lower-bridge transistor. The drain of the second lower-bridge transistor is connected to the second terminal of the boost charge pump. The first terminal of the first upper bridge switch is connected to a positive power supply voltage. The second terminal of the first upper-bridge switch is connected to the source of the first upper-bridge transistor and the drain of the second upper-bridge transistor. The first terminal of the first downbridge switch is connected to a negative power supply voltage, and the second terminal of the first downbridge switch is connected to the drain of the first downbridge transistor and the source of the second downbridge transistor.

4. The input buffer according to claim 3, characterized in that, The boost charge pump includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first capacitor, and a second capacitor, wherein... The first terminal of the first switch and the first terminal of the second switch are connected to a positive power supply voltage. The second terminal of the first switch is connected to the first terminal of the fourth switch and the second terminal of the first capacitor. The second terminal of the second switch and the second terminal of the third switch are connected to the first terminal of the first capacitor. The first terminal of the third switch serves as the first terminal of the boost charge pump and is connected to the second terminal of the first upper bridge transistor. The second terminal of the fourth switch is connected to the first terminal of the second capacitor and the first terminal of the fifth switch. The second terminal of the second capacitor is connected to the first terminal of the seventh switch and the first terminal of the sixth switch. The second terminal of the seventh switch serves as the second terminal of the boost charge pump and is connected to the second terminal of the Pth lower-bridge transistor. The second terminal of the fifth switch and the second terminal of the sixth switch are connected to a negative power supply voltage.

5. The input buffer according to claim 4, characterized in that, The input buffer also includes: The control module, connected to the control terminals of each switch, is used for: During the pre-charging phase, the first switch, the third switch, the fourth switch, the fifth switch, the seventh switch, the first upper bridge switch, and the first lower bridge switch are controlled to be turned on, while the second switch and the sixth switch are controlled to be turned off. After maintaining the pre-charging phase for a first duration, the coarse tracking phase begins. During the coarse tracking phase, the first switch, the second switch, the third switch, the fifth switch, and the sixth switch are controlled to be turned off, and the seventh switch is controlled to be turned on. The first upper bridge switch, the first lower bridge switch, and the fourth switch are also controlled to be turned off. After the coarse tracking phase is maintained for a second duration, the fine tracking phase begins. In the fine tracking phase, the second switch, the sixth switch, the first upper bridge switch, and the first lower bridge switch are turned on, while the first switch, the third switch, the fifth switch, and the seventh switch are turned off. The fine tracking phase is maintained for a third duration.

6. The input buffer according to claim 5, characterized in that, The second duration is less than or equal to the third duration, and the third duration is less than the first duration. The input buffer operates on a preset duration, which is greater than or equal to the sum of the first duration, the second duration, and the third duration.

7. The input buffer according to claim 4, characterized in that, The first capacitor and the second capacitor have the same capacitance value.

8. An analog-to-digital converter module, characterized in that, The analog-to-digital converter module includes a boost charge pump powered input buffer as described in any one of claims 1 to 7.

9. A computing chip, characterized in that, The chip includes the analog-to-digital converter module as described in claim 8.

10. An electronic device, characterized in that, The electronic device includes the computing chip as described in claim 9.

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