Wide-input switch type step-down circuit

Abstract

The invention discloses a wide-input switch type step-down circuit, relates to the technical field of integrated circuits, and solves the technical problems that the input voltage range of the step-down circuit is relatively narrow and the output voltage precision is relatively low. According to the technical scheme, the circuit is characterized in that the circuit processes the output voltage and the inductive current to generate a switching signal to control the on and off of a power NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor); and the stability of the output voltage OUT is realized. The high-side power supply circuit supplies power to the floating power supply BST, the internal power supply circuit supplies power to the reference circuit, the control circuit and the like, when the circuits are started and the output voltage OUT is low, the power supply of the internal circuit comes from the input VIN, and when the output voltage rises, the internal power supply is supplied with power by the output OUT, so that the power consumption of the circuits is reduced, and the efficiency of the circuits is improved. The input voltage VIN range of the circuit is very wide and is from low to several volts to high to hundreds of volts; the output current can be adjusted through an external resistor R0 so as to adapt to different applications; in addition, the circuit has the advantages of low power consumption and high efficiency.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a wide-input switching buck circuit. Background Technology

[0002] Switching step-down circuits are widely used in home appliances and electricity meters due to their advantages of high power output and high efficiency. With the advancement of technology, the industry has increasingly higher requirements for product performance, such as higher withstand voltage, wider input range, higher efficiency, and better flexibility of use.

[0003] An existing high-voltage switching step-down circuit, such as Figure 1 As shown, the circuit includes a step-down circuit and its peripheral circuitry. The AC signal ACIN is converted into a high-voltage DC signal VIN by a full-wave rectifier circuit. VIN is then output as a low-voltage signal OUT by the step-down circuit. The power supply VCC for the step-down circuit is jointly powered by a high-voltage startup circuit and a high-voltage diode DBST. This circuit structure can effectively achieve high-to-low voltage conversion, but it has certain drawbacks. The circuit indirectly detects the output voltage OUT by sensing the VCC voltage, resulting in lower output voltage accuracy. The high-voltage diode DBST is not easily integrated. The RCS of the resistor affects the on-resistance of the high-voltage switching NMOS transistor (HVNM), thus reducing circuit efficiency. Summary of the Invention

[0004] This application provides a wide-input switching buck circuit, the technical purpose of which is to enable the buck circuit to have a wide input voltage range, high operating efficiency, high output voltage accuracy, and the maximum output current can be adjusted by an overcurrent resistor.

[0005] The above-mentioned technical objective of this application is achieved through the following technical solution:

[0006] A wide-input switching buck circuit includes an internal power supply circuit, a high-side power supply circuit, a reference circuit, an oscillator, a control circuit, a level conversion circuit, a buffer BUF0, a capacitor C0, a capacitor C1, a high-voltage NMOS transistor M0, an inductor L0, a resistor R0, a resistor R1, a resistor R2, and a diode D0.

[0007] The high-voltage input terminal of the internal power supply circuit is connected to the input signal VIN and to the drain terminal of the high-voltage NMOS transistor M0; the low-voltage input terminal is connected to one end of resistor R1, the second current detection input terminal of the control circuit, one end of resistor R0, and one end of capacitor C0; the output terminal is connected to the input terminal of the high-side power supply circuit, the low-side power supply terminal of the level conversion circuit, the power supply terminal of the reference circuit, the power supply terminal of the oscillator, and the power supply terminal of the control circuit.

[0008] The output end of the high-side power supply circuit is connected with the high-side power supply end of the level conversion circuit, the power supply end of the buffer BUF0 and one end of the capacitor C1, and serves as a floating power supply BST;

[0009] The reference voltage input end of the control circuit is connected with the output end of the reference circuit; the clock input end is connected with the output end of the oscillator; the voltage feedback input end is connected with the other end of the resistor R1 and one end of the resistor R2; the first current detection input end is connected with one end of the inductor L0 and the other end of the resistor R0; and the output end is connected with the input end of the level conversion circuit;

[0010] The floating ground end of the level conversion circuit is connected with the other end of the inductor L0, the floating ground end of the buffer BUF0, the other end of the capacitor C1, the source end of the high-voltage NMOS tube M0 and the negative end of the diode D0, and serves as a floating ground SW;

[0011] The output end of the buffer BUF0 is connected with the gate end of the high-voltage NMOS tube M0;

[0012] The other end of the resistor R2, the positive end of the diode D0 and the other end of the capacitor C0 are all grounded.

[0013] Preferably, the control circuit comprises an amplifier 1, an amplifier 2, a comparator 1 and an RS flip-flop 1; the non-inverting input end of the amplifier 1 serves as a reference voltage input end, the inverting input end serves as a feedback input end, and the output end is connected with the inverting input end of the comparator 1; the non-inverting input end of the amplifier 2 serves as a first current detection input end, the inverting input end serves as a second current detection input end, and the output end is connected with the non-inverting input end of the comparator 1; the output end of the comparator 1 is connected with the reset end R of the RS flip-flop 1; the set end S of the RS flip-flop 1 serves as a clock input end, and the output end Q outputs a signal PWM.

[0014] Preferably, the control circuit comprises an amplifier 2, a comparator 2, a comparator 3, an AND gate AND1 and an RS flip-flop 1; the inverting input end of the comparator 2 serves as a feedback input end, the non-inverting input end serves as a reference voltage input end and is connected with the non-inverting input end of the comparator 3, and the output end is connected with the first input end of the AND gate AND1; the non-inverting input end of the amplifier 2 serves as a first current detection input end, the inverting input end serves as a second current detection input end, and the output end is connected with the inverting input end of the comparator 3; the output end of the comparator 3 is connected with the second input end of the AND gate AND1; the output end of the AND gate AND1 is connected with the set end S of the RS flip-flop 1; the reset end R of the RS flip-flop 1 serves as a clock input end, and the output end Q outputs a signal PWM.

[0015] Preferably, the internal power supply circuit comprises an N-type JFET tube J1 and a diode D1; the drain of the N-type JFET tube J1 is the high-voltage input end, the gate is grounded, and the source is connected with the negative end of the diode D1 and serves as the output end; and the positive end of the diode D1 is the low-voltage input end.

[0016] Preferably, the internal power supply circuit comprises an N-type JFET tube J1, a diode D1, a resistor R3, a voltage drop circuit, a PMOS tube M1, an NMOS tube M2 and a comparator 4; the drain of the N-type JFET tube J1 is the high-voltage input end, the gate is grounded, and the source is connected with the input end of the voltage drop circuit, one end of the resistor R3 and the source of the PMOS tube M1; the positive end of the diode D1 is connected with the inverting input end of the comparator 4 and serves as the output end, and the negative end is connected with the drain of the PMOS tube M1 and serves as the output end; the other end of the resistor R3 is connected with the gate of the PMOS tube M1 and the drain of the NMOS tube; the non-inverting input end of the comparator 4 is connected with the output end of the voltage drop circuit, and the output end is connected with the gate of the NMOS tube M2; and the source of the NMOS tube M2 is grounded.

[0017] Preferably, the high-side power supply circuit comprises a diode D2, the positive end of the diode D2 is the input end, and the negative end is the output end.

[0018] Preferably, the high-side power supply circuit comprises a frequency detection circuit, an AND gate AND2, a capacitor C2, a diode D2, a diode D3 and a diode D4; the input end of the frequency detection circuit is the frequency detection input end of the high-side power supply circuit, and the output end is connected with one input end of the AND gate AND2; the other input end of the AND gate AND2 is the clock signal input end, and the output end is connected with one end of the capacitor C2; the other end of the capacitor C2 is connected with the negative end of the diode D3 and the positive end of the diode D4; the positive end of the diode D2 is connected with the positive end of the diode D3 and serves as the voltage input end, and the negative end is connected with the negative end of the diode D4 and serves as the output end.

[0019] Preferably, the frequency detection circuit comprises a counter, a buffer BUF1, an RS flip-flop 2 and a D flip-flop; the first input end of the counter is the clock signal input end, the second input end is connected with the input end of the buffer BUF1 and the clock input end Clk of the D flip-flop and serves as the frequency detection input end, and the output end is connected with the set end S of the RS flip-flop 2; the output end Q of the RS flip-flop 2 is connected with the data input end D of the D flip-flop; the enable end EN of the D flip-flop is connected with the signal VDDIN, and the output end Q outputs the signal FL.

[0020] Preferably, the level conversion circuit comprises an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, a PMOS tube M7, a PMOS tube M8, a high-voltage PMOS tube M5, a high-voltage PMOS tube M6, a high-voltage NMOS tube M3, a high-voltage NMOS tube M4, a diode D5 and a diode D6; the input end of the inverter INV1 is used as a frequency detection input end, the power supply end is connected with the power supply end of the inverter INV2 and used as a low-side power supply end, the ground end is connected with the ground end of the inverter INV2, the source end of the high-voltage NMOS tube M3 and the source end of the high-voltage NMOS tube M4 and used as a ground end, and the output end is connected with the input end of the inverter INV2 and the gate end of the high-voltage NMOS tube M4; the output end of the inverter INV2 is connected with the gate end of the high-voltage NMOS tube M3; the drain end of the high-voltage NMOS tube M3 is connected with the drain end of the high-voltage PMOS tube M5; the drain end of the high-voltage NMOS tube M4 is connected with the drain end of the high-voltage PMOS tube M6; the source end of the high-voltage PMOS tube M5 is connected with the drain end of the PMOS tube M7, the gate end of the PMOS tube M8 and the negative end of the diode D5, the gate end is connected with the positive end of the diode D5, the positive end of the diode D6, the gate end of the high-voltage PMOS tube M6, the lower end of the inverter INV3 and the lower end of the inverter INV4 and used as a floating ground SW; the source end of the high-voltage PMOS tube M6 is connected with the negative end of the diode D6, the gate end of the PMOS tube M7, the drain end of the PMOS tube M8 and the input end of the inverter INV3; the output end of the inverter INV3 is connected with the input end of the inverter INV4; the output end of the inverter INV4 outputs a signal; and the source end of the PMOS tube M7 is connected with the source end of the PMOS tube M8, the upper end of the inverter INV3 and the upper end of the inverter INV4 and used as a floating power supply BST.

[0021] The wide input switching type step-down circuit has the advantages that: the power switch device control circuit adopts the floating power supply and bootstrap power supply technology, can resist high voltage, is compatible with low voltage, and has a wide input voltage; after starting, the circuit can close the high-voltage current, reduce internal power consumption, and has high working efficiency; the circuit directly samples the output voltage and then feeds back to the control circuit to adjust the output voltage, so that the output voltage has high precision; and the circuit feeds back the output current signal by sampling the overcurrent resistance voltage drop, and the maximum output current can be adjusted by the overcurrent resistance, so that the circuit can adapt to more flexible applications. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 FIG. 1 is a schematic diagram of an existing switching step-down circuit;

[0023] Figure 2 FIG. 2 is a schematic diagram of a wide input switching type step-down circuit in an embodiment of the present application;

[0024] Figure 3 A structure diagram of a control circuit in an embodiment of the present application;

[0025] Figure 4 Another structure diagram of a control circuit in an embodiment of the present application;

[0026] Figure 5 A structure diagram of an internal power supply circuit in an embodiment of the present application;

[0027] Figure 6 Another structure diagram of an internal power supply circuit in an embodiment of the present application;

[0028] Figure 7 A structure diagram of a voltage drop circuit in an embodiment of the present application;

[0029] Figure 8 A structure diagram of a high-side power supply circuit in an embodiment of the present application;

[0030] Figure 9 Another structure diagram of a high-side power supply circuit in an embodiment of the present application;

[0031] Figure 10 A structure diagram of a frequency detection circuit in an embodiment of the present application;

[0032] Figure 11 A structure diagram of a level conversion circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions of the present application will be described in detail below with reference to the accompanying drawings.

[0034] As shown in Figure 2 the wide input switching type step-down circuit described in the present application includes an internal power supply circuit, a high-side power supply circuit, a reference circuit, an oscillator, a control circuit, a level conversion circuit, a buffer BUF0, a capacitor C0, a capacitor C1, a high-voltage NMOS tube M0, an inductor L0, a resistor R0, a resistor R1, a resistor R2 and a diode D0.

[0035] The high voltage input end of the internal power supply circuit is connected with the input signal VIN and the drain end of the high voltage NMOS M0; the low voltage input end is connected with one end of the resistor R1, the second current detection input end of the control circuit, one end of the resistor R0 and one end of the capacitor C0; the output end is connected with the input end of the high side power supply circuit, the low side power supply end of the level conversion circuit, the power supply end of the reference circuit, the power supply end of the oscillator and the power supply end of the control circuit. The output end of the high side power supply circuit is connected with the high side power supply end of the level conversion circuit, the power supply end of the buffer BUF0 and one end of the capacitor C1, and serves as the floating power supply BST. The reference voltage input end of the control circuit is connected with the output end of the reference circuit; the clock input end is connected with the output end of the oscillator; the voltage feedback input end is connected with the other end of the resistor R1 and one end of the resistor R2; the first current detection input end is connected with one end of the inductor L0 and the other end of the resistor R0; the output end is connected with the input end of the level conversion circuit; the floating ground end of the level conversion circuit is connected with the other end of the inductor L0, the floating ground end of the buffer BUF0, the other end of the capacitor C1, the source end of the high voltage NMOS M0 and the negative end of the diode D0, and serves as the floating ground SW. The output end of the buffer BUF0 is connected with the gate end of the high voltage NMOS M0. The other end of the resistor R2, the positive end of the diode D0 and the other end of the capacitor C0 are grounded.

[0036] Figure 2The working principle of the circuit is that: the internal power supply circuit converts the high voltage signal VIN and the output OUT into internal power supply, and provides power supply for the high-side power supply circuit, the reference circuit, the oscillator, the control circuit and the level conversion circuit, the high-side power supply circuit provides power supply for the level conversion circuit and the buffer BUF0. The reference circuit outputs a stable voltage signal VREF which is approximately independent of power supply and temperature. The oscillator outputs a clock signal CLK with fixed frequency. The sampling signal VFB is obtained by sampling the output voltage OUT through the voltage dividing resistors R1 and R2 and feeding back to the control circuit. The voltage VCS and the output voltage OUT across the resistor R0 are fed back to the control circuit, so as to sample the current flowing through the resistor R0. The control circuit generates a PWM signal according to the sampled output voltage and current, the PWM signal is processed by the level conversion circuit, and then the high-voltage NMOS transistor M0 is controlled to be turned on or turned off through the buffer BUF0. The control mode can be described as: when the output signal OUT is lower than the set value, the high-voltage NMOS transistor M0 is turned on, otherwise, the high-voltage NMOS transistor M0 is turned off; when the current flowing through the resistor R0 is low, the high-voltage NMOS transistor M0 is turned on, otherwise, the high-voltage NMOS transistor M0 is turned off. The circuit can convert the high-voltage DC signal VIN into a low-voltage stable signal OUT. The high-side power supply circuit supplies power to the floating power supply BST, and the internal power supply circuit supplies power to the reference circuit and the control circuit. When the circuit starts, the power supply of the internal circuit comes from VIN, and when the output voltage rises, the internal power supply is supplied by the output OUT, so as to reduce the power consumption of the circuit and improve the efficiency of the circuit.

[0037] Preferably, the control circuit has two structures, one structure is as shown in Figure 3 The non-inverting input terminal of the amplifier 1 is used as the reference voltage input terminal, the inverting input terminal is used as the feedback input terminal, and the output terminal is connected with the inverting input terminal of the comparator 1; the non-inverting input terminal of the amplifier 2 is used as the first current detection input terminal, the inverting input terminal is used as the second current detection input terminal, and the output terminal is connected with the non-inverting input terminal of the comparator 1; the output terminal of the comparator 1 is connected with the reset terminal R of the RS flip-flop 1; the set terminal S of the RS flip-flop 1 is used as the clock input terminal, and the output terminal Q outputs the signal PWM.

[0038] Figure 3The principle of the control circuit is that the circuit adopts voltage and current double-loop control, simultaneously amplifies output voltage and output current, amplifier 1 amplifies the difference between reference voltage VREF and sampling voltage VFB, and generates voltage VO, amplifier 2 amplifies the difference between VCS and OUT, and generates voltage VS, VO and VS are compared to generate the reset signal of RS flip-flop 1, the set signal of RS flip-flop 1 comes from clock signal CLK, and RS flip-flop 1 outputs PWM signal. The ripple of the output voltage OUT can be smaller, and the output voltage is more stable.

[0039] Preferably, another structure of the control circuit is as shown in Figure 4 The inverse input end of the comparator 2 is used as a feedback input end, the same-phase input end is used as a reference voltage input end and is connected with the same-phase input end of the comparator 3, and the output end is connected with the first input end of the AND gate AND1; the same-phase input end of the amplifier 2 is used as a first current detection input end, the inverse input end is used as a second current detection input end, and the output end is connected with the inverse input end of the comparator 3; the output end of the comparator 3 is connected with the second input end of the AND gate AND1; the output end of the AND gate AND1 is connected with the set end S of the RS flip-flop 1; the reset end R of the RS flip-flop 1 is used as a clock input end, and the output end Q outputs signal PWM.

[0040] Figure 4 The principle of the control circuit is that the comparator 2 compares output sampling voltage VFB and reference voltage VREF, and outputs level signal VO1, the amplifier 2 amplifies the difference between voltage signal VCS and OUT, and generates voltage VS, VS and VREF are compared through the comparator 3, the output voltage and VO1 are operated through the AND gate NAD1, and are transmitted to the set end of the RS flip-flop 1, the reset end of the RS flip-flop 1 comes from clock signal CLK, and the RS flip-flop 1 outputs PWM signal. The control mode of the structure is relatively simple, and a wider input range can be realized.

[0041] Preferably, the internal power supply circuit has two structures, one structure is as shown in Figure 5 The drain end of the N-type JFET tube J1 is used as a high-voltage input end, the gate end is grounded, the source end is connected with the negative end of the diode D1 and is used as an output end, and the positive end of the diode D1 is used as a low-voltage input end.

[0042] Figure 5The principle of the internal power supply circuit is that N-type JFET tube J1 is a depletion mode N-type junction field effect transistor (NJFET), and its opening threshold is negative voltage (VTHJ1). When the gate is grounded and the source voltage (VDDIN) is low, N-type JFET tube J1 is in the on state. When VDDIN is higher than the absolute value of the opening threshold of N-type JFET tube J1 (|VTHJ1|), N-type JFET tube J1 is turned off. Therefore, when OUT is low, the VDDIN voltage is approximately equal to the VIN voltage. When the OUT voltage minus the voltage drop (VD1) of diode D1 is greater than |VTHJ1|, N-type JFET tube J1 is turned off, and VDDIN is powered only through D1.

[0043] Preferably, another structure of the internal power supply circuit is as shown in Figure 6 The N-type JFET tube J1 has a high-voltage input end, a grounded gate end, and a source end connected to the input end of the voltage drop circuit, one end of the resistor R3, and the source end of the PMOS tube M1. The positive end of the diode D1 is connected to the inverting input end of the comparator 4 and serves as an output end, and the negative end is connected to the drain end of the PMOS tube M1 and serves as an output end. The other end of the resistor R3 is connected to the gate end of the PMOS tube M1 and the drain end of the NMOS tube. The non-inverting input end of the comparator 4 is connected to the output end of the voltage drop circuit, and the output end is connected to the gate end of the NMOS tube M2. The source end of the NMOS tube M2 is grounded.

[0044] Figure 6 The principle of the internal power supply circuit is that the voltage drop circuit in the circuit reduces the source voltage of N-type JFET tube J1 by a fixed value, and then serves as the non-inverting input of the comparator 4. When the OUT voltage is low, the comparator 4 outputs high, making the NMOS tube M2 conductive and the PMOS tube M1 conductive, and the VDDIN voltage is approximately equal to the VIN. When the OUT voltage rises and is higher than the source voltage of N-type JFET tube J1 by a fixed voltage value, the comparator 4 outputs low, the NMOS tube M2 is turned off, the PMOS tube M1 is turned off, and VDDIN is powered only by OUT through D1. This circuit is suitable for N-type JFET tube J1 with a high absolute value of the opening threshold, which is higher than the set voltage of OUT.

[0045] Preferably, Figure 7 The internal power supply circuit is Figure 6 The structure diagram of the voltage drop circuit in the internal power supply circuit is shown. The voltage drop circuit includes an NMOS tube M10, the source end of which is connected to the non-inverting input end of the comparator 4, and the gate end and drain end are connected to the source end of the N-type JFET tube J1, one end of the resistor R3, and the source end of the PMOS tube M1.

[0046] Preferably, the high-side power supply circuit has two structures, one structure as shown in Figure 8 , comprising a diode D2, the positive end of the diode D2 as an input end, and the negative end as an output end.

[0047] Preferably, the other structure of the high-side power supply circuit is as shown in Figure 9 , comprising a frequency detection circuit, an AND gate AND2, a capacitor C2, a diode D2, a diode D3 and a diode D4; the input end of the frequency detection circuit as the frequency detection input end of the high-side power supply circuit, and the output end connected with one input end of the AND gate AND2; the other input end of the AND gate AND2 as a clock signal input end, and the output end connected with one end of the capacitor C2; the other end of the capacitor C2 connected with the negative end of the diode D3 and the positive end of the diode D4; the positive end of the diode D2 connected with the positive end of the diode D3 and as a voltage input end, and the negative end connected with the negative end of the diode D4 and as an output end.

[0048] Preferably, as shown in Figure 10 , the frequency detection circuit comprises a counter, a buffer BUF1, an RS flip-flop 2 and a D flip-flop; the first input end of the counter as a clock signal input end, the second input end connected with the input end of the buffer BUF1 and the clock input end Clk of the D flip-flop and as a frequency detection input end, and the output end connected with the set end S of the RS flip-flop 2; the output end Q of the RS flip-flop 2 connected with the data input end D of the D flip-flop; the enable end EN of the D flip-flop connected with the signal VDDIN, and the output end Q outputting the signal FL.

[0049] Figure 9 、 Figure 10 The working principle of the high-side power supply circuit is as follows: when the PWM frequency is high, FL is low, and the output of the AND gate AND2 is 0; when the PWM frequency is low, FL is high, and the output of the AND gate AND2 is the same phase signal of CLK, which supplies power to BST through the capacitor C2. This solves the problem of insufficient power supply of the high-side floating power BST-SW at low frequency.

[0050] Preferably, as shown in Figure 11As shown, the level conversion circuit comprises an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, a PMOS transistor M7, a PMOS transistor M8, a high-voltage PMOS transistor M5, a high-voltage PMOS transistor M6, a high-voltage NMOS transistor M3, a high-voltage NMOS transistor M4, a diode D5 and a diode D6; an input end of the inverter INV1 is used as a frequency detection input end, a power supply end is connected with a power supply end of the inverter INV2 and used as a low-side power supply end, a ground end is connected with a ground end of the inverter INV2, a source end of the high-voltage NMOS transistor M3 and a source end of the high-voltage NMOS transistor M4 and used as a ground end, and an output end is connected with an input end of the inverter INV2 and a gate end of the high-voltage NMOS transistor M4; an output end of the inverter INV2 is connected with a gate end of the high-voltage NMOS transistor M3; a drain end of the high-voltage NMOS transistor M3 is connected with a drain end of the high-voltage PMOS transistor M5; a drain end of the high-voltage NMOS transistor M4 is connected with a drain end of the high-voltage PMOS transistor M6; a source end of the high-voltage PMOS transistor M5 is connected with a drain end of the PMOS transistor M7, a gate end of the PMOS transistor M8 and a negative end of the diode D5, a gate end is connected with a positive end of the diode D5, a positive end of the diode D6, a gate end of the high-voltage PMOS transistor M6, a lower end of the inverter INV3 and a lower end of the inverter INV4 and used as a floating ground SW; a source end of the high-voltage PMOS transistor M6 is connected with a negative end of the diode D6, a gate end of the PMOS transistor M7, a drain end of the PMOS transistor M8 and an input end of the inverter INV3; an output end of the inverter INV3 is connected with an input end of the inverter INV4; an output end of the inverter INV4 outputs a signal; and a source end of the PMOS transistor M7 is connected with a source end of the PMOS transistor M8, an upper end of the inverter INV3 and an upper end of the inverter INV4 and used as a floating power supply BST. The level conversion circuit can convert a low-voltage signal PWM into a high-voltage signal.

[0051] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware, and the program can be stored in a computer readable storage medium, which can be a read-only memory, a magnetic disk or an optical disk.

[0052] The above description is only used to explain the embodiments of the present application, and any modification, equivalent replacement, improvement and the like made within the spirit and principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A wide-input switching buck circuit, characterized in that, It includes an internal power supply circuit, a high-side power supply circuit, a reference circuit, an oscillator, a control circuit, a level conversion circuit, a buffer BUF0, a capacitor C0, a capacitor C1, a high-voltage NMOS transistor M0, an inductor L0, a resistor R0, a resistor R1, a resistor R2, and a diode D0; The high-voltage input terminal of the internal power supply circuit is connected to the input signal VIN and to the drain terminal of the high-voltage NMOS transistor M0; the low-voltage input terminal is connected to one end of resistor R1, the second current detection input terminal of the control circuit, one end of resistor R0, and one end of capacitor C0; the output terminal is connected to the input terminal of the high-side power supply circuit, the low-side power supply terminal of the level conversion circuit, the power supply terminal of the reference circuit, the power supply terminal of the oscillator, and the power supply terminal of the control circuit. The output of the high-side power supply circuit is connected to the high-side power supply terminal of the level conversion circuit, the power supply terminal of the buffer BUF0, and one end of the capacitor C1, and serves as the floating power supply BST. The reference voltage input terminal of the control circuit is connected to the output terminal of the reference circuit; The clock input is connected to the output of the oscillator; the voltage feedback input is connected to the other end of resistor R1 and one end of resistor R2; the first current detection input is connected to one end of inductor L0 and the other end of resistor R0; the output is connected to the input of the level conversion circuit. The floating ground terminal of the level conversion circuit is connected to the other end of inductor L0, the floating ground terminal of buffer BUF0, the other end of capacitor C1, the source terminal of high-voltage NMOS transistor M0, and the negative terminal of diode D0, and serves as the floating ground SW. The output terminal of the buffer BUF0 is connected to the gate terminal of the high-voltage NMOS transistor M0; The other end of resistor R2, the positive terminal of diode D0, and the other end of capacitor C0 are all grounded.

2. The wide-input switching buck circuit as described in claim 1, characterized in that, The control circuit includes amplifier 1, amplifier 2, comparator 1, and RS flip-flop 1. The non-inverting input of amplifier 1 serves as the reference voltage input, the inverting input serves as the feedback input, and the output is connected to the inverting input of comparator 1. The non-inverting input of amplifier 2 serves as the first current detection input, the inverting input serves as the second current detection input, and the output is connected to the non-inverting input of comparator 1. The output of comparator 1 is connected to the reset input R of RS flip-flop 1. The set input S of RS flip-flop 1 serves as the clock input, and the output Q outputs the PWM signal.

3. The wide-input switching buck circuit as described in claim 1, characterized in that, The control circuit includes amplifier 2, comparator 2, comparator 3, AND gate AND1, and RS flip-flop 1. The inverting input of comparator 2 serves as the feedback input, the non-inverting input serves as the reference voltage input and is connected to the non-inverting input of comparator 3, and the output is connected to the first input of AND gate AND1. The non-inverting input of amplifier 2 serves as the first current detection input, the inverting input serves as the second current detection input, and the output is connected to the inverting input of comparator 3. The output of comparator 3 is connected to the second input of AND gate AND1. The output of AND gate AND1 is connected to the set input S of RS flip-flop 1. The reset input R of RS flip-flop 1 serves as the clock input, and the output Q outputs the PWM signal.

4. The wide-input switching buck circuit as described in claim 1, characterized in that, The internal power supply circuit includes an N-type JFET J1 and a diode D1; the drain terminal of the N-type JFET J1 serves as the high-voltage input terminal, the gate terminal is grounded, and the source terminal is connected to the negative terminal of the diode D1 and serves as the output terminal; the positive terminal of the diode D1 serves as the low-voltage input terminal.

5. The wide-input switching buck circuit as described in claim 1, characterized in that, The internal power supply circuit includes an N-type JFET J1, a diode D1, a resistor R3, a voltage drop circuit, a PMOS transistor M1, an NMOS transistor M2, and a comparator 4. The drain of the N-type JFET J1 serves as the high-voltage input, its gate is grounded, and its source is connected to the input of the voltage drop circuit, one end of the resistor R3, and the source of the PMOS transistor M1. The positive terminal of the diode D1 is connected to the inverting input of the comparator 4 and serves as its output, while its negative terminal is connected to the drain of the PMOS transistor M1 and serves as its output. The other end of the resistor R3 is connected to the gate of the PMOS transistor M1 and the drain of the NMOS transistor. The non-inverting input of the comparator 4 is connected to the output of the voltage drop circuit, and its output is connected to the gate of the NMOS transistor M2. The source of the NMOS transistor M2 is grounded.

6. The wide-input switching buck circuit as described in claim 1, characterized in that, The high-side power supply circuit includes a diode D2, with the positive terminal of the diode D2 serving as the input terminal and the negative terminal serving as the output terminal.

7. The wide-input switching buck circuit as described in claim 1, characterized in that, The high-side power supply circuit includes a frequency detection circuit, an AND gate AND2, a capacitor C2, a diode D2, a diode D3, and a diode D4. The input terminal of the frequency detection circuit serves as the frequency detection input terminal of the high-side power supply circuit, and its output terminal is connected to one input terminal of the AND gate AND2. The other input terminal of the AND gate AND2 serves as the clock signal input terminal, and its output terminal is connected to one end of the capacitor C2. The other end of the capacitor C2 is connected to the negative terminal of the diode D3 and the positive terminal of the diode D4. The positive terminal of the diode D2 is connected to the positive terminal of the diode D3 and serves as the voltage input terminal, and its negative terminal is connected to the negative terminal of the diode D4 and serves as the output terminal.

8. The wide-input switching buck circuit as described in claim 7, characterized in that, The frequency detection circuit includes a counter, a buffer BUF1, an RS flip-flop 2, and a D flip-flop. The first input terminal of the counter serves as the clock signal input terminal, and the second input terminal is connected to the input terminal of the buffer BUF1 and the clock input terminal Clk of the D flip-flop, serving as the frequency detection input terminal. The output terminal is connected to the set terminal S of the RS flip-flop 2. The output terminal Q of the RS flip-flop 2 is connected to the data input terminal D of the D flip-flop. The enable terminal EN of the D flip-flop is connected to the signal VDDIN, and the output terminal Q outputs the signal FL.

9. The wide-input switching buck circuit as described in claim 1, characterized in that, The level conversion circuit includes inverters INV1, INV2, INV3, and INV4, PMOS transistors M7 and M8, high-voltage PMOS transistors M5 and M6, high-voltage NMOS transistors M3 and M4, diodes D5 and D6. The input terminal of inverter INV1 serves as the frequency detection input terminal. Its power supply terminal is connected to the power supply terminal of inverter INV2 and serves as the low-side power supply terminal. Its ground terminal is connected to the ground terminal of inverter INV2, the source terminal of high-voltage NMOS transistor M3, and the source terminal of high-voltage NMOS transistor M4 and serves as the ground terminal. Its output terminal is connected to the input terminal of inverter INV2 and the gate terminal of high-voltage NMOS transistor M4. The output terminal of inverter INV2 is connected to the gate terminal of high-voltage NMOS transistor M3. The drain terminal of high-voltage NMOS transistor M3 is connected to the drain terminal of high-voltage PMOS transistor M5. The drain of OS transistor M4 is connected to the drain of high-voltage PMOS transistor M6; the source of high-voltage PMOS transistor M5 is connected to the drain of PMOS transistor M7, the gate of PMOS transistor M8, and the negative terminal of diode D5. The gate of PMOS transistor M5 is connected to the positive terminals of diodes D5 and D6, the gate of high-voltage PMOS transistor M6, the lower terminal of inverter INV3, and the lower terminal of inverter INV4, serving as a floating ground SW; the source of high-voltage PMOS transistor M6 is connected to the negative terminal of diode D6, the gate of PMOS transistor M7, the drain of PMOS transistor M8, and the input of inverter INV3; the output of inverter INV3 is connected to the input of inverter INV4; the output of inverter INV4 outputs a signal; the source of PMOS transistor M7 is connected to the source of PMOS transistor M8, the upper terminal of inverter INV3, and the upper terminal of INV4, serving as a floating power supply BST.

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