Class D amplification system and class D amplification circuit

Abstract

The invention discloses a D-type amplification system and a D-type amplification circuit. The D-type amplification system comprises a first digital-to-analog converter, a D-type amplification circuit and a second digital-to-analog converter, wherein the first digital-to-analog converter converts a digital input signal to generate an analog input signal; the D-type amplifier circuit generates an output signal in a pulse width modulation manner according to an analog input signal, and the second digital-to-analog converter is configured to generate a common-mode adjustment current to adjust a common-mode voltage of the analog input signal according to one of: (1) a common-mode voltage of the analog input signal; and / or (2) a driving voltage. Wherein the driving voltage is used for supplying power to a power level circuit of the D-type amplifying circuit. The second digital-to-analog converter is based on (A) a level state of the output signal; and / or (B) a level state of a pulse width modulation signal of the class D amplification circuit to determine an option of a common mode adjustment current.

Description

[0001] This application is a divisional application of application number 202110302552.8, filed on March 22, 2021, entitled "Class D Amplification System and Class D Amplification Circuit". Technical Field

[0002] This invention relates to Class D amplification systems, and more particularly to Class D amplification systems in which the common-mode voltage is adjusted via a common-mode current-based digital-to-analog converter. The invention specifically relates to a Class D amplifier in which the common-mode voltage is adjusted via a common-mode current-based digital-to-analog converter. Background Technology

[0003] Please see Figure 1 This shows a known Class D amplification system. For example... Figure 1 As shown, this known Class D amplification system 10 includes a voltage-to-digital converter 101, a low-pass filter 102, and a Class D amplifier 103. As... Figure 1 As shown, the Class D amplifier 103 includes an amplifier 1031. This known Class D amplification system 10 utilizes amplifier 1031 and low-pass filter 102 to control the common-mode voltages of the positive sub-signal Viip and the negative sub-signal Viin of the analog input signal Vii at the analog input node 105 of the Class D amplifier 103. However, the voltage-to-analog converter 101, the low-pass filter 102, and the amplifier 1031 all contribute additional noise. Summary of the Invention

[0004] In one viewpoint, the present invention provides a Class D amplification system comprising: an input current-based digital-to-analog converter for converting a digital input signal and generating an analog input signal at an analog input node, wherein the analog input signal includes a positive analog input signal and a negative analog input signal, respectively generated at a positive analog input node and a negative analog input node included in the analog input node; a Class D amplification circuit coupled to the input current-based digital-to-analog converter, the Class D amplification circuit comprising: a pulse width modulator for generating a pulse width modulation signal according to the analog input signal, the pulse width modulation signal including a positive pulse width modulation sub-signal and a negative pulse width modulation sub-signal; a full-bridge power stage circuit for generating an output signal according to the pulse width modulation signal, the output signal including a positive output sub-signal and a negative output sub-signal, wherein the full-bridge power stage circuit is powered by a drive voltage; and a feedback element for feeding back the output signal to the analog input. A node; and a common-mode current-based digital-to-analog converter coupled to the analog input node for generating a common-mode adjustment current, comprising a positive common-mode sub-adjustment current and a negative common-mode sub-adjustment current, generated at the positive analog input node and the negative analog input node, respectively; wherein the common-mode current-based digital-to-analog converter selectively determines the positive common-mode sub-adjustment current and the negative common-mode adjustment current in relation to a common-mode voltage of the analog input signal, or simultaneously in relation to the common-mode voltage of the analog input signal and the drive voltage, based on (A) the difference between the level states of the positive output sub-signal and the negative output sub-signal, or based on (B) the difference between the level states of the positive pulse width modulation sub-signal and the negative pulse width modulation sub-signal, or based on (C) a combination of the difference between the level states of the positive output sub-signal and the negative output sub-signal and the difference between the level states of the positive pulse width modulation sub-signal and the negative pulse width modulation sub-signal.

[0005] In one embodiment, the Class D amplifier circuit further includes a first amplifier coupled between the pulse width modulator and the analog input node for buffering and amplifying the analog input signal.

[0006] In one embodiment, the Class D amplifier circuit further includes a second amplifier coupled between the analog input node and the input terminal of the first amplifier, the second amplifier being used to control the common-mode voltage of the analog input signal via a virtual grounding method.

[0007] In one embodiment, the positive common-mode adjustment current and the negative common-mode adjustment current are positively correlated with the common-mode voltage of the analog input signal.

[0008] In one embodiment, in option (A) or (C), when both the positive output sub-signal and the negative output sub-signal are in a high-level state, the common-mode adjustment current is negatively correlated with the drive voltage.

[0009] In one embodiment, in option (A) or (C), when the level states of the positive output sub-signal and the negative output sub-signal are different, the common-mode adjustment current is negatively correlated with 1 / 2 of the drive voltage.

[0010] In one embodiment, in an adaptive voltage positioning mode, the common-mode adjustment current is also positively correlated with a preset voltage difference, wherein the preset voltage difference is related to the amplitude of the output signal, the slope of the output signal, and the impedance value of the feedback element, wherein in the adaptive voltage positioning mode, a target value of the common-mode voltage of the analog input signal is synchronous with and related to a common-mode voltage of the output signal.

[0011] In one embodiment, under the adaptive voltage positioning mode, and in option (A), when the level states of the positive output sub-signal and the negative output sub-signal are the same, the common-mode adjustment current is also positively correlated with the preset voltage difference.

[0012] In one embodiment, in the adaptive voltage positioning mode and also with a fast response mode, corresponding to option (C), when the level states of the positive output sub-signal and the positive pulse width modulation sub-signal are different, and / or when the level states of the negative output sub-signal and the negative pulse width modulation sub-signal are different, the common-mode adjustment current is also positively correlated with the product of the preset voltage difference and a preset coefficient.

[0013] In one embodiment, the preset coefficient is a real number between 0 and 1.

[0014] In one embodiment, the common-mode adjustment current is inversely related to the impedance value of the feedback element.

[0015] In one embodiment, the common-mode current-based digital-to-analog converter includes: a decoder for decoding a switching control signal based on the pulse width modulation signal and the clamped output signal; and a current determination circuit including a plurality of intermediate current sources and a plurality of adjustment switches, wherein the switching control signal is used to control the plurality of adjustment switches to switch the plurality of intermediate current sources to generate the corresponding common-mode adjustment current.

[0016] In one embodiment, the common-mode current-based digital-to-analog converter further includes a voltage clamp for clamping the output signal to generate the clamped output signal.

[0017] In one embodiment, the voltage clamp includes: a clamping transistor for generating an intermediate signal based on the output signal and a signal power supply; and a buffer for generating the clamped output signal based on the intermediate signal, wherein the signal power supply supplies power to the buffer.

[0018] In one embodiment, the current determination circuit includes: at least one voltage-to-current conversion circuit for converting the common-mode voltage or the drive voltage of the analog input signal into at least one corresponding reference current; and a plurality of current mirrors for mirroring the plurality of intermediate current sources according to the at least one reference current.

[0019] In one embodiment, the common-mode current digital-to-analog converter is disabled when the output signal is zero to reduce noise.

[0020] In one embodiment, in option (C), the common-mode current-based digital-to-analog converter selectively determines the common-mode adjustment current relative to the common-mode voltage of the analog input signal, or simultaneously relative to the common-mode voltage of the analog input signal and the drive voltage, based on the delay relationship between the output signal and the pulse width modulation signal.

[0021] In another viewpoint, the present invention provides a Class D amplifier circuit for receiving an analog input signal from an analog input node and converting the analog input signal to generate an output signal, wherein the analog input signal includes a positive analog input signal and a negative analog input signal, respectively generated at a positive analog input node and a negative analog input node included in the analog input node. The Class D amplifier circuit includes: a pulse width modulator for generating a pulse width modulated signal based on the analog input signal, which includes a positive pulse width modulated sub-signal and a negative pulse width modulated sub-signal; a full-bridge power stage circuit for generating the output signal based on the pulse width modulated signal, which includes a positive output sub-signal and a negative output sub-signal, wherein the full-bridge power stage circuit is powered by a drive voltage; a feedback element for feeding the output signal back to the analog input node; and a common-mode current digital analog-to-digital converter. A common-mode converter, coupled to the analog input node, generates a common-mode adjustment current, including a positive common-mode sub-adjustment current and a negative common-mode sub-adjustment current, generated at the positive analog input node and the negative analog input node, respectively; wherein the common-mode current-based digital-to-analog converter selectively determines the positive common-mode sub-adjustment current and the negative common-mode adjustment current in relation to a common-mode voltage of the analog input signal, or simultaneously in relation to the common-mode voltage of the analog input signal and the drive voltage, based on (A) the difference between the level states of the positive output sub-signal and the negative output sub-signal, or based on (B) the difference between the level states of the positive pulse width modulation sub-signal and the negative pulse width modulation sub-signal, or based on (C) a combination of the difference between the level states of the positive output sub-signal and the negative output sub-signal and the difference between the level states of the positive pulse width modulation sub-signal and the negative pulse width modulation sub-signal.

[0022] One advantage of this invention is that by utilizing an input current-based digital-to-analog converter, the second amplifier can be omitted, thereby further reducing noise. Furthermore, when the output signal is zero, the common-mode current-based digital-to-analog converter can further reduce noise by disabling it.

[0023] Another advantage of the present invention is that the common-mode current digital-to-analog converter of the present invention enhances the response speed of the common-mode voltage of the analog input signal in a nonlinear manner to compensate for the insufficient bandwidth or slew rate of the linear amplifier circuit of the Class D amplifier circuit (e.g., but not limited to the first amplifier and the second amplifier), and can reduce the slew rate, bandwidth or current requirements of the second amplifier.

[0024] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features, and effects achieved by the present invention. Attached Figure Description

[0025] Figure 1 Show a known Class D amplification system.

[0026] Figure 2 This is a circuit diagram of a Class D amplifier system according to an embodiment of the present invention.

[0027] Figure 3 This is a circuit diagram of a Class D amplifier system according to another embodiment of the present invention.

[0028] Figure 4 This is a circuit diagram of a common-mode current digital-to-analog converter for a Class D amplifier system according to an embodiment of the present invention.

[0029] Figure 5 This is a circuit diagram of a voltage clamp for a common-mode current-type digital-to-analog converter in a Class D amplification system, according to an embodiment of the present invention.

[0030] Figure 6 This is a reference table showing the signals of a common-mode current digital-to-analog converter of a Class D amplifier system according to an embodiment of the present invention.

[0031] Figure 7 This is a reference table showing the signals of a common-mode current-type digital-to-analog converter of a Class D amplifier system according to another embodiment of the present invention.

[0032] Figure 8 This is a reference table showing the signals of a common-mode current digital-to-analog converter of a Class D amplifier system according to another embodiment of the present invention.

[0033] Figure 9 It corresponds to Figure 6 The waveform diagram of the operation.

[0034] Figure 10 It corresponds to Figure 7 The waveform diagram of the operation.

[0035] Figure 11 It corresponds to Figure 8 The waveform diagram of the operation.

[0036] Figure 12 This is a circuit diagram illustrating the current determination circuit of a common-mode current-based digital-to-analog converter in a Class D amplifier system according to an embodiment of the present invention.

[0037] Explanation of symbols in the diagram

[0038] 10, 20, 20': Class D amplification system

[0039] 101: Voltage-type digital-to-analog converter

[0040] 102: Low-pass filter

[0041] 103: Class D amplifier

[0042] 1031: Amplifier

[0043] 105, 205: Analog input nodes

[0044] 105n, 205n: Negative child nodes

[0045] 105p, 205p: Positive child nodes

[0046] 201: Input Current Type Digital-to-Analog Converter

[0047] 202: Second Amplifier

[0048] 203: Class D amplifier circuit

[0049] 2031: Pulse Width Modulator

[0050] 2032: Full-bridge power stage circuit

[0051] 2033: Feedback Components

[0052] 2034: The First Amplifier

[0053] 204: Common-mode current digital-to-analog converter

[0054] 2041: Decoder

[0055] 2042n, 2042p: Current-determining circuits

[0056] 20421a, 20421b, 20421c: Voltage-to-current conversion circuits

[0057] 204211a, 204211b, 204211c: Error amplifiers

[0058] 204212a, 204212b, 204212c: Resistors

[0059] 204213, 20422a, 20422b, 20422c: Current mirrors

[0060] 2043[1:2]: Voltage clamp

[0061] B[1:2]: Buffer

[0062] Gd[1:n], Gu[1:n]: Switch control signals

[0063] Ica: Common-mode regulation current

[0064] Ican: Negative signal

[0065] Icap: positron signal

[0066] Vii: Analog input signal

[0067] Viin: Negative signal

[0068] Viip: positron signal

[0069] INd: Digital input signal

[0070] INdn: Negative signal

[0071] INdp: positron signal

[0072] Idn[1:n], Idn[1], Idn[2], Iup[1:n], Iup[1]~Iup[8]: Intermediate current source

[0073] Irf1, Irf2, Irf3: Reference currents

[0074] Na: Node

[0075] Om[1:2]: Intermediate signal

[0076] Opwm: Pulse Width Modulation Signal

[0077] Opwmn: Negative signal

[0078] Opwmp: positron signal

[0079] OUTc[1:2]: Clamped output signal

[0080] PVDD: Drive voltage

[0081] Qc[1:2]: Clamped transistor

[0082] Qd[1], Qd[2], Qu[1]~Qu[8]: mirror transistors

[0083] Qia, Qib, Qiic: Conversion transistor

[0084] Qm: Mirror transistor

[0085] Rf: Impedance value

[0086] Sd[1:n], Sd[1], Sd[2], Su[1:n], Su[1]~Su[8]: Adjust the switch

[0087] VDD: Signal power supply

[0088] Vout: Output signal

[0089] Voutn: Negative signal

[0090] Voutp: positron signal Detailed Implementation

[0091] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0092] Figure 2 This is a circuit diagram (Class D amplifier system 20) showing a Class D amplifier system according to an embodiment of the present invention. Figure 2 As shown, the Class D amplification system 20 of the present invention includes an input current-based digital-to-analog converter 201, a Class D amplifier circuit 203, and a common-mode current-based digital-to-analog converter 204. The input current-based digital-to-analog converter 201 converts the digital input signal INd to generate an analog input signal Vii at the analog input node 205. The Class D amplifier circuit 203 is coupled to the input current-based digital-to-analog converter 201. (Refer to...) Figure 2The Class D amplifier circuit 203 includes a pulse width modulator 2031, a full-bridge power stage circuit 2032, a feedback element 2033, and a first amplifier 2034. The input terminal of the pulse width modulator 2031 is coupled to the output terminal of the input current-based digital-to-analog converter 201, and the pulse width modulator 2031 generates a pulse width modulation signal Opwm based on the analog input signal Vii. The input terminal of the full-bridge power stage circuit 2032 is coupled to the output terminal of the pulse width modulator 2031, and the full-bridge power stage circuit 2032 generates an output signal Vout based on the pulse width modulation signal Opwm. The full-bridge power stage circuit 2032 is powered by a drive voltage PVDD. The feedback element 2033 is coupled between the output terminal of the full-bridge power stage circuit 2032 and the input terminal of the first amplifier 2034, and is used to feed back the output signal Vout to the corresponding analog input node 205. In one embodiment, the impedance value of the feedback element 2033 is Rf. The first amplifier 2034 is coupled between the pulse width modulator 2031 and the analog input node 205 to buffer and amplify the analog input signal Vii.

[0093] like Figure 2 As shown, a common-mode current-based digital-to-analog converter 204 is coupled to the analog input node 205 to generate a common-mode adjustment current Ica. Since the signals in the Class D amplifier system 20 are fully differential signals, the digital input signal INd, the analog input signal Vii, the pulse width modulation signal Opwm, the output signal Vout, and the common-mode adjustment current Ica are all paired, each including a corresponding positive and negative sub-signals. For example, the positive sub-signal INdp and the negative sub-signal INdn of the digital input signal INd, the positive sub-signal Viip and the negative sub-signal Viin of the analog input signal Vii, the positive sub-signal Opwmp and the negative sub-signal Opwmn of the pulse width modulation signal Opwm, the positive sub-signal Voutp and the negative sub-signal Voutn of the output signal Vout, and the positive sub-signal Icap and the negative sub-signal Ican of the common-mode adjustment current Ica. In one embodiment, the positive sub-signal Icap and the negative sub-signal Ican of the common-mode adjustment current Ica are equal. The analog input nodes 205 are also paired, including positive child node 205p and negative child node 205n, and the feedback elements 2033 are also paired, including positive feedback element 2033p and negative feedback element 2033n.

[0094] Figure 3 This is a circuit diagram of a Class D amplifier system according to another embodiment of the present invention. This embodiment is similar to... Figure 2The difference in this embodiment lies in that the Class D amplification system 20' further includes a second amplifier 202, coupled between the analog input node 205 and the input terminal of the first amplifier 2034. The second amplifier 202 is used to control the common-mode voltage Viic of the analog input signal Vii through a virtual grounding method. The input current digital-to-analog converter 201, the Class D amplification circuit 203, and the common-mode current digital-to-analog converter 204 in this embodiment are similar to Figure 2 The input current-type digital-to-analog converter 201, the Class D amplifier circuit 203, and the common-mode current-type digital-to-analog converter 204 are described in detail, so their detailed descriptions are omitted.

[0095] It is worth noting that, in one embodiment, the filtering function required by the Class D amplification system on its signal path can be performed digitally in the pre-stage digital signal processing circuit that generates the digital input signal INd. In another embodiment, the aforementioned filtering function can be achieved by configuring the impedance value of the feedback element 2033.

[0096] Figure 4 This is a circuit diagram (common-mode current digital-to-analog converter 204) of a Class D amplifier system according to an embodiment of the present invention. Figure 4 As shown, the common-mode current digital-to-analog converter 204 includes a decoder 2041, a current determining circuit 2042n and 2042p, and a voltage clamp 2043 [1:2].

[0097] Decoder 2041 is used to decode and generate a switch control signal Gu[1:n] and Gd[1:n] based on the pulse width modulation signal Opwm and / or the output signal Vout.

[0098] The current determining circuits 2042n and 2042p include multiple intermediate current sources Iup[1:n] and Idn[1:n] and multiple adjusting switches Su[1:n] and Sd[1:n], where n is greater than or equal to 1. Switch control signals Gu[1:n] and Gd[1:n] are used to control the corresponding multiple adjusting switches Su[1:n] and Sd[1:n] respectively, thereby switching the corresponding multiple intermediate current sources Iup[1:n] and Idn[1:n] to generate the corresponding common-mode adjusting current Ica. In one embodiment, when the output signal Vout is zero, the common-mode current-based digital-to-analog converter 204 is disabled to reduce noise. In other words, at this time, the multiple adjusting switches Su[1:n] and Sd[1:n] are all open circuits, and the common-mode adjusting current Ica is 0.

[0099] In one embodiment, when the power supply level of the full-bridge power stage circuit 2032 is different from the internal power supply level of the signal processing circuit (e.g., common-mode current digital-to-analog converter 204), a voltage clamp 2043 [1:2] can be configured, for example, before the decoder 2041, to clamp the output signal Vout and generate a clamped output signal OUTc [1:2], so as to avoid the output signal Vout being too high and burning out the signal processing circuit in the common-mode current digital-to-analog converter 204.

[0100] Figure 5 This is a circuit diagram illustrating the voltage clamp of a common-mode current-based digital-to-analog converter in a Class D amplifier system, according to an embodiment of the present invention. Figure 5 As shown, each of the voltage clampers 2043[1:2] includes a corresponding clamping transistor Qc[1:2] and a buffer B[1:2]. The source terminal of the clamping transistor Qc[1:2] is coupled to the input terminal of the buffer B[1:2], and the drain terminal of the clamping transistor Qc[1:2] receives the output signals Voutp and Voutn respectively. The gate terminal of the clamping transistor Qc[1:2] is coupled to a signal power supply VDD. The clamping transistor Qc[1:2] is used to generate a corresponding intermediate signal Om[1:2] according to the output signal Vout and the signal power supply VDD. The buffer B[1:2] is used to generate a clamped output signal OUTc[1:2] according to the intermediate signal Om[1:2]. In one embodiment, the signal power supply VDD supplies power to the buffer B[1:2].

[0101] In one embodiment, the common-mode adjustment current Ica is related to one of the following options: (1) the common-mode voltage Viic of the analog input signal Vii; (2) the drive voltage PVDD; or (3) the common-mode voltage Viic of the analog input signal Vii and the drive voltage PVDD.

[0102] In one embodiment, the common-mode current-mode digital-to-analog converter 204 determines the option of the common-mode adjustment current Ica based on one of the following states: (A) based on the level state of the output signal Vout (specifically, based on the level states of the positive sub-signals Voutp and Voutn of the output signal Vout); (B) based on the level state of the pulse width modulation signal Opwm (specifically, based on the level states of the positive sub-signals Opwmp and Opwmn of the pulse width modulation signal Opwm); or (C) based on the level state of the output signal Vout and the level state of the pulse width modulation signal Opwm.

[0103] Figures 6-8 This is a lookup table showing the signals of a common-mode current-based digital-to-analog converter in a Class D amplifier system according to an embodiment of the present invention. Figure 6This illustrates a common-mode current digital-to-analog converter operating in normal mode. Figure 7 This illustrates a common-mode current-based digital-to-analog converter operating in adaptive voltage position (AVP) mode. Figure 8 This illustration shows a common-mode current-mode digital-to-analog converter operating in an adaptive voltage positioning mode with fast response (QR).

[0104] Figures 9-11 To correspond to respectively Figures 6-8 The waveform diagram is shown below. Please also refer to... Figure 6 and Figure 9 Specifically, in normal mode, the options for the common-mode adjustment current Ica can be determined solely based on the level of the output signal Vout.

[0105] like Figure 6 As shown, in one embodiment, in normal mode, the common-mode adjustment current Ica is positively correlated with the common-mode voltage Viic of the analog input signal Vii.

[0106] like Figure 6 As shown, in one embodiment, the common-mode adjustment current Ica is negatively correlated with the drive voltage PVDD. It should be noted that in this embodiment, the current direction of the common-mode adjustment current Ica is as follows: Figures 2-4 as well as Figure 12 direction shown.

[0107] Specifically, such as Figure 6 As shown, in one embodiment, under normal operating mode, when the positive sub-signal Voutp and the negative sub-signal Voutn of the output signal Vout are both in a high-level state (e.g., ... Figure 6 As shown, when the high-level state is marked as 1, the common-mode adjustment current Ica is negatively correlated with the driving voltage PVDD. When the levels of the positive sub-signal Voutp and the negative sub-signal Voutn of the output signal Vout are different (e.g., ...), the common-mode adjustment current Ica is negatively correlated with the driving voltage PVDD. Figure 6 As shown, when one is a high level and the other is a low level, the common-mode adjustment current Ica is negatively correlated with half of the driving voltage PVDD. In one embodiment, when the positive sub-signal Voutp and the negative sub-signal Voutn of the output signal Vout are both in a low level state (e.g., ...), the common-mode adjustment current Ica is negatively correlated with half of the driving voltage PVDD. Figure 6 As shown, when the low-level state is marked as 0, the common-mode adjustment current Ica is not related to the driving voltage PVDD.

[0108] In one embodiment, such as Figure 6 As shown, the common-mode adjustment current Ica is inversely correlated with the impedance value Rf of the feedback element 2033.

[0109] In another embodiment, it is also possible to Figure 6 The level state of the output signal Vout is replaced by an option to determine the common-mode adjustment current Ica based on the level state of the pulse width modulation signal Opwm. In other words, in one embodiment, the relationship between the level state of the pulse width modulation signal Opwm and the option of the common-mode adjustment current Ica can be compared with... Figure 6 The relationship between the level state of the output signal Vout and the option of the common-mode adjustment current Ica.

[0110] Please also refer to Figure 7 and Figure 10 This embodiment is the same as the one described above. Figure 6 and Figure 9 Similar to the adaptive voltage positioning mode, the difference lies in that, in this mode, the common-mode adjustment current Ica is also positively correlated with a preset voltage difference ΔV. In one embodiment, the preset voltage difference ΔV is related to the amplitude of the output signal Vout, the slope of the output signal Vout, and the impedance value Rf of the feedback element 2033. In one embodiment, in the adaptive voltage positioning mode, a target value of the common-mode voltage Viic of the analog input signal Vii is synchronously and related to a common-mode voltage of the output signal Vout (e.g., ...). Figure 10 As shown), when the common-mode voltage Viic is converted to the common-mode voltage of the output signal Vout, the common-mode voltage Viic adaptively adjusts its target level according to the common-mode voltage of the output signal Vout. That is, adaptive voltage positioning. This reduces the ripple of the common-mode voltage Viic of the analog input signal Vii, and thus also reduces, for example, the slew rate, bandwidth, or current requirements of the second amplifier 202. Figure 10 As shown, the waveform of the analog input signal Vii (Viip, Viin) approaches the waveform of the output signal Vout (Voutp, Voutn). Here, "approaches" refers only to the waveform, not the magnitude.

[0111] like Figure 7 As shown, in a specific embodiment, in adaptive voltage positioning mode, when the positive sub-signal Voutp of the output signal Vout and the negative sub-signal Voutn of the output signal Vout are at the same level (e.g., Figure 7 As shown, when all are at high level or all are at low level, the common-mode adjustment current Ica is also positively correlated with the preset voltage difference ΔV.

[0112] Please also refer to Figure 8 and Figure 11 This embodiment is the same as the one described above. Figure 7 and Figure 10 Similar, the difference lies in, such as Figure 8As shown, in one embodiment, in an adaptive voltage positioning mode with fast response, the option of common-mode adjustment current Ica is determined simultaneously based on the level state of the output signal Vout and the level state of the pulse width modulation signal Opwm, and the common-mode adjustment current Ica has a more detailed correlation with the preset voltage difference ΔV. Figure 11 As shown, the waveform of the analog input signal Vii (Viip, Viin) is closer to the waveform of the output signal Vout (Voutp, Voutn). In fact, for example... Figure 3 As can be seen from the embodiments, the pulse width modulation signal Opwm is the pre-amplifier signal of the output signal Vout. Therefore, from one point of view, in Figure 8 In the embodiments, the option of the common-mode adjustment current Ica (i.e., the adjustment method) is determined based on the delay relationship between the pulse width modulation signal Opwm and the output signal Vout. In other words, especially when there is a delay between the pulse width modulation signal Opwm and the output signal Vout, that is, when the level state of the output signal Vout is different from the level state of the pulse width modulation signal Opwm, the adjustment is further determined based on, for example... Figure 8 And adjust the common-mode adjustment current Ica.

[0113] Specifically Figure 8 For example, when the positive sub-signal Voutp of the output signal Vout is at a different level than the positive sub-signal Opwmp of the pulse width modulation signal Opwm (e.g.) Figure 8 As shown, the positive sub-signal Voutp is at a high level and the positive sub-signal Opwmp is at a low level, or the positive sub-signal Voutp is at a low level and the positive sub-signal Opwmp is at a high level), and / or, when the level states of the negative sub-signal Voutn of the output signal Vout and the negative sub-signal Opwmn of the pulse width modulation signal Opwm are different (e.g., Figure 8 As shown, when the negative sub-signal Voutn is at a high level and the negative sub-signal Opwmn is at a low level, or vice versa, the common-mode adjustment current Ica is positively correlated with the product of a preset voltage difference ΔV and a preset coefficient (e.g., K1~K6). It should be noted that K1~K6 determine the degree to which the waveforms of the analog input signals Vii (Viip, Viin) and the output signals Vout (Voutp, Voutn) approximate each other.

[0114] Please also refer to Figure 11In the adaptive voltage positioning mode with fast response, the common-mode adjustment current Ica can adaptively enhance the response speed of the common-mode voltage Viic of the analog input signal Vii in a nonlinear manner according to the product of the aforementioned preset voltage difference ΔV and a preset coefficient (e.g., K1~K6), thereby assisting the linear amplifier circuit of the Class D amplifier circuit (e.g., but not limited to the first amplifier 2034 and the second amplifier 202) to compensate for insufficient bandwidth or torsion. This allows the common-mode voltage Viic of the analog input signal Vii to quickly reach a stable state and reduces the ripple of the common-mode voltage Viic, thereby also reducing the torsion, bandwidth, or current requirements of the second amplifier 202. In one embodiment, the preset coefficients, for example, K1~K6, are real numbers between 0 and 1.

[0115] Specifically, refer to Figure 6 When the positive sub-signal Voutp of the output signal Vout is in a high-level state (e.g., corresponding to the drive voltage PVDD) and the negative sub-signal Voutn of the output signal Vout is in a high-level state (e.g., corresponding to the drive voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii minus the drive voltage PVDD divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be the net inflow from the analog input node 205.

[0116] Please continue reading. Figure 6 When the positive sub-signal Voutp of the output signal Vout is at a high level (e.g., corresponding to the drive voltage PVDD) and the negative sub-signal Voutn of the output signal Vout is at a low level (e.g., zero), or when the positive sub-signal Voutp of the output signal Vout is at a low level (e.g., zero) and the negative sub-signal Voutn of the output signal Vout is at a high level (e.g., corresponding to the drive voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii minus half of the drive voltage PVDD, divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be a net inflow from the analog input node 205. When the positive sub-signal Voutp of the output signal Vout is at a low level (e.g., zero) and the negative sub-signal Voutn of the output signal Vout is at a low level (e.g., zero), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii divided by the impedance value Rf of the feedback element 2033. It should be noted that, in this case, the common-mode regulation current Ica can be a net outflow to the analog input node 205.

[0117] Please refer to the following: Figure 7When the positive sub-signal Voutp of the output signal Vout is at a high level (e.g., corresponding to the drive voltage PVDD), and the negative sub-signal Voutn of the output signal Vout is at a high level (e.g., corresponding to the drive voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii plus the preset voltage difference ΔV minus the drive voltage PVDD, divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be a net inflow from the analog input node 205. When the positive sub-signal Voutp of the output signal Vout is at a high level (e.g., corresponding to the drive voltage PVDD) and the negative sub-signal Voutn of the output signal Vout is at a low level (e.g., zero), or when the positive sub-signal Voutp of the output signal Vout is at a low level (e.g., zero) and the negative sub-signal Voutn of the output signal Vout is at a high level (e.g., corresponding to the drive voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii minus half the drive voltage PVDD, divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be a net inflow from the analog input node 205. When the positive sub-signal Voutp of the output signal Vout is at a low level (e.g., zero), and the negative sub-signal Voutn of the output signal Vout is at a low level (e.g., zero), the common-mode adjustment current Ica is the sum of the common-mode voltage Viic of the analog input signal Vii and the preset voltage difference ΔV, divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be a net outflow to the analog input node 205.

[0118] Please refer to the following: Figure 8When the positive sub-signal Opwmp of the pulse width modulation signal Opwm is in a high-level state (e.g., corresponding to the signal power supply VDD), and the negative sub-signal Opwmn of the pulse width modulation signal Opwm is in a high-level state (e.g., corresponding to the signal power supply VDD), (1) when the positive sub-signal Voutp of the output signal Vout is in a high-level state (e.g., corresponding to the driving voltage PVDD), and the negative sub-signal Voutn of the output signal Vout is in a high-level state (e.g., corresponding to the driving voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii plus the preset voltage difference ΔV minus the value of the driving voltage PVDD divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be the net inflow from the analog input node 205; (2) when the positive sub-signal Voutp of the output signal Vout is in a high-level state (e.g., corresponding to the driving voltage PVDD), and the negative sub-signal Voutn of the output signal Vout is in a high-level state (e.g., corresponding to the driving voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii plus the value of the driving voltage PVDD divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be the net inflow from the analog input node 205; When the output signal Vout is in a low-level state (e.g., zero), or when the positive sub-signal Voutp of the output signal Vout is in a low-level state (e.g., zero), and the negative sub-signal Voutn of the output signal Vout is in a high-level state (e.g., corresponding to the driving voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii plus a first coefficient K1 multiplied by a preset voltage difference ΔV minus half of the driving voltage PVDD divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be the net inflow from the analog input node 205; or (3) when the positive sub-signal Voutp of the output signal Vout is in a low-level state (e.g., zero), and the negative sub-signal Voutn of the output signal Vout is in a low-level state (e.g., zero), the common-mode adjustment current Ica is the sum of the common-mode voltage Viic of the analog input signal Vii and a second coefficient K2 multiplied by a preset voltage difference ΔV divided by the impedance value Rf of the feedback element 2033. It should be noted that, in this case, the common-mode adjustment current Ica can be a net outflow to the analog input node 205. In one embodiment, both the first coefficient K1 and the second coefficient K2 are real numbers between 0 and 1.

[0119] Continue to refer to Figure 8When the positive sub-signal Opwmp of the pulse width modulation signal Opwm is in a high-level state (e.g., corresponding to the signal power supply VDD), and the negative sub-signal Opwmn of the pulse width modulation signal Opwm is in a low-level state (e.g., zero), or when the positive sub-signal Opwmp of the pulse width modulation signal Opwm is in a low-level state (e.g., zero), and the negative sub-signal Opwmn of the pulse width modulation signal Opwm is in a high-level state (e.g., corresponding to the signal power supply VDD), (1) when the positive sub-signal Voutp of the output signal Vout is in a high-level state. In the quasi-state (e.g., corresponding to the driving voltage PVDD), when the negative sub-signal Voutn of the output signal Vout is in the high-level quasi-state (e.g., corresponding to the driving voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii plus a third coefficient K3 multiplied by the preset voltage difference ΔV minus the driving voltage PVDD divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be the net inflow from the analog input node 205; (2) when the output signal Vo When the positive sub-signal Voutp of the output signal Vout is at the same level as the positive sub-signal Opwmp of the pulse width modulation signal Opwm, and the negative sub-signal Voutn of the output signal Vout is at the same level as the negative sub-signal Opwmn of the pulse width modulation signal Opwm, and the positive sub-signal Voutp of the output signal Vout is not equal to the negative sub-signal Voutn of the output signal Vout, the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii minus half the driving voltage PVDD, divided by the feedback element. Regarding the impedance value Rf of feedback element 2033, it should be noted that in this case, the common-mode adjustment current Ica can be a net inflow from analog input node 205; or (3) when the positive sub-signal Voutp of output signal Vout is in a low-level state (e.g., zero), and the negative sub-signal Voutn of output signal Vout is in a low-level state (e.g., zero), the common-mode adjustment current Ica is the sum of the common-mode voltage Viic of analog input signal Vii and a fourth coefficient K4 multiplied by a preset voltage difference ΔV, divided by the impedance value Rf of feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be a net outflow to analog input node 205. In one embodiment, the third coefficient K3 and the fourth coefficient K4 are both real numbers between 0 and 1.

[0120] Continue to refer to Figure 8When the positive sub-signal Opwmp of the pulse width modulation signal Opwm is in a low level state (e.g., zero), and the negative sub-signal Opwmn of the pulse width modulation signal Opwm is in a low level state (e.g., zero), (1) when the positive sub-signal Voutp of the output signal Vout is in a high level state (e.g., corresponding to the driving voltage PVDD), and the negative sub-signal Voutn of the output signal Vout is in a high level state (e.g., corresponding to the driving voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii plus a fifth coefficient K5 multiplied by the preset voltage difference ΔV minus the value of the driving voltage PVDD divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be the net inflow from the analog input node 205; (2) when the positive sub-signal Voutp of the output signal Vout is in a high level state (e.g., corresponding to the driving voltage PVDD), and the negative sub-signal Voutn of the output signal Vout is in a high level state (e.g., corresponding to the driving voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii plus a fifth coefficient K5 multiplied by the preset voltage difference ΔV minus the value of the driving voltage PVDD divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be the net inflow from the analog input node 205; When n is in a low level state (e.g., zero), or when the positive sub-signal Voutp of the output signal Vout is in a low level state (e.g., zero), and the negative sub-signal Voutn of the output signal Vout is in a high level state (e.g., corresponding to the driving voltage PVDD), the common-mode adjustment current Ica is the common-mode voltage Viic of the analog input signal Vii plus a sixth coefficient K6 multiplied by the preset voltage difference ΔV minus half of the driving voltage PVDD divided by the impedance value Rf of the feedback element 2033. It should be noted that in this case, the common-mode adjustment current Ica can be the net inflow from the analog input node 205; or (3) when the positive sub-signal Voutp of the output signal Vout is in a low level state (e.g., zero), and the negative sub-signal Voutn of the output signal Vout is in a low level state (e.g., zero), the common-mode adjustment current Ica is the sum of the common-mode voltage Viic of the analog input signal Vii and the preset voltage difference ΔV divided by the impedance value Rf of the feedback element 2033. It should be noted that, in this case, the common-mode adjustment current Ica can be a net outflow to the analog input node 205. In one embodiment, both the fifth coefficient K5 and the sixth coefficient K6 are real numbers between 0 and 1.

[0121] Figure 12 This is a circuit diagram of a specific embodiment of the current-determining circuit in a common-mode current-based digital-to-analog converter of a Class D amplification system according to the present invention. (Refer to...) Figure 12The current determining circuit (2042p or 2042n) includes voltage-to-current conversion circuits 20421a, 20421b, and 20421c, and multiple current mirrors 20422a, 20422b, and 20422c. Voltage-to-current conversion circuit 20421a converts the common-mode voltage Viic of the analog input signal Vii into a reference current Irf1, while voltage-to-current conversion circuit 20421b converts the driving voltage PVDD into a reference current Irf2. Voltage-to-current conversion circuit 20421c converts a preset voltage difference ΔV into a reference current Irf3. In one embodiment, the preset voltage difference ΔV is related to the amplitude of the output signal Vout, the slope of the output signal Vout, and the impedance value Rf of the feedback element 2033. By coupling and combining the aforementioned reference currents Irf1 to Irf3 in an appropriate ratio, the aforementioned... Figures 6-8 The common-mode regulation current Ica is detailed below.

[0122] like Figure 12 As shown, in one embodiment, voltage-to-current conversion circuits 20421a, 20421b and 20421c respectively include an error amplifier 204211a, 204211b and 204211c, a resistor 204212a, 204212b and 204212c and a conversion transistor Qia, Qib and Qiic. The outputs of error amplifiers 204211a, 204211b, and 204211c are coupled to the gates of switching transistors Qia, Qib, and Qic, respectively. The drain of switching transistor Qia and the non-inverting input of error amplifier 204211a are coupled to one end of resistor 204212a. The source of switching transistor Qib and the inverting input of error amplifier 204211b are coupled to one end of resistor 204212b. The drain of switching transistor Qic and the non-inverting input of error amplifier 204211c are coupled to one end of resistor 204212c. The other ends of resistors 204212a, 204212b, and 204212c are coupled to ground.

[0123] Through the feedback loop design of error amplifiers 204211a, 204211b, and 204211c, the inverting and non-inverting inputs of the error amplifiers 204211a, 204211b, and 204211c are locked to the same voltage, such as the common-mode voltage Viic, the driving voltage PVDD, and the preset voltage difference ΔV, respectively, to generate reference currents Irf1, Irf2, and Irf3. In one embodiment, the reference current Irf1 is equal to the common-mode voltage Viic divided by the impedance value Rf of resistor 204212a, the reference current Irf2 is equal to the driving voltage PVDD divided by the impedance value Rf of resistor 204212b, and the reference current Irf3 is equal to the preset voltage difference ΔV divided by the impedance value Rf of resistor 204212c.

[0124] Multiple current mirrors 20422a, 20422b, and 20422c are used to mirror and generate multiple intermediate current sources Iup[1], Idn[1]~Idn[2], and Iup[2]~Iup[8] according to reference currents Irf1, Irf2, and Irf3, respectively. In one embodiment, the multiple current mirrors 20422a, 20422b, and 20422c each include one or more mirror transistors. For example, current mirror 20422a includes mirror transistor Qu[1], current mirror 20422b includes mirror transistors Qm, Qd[1]~Qd[2], and current mirror 20422c includes mirror transistors Qu[2]~Qu[8].

[0125] The source terminal of the mirror transistor Qu[1] and the source terminal of the conversion transistor Qia of the voltage-to-current conversion circuit 20421a are coupled to a node. The gate terminal of the mirror transistor Qu[1] is coupled to the gate terminal of the conversion transistor Qia. The aspect ratios of the mirror transistor Qu[1] and the conversion transistor Qia are equal, so that the current at the drain terminal of the mirror transistor Qu[1] is equal to the reference current Irf1, thus generating the intermediate current source Iup[1]. The source terminal of the mirror transistor Qu[8] and the source terminal of the conversion transistor Qiic of the voltage-to-current conversion circuit 20421c are coupled to a node. The gate terminal of the mirror transistor Qu[8] is coupled to the gate terminal of the conversion transistor Qiic. The aspect ratios of the mirror transistor Qu[8] and the conversion transistor Qiic are equal, so that the current at the drain terminal of the mirror transistor Qu[8] is equal to the reference current Irf3, thus generating the intermediate current source Iup[8].

[0126] Similarly, the source terminal of the mirror transistor Qd[1] and the source terminal of the mirror transistor Qm are coupled to a ground potential, and the gate terminal of the mirror transistor Qd[1] is coupled to the gate terminal of the mirror transistor Qm. The aspect ratios of the mirror transistor Qd[1] and the mirror transistor Qm are equal, so that the current at the drain terminal of the mirror transistor Qd[1] is equal to the reference current Irf2 obtained by the mirror transistor Qm through the current mirror 204213 self-converting transistor Qib, thereby generating the intermediate current source Idn[1]. Similarly, mirror transistors Qd[2] and Qu[2]~Qu[7] can generate intermediate current sources Idn[2] and Iup[2]~Iup[7] using the same principle. The aspect ratios of mirror transistors Qd[2] and Qu[2]~Qu[7] can be adjusted to be in a specific ratio to the aspect ratios of mirror transistors Qd[1] and Qu[8], respectively, so that the current magnitude of intermediate current source Idn[2] is 1 / 2 of the current magnitude of intermediate current source Idn[1], and the current magnitudes of intermediate current sources Iup[2]~Iup[7] are multiples of the current magnitude of intermediate current source Iup[8] by K6, K5, K4, K3, K2, and K1, respectively. In one embodiment, K1~K6 are real numbers between 0 and 1.

[0127] Intermediate current sources Iup[1], Idn[1]~Idn[2] and Iup[2]~Iup[8] are coupled to node Na via adjusting switches Su[1], Sd[1]~Sd[2] and Su[2]~Su[8] respectively. Figures 6-8 To meet the requirements, the corresponding adjustment switches Su[1]~Su[8] and Sd[1]~Sd[2] are controlled to switch the corresponding intermediate current sources Iup[1]~Iup[8] and Idn[1]~Idn[2], thereby generating a common-mode adjustment current Ica. It should be noted that, in the corresponding Figure 6 In the embodiments, Figure 12 The circuits (20421c, 20422c) related to the preset voltage difference ΔV can be omitted.

[0128] As described above, this invention provides a Class D amplification system that further reduces noise by utilizing an input current-based digital-to-analog converter 201, which eliminates the need for a second amplifier 202. Furthermore, when the output signal is zero, the common-mode current-based digital-to-analog converter 204 can be disabled to further reduce noise. In addition, the common-mode adjustment current generated by the common-mode current-based digital-to-analog converter 204 of this invention enhances the response speed of the common-mode voltage Viic of the analog input signal Vii in a non-linear manner, thereby assisting in addressing insufficient bandwidth or slew rate of the linear amplification circuits in the Class D amplification circuit (e.g., but not limited to the first amplifier 2034 and the second amplifier 202), and reducing the slew rate, bandwidth, or current requirements of the second amplifier 202.

[0129] From one perspective, in one embodiment, the common-mode current digital-to-analog converter can be integrated into a Class D amplifier circuit.

[0130] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the broadest scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many ways to combine them, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A Class D amplification system, characterized in that, Include: An input current type digital-to-analog converter is used to convert a digital input signal and generate an analog input signal at an analog input node, wherein the analog input signal includes a positive analog input signal and a negative analog input signal, which are generated at a positive analog input node and a negative analog input node, respectively. A Class D amplifier circuit is coupled to the input current-based digital-to-analog converter. The Class D amplifier circuit includes: A pulse width modulator is used to generate a pulse width modulated signal based on the analog input signal, which includes a positive pulse width modulator sub-signal and a negative pulse width modulator sub-signal; A full-bridge power stage circuit for generating an output signal based on the pulse width modulation signal, the output signal including a positive output sub-signal and a negative output sub-signal, wherein the full-bridge power stage circuit is powered by a drive voltage; and A feedback element is used to feed the output signal back to the analog input node; and A common-mode current-based digital-to-analog converter, coupled to the analog input node, is used to generate a common-mode adjustment current, which includes a positive common-mode sub-adjustment current and a negative common-mode adjustment current, generated at the positive analog input node and the negative analog input node, respectively. The common-mode current-type digital-to-analog converter selectively determines the positive common-mode sub-adjustment current and the negative common-mode sub-adjustment current in relation to a common-mode voltage of the analog input signal, or simultaneously in relation to the common-mode voltage of the analog input signal and the drive voltage, based on (A) the difference between the level states of the positive output sub-signal and the negative output sub-signal, or based on (B) the difference between the level states of the positive pulse width modulation sub-signal and the negative pulse width modulation sub-signal, or based on (C) a combination of the difference between the level states of the positive output sub-signal and the negative output sub-signal and the difference between the level states of the positive pulse width modulation sub-signal and the negative pulse width modulation sub-signal.

2. The Class D amplification system as described in claim 1, wherein, The Class D amplifier circuit also includes a first amplifier coupled between the pulse width modulator and the analog input node to buffer and amplify the analog input signal.

3. The Class D amplification system as described in claim 2, wherein, The Class D amplifier circuit also includes a second amplifier coupled between the analog input node and the input terminal of the first amplifier. The second amplifier is used to control the common-mode voltage of the analog input signal through a virtual grounding method.

4. The Class D amplification system as described in claim 1, wherein, The positive common-mode adjustment current and the negative common-mode adjustment current are positively correlated with the common-mode voltage of the analog input signal.

5. The Class D amplification system as described in claim 4, wherein, In option (A) or (C), when both the positive output sub-signal and the negative output sub-signal are in a high-level state, the common-mode adjustment current is negatively correlated with the drive voltage.

6. The Class D amplification system as described in claim 4, wherein, In option (A) or (C), when the level states of the positive output sub-signal and the negative output sub-signal are different, the common-mode adjustment current is negatively correlated with 1 / 2 of the drive voltage.

7. The Class D amplification system as described in claim 4, wherein, In an adaptive voltage positioning mode, the common-mode adjustment current is also positively correlated with a preset voltage difference, wherein the preset voltage difference is related to the amplitude of the output signal, the slope of the output signal, and the impedance value of the feedback element, wherein in the adaptive voltage positioning mode, a target value of the common-mode voltage of the analog input signal is synchronous with and related to a common-mode voltage of the output signal.

8. The Class D amplification system as described in claim 7, wherein, In this adaptive voltage positioning mode, and in option (A), when the level states of the positive output sub-signal and the negative output sub-signal are the same, the common-mode adjustment current is also positively correlated with the preset voltage difference.

9. The Class D amplification system as described in claim 8, wherein, In the adaptive voltage positioning mode and the fast response mode, corresponding to option (C), when the level states of the positive output sub-signal and the positive pulse width modulation sub-signal are different, and / or when the level states of the negative output sub-signal and the negative pulse width modulation sub-signal are different, the common mode adjustment current is also positively correlated with the product of the preset voltage difference and a preset coefficient.

10. The Class D amplification system as described in claim 9, wherein, The preset coefficient is a real number between 0 and 1.

11. The Class D amplification system as claimed in claim 1, wherein, The common-mode adjustment current is inversely related to the impedance value of the feedback element.

12. The Class D amplification system as claimed in any one of claims 4 to 10, wherein, The common-mode adjustment current is inversely related to the impedance value of the feedback element.

13. The Class D amplification system as claimed in claim 1, wherein, This common-mode current-to-digital converter includes: A decoder for decoding and generating a switching control signal based on the pulse width modulation signal and the clamped output signal; and A current determining circuit includes multiple intermediate current sources and multiple adjusting switches, wherein the switch control signal is used to control the multiple adjusting switches to switch the multiple intermediate current sources to generate the corresponding common-mode adjusting current.

14. The Class D amplification system as described in claim 13, wherein, The common-mode current-mode digital-to-analog converter also includes a voltage clamper to clamp the output signal, thereby generating the clamped output signal.

15. The Class D amplification system as described in claim 14, wherein, The voltage clamp includes: A clamping transistor for generating an intermediate signal based on the output signal and a signal power supply; and A buffer is provided for generating the clamped output signal based on the intermediary signal, wherein the signal power supply is provided to the buffer.

16. The Class D amplification system as claimed in claim 13, wherein, The current-determining circuit includes: At least one voltage-to-current conversion circuit is used to convert the common-mode voltage or the drive voltage of the analog input signal into a corresponding reference current, respectively; and Multiple current mirrors are used to mirror the multiple intermediate current sources based on the at least one reference current.

17. The Class D amplification system as claimed in claim 1, wherein, When the output signal is zero, the common-mode current digital-to-analog converter is disabled to reduce noise.

18. The Class D amplification system as claimed in claim 1, wherein, In option (C), the common-mode current-based digital-to-analog converter selectively determines the common-mode adjustment current relative to the common-mode voltage of the analog input signal, or simultaneously relative to the common-mode voltage of the analog input signal and the drive voltage, based on the delay relationship between the output signal and the pulse width modulation signal.

19. A Class D amplifier circuit, characterized in that, The Class D amplifier circuit is used to receive an analog input signal from an analog input node and convert the analog input signal to generate an output signal, wherein the analog input signal includes a positive analog input signal and a negative analog input signal, which are generated at a positive analog input node and a negative analog input node, respectively. The Class D amplifier circuit includes: A pulse width modulator is used to generate a pulse width modulated signal based on the analog input signal, which includes a positive pulse width modulator sub-signal and a negative pulse width modulator sub-signal; A full-bridge power stage circuit is used to generate the output signal according to the pulse width modulation signal, which includes a positive output sub-signal and a negative output sub-signal, wherein the full-bridge power stage circuit is powered by a drive voltage. A feedback element is used to feed the output signal back to the analog input node; and A common-mode current-based digital-to-analog converter, coupled to the analog input node, is used to generate a common-mode adjustment current, which includes a positive common-mode sub-adjustment current and a negative common-mode adjustment current, generated at the positive analog input node and the negative analog input node, respectively. The common-mode current-type digital-to-analog converter selectively determines the positive common-mode sub-adjustment current and the negative common-mode sub-adjustment current in relation to a common-mode voltage of the analog input signal, or simultaneously in relation to the common-mode voltage of the analog input signal and the drive voltage, based on (A) the difference between the level states of the positive output sub-signal and the negative output sub-signal, or based on (B) the difference between the level states of the positive pulse width modulation sub-signal and the negative pulse width modulation sub-signal, or based on (C) a combination of the difference between the level states of the positive output sub-signal and the negative output sub-signal and the difference between the level states of the positive pulse width modulation sub-signal and the negative pulse width modulation sub-signal.

20. The Class D amplifier circuit as described in claim 19, wherein, It also includes a first amplifier coupled between the pulse width modulator and the analog input node to buffer and amplify the analog input signal.

21. The Class D amplifier circuit as described in claim 20, wherein, It also includes a second amplifier coupled between the analog input node and the input of the first amplifier, the second amplifier being used to control the common-mode voltage of the analog input signal via a virtual grounding method.

22. The Class D amplifier circuit as described in claim 19, wherein, The positive common-mode adjustment current and the negative common-mode adjustment current are positively correlated with the common-mode voltage of the analog input signal.

23. The Class D amplifier circuit as described in claim 22, wherein, In option (A) or (C), when both the positive output sub-signal and the negative output sub-signal are in a high-level state, the common-mode adjustment current is negatively correlated with the drive voltage.

24. The Class D amplifier circuit as described in claim 22, wherein, In option (A) or (C), when the level states of the positive output sub-signal and the negative output sub-signal are different, the common-mode adjustment current is negatively correlated with 1 / 2 of the drive voltage.

25. The Class D amplifier circuit as described in claim 22, wherein, In an adaptive voltage positioning mode, the common-mode adjustment current is also positively correlated with a preset voltage difference, wherein the preset voltage difference is related to the amplitude of the output signal, the slope of the output signal, and the impedance value of the feedback element, wherein in the adaptive voltage positioning mode, a target value of the common-mode voltage of the analog input signal is synchronous with and related to a common-mode voltage of the output signal.

26. The Class D amplifier circuit as described in claim 25, wherein, In this adaptive voltage positioning mode, and in option (A), when the level states of the positive output sub-signal and the negative output sub-signal are the same, the common-mode adjustment current is also positively correlated with the preset voltage difference.

27. The Class D amplifier circuit as described in claim 26, wherein, In the adaptive voltage positioning mode and the fast response mode, corresponding to option (C), when the level states of the positive output sub-signal and the positive pulse width modulation sub-signal are different, and / or when the level states of the negative output sub-signal and the negative pulse width modulation sub-signal are different, the common mode adjustment current is also positively correlated with the product of the preset voltage difference and a preset coefficient.

28. The Class D amplifier circuit as described in claim 27, wherein, The preset coefficient is a real number between 0 and 1.

29. The Class D amplifier circuit as described in claim 19, wherein, The common-mode adjustment current is inversely related to the impedance value of the feedback element.

30. The Class D amplifier circuit as described in any one of claims 22 to 28, wherein, The common-mode adjustment current is inversely related to the impedance value of the feedback element.

31. The Class D amplifier circuit as described in claim 19, wherein, This common-mode current-to-digital converter includes: A decoder for decoding and generating a switching control signal based on the pulse width modulation signal and the clamped output signal; and A current determining circuit includes multiple intermediate current sources and multiple adjusting switches, wherein the switch control signal is used to control the multiple adjusting switches to switch the multiple intermediate current sources to generate the corresponding common-mode adjusting current.

32. The Class D amplifier circuit as described in claim 31, wherein, The common-mode current-mode digital-to-analog converter also includes a voltage clamper to clamp the output signal, thereby generating the clamped output signal.

33. The Class D amplifier circuit as described in claim 32, wherein, The voltage clamp includes: A clamping transistor for generating an intermediate signal based on the output signal and a signal power supply; and A buffer is provided for generating the clamped output signal based on the intermediary signal, wherein the signal power supply is provided to the buffer.

34. The Class D amplifier circuit as described in claim 31, wherein, The current-determining circuit includes: At least one voltage-to-current conversion circuit is used to convert the common-mode voltage or the drive voltage of the analog input signal into a corresponding reference current, respectively; and Multiple current mirrors are used to mirror the multiple intermediate current sources based on the at least one reference current.

35. The Class D amplifier circuit as described in claim 19, wherein, When the output signal is zero, the common-mode current digital-to-analog converter is disabled to reduce noise.

36. The Class D amplifier circuit as described in claim 19, wherein, In option (C), the common-mode current-based digital-to-analog converter selectively determines the common-mode adjustment current relative to the common-mode voltage of the analog input signal, or simultaneously relative to the common-mode voltage of the analog input signal and the drive voltage, based on the delay relationship between the output signal and the pulse width modulation signal.

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