On-chip reconfigurable vector synthesis phase shifter for phased array systems

Abstract

The application belongs to the field of wireless communication, and relates to a phase shifter in a phased array system, and specifically provides an on-chip reconfigurable vector synthesis phase shifter for a phased array system, which meets the application requirements of wide working bandwidth, high beam scanning precision and low cost of future phased array systems. The on-chip reconfigurable vector synthesis phase shifter comprises a reconfigurable IQ signal generation network, a VGA array and a vector synthesis network, wherein the reconfigurable IQ signal generation network is composed of RC polyphase filters and RL polyphase filters in cascade, and a transistor switch is arranged in each of the RC polyphase filters and the RL polyphase filters; the first reconfiguration mode and the second reconfiguration mode are switched by combination of two switch signals S1 and S2. Through reconfiguration mode switching, the application can realize orthogonal signal output of 3.3GHz~28.5GHz, and the coverage bandwidth reaches 158%, and has the advantages of small chip area, low cost, high precision and the like.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of wireless communication, and relates to a phase shifter in a phased array system, and particularly provides a low-cost, ultra-wideband and high-precision on-chip reconfigurable vector synthesis phase shifter for a phased array system. BACKGROUND

[0002] In recent years, with the continuous development of wireless communication application scenarios, the performance requirements of radio frequency microwave communication systems are becoming higher and higher. The phased array technology has the advantages of high resolution, high anti-interference capability and fast beam scanning, and has become a research hotspot in the fields of 5G millimeter wave communication, satellite communication, automobile radar and space exploration. A phased array system is generally composed of hundreds of antenna array units. By changing the phase and amplitude of each antenna, the electromagnetic waves of multiple transmitting or receiving units are interfered and superimposed in space, coherently superimposed in a specific direction, and canceled in other directions, so that the entire antenna array realizes dynamic adjustment of beam pointing, shape and function. As a core device for adjusting the phase in the phased array system, the phase shifter is crucial to the performance of the phased array system. The phase accuracy of the phase shifter affects the beam scanning accuracy and beam quality of the phased array system. The frequency bandwidth of the phase shifter affects the working frequency bandwidth of the phased array system. The power capacity and noise figure of the phase shifter affect the sensitivity and dynamic range of the phased array system. The layout area of the phase shifter affects the integration cost of the phased array system. Therefore, it is of great significance and practical value to study a low-cost, ultra-wideband and high-precision phase shifter.

[0003] At present, silicon-based CMOS process on-chip phase shifters are divided into active structures and passive structures. Passive phase shifters mainly include reflective phase shifters, high-low pass type phase shifters and load line type phase shifters, which have the advantages of simple structure, high linearity, etc., but have large insertion loss, and it is difficult to realize high phase resolution and high phase accuracy, which is difficult to meet the demand of high-performance phased array system for beam scanning accuracy and beam quality. Active phase shifters mainly include vector synthesis phase shifters, which have the advantage of high phase shift accuracy, making them the mainstream structure of high-performance phased array systems. However, the bandwidth of the vector synthesis phase shifter with traditional structure is narrow, which is difficult to meet the wideband performance requirements of multi-band and multi-standard wireless communication systems.

[0004] In order to solve the bandwidth problem of the active phase shifter, two independent phase shifters are often connected in parallel, and switching is realized through a switch. This method can expand the bandwidth, but the circuit structure is complex, which can introduce additional parasitic effects and losses, and the layout area is increased by several times, which is not conducive to the integration of large-scale phased array systems, and the system cost is greatly increased. In addition, using a multi-stage IQ (quadrature) signal generation network can also achieve wideband performance, but the loss will increase significantly with the number of stages. Moreover, although the bandwidth range is wider than that of a single-stage IQ (quadrature) signal generation network, it is still limited by the bandwidth performance of the IQ (quadrature) signal generation network. At the same time, this method also greatly increases the chip area and the system cost of the phased array system.

[0005] Therefore, in order to meet the application requirements of wide working bandwidth, high beam scanning precision and low cost of future phased array systems, the present application proposes a small-area, low-cost, ultra-wideband and high-precision on-chip reconfigurable vector synthesis phase shifter based on a silicon-based CMOS process. SUMMARY

[0006] The present application aims to provide an on-chip reconfigurable vector synthesis phase shifter for a phased array system, which aims to meet the application requirements of wide working bandwidth, high beam scanning precision and low cost of future phased array systems.

[0007] To achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows:

[0008] An on-chip reconfigurable vector synthesis phase shifter for a phased array system comprises a reconfigurable IQ signal generation network, a VGA array and a vector synthesis network. Four quadrature signals are generated by the reconfigurable IQ signal generation network from an input differential signal, amplified by the VGA array, and then synthesized into an output differential signal by the vector synthesis network. The reconfigurable IQ signal generation network is composed of a RC polyphase filter and an RL polyphase filter in cascade. Transistor switches are arranged in the RC polyphase filter and the RL polyphase filter respectively, and the first reconfiguration mode and the second reconfiguration mode are switched by two switch signals S1 and S2.

[0009] Further, the RC polyphase filter is composed of four RC networks, and each RC network is composed of an R branch and a C branch. The R branch comprises two resistors and a transistor switch, and the two resistors are connected in parallel, with one of the resistors connected to the transistor switch. The C branch comprises two capacitors and a transistor switch, and the two capacitors are connected in parallel, with one of the capacitors connected to the transistor switch.

[0010] The input ends of the R branch and the C branch in each RC network are connected, and the first RC network inputs a Vin+ signal and the third RC network inputs a Vin- signal.

[0011] The output end of the R branch in the first RC network is connected with the output end of the C branch in the fourth RC network, and leads to the first output end of the RC polyphase filter;

[0012] The output end of the C branch in the first RC network is connected with the output end of the R branch in the second RC network, and leads to the second output end of the RC polyphase filter;

[0013] The output end of the C branch in the second RC network is connected with the output end of the R branch in the third RC network, and leads to the third output end of the RC polyphase filter;

[0014] The output end of the C branch in the third RC network is connected with the output end of the R branch in the fourth RC network, and leads to the fourth output end of the RC polyphase filter.

[0015] Further, the RL polyphase filter is composed of four RL networks, and each RL network is composed of an R branch and an L branch; the R branch comprises two resistors and a transistor switch, the two resistors are connected in parallel, and one of the two resistors is connected with the transistor switch; the L branch is composed of one inductor;

[0016] The output end of the R branch and the output end of the L branch in each RL network are connected, and the first RL network to the fourth RL network outputs I+ signal, Q+ signal, I- signal and Q- signal in sequence;

[0017] The input end of the R branch in the first RL network is connected with the input end of the L branch in the fourth RL network, and is connected with the first output end of the RC polyphase filter correspondingly;

[0018] The input end of the L branch in the first RL network is connected with the input end of the R branch in the second RL network, and is connected with the second output end of the RC polyphase filter correspondingly;

[0019] The input end of the L branch in the second RL network is connected with the input end of the R branch in the third RL network, and is connected with the third output end of the RC polyphase filter correspondingly;

[0020] The input end of the L branch in the third RL network is connected with the input end of the R branch in the fourth RL network, and is connected with the fourth output end of the RC polyphase filter correspondingly.

[0021] Further, the transistor switch in the R branch of the RC polyphase filter is controlled by a switch signal S2, and the transistor switch in the C branch is controlled by a switch signal S1; the transistor switch in the R branch of the RL polyphase filter is controlled by the switch signal S2; when the switch signal S1 is turned on and the switch signal S2 is turned off, the on-chip reconfigurable vector synthesis phase shifter works in a first reconfiguration mode; when the switch signal S2 is turned on and the switch signal S1 is turned off, the on-chip reconfigurable vector synthesis phase shifter works in a second reconfiguration mode.

[0022] Further, the VGA array adopts a digital control circuit rudder structure, which is composed of six transistor array units in parallel, and the transistor size ratio of the six transistor array units is 1, 2, 4, 8, 16 and 32.

[0023] Further, the vector synthesis network is composed of a radio frequency transmission line and an output matching transformer.

[0024] Based on the above technical solutions, the application has the following beneficial effects:

[0025] The application provides a reconfigurable IQ (quadrature) signal generation network, which can realize 3.3GHz-28.5GHz quadrature signal output through reconfigurable mode switching, and has a coverage bandwidth of 158%; the reconfigurable IQ signal generation network is mainly composed of transistor switches, resistors and capacitors, and has a very small layout area in a silicon-based CMOS process, so that the reconfigurable IQ signal generation network has the advantages of small chip area and low cost while realizing ultra-wideband, and even has a smaller chip area than many existing narrowband structures; meanwhile, a reconfigurable vector synthesis phase shifter is formed on the basis of the reconfigurable IQ (quadrature) signal generation network, and has very excellent phase shift accuracy and amplitude accuracy, and the performance reaches the industry leading level.

[0026] In summary, the application provides an on-chip reconfigurable vector synthesis phase shifter for a phased array system, which has the advantages of small area, ultra-wideband, high precision and the like, and greatly reduces the integration cost of the phased array system, and has a significant cost advantage for future super large scale array number phased array systems. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 FIG. 1 is a schematic diagram of the working principle of the vector synthesis phase shifter in the application.

[0028] Figure 2 FIG. 2 is a structural schematic diagram of the reconfigurable IQ (quadrature) generation network in the application.

[0029] Figure 3 FIG. 3 is a layout layout schematic diagram of the reconfigurable IQ (quadrature) generation network in the application.

[0030] Figure 4 FIG. 4 is an input insertion loss simulation result diagram of the reconfigurable IQ (quadrature) generation network in the application.

[0031] Figure 5 FIG. 5 is a phase simulation result diagram of the reconfigurable IQ (quadrature) generation network in the application.

[0032] Figure 6 FIG. 6 is a structural schematic diagram of the on-chip reconfigurable vector synthesis phase shifter for the phased array system in the application.

[0033] Figure 7 The structure schematic diagram of VGA (variable gain amplifier) array in the application.

[0034] Figure 8 The RMS amplitude accuracy result diagram of the on-chip reconfigurable vector synthesis phase shifter for the phased array system in the application.

[0035] Figure 9 The RMS phase accuracy result diagram of the on-chip reconfigurable vector synthesis phase shifter for the phased array system in the application.

[0036] The above Figure 2 In the above, 101 is an RC polyphase filter, and 102 is an RL polyphase filter. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and beneficial effects of the application more clear and explicit, the application is further described in detail below in combination with the drawings and examples.

[0038] The embodiment proposes an on-chip reconfigurable vector synthesis phase shifter with small area, ultra-wideband and high precision based on a silicon-based CMOS process, which is composed of an IQ (quadrature) signal generation network, a VGA (variable gain amplifier) unit and a vector synthesis network. Figure 1 As shown in the figure, the input differential signal (Vin+ signal and Vin- signal) generates four quadrature signals through the IQ (quadrature) signal generation network, and the four quadrature signals are divided into I-channel signals and Q-channel signals, wherein the phase of the I-channel signals is 0° (I+ signal) and 180° (I- signal), and the phase of the Q-channel signals is 90° (Q+ signal) and 270° (Q- signal). The I-channel signals and the Q-channel signals will enter the VGA unit for amplification respectively. The I-channel signals become I'+ signal and I'- signal after being amplified by the VGA unit, and the Q-channel signals become Q'+ signal and Q'- signal after being amplified by the VGA unit. The four signals are finally vector synthesized in the vector synthesis network. The Q'+ signal and the I'+ signal are vector synthesized to generate the Vout+ signal, and the Q'- signal and the I'- signal are vector synthesized to generate the Vout- signal. The synthesized Vout+ and Vout- are also differential signals. In this process, the amplitude of the I-channel signals and the Q-channel signals can be controlled by adjusting the amplification multiple of the VGA (variable gain amplifier) unit. Finally, the output signal with any phase is generated through the vector synthesis principle, and the phase shifting function is achieved.

[0039] The IQ (quadrature) signal generation network is a core part of the vector synthesis phase shifter, and the wider the working bandwidth of the IQ (quadrature) signal generation network is, the wider the working frequency of the phase shifter is; in a conventional design, a three-stage or more than three-stage IQ (quadrature) generation network is often used to realize the bandwidth performance, but the loss will be significantly increased with the number of stages, and the bandwidth expansion is limited by the parasitic characteristics of inductance and capacitance, and the improvement effect is limited; in addition, this structure will greatly increase the chip area, and for a phased array system with thousands of channels, the system integration cost is unacceptable; therefore, in order to realize the design of a low-cost and ultra-wideband vector synthesis phase shifter, the embodiment creatively proposes a reconfigurable IQ (quadrature) generation network with small area and ultra-wideband characteristics, which is improved from an RC (resistor / capacitor) polyphase filter quadrature generation network to an RC-RL (resistor / capacitor-resistor / inductor) polyphase filter structure, and the reconfiguration of the capacitance value and the resistance value is realized through the switching, so as to expand the bandwidth.

[0040] In the embodiment, the reconfigurable IQ (quadrature) generation network is as shown in Figure 2 The RC-RL (resistor / capacitor-resistor / inductor) structure is used to form a two-stage IQ (signal) generation network, which is composed of an RC polyphase filter 101 and an RL polyphase filter 102.

[0041] The RC polyphase filter 101 is composed of four RC networks, each of which is composed of an R branch and a C branch.

[0042] The input ends of the R branch and the C branch in each RC network are connected, and the first RC network inputs a Vin+ signal and the third RC network inputs a Vin- signal.

[0043] The output end of the R branch in the first RC network is connected with the output end of the C branch in the fourth RC network, and a first output end of the RC polyphase filter is led out.

[0044] The output end of the C branch in the first RC network is connected with the output end of the R branch in the second RC network, and a second output end of the RC polyphase filter is led out.

[0045] The output end of the C branch in the second RC network is connected with the output end of the R branch in the third RC network, and a third output end of the RC polyphase filter is led out.

[0046] The output end of the C branch in the third RC network is connected with the output end of the R branch in the fourth RC network, and a fourth output end of the RC polyphase filter is led out.

[0047] Specifically, the RC polyphase filter 101 is composed of resistors R11~R18, capacitors C11~C18, and transistor switches M11~M18; wherein, the resistor R11, the resistor R12, the capacitor C11, the capacitor C12, the transistor switch M11 and the transistor switch M12 constitute a first RC network, the resistor R13, the resistor R14, the capacitor C13, the capacitor C14, the transistor switch M13 and the transistor switch M14 constitute a second RC network, the resistor R15, the resistor R16, the capacitor C15, the capacitor C16, the transistor switch M15 and the transistor switch M16 constitute a third RC network, and the resistor R17, the resistor R18, the capacitor C17, the capacitor C18, the transistor switch M17 and the transistor switch M18 constitute a fourth RC network; the transistor switches M11, M13, M15 and M17 are controlled by the switch signal S2, and the transistor switches M12, M14, M16 and M18 are controlled by the switch signal S1.

[0048] The RL polyphase filter 102 is composed of four RL networks, and each RL network is composed of an R branch and an L branch; the R branch includes two resistors and a transistor switch, the two resistors are connected in parallel, and one of the two resistors is connected to the transistor switch; the L branch is composed of one inductor;

[0049] The output terminals of the R branch and the L branch in each RL network are connected, and the first RL network to the fourth RL network output I+ signal, Q+ signal, I- signal and Q- signal in turn;

[0050] The input terminal of the R branch in the first RL network is connected to the input terminal of the L branch in the fourth RL network, and the first output terminal of the RC polyphase filter is connected correspondingly;

[0051] The input terminal of the L branch in the first RL network is connected to the input terminal of the R branch in the second RL network, and the second output terminal of the RC polyphase filter is connected correspondingly;

[0052] The input terminal of the L branch in the second RL network is connected to the input terminal of the R branch in the third RL network, and the third output terminal of the RC polyphase filter is connected correspondingly;

[0053] The input terminal of the L branch in the third RL network is connected to the input terminal of the R branch in the fourth RL network, and the fourth output terminal of the RC polyphase filter is connected correspondingly.

[0054] Specifically, the RL multiphase filter 102 is composed of resistors R21~R28, inductors L21~L24, and transistor switches M21~M24. Among them, resistors R21, R22, inductors L21 and transistor switch M21 form the first RL network; resistors R23, R24, inductors L22 and transistor switch M22 form the second RL network; resistors R25, R26, inductors L23 and transistor switch M23 form the third RL network; and resistors R27, R28, inductors L24 and transistor switch M24 form the fourth RL network. Transistor switches M21~M24 are controlled by switching signal S2.

[0055] Depend on Figure 2 As can be seen, the reconfigurable IQ (orthogonal) generation network in this embodiment is mainly composed of resistors and capacitors, and the layout area of ​​resistors and capacitors is almost negligible in CMOS technology; therefore, by reasonably arranging the inductor positions, the reconfigurable IQ (orthogonal) generation network provided in this embodiment can achieve layout with a very small chip area, such as... Figure 3 As shown, a ring layout design is adopted, in which the first-stage RC multiphase filter 101 surrounds the second-stage RL multiphase filter 102. Since the layout area of ​​resistors and capacitors in CMOS technology is small, they are arranged in the center of the layout to reduce the layout area, while the inductor, which accounts for the largest proportion of the layout area in the circuit, is arranged in the center of the layout. Figure Four This design optimizes the use of space in every corner, thereby increasing the utilization rate of the layout area; ultimately, the layout area designed using CMOS technology in this embodiment is as low as 0.023 mm². 2 (100um×230um), the layout area is reduced by at least half compared to conventionally designed IQ (orthogonal) signal generation networks.

[0056] The reconfigurable IQ (orthogonal) generation network has a first reconstruction mode and a second reconstruction mode, which are switched by switching signals S1 and S2; the first reconstruction mode is that switching signal S1 is on and switching signal S2 is off, and the second reconstruction mode is that switching signal S2 is on and switching signal S1 is off; for example Figure 4 and Figure 5 The figure shows the input insertion loss and phase of the reconfigurable IQ (orthogonal) generation network. S21 represents the insertion loss of the Q+ signal, S31 represents the insertion loss of the Q- signal, S41 represents the insertion loss of the I+ signal, and S51 represents the insertion loss of the I- signal. As can be seen from the figure, according to the orthogonal signal requirements of amplitude <0.5dB and phase <1°, the first reconstruction mode covers 3.3 GHz ~ 14 GHz, and the second reconstruction mode covers 13 GHz ~ 28.5 GHz. Therefore, the working bandwidth of the reconfigurable IQ (orthogonal) generation network is 3.3 GHz ~ 28.5 GHz, with a coverage bandwidth of up to 158% (25.2 GHz), achieving an ultra-wideband working bandwidth.

[0057] Based on the above reconfigurable IQ (quadrature) generation network, the embodiment provides a reconfigurable vector synthesis phase shifter on chip for phased array system, which has a structure as shown in the figure Figure 6 The reconfigurable vector synthesis phase shifter on chip for phased array system includes a reconfigurable IQ (quadrature) signal generation network, an I-path VGA (variable gain amplifier) array, a Q-path VGA (variable gain amplifier) array, and a vector synthesis network. The input differential signal (Vin+ signal and Vin- signal) generates four quadrature signals including I-path signals and Q-path signals through the reconfigurable IQ (quadrature) signal generation network. The I-path signals include I+ signal and I- signal, and the Q-path signals include Q+ signal and Q- signal. The I-path signals and the Q-path signals enter the VGA arrays for amplification, respectively. The I-path signals become I'+ signal and I'- signal after being amplified by the VGA units, and the Q-path signals become Q'+ signal and Q'- signal after being amplified by the VGA units. The four signals are finally subjected to vector synthesis in the vector synthesis network. The Q'+ signal and the I'+ signal are subjected to vector synthesis to generate Vout+ signal, and the Q'- signal and the I'- signal are subjected to vector synthesis to generate Vout- signal. The synthesized Vout+ and Vout- are also differential signals.

[0058] In order to improve the phase precision, the VGA (variable gain amplifier) array in the embodiment adopts a digital control circuit rudder structure. The structure realizes very fine gain control through control signals to realize transistor array switching, thereby improving the phase precision of vector synthesis. In different control states, each pair of transistors always keeps one path conducting, thereby keeping the input and output impedance, current and other parameters consistent, which is beneficial to wideband circuit design.

[0059] The VGA (variable gain amplifier) array is composed of six transistor array units in parallel as shown in the figure Figure 7 The transistor size ratio of the six transistor array units is 1, 2, 4, 8, 16, and 32. Different sizes of transistors are switched through digital modules to achieve fine gain control, thereby realizing high-precision phase synthesis.

[0060] Each transistor array unit is composed of transistors M31, M32, M33, M34, M35, M36, resistors R31 and R32, the source electrode of the transistor M31 is connected with the source electrode of the transistor M32 and the drain electrode of the transistor M35, the drain electrode of the transistor M31 is connected with the drain electrode of the transistor M33 and outputs Q'- / I'-signal, the gate electrode of the transistor M31 is connected with the gate electrode of the transistor M34 and inputs digital control signal Qctrl<5:0> / Ictrl<5:0>, the source electrode of the transistor M32 is connected with the source electrode of the transistor M35 and the source electrode of the transistor M31, the drain electrode of the transistor M32 is connected with the drain electrode of the transistor M34 and outputs Q'+ / I'+signal, the gate electrode of the transistor M32 is connected with the gate electrode of the transistor M33 and inputs digital control signal , the source electrode of the transistor M33 is connected with the drain electrode of the transistor M36 and the source electrode of the transistor M34, the source electrode of the transistor M34 is connected with the drain electrode of the transistor M36 and the source electrode of the transistor M33, the source electrode of the transistor M35 is connected with the power supply ground, the gate electrode of the transistor M35 inputs Q+ / I- signal, the source electrode of the transistor M36 is connected with the power supply ground, the gate electrode of the transistor M36 inputs Q- / I+ signal; one end of the resistor R31 is connected with voltage bias VBIAS, the other end is connected with the gate electrode of the transistor M35; one end of the resistor R32 is connected with voltage bias VBIAS, the other end is connected with the gate electrode of the transistor M36; the transistor array unit ensures the working current of the transistors M35 and M36 constant through the fixed voltage bias VBIAS, the amplifier gain change is realized through two groups of digital control voltage Qctrl<5:0> / Ictrl<5:0>, when one of them is in low-voltage off mode, the other is in high-voltage on mode, therefore, M31 and M34, M32 and M33 will always have a group of transistor array turned on, the amplifier current and input and output impedance will not change with the number of digital control voltage on, at the same time, two groups of digital control voltage can realize the polarity inversion of input differential signal, thereby generating IQ signals of different polarities; in addition, the number of on bits of the control digital control voltage can change the number of on transistors of the whole transistor array, thereby changing the number of current rudders, realizing fine gain control.

[0061] The vector synthesis network is composed of radio frequency transmission line and output matching transformer, the four-way output orthogonal signals of the VGA (variable gain amplifier) array are connected together through the radio frequency transmission line, realizing the current synthesis of the output signal; the output matching transformer realizes wideband output matching.

[0062] ​In summary, the embodiment provides a small area, ultra-wideband, high precision on-chip reconfigurable vector synthesis phase shifter based on silicon-based CMOS process, which realizes mode switching through transistor switching in the reconfigurable IQ (quadrature) signal generation network, thereby covering the ultra-wideband operating bandwidth, and has lower phase shift RMS and amplitude RMS, and the performance reaches the industry frontier. Figure 8 As shown in Figure 9 The simulation results of the amplitude RMS and the phase shift RMS of the on-chip reconfigurable vector synthesis phase shifter in the embodiment are shown in the figure, in a high-performance phased array system, the phase RMS is often required to be less than 3°, and the amplitude RMS is less than 0.2dB, as shown in the figure, the first reconfiguration mode in the embodiment can meet the application requirements of 3.3GHz~13GHz, and the second reconfiguration mode can meet the application requirements of 11GHz~28.5GHz, therefore, the phase shifter meets the working bandwidth of 3.3GHz~28.5GHz, and the working bandwidth covers up to 158%(25.2GHz), and the phase shifter can completely meet the requirements of future wireless communication systems such as 5G communication, satellite communication and military radar.

[0063] The above is only a specific embodiment of the present application, any feature disclosed in the specification can be replaced by other equivalent or similar purpose alternative features unless specifically described, and all features disclosed or all steps in the method or process can be combined in any way except for mutually exclusive features and / or steps.

Claims

1. An on-chip reconfigurable vector synthesis phase shifter for a phased array system, comprising: The system comprises a reconfigurable IQ signal generation network, a VGA array, and a vector synthesis network. An input differential signal is generated into four orthogonal signals by the reconfigurable IQ signal generation network, amplified by the VGA array, and then synthesized by the vector synthesis network into an output differential signal. The reconfigurable IQ signal generation network is characterized by being composed of a cascaded RC polyphase filter and an RL polyphase filter. Transistor switches are respectively installed in the RC and RL polyphase filters, and the switching between a first reconstruction mode and a second reconstruction mode is achieved through the combination of two switch signals S1 and S2. The RC multiphase filter consists of four RC networks, each consisting of an R branch and a C branch. The R branch includes two resistors and one transistor switch, with the two resistors connected in parallel and one of the resistors connected to the transistor switch. The C branch includes two capacitors and one transistor switch, with the two capacitors connected in parallel and one of the capacitors connected to the transistor switch. In each RC network, the input terminals of the R branch and the C branch are connected, and the first RC network inputs the Vin+ signal, and the third RC network inputs the Vin- signal. The output of the R branch in the first RC network is connected to the output of the C branch in the fourth RC network, and the first output of the RC polyphase filter is drawn out. The output of the C branch in the first RC network is connected to the output of the R branch in the second RC network, and the second output of the RC polyphase filter is drawn out. The output of the C branch in the second RC network is connected to the output of the R branch in the third RC network, and the third output of the RC polyphase filter is brought out. The output of the C branch in the third RC network is connected to the output of the R branch in the fourth RC network, and the fourth output of the RC polyphase filter is brought out. The RL multiphase filter consists of four RL networks, each consisting of an R branch and an L branch. The R branch includes two resistors and one transistor switch, with the two resistors connected in parallel and one of them connected to the transistor switch. The L branch consists of one inductor. In each RL network, the output terminals of the R branch and the L branch are connected, and the first to fourth RL networks output I+ signal, Q+ signal, I- signal and Q- signal respectively; The input of the R branch in the first RL network is connected to the input of the L branch in the fourth RL network, and is correspondingly connected to the first output of the RC polyphase filter. The input terminal of the L branch in the first RL network is connected to the input terminal of the R branch in the second RL network, and is correspondingly connected to the second output terminal of the RC polyphase filter; The input of the L branch in the second RL network is connected to the input of the R branch in the third RL network, and is correspondingly connected to the third output of the RC polyphase filter. The input of the L branch in the third RL network is connected to the input of the R branch in the fourth RL network, and is correspondingly connected to the fourth output of the RC polyphase filter.

2. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 1, characterized in that, In the R branch of the RC multiphase filter, the transistor switch is controlled by the switching signal S2, and the transistor switch in the C branch is controlled by the switching signal S1.

3. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 1, characterized in that, In the R branch of the RL multiphase filter, the transistor switch is controlled by the switching signal S2.

4. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 1, characterized in that, When switch signal S1 is on and switch signal S2 is off, the on-chip reconfigurable vector synthesizer phase shifter operates in the first reconstruction mode. When switch signal S2 is on and switch signal S1 is off, the on-chip reconfigurable vector synthesizer phase shifter operates in the second reconstruction mode.

5. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 1, characterized in that, The VGA array adopts a numerically controlled circuit rudder structure, which is composed of six transistor array units connected in parallel. The transistor size ratio of the six transistor array units is 1, 2, 4, 8, 16, and 32.

6. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 1, characterized in that, The vector synthesis network consists of a radio frequency transmission line connected to an output matching transformer.

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