Driving circuit and power module for three-transistor parallel SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

Abstract

The invention relates to the technical field of power semiconductor device driving design, in particular to a driving circuit and a power module for a three-transistor parallel SiC MOSFET, which comprise a first circuit unit and a second circuit unit with the same structure, and each of the first circuit unit and the second circuit unit comprises a driving chip and a SiC MOSFET three-transistor parallel matrix. The power supply end of the driving chip is connected with a driving auxiliary source filter circuit, a PWM input signal is connected with the input end of the driving chip through an input filter circuit, the output end of the driving chip is sequentially connected with a driving grid network circuit and a driving protection circuit, and the output ends of a to-be-driven SiC MOSFET and the SiC MOSFET parallel matrix are output after passing through an output filter circuit. According to the invention, the peak voltage can be effectively reduced, and the current sharing effect and the three-tube parallel reliability are improved.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device drive design technology, specifically to a drive circuit and power module for three parallel SiC MOSFETs. Background Technology

[0002] As fast charging technology for new energy vehicles develops towards an 800V high-voltage platform and 480kW and above supercharging power, extremely high requirements are placed on the current output capability of the core power module of the charging pile. The current capability of a single or two SiC MOSFETs has approached the physical limit and cannot meet market demand. Therefore, adopting multi-tube parallel technology has become an inevitable choice to improve the current level of the module.

[0003] Common parallel connection schemes in the industry include using a single ultra-high current module, even-number parallel connection, and odd-number parallel connection, as follows: Ultra-high current modules: The advantage is that there is no parallel current sharing problem, but the disadvantages include high cost, inflexible inventory, and thick heat dissipation base plate with high thermal resistance, making it difficult to apply on a large scale in the cost-sensitive commercial charging pile field.

[0004] Two tubes in parallel: Current sharing is the easiest to achieve and the layout is easy to make symmetrical, but its current boost capability is limited, usually less than 400A, which cannot meet the current requirements of the next generation of supercharging modules for 600A and above.

[0005] Four (or more even) tubes in parallel: Although they can provide a larger current, they have problems such as complex layout, large PCB area, increased drive circuits, and significantly increased cost; their symmetry can be achieved by "two-by-two symmetry" recombination, which is less difficult than three tubes in parallel, but the system complexity and cost often exceed expectations.

[0006] Three-tube parallel configuration achieves the best balance in current capability, cost, heat dissipation, and layout flexibility; requires only three discrete components, making it far more cost-effective than a single module; its heat dissipation surface is flat and dispersed, resulting in high thermal management efficiency; it offers flexible material availability and low supply chain risk.

[0007] Therefore, three-tube parallel connection has become the industry's preferred architecture in terms of cost and performance trade-offs. However, three-tube parallel connection is also the most difficult solution for current sharing. Due to the inherent asymmetry in physical layout, its difficulty is far greater than that of two-tube and four-tube parallel connection: the copper foil path of the middle tube in three-tube parallel connection is naturally 2-3mm shorter, and the parasitic inductance difference is directly coupled to the drive circuit. A turn-on slope of 3A / ns can generate a 3V gate spike. Once the current deviation is >10%, the junction temperature of the middle tube is transiently 20°C higher. The negative temperature coefficient of SiC further concentrates the current, eventually leading to a "thermal-avalanche" cascading failure, resulting in a high field repair rate.

[0008] Therefore, a three-transistor parallel solution that can effectively reduce peak voltage and has high reliability is needed. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the prior art and provide a driving circuit and power module for three parallel SiC MOSFETs, which effectively reduces peak voltage and improves the reliability of the three parallel MOSFETs.

[0010] To achieve the above objectives / to solve the above technical problems, the present invention is implemented using the following technical solution: In a first aspect, the present invention provides a driving circuit for three parallel SiC MOSFETs, comprising a first circuit unit and a second circuit unit with identical structures. The SiC MOSFETs of the first circuit unit and the second circuit unit are connected in series. Both the first circuit unit and the second circuit unit include a driving chip and a parallel matrix of three SiC MOSFETs. The power supply terminal of the driving chip is connected to a driving auxiliary power filter circuit. The PWM input signal is connected to the input terminal of the driving chip after passing through an input filter circuit. The output terminal of the driving chip is connected to the input terminal of a driving gate network circuit. The output terminal of the driving gate network is connected to the input terminals of multiple driving protection circuits. The output terminals of the multiple driving protection circuits are each connected to one of the SiC MOSFETs to be driven in the parallel matrix of three SiC MOSFETs. The output terminal of the parallel matrix of SiC MOSFETs is output after passing through an output filter circuit.

[0011] In conjunction with the first aspect, optionally, the first circuit unit includes a driver chip U1, an input filter circuit including a resistor R3, a first pin of the driver chip U1 connected to a 5V power supply via resistor R3, a second pin of the driver chip U1 connected to a 5V power supply via capacitor C3 and resistor R3, a capacitor C2 connected in parallel across capacitor C3, a third pin of the driver chip U1 connected to a PWM input signal via resistor R1, a third pin of the driver chip U1 also connected to ground via resistor R2, and a fourth pin of the driver chip U1 connected to ground via capacitor C1.

[0012] In conjunction with the first aspect, optionally, the auxiliary power supply filter circuit includes resistors R7 and R8. The eighth pin of the driver chip U1 is connected to the VCC terminal of the external auxiliary power supply through resistor R7. The fifth pin of the driver chip U1 is connected to the VEE terminal of the external auxiliary power supply through resistor R8. The eighth pin of the driver chip U1 is also connected to the fifth pin of the driver chip U1 through capacitors C4 and C5 in sequence. A capacitor C6 is connected in parallel across capacitors C4 and C5. The middle side of capacitors C4 and C5 is connected to the high-voltage ground of the source of multiple SiC MOSFETs in the first circuit unit.

[0013] In conjunction with the first aspect, optionally, the driving gate network circuit includes a resistor R4. The seventh pin of the driving chip U1 is connected to the driving protection circuit as the DRVH terminal after passing through the resistor R4. A resistor R5 is connected in parallel across the two ends of the resistor R4. The seventh pin of the driving chip U1 is connected to the cathode of the diode D1. The anode of the diode D1 is connected to the DRVH terminal after passing through the resistor R6. The sixth pin of the driving chip U1 is connected to the driving protection circuit as the CLAMPH terminal.

[0014] In conjunction with the first aspect, optionally, the drive protection circuit includes a short-circuit protection branch and a local absorption branch connected in series, as well as a current-limiting branch connected in parallel across the local absorption branch, wherein the local absorption branch is connected in parallel between the gate and the Kelvin source of each SiC MOSFET.

[0015] In conjunction with the first aspect, optionally, the short-circuit protection branch includes a Schottky diode D3, the cathode of which is connected to the sixth pin of the driver chip U1, and the anode of which is connected to the gate of the SiC MOSFET Q1. The local absorption branch includes a capacitor C13, a resistor R20, and a resistor R19 connected in series. The local absorption branch is connected in parallel between the gate of the SiC MOSFET Q1 and the Kelvin source. The series branch of capacitor C13 and resistor R20 is also connected in parallel between the gate of the SiC MOSFET Q1 and the Kelvin source. The current limiting branch includes a current limiting resistor R18. The gate of the SiC MOSFET Q1 is also connected to the RDVH terminal after passing through resistor R17.

[0016] In conjunction with the first aspect, optionally, the SiC MOSFET of the first circuit unit and the SiC MOSFET of the second circuit unit are connected in series, including: the source of the SiC MOSFET of the first circuit unit is connected to the drain of the SiC MOSFET of the second circuit unit.

[0017] In conjunction with the first aspect, optionally, the output filter circuit includes capacitors C19, C20, C21, C22, C23, and C24 connected in parallel. One end of the output filter circuit is connected to the drain of the SiC MOSFET in the first circuit unit, and the other end of the output filter circuit is connected to the source of the SiC MOSFET in the second circuit unit.

[0018] In a second aspect, the present invention provides a power module including a drive circuit for three parallel SiC MOSFETs as described in any one of the first aspects.

[0019] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: This application uses an input filter circuit to RC attenuate the input power supply and PWM signal, avoiding high-frequency circulating current crosstalk; it uses a drive auxiliary power source filter circuit to attenuate both the positive and negative rails of the external auxiliary power source simultaneously, ensuring that the auxiliary power source drop is less than a preset value when the drive current jumps; it uses a drive protection circuit to reduce Vds spikes, and further reduces Vds spikes through the drive gate network circuit and drive protection circuit; and it uses an output filter circuit to provide a high-frequency loop, further reducing Vds spikes. Through the coordinated operation of various circuits, this application effectively reduces peak voltage and provides a highly reliable three-transistor parallel drive scheme. Attached Figure Description

[0020] Figure 1 This is the circuit diagram part of the invention. Figure 1 ; Figure 2 This is the circuit diagram part of the invention. Figure 2 ; Figure 3 This is the circuit diagram of the drive protection circuit of the present invention; Figure labels: 1 is PWM signal input; 2 is input filter circuit; 3 is drive gate network circuit; 4 is drive auxiliary source filter circuit; 5 is drive protection circuit; 6 is output filter circuit; 51 is short circuit protection branch; 52 is current limiting branch; 53 is local absorption branch. Detailed Implementation

[0021] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations thereof. In the absence of conflict, the embodiments and technical features in the embodiments can be combined with each other.

[0022] In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order of the technical features indicated.

[0023] In the description of this invention, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0024] Example 1:

[0025] like Figure 1 and Figure 2 As shown, this invention provides a driving circuit for three parallel SiC MOSFETs, including a first circuit unit and a second circuit unit with identical structures. The SiC MOSFETs in the first circuit unit and the SiC MOSFETs in the second circuit unit are connected in series. Both the first circuit unit and the second circuit unit include a driving chip and a parallel matrix of three SiC MOSFETs. Specifically, the parallel matrix of three SiC MOSFETs consists of three SiC MOSFETs connected in parallel. In some illustrative embodiments, 650V / 120A SiC MOSFETs are selected. The power supply terminal of the driving chip is connected to a driving auxiliary power filter circuit 4. The PWM input signal 1 is connected to the input terminal of the driving chip after passing through an input filter circuit 2. The output terminal of the driving chip is connected to the input terminal of a driving gate network circuit 3. The output terminal of the driving gate network circuit 3 is connected to the input terminals of multiple driving protection circuits 5. The output terminals of the multiple driving protection circuits 5 are each connected to one of the SiC MOSFETs to be driven in the parallel matrix of three SiC MOSFETs. The output terminal of the parallel matrix of SiC MOSFETs is output after passing through an output filter circuit 6.

[0026] The SiC MOSFET of the first circuit unit and the SiC MOSFET of the second circuit unit are connected in series, wherein the source of the SiC MOSFET of the first circuit unit is connected to the drain of the SiC MOSFET of the second circuit unit.

[0027] In some embodiments, such as Figure 1 In the first circuit unit, a driver chip U1 is included. In some specific examples, the model of driver chip U1 is 1ED3122MU12H. The input filter circuit 2 includes a resistor R3. The first pin of driver chip U1 is connected to a 5V power supply through resistor R3. The second pin of driver chip U1 is connected to a 5V power supply through capacitor C3 and resistor R3 in sequence. A capacitor C2 is connected in parallel across capacitor C3. The third pin of driver chip U1 is connected to the PWM input signal 1 through resistor R1. The third pin of driver chip U1 is also grounded through resistor R2. The fourth pin of driver chip U1 is grounded through capacitor C1. In the input filter circuit 2, resistors R1-R3 and capacitors C1-C3 form a π-type filter, which performs RC attenuation on the input power supply and PWM signal, respectively. The cutoff frequency is set to 1 / 10 of the switching frequency. During layout, this network is close to the power supply and signal pins of driver chip U1 to avoid high-frequency circulating current crosstalk.

[0028] like Figure 1As shown, the auxiliary power supply filter circuit 4 includes resistors R7 and R8. The eighth pin of the driver chip U1 is connected to the VCC terminal of the external auxiliary power supply through resistor R7. The fifth pin of the driver chip U1 is connected to the VEE terminal of the external auxiliary power supply through resistor R8. The eighth pin of the driver chip U1 is also connected to the fifth pin of the driver chip U1 through capacitors C4 and C5 in sequence. A capacitor C6 is connected in parallel across capacitors C4 and C5. The middle side of capacitors C4 and C5 is connected to the high-voltage ground of the source of multiple SiC MOSFETs in the first circuit unit. Capacitors C4-C6, together with resistors R7 and R8, form an RC-π type filter, which attenuates the positive and negative rails of the external auxiliary power supply simultaneously, ensuring that the drop in auxiliary power supply voltage is less than a preset value when the drive current jumps. In some embodiments, the preset value is 0.5V.

[0029] like Figure 1 As shown, the driving gate network circuit 3 includes a resistor R4. The seventh pin of the driving chip U1 is connected to the driving protection circuit as the DRVH terminal after passing through the resistor R4. A resistor R5 is connected in parallel across the two ends of the resistor R4. The seventh pin of the driving chip U1 is connected to the cathode of the diode D1. The anode of the diode D1 is connected to the DRVH terminal after passing through the resistor R6. The sixth pin of the driving chip U1 is connected to the driving protection circuit as the CLAMPH terminal. Resistors R4-R6 and diode D1 form a current limiting and reverse connection protection integrated network. When reverse connection is applied, S34 is cut off with high resistance and automatically recovers in the forward direction. Resistors R4 and R5 are the gate resistors Rg. In some embodiments, an 11Ω / 0.25W gate resistor is selected. If the turn-off oscillation amplitude is less than 1V, the gate resistor Rg can be adjusted to 5Ω.

[0030] like Figure 2 and Figure 3 As shown, the drive protection circuit 5 includes a short-circuit protection branch 51 and a local absorption branch 53 connected in series, and a current limiting branch 52 connected in parallel across the local absorption branch. The local absorption branch 53 is connected in parallel between the gate and the Kelvin source of each SiC MOSFET.

[0031] like Figure 3As shown, the short-circuit protection branch 51 includes a Schottky diode D3. The cathode of the Schottky diode D3 is connected to the sixth pin of the driver chip U1, and the anode of the Schottky diode D3 is connected to the gate of the SiC MOSFET Q1. When a short circuit causes energy backflow through the Miller capacitor and the gate voltage exceeds Vcc + 0.3 V, the Schottky diode D3 conducts within 5 ns, bypassing the backflow current to the power supply. In actual measurements, it can reduce the gate overshoot from 4.2 V to 1.8 V, protecting the internal OUT / CLAMP cell of the driver chip from breakdown by an excess of 500 mA / 10µs energy. The local absorption branch 53 includes a capacitor C13, a resistor R20, and a resistor R19 connected in series. The local absorption branch 53 is connected in parallel between the gate and the Kelvin source of the SiC MOSFET Q1. The series branch of capacitor C13 and resistor R20 is also connected in parallel to the SiC MOSFET Q1. When routing the PCB, the width and length of the trace between the gate and the Kelvin source of the MOSFET Q1 should be as small as possible, and the parasitic inductance of the drive circuit should be <1 nH. The current limiting branch includes the current limiting resistor R18. The gate of the SiC MOSFET Q1 is also connected to the RDVH terminal after passing through resistor R17. In this circuit, resistor R19 is a current-sharing resistor used to suppress static current differences. Capacitor C13 and resistor R20 form an RC branch. Capacitor C13, resistor R20, and resistor R19 are connected in parallel between the gate and the Kelvin source, forming a local high-frequency loop. This loop is used to absorb high-frequency noise from the drive lead coupling and compensate for the asymmetry dv / dt caused by the positional differences of the electrolytic capacitors. In actual measurements, this can reduce the Vds spike by 8-12 V, effectively reducing the Vds spike. At the same time, the drive gate network circuit is connected to the drive protection circuit. Resistors R4 and R5 in the drive gate network circuit and capacitor C13 in the drive protection circuit also form an RC absorption, further reducing the Vds spike. The above example uses the drive protection circuit of SiC MOSFET Q1. The same principle applies to other SiC MOSFETs, and will not be repeated here.

[0032] The output filter circuit 6 includes capacitors C19, C20, C21, C22, C23, and C24 connected in parallel. One end of the output filter circuit is connected to the drain of the SiC MOSFET in the first circuit unit, and the other end of the output filter circuit is connected to the source of the SiC MOSFET in the second circuit unit. Figure 2As shown, the commutation circuit is located between the upper and lower transistors. When turned on, the reverse recovery current of the body diode will not concentrate on a single MOSFET because the SiC MOSFET Q5 is closest to the SiCMOS MOSFET Q6. The parasitic inductance of the line to the SiC MOSFET Q2 limits the reverse recovery current. The situation is similar for other MOSFETs. The electrolytic capacitors connected in parallel to the transistors are spaced unequally apart. Therefore, adding capacitors C22-C24 helps to weaken this asymmetry and also provides a high-frequency circuit, reducing the Vds spike.

[0033] The second circuit unit includes a driver chip U2. The third pin of the driver chip U2 is connected to another PWM input signal through resistor R16. The eighth pin of the driver chip U2 is connected to the VCC terminal of another external auxiliary power source through resistor R10. The fifth pin of the driver chip U2 is connected to the VEE terminal of another external auxiliary power source through resistor R9. The eighth pin of the driver chip U2 is also connected to the fifth pin of the driver chip U2 through capacitors C9 and C8 in sequence. The middle side of capacitors C9 and C8 is connected to the low-voltage ground of the sources of multiple SiC MOSFETs in the second circuit unit. The second circuit unit has the same structural layout as the first circuit unit, and will not be described in detail here.

[0034] Example 2:

[0035] The present invention provides a power module, including a driving circuit for three parallel SiC MOSFETs as described in Embodiment 1.

[0036] The power module provided in the embodiments of the present invention can execute the driving circuit for three parallel SiC MOSFETs provided in any embodiment of the present invention, and has the corresponding functions and beneficial effects of the driving circuit.

[0037] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A driving circuit for three parallel SiC MOSFETs, characterized in that, The system includes a first circuit unit and a second circuit unit with identical structures. The SiC MOSFETs of the first circuit unit and the second circuit unit are connected in series. Both the first and second circuit units include a driver chip and a parallel matrix of three SiC MOSFETs. The power supply terminal of the driver chip is connected to a driver auxiliary power filter circuit. The PWM input signal is connected to the input terminal of the driver chip after passing through an input filter circuit. The output terminal of the driver chip is connected to the input terminal of a driver gate network circuit. The output terminal of the driver gate network is connected to the input terminals of multiple driver protection circuits. The output terminals of the multiple driver protection circuits are each connected to one of the SiC MOSFETs to be driven in the parallel matrix of three SiC MOSFETs. The output terminal of the parallel matrix of SiC MOSFETs is output after passing through an output filter circuit.

2. The driving circuit for three parallel SiC MOSFETs according to claim 1, characterized in that, The first circuit unit includes a driver chip U1, and the input filter circuit includes a resistor R3. The first pin of the driver chip U1 is connected to a 5V power supply after passing through the resistor R3. The second pin of the driver chip U1 is connected to a 5V power supply after passing through the capacitor C3 and the resistor R3 in sequence. A capacitor C2 is connected in parallel across the two ends of the capacitor C3. The third pin of the driver chip U1 is connected to a PWM input signal after passing through the resistor R1. The third pin of the driver chip U1 is also grounded after passing through the resistor R2. The fourth pin of the driver chip U1 is grounded after passing through the capacitor C1.

3. The driving circuit for three parallel SiC MOSFETs according to claim 2, characterized in that, The auxiliary power supply filter circuit includes resistors R7 and R8. The eighth pin of the driver chip U1 is connected to the VCC terminal of the external auxiliary power supply through resistor R7. The fifth pin of the driver chip U1 is connected to the VEE terminal of the external auxiliary power supply through resistor R8. The eighth pin of the driver chip U1 is also connected to the fifth pin of the driver chip U1 through capacitors C4 and C5. A capacitor C6 is connected in parallel across capacitors C4 and C5. The middle side of capacitors C4 and C5 is connected to the high-voltage ground of the source of multiple SiC MOSFETs in the first circuit unit.

4. The driving circuit for three parallel SiC MOSFETs according to claim 2, characterized in that, The driving gate network circuit includes resistor R4. The seventh pin of the driving chip U1 is connected to the driving protection circuit as the DRVH terminal after passing through resistor R4. Resistor R5 is connected in parallel across resistor R4. The seventh pin of the driving chip U1 is connected to the cathode of diode D1. The anode of diode D1 is connected to the DRVH terminal after passing through resistor R6. The sixth pin of the driving chip U1 is connected to the driving protection circuit as the CLAMPH terminal.

5. The driving circuit for three parallel SiC MOSFETs according to claim 4, characterized in that, The drive protection circuit includes a short-circuit protection branch and a local absorption branch connected in series, as well as a current-limiting branch connected in parallel across the local absorption branch. The local absorption branch is connected in parallel between the gate and the Kelvin source of each SiC MOSFET.

6. The driving circuit for three parallel SiC MOSFETs according to claim 5, characterized in that, The short-circuit protection branch includes a Schottky diode D3, the cathode of which is connected to the sixth pin of the driver chip U1, and the anode of which is connected to the gate of the SiC MOSFET Q1. The local absorption branch includes a capacitor C13, a resistor R20, and a resistor R19 connected in series. The local absorption branch is connected in parallel between the gate and the Kelvin source of the SiC MOSFET Q1. The series branch of capacitor C13 and resistor R20 is also connected in parallel between the gate and the Kelvin source of the SiC MOSFET Q1. The current limiting branch includes a current limiting resistor R18. The gate of the SiC MOSFET Q1 is also connected to the RDVH terminal after passing through resistor R17.

7. The driving circuit for three parallel SiC MOSFETs according to claim 1, characterized in that, The SiC MOSFET of the first circuit unit and the SiC MOSFET of the second circuit unit are connected in series, wherein the source of the SiC MOSFET of the first circuit unit is connected to the drain of the SiC MOSFET of the second circuit unit.

8. The driving circuit for three parallel SiC MOSFETs according to claim 7, characterized in that, The output filter circuit includes capacitors C19, C20, C21, C22, C23, and C24 connected in parallel. One end of the output filter circuit is connected to the drain of the SiC MOSFET in the first circuit unit, and the other end of the output filter circuit is connected to the source of the SiC MOSFET in the second circuit unit.

9. A power module, characterized in that, Includes the drive circuit for three parallel SiC MOSFETs as described in any one of claims 1-8.

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